Display device and electronic device including the same

Abstract

Disclosed are a display device including: a substrate; a sub-pixel on the substrate; a via layer on the substrate and including a recess pattern recessed in a direction toward the substrate; and a pixel definition layer defining an emission area and on the via layer in a non-emission area around the emission area. The pixel definition layer defines a light emission opening corresponding to the emission area and a dummy opening exposing a portion of the via layer in the non-emission area. In a plan view, the recess pattern of the via layer and the dummy opening of the pixel definition layer are superposed on each other. The display device has improved reliability.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0079583, filed on June 19, 2024, and Korean Patent Application No. 10-2024-0103859, filed on August 5, 2024, both of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0003] Recently, with the increasing interest in information displays, research and development of display devices are ongoing. Utility Model Content

[0004] One or more aspects of this disclosure relate to a display device with improved reliability and a method of manufacturing the same.

[0005] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosed embodiments presented.

[0006] A display device according to one or more embodiments includes: a substrate; sub-pixels on the substrate; a via layer disposed on the substrate and including (defining) a recessed pattern recessed in a direction toward the substrate; and a pixel defining layer defining an emitting region and disposed on the via layer in a non-emitting region positioned around the emitting region. The pixel defining layer includes (defining) a light-emitting opening corresponding to the emitting region and a dummy opening exposing a portion of the via layer in the non-emitting region. In a plan view, the recessed pattern of the via layer and the dummy opening of the pixel defining layer intersect (overlay) each other.

[0007] In one or more embodiments, a sub-pixel may include: a first sub-pixel that emits light of a first color; a second sub-pixel that emits light of a second color; and a third sub-pixel that emits light of a third color. The emitting region may include: a first emitting region that forms (defines) the first sub-pixel; a second emitting region that forms (defines) the second sub-pixel; and a third emitting region that forms (defines) the third sub-pixel.

[0008] In one or more embodiments, the dummy opening may include: a first dummy opening extending in a first direction in a non-emissive region between a first sub-pixel and a second sub-pixel and in a non-emissive region between a second sub-pixel and a third sub-pixel; and a second dummy opening extending in a second direction intersecting the first direction in a non-emissive region between the first sub-pixel and the third sub-pixel.

[0009] In one or more embodiments, the recessed pattern may include: a first recessed pattern extending in a second direction and intersecting (overlapping) with a first dummy opening; and a second recessed pattern extending in the first direction and intersecting (overlapping) with a second dummy opening.

[0010] In one or more embodiments, the first dummy opening and the second dummy opening may be spaced apart and / or separated (e.g., spaced apart or separated).

[0011] The first dummy opening and the second dummy opening can be connected.

[0012] In one or more embodiments, a first end portion of the pixel defining layer on an opposite side of the pixel defining layer defines a first dummy opening between the first ends and may be arranged in a first recessed pattern. A second end portion of the pixel defining layer on an opposite side of the pixel defining layer defines a second dummy opening between the second ends and may be arranged in a second recessed pattern.

[0013] In one or more embodiments, the boundary points between the upper surface of the via layer and the recessed pattern can be covered by a pixel-defining layer.

[0014] In one or more embodiments, a first end of the pixel defining layer may contact a first recessed pattern to define a first trench. A second end of the pixel defining layer may contact a second recessed pattern to define a second trench.

[0015] In one or more embodiments, the display device may further include: an anode electrode disposed between a via layer and a pixel defining layer in each of the sub-pixels and exposed through a light-emitting opening in the pixel defining layer; an emitting structure disposed on the anode electrode and the pixel defining layer; and a cathode electrode disposed on the emitting structure.

[0016] In one or more embodiments, the emitting structure may include: a first emitting unit disposed on an anode electrode and a pixel defining layer and emitting light; an intermediate layer disposed on the first emitting unit; and a second emitting unit disposed on the intermediate layer and emitting light. The first emitting unit and the intermediate layer may be disconnected at each of the first trench and the second trench, and the second emitting unit may not be disconnected at the first trench and the second trench.

[0017] In one or more embodiments, the first trench may include (define) a first gap surrounded by the first recessed pattern, the first end of the pixel-defining layer, the first emitting unit, the intermediate layer, and the second emitting unit (defined by the first recessed pattern, the first end of the pixel-defining layer, the first emitting unit, the intermediate layer, and the second emitting unit). The second trench may include (define) a second gap defined by the second recessed pattern, the second end of the pixel-defining layer, the first emitting unit, the intermediate layer, and the second emitting unit.

[0018] In one or more embodiments, the first recessed pattern may include a plurality of first recessed patterns arranged along a first direction. The second recessed pattern may include a plurality of second recessed patterns arranged along a second direction.

[0019] In one or more embodiments, each of the plurality of first recessed patterns may intersect (overlay) with a first dummy opening. Each of the plurality of second recessed patterns may intersect (overlay) with a second dummy opening.

[0020] In one or more embodiments, the first dummy opening may include a plurality of first sub-dummy openings that are spaced apart and / or separated from each other (e.g., spaced apart or separated). At least one of the plurality of first sub-dummy openings may intersect (overlap) with one of the first recessed patterns.

[0021] In one or more embodiments, the dummy opening may include: a first dummy opening extending in a first direction in a non-emissive region between a first sub-pixel and a second sub-pixel, and in a non-emissive region between a second sub-pixel and a third sub-pixel; and a second dummy opening extending in the first direction in a non-emissive region between the first sub-pixel and the third sub-pixel. The second dummy opening may include a plurality of second sub-dummy openings extending in the first direction and arranged along a second direction intersecting the first direction.

[0022] In one or more embodiments, the recessed pattern may include: a first recessed pattern extending in a second direction and intersecting (overlapping) with a first dummy opening; and a second recessed pattern extending in the second direction and intersecting (overlapping) with a plurality of second sub-dummy openings. The second recessed pattern may be provided in the form of a line (e.g., it may have a line shape).

[0023] In one or more embodiments, the dummy opening may include: a first dummy opening extending in a second direction within a non-emitting region between a first sub-pixel and a second sub-pixel; and a second dummy opening extending in the second direction within a non-emitting region between a second sub-pixel and a third sub-pixel. The recessed pattern may extend in a first direction intersecting the second direction and may intersect (overlay) each of the first and second dummy openings.

[0024] A display device according to one or more embodiments includes: a substrate; a first sub-pixel, a second sub-pixel, and a third sub-pixel on the substrate; a via layer disposed on the substrate and including (defining) a recessed pattern recessed in a direction toward the substrate; and a pixel defining layer on the via layer in a non-emitting region, defining a first emitting region of the first sub-pixel, a second emitting region of the second sub-pixel, and a third emitting region of the third sub-pixel. The pixel defining layer includes (defining) a first opening corresponding to the first emitting region, a second opening corresponding to the second emitting region, a third opening corresponding to the third emitting region, and a dummy opening exposing a portion of the via layer in the non-emitting region. In a plan view, the recessed pattern of the via layer and the dummy opening of the pixel defining layer intersect (overlay) each other.

[0025] In one or more embodiments of this disclosure, a method of manufacturing a display device having sub-pixels including an emitting region includes: forming a via layer on a substrate including a recessed pattern recessed in a direction toward the substrate; forming a pixel defining layer defining the emitting region on the via layer in a non-emitting region surrounding the emitting region; and forming an emitting structure on the pixel defining layer. The pixel defining layer includes (defining) a light-emitting opening corresponding to the emitting region and a dummy opening exposing a portion of the via layer in the non-emitting region. In a plan view, the recessed pattern of the via layer and the dummy opening of the pixel defining layer intersect (overlay) each other.

[0026] An electronic device according to one or more embodiments includes a display device comprising: a substrate; a sub-pixel on the substrate; a via layer on the substrate, defining a recessed pattern in a direction toward the substrate; and a pixel defining layer defining an emitting region and, in a non-emitting region surrounding the emitting region, on the via layer. The pixel defining layer defines a light-emitting opening corresponding to the emitting region and a dummy opening exposing a portion of the via layer in the non-emitting region. In a plan view, the recessed pattern of the via layer and the dummy opening of the pixel defining layer overlap each other.

[0027] According to one or more embodiments, in the non-emitting region between sub-pixels, the intermediate layer (or charge generation layer) can be disconnected at a trench formed by the intersection (overlap) of the recessed pattern (or groove) of the via layer and the dummy opening of the pixel defining layer. Therefore, current flowing through the intermediate layer to adjacent sub-pixels can be reduced or prevented, thereby improving the reliability of the display device.

[0028] The effects according to one or more embodiments are not limited to the effects described above, and a wider variety of effects may be included in this specification. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0030] Figure 1 This is a schematic plan view illustrating a display device according to one or more embodiments of the present disclosure.

[0031] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic block diagram of a display device.

[0032] Figure 3 This is an illustrative representation of one or more embodiments according to the present disclosure. Figure 1 A circuit diagram showing the electrical connections of components within a sub-pixel.

[0033] Figure 4A This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels.

[0034] Figure 4B This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels.

[0035] Figure 4C This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels.

[0036] Figure 5 It is according to one or more embodiments of this disclosure along Figure 4A A schematic cross-sectional view taken from line I-I'.

[0037] Figure 6 This illustrates one or more embodiments according to the present disclosure, including... Figure 5 A schematic cross-sectional view of the emitting structure in one of the first to third light-emitting elements.

[0038] Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic plan view of the display area.

[0039] Figure 8 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view taken from line II-II'.

[0040] Figure 9According to one or more embodiments of this disclosure Figure 8 An enlarged schematic cross-sectional view of region EA.

[0041] Figure 10 This illustrates one or more embodiments according to the present disclosure. Figure 7 A schematic perspective view of the via layer and pixel-limiting layer.

[0042] Figures 11 to 15 It is along Figure 7 The line II-II' shows a schematic cross-sectional view (view) of a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0043] Figures 16 to 18 Each of these is a schematic plan view showing a region of a display device according to one or more embodiments of the present disclosure.

[0044] Figure 19 This is a schematic plan view showing the display area of ​​a display device according to one or more embodiments of the present disclosure.

[0045] Figure 20 This is a block diagram of an electronic device according to an embodiment.

[0046] Figure 21 Schematic diagrams of various embodiments of the electronic device are shown. Detailed Implementation

[0047] This disclosure can be modified in many alternative forms, and therefore specific embodiments will be shown and described in more detail in the accompanying drawings. However, it should be understood that this is not intended to limit this disclosure to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure.

[0048] In the following description, exemplary embodiments will be presented in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not essential for a full understanding of the aspects and features of this disclosure may not be described.

[0049] It will be understood that when an element, such as a region, layer, membrane, area, or portion, is referred to as being "on" or "connected to" another element, the element may be directly on or connected to the other element, or one or more intervening elements may be present. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "immediately adjacent to" another element or layer, no intervening element or layer is present. Furthermore, it will be understood that when an element is referred to as being "between two elements," the element may be the only element between the two elements, or one or more intervening elements may be present.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Unless otherwise clearly stated in the disclosure, expressions such as “at least one of…”, “multiple…”, “one of…”, and other prepositional phrases preceding or following a list of elements, if written as a conjunction list, should be understood to include disjunction, and vice versa. For example, expressions such as “at least one of a, b, and c”, “one selected from the group consisting of a, b, and c”, “at least one selected from a, b, and c”, “at least one from a, b, and c”, “from one of a, b, and c”, “at least one of a to c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section.

[0053] For ease of explanation, spatial relative terms such as “above,” “below,” “lower,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature (or other elements or features). It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0054] Various embodiments are described with reference to the accompanying drawings, which illustrate exemplary embodiments. Therefore, it will be contemplated that, for example, the shape may vary depending on tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but should be interpreted as including variations in shape caused, for example, by manufacturing processes. Thus, the shapes shown in the drawings may not represent the actual shapes of areas of the device, and this embodiment is not limited thereto. Additionally, in the drawings, the relative dimensions of elements, layers, and areas may be exaggerated for clarity.

[0055] Unless otherwise stated, the same reference numerals denote the same elements throughout the accompanying drawings and written description, and therefore, their repeated description is not required. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0056] As used herein, the term “use” and its variants may be considered synonymous with the term “utilize” and its variants, respectively.

[0057] In the context of this disclosure and unless otherwise defined, a plan view is an orthogonal projection of a three-dimensional object onto a horizontal plane passing through that three-dimensional object. That is, a plan view is a top-down view showing the layout and spatial relationships of various elements within an object or structure. A plan view based on a third direction DR3 refers to a top-down view of the display panel, as if looking directly down at the surface from above. In this context, the third direction DR3 is a direction perpendicular to or orthogonal to the plane defined by the first direction DR1 and the second direction DR2. This means that in the plan view, the arrangement of subpixels, pads (also referred to as "solder pads"), and other components as they are placed on the substrate can be seen without any perspective distortion.

[0058] Figure 1 This is a schematic plan view illustrating a display device DD according to one or more embodiments of the present disclosure. For convenience, Figure 1 The structure of the display device DD (e.g., the display panel DP provided in the display device DD) is briefly shown with the display area DA where the image is displayed as the center.

[0059] Reference Figure 1 The display device DD (or display panel DP) may include a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. The non-display area NDA may be arranged around the display area DA.

[0060] The display panel (DP) can include a base (SUB), subpixels (SP), and pads (PD).

[0061] The substrate SUB may include a transparent insulating material to allow light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0062] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, or a crystalline glass substrate.

[0063] The flexible substrate can be one of a membrane substrate comprising polymeric organic materials and a plastic substrate. For example, the flexible substrate may include at least any one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0064] One area on the substrate SUB can be configured as a display area DA in which sub-pixels SP (or pixels PXL) are arranged, and the remaining areas on the substrate SUB can be configured as non-display areas NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA, wherein the display area DA includes a pixel area in which each sub-pixel SP (or each pixel PXL) is arranged, and the non-display area NDA is arranged around (or adjacent to) the display area DA.

[0065] The display area DA can have various shapes. For example, the display area DA can be set in a variety of shapes (such as a closed polygon with sides composed of straight lines, a circle or ellipse with sides composed of curves, or a semicircle or semi-ellipse with sides composed of both straight lines and curves).

[0066] The non-display area NDA can be located on at least one side of the display area DA. For example, the non-display area NDA can surround the periphery of the display area DA. Subpixels SP can be arranged in a matrix on the substrate SUB along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of subpixels SP is not limited to this. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0067] Two or more sub-pixels SP can constitute a single pixel PXL, but this disclosure is not limited thereto.

[0068] In the non-display area NDA on the substrate SUB, components for controlling the sub-pixels SP can be arranged. For example, wiring electrically connected to the sub-pixels SP can be arranged in the non-display area NDA. The wiring may include, for example, gate lines and data lines.

[0069] To drive the subpixel SP, a driver electrically connected to the subpixel SP can be arranged (or integrated) in the non-display area NDA of the display panel DP. The pad PD can be arranged on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the subpixel SP via wiring. For example, the pad PD can be electrically connected to the subpixel SP via a data line.

[0070] In one or more embodiments, the circuit board can be electrically connected to the pad PD via a conductive adhesive component, such as an anisotropic conductive film. The circuit board can be a flexible circuit board or a flexible film made of a flexible material. A driver can be mounted on the circuit board and electrically connected to the pad PD.

[0071] In one or more embodiments, the display panel DP may have a flat display surface. According to one or more embodiments, the display panel DP may have a display surface that is at least partially rounded. In one or more embodiments, the display panel DP may be flexible, foldable, or rollable. In such embodiments, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0072] The display device DD according to one or more embodiments of this disclosure can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and / or ultra-mobile PCs (UMPCs). Optionally, the display device DD according to one or more embodiments can be applied as a display unit for televisions, laptop computers, monitors, billboards, and / or Internet of Things (IoT) devices. Optionally, the display device DD according to one or more embodiments can be applied to wearable devices such as smartwatches, watch phones, glasses-type (or similar) displays, and / or head-mounted displays (HMDs). Optionally, the display device DD according to one or more embodiments can be applied to automotive displays, such as displays in vehicle dashboards, vehicle center dashboards, central information displays (CIDs) arranged on vehicle dashboards, interior mirror displays replacing vehicle side mirrors, and / or displays arranged on the back of the front seats for the entertainment of rear-seat passengers.

[0073] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic block diagram of the display device DD.

[0074] Reference Figure 1 and Figure 2 A display device DD according to one or more embodiments may include a display panel DP, a driver, and a wiring unit.

[0075] The display panel (DP) can display an image in response to data signals (DATA) and scan signals supplied from the data driver (DDV) and the scan driver (SDV). The display panel (DP) may include multiple sub-pixels (SP) for displaying the image.

[0076] The driver may include an image processor (IPP), a timing controller (TC), a data driver (DDV), and a scan driver (SDV).

[0077] The image processor (IPP) can output a data enable signal DE and an externally supplied data signal DATA. In addition to the data enable signal DE, the image processor (IPP) can output one or more of the following: a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0078] The timing controller TC can receive data enable signals (DE or drive signals) and data signals (DATA) from the image processor IPP, including vertical synchronization signals, horizontal synchronization signals, and / or clock signals. Based on the drive signals, the timing controller TC can output a gate control signal (GCS) to control the operating timing of the scan driver SDV and a data control signal (DCS) to control the operating timing of the data driver DDV.

[0079] The data driver DDV responds to the data control signal DCS supplied from the timing controller TC to output the data signal DATA by converting the data signal DATA supplied from the timing controller TC into a corresponding data voltage. The data driver DDV can supply data voltage to data lines D1 to Dm. The data voltage supplied to data lines D1 to Dm can be supplied to the sub-pixel SP selected by the scan signal.

[0080] The scan driver SDV can apply scan signals to scan lines S1 to Sn in response to the gate control signal GCS supplied from the timing controller TC. For example, once the scan signals are sequentially supplied to scan lines S1 to Sn, the scan driver SDV can allow the sequential selection of sub-pixels SP on a horizontal line basis.

[0081] Figure 3 This is an illustrative representation of one or more embodiments according to the present disclosure. Figure 1 A circuit diagram showing the electrical connections of components in a sub-pixel SP. For ease of explanation, Figure 3 The sub-pixel shown is the sub-pixel SP located in the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj.

[0082] Reference Figures 1 to 3 Subpixels SP can be arranged in the i-th horizontal line (or the i-th pixel row). Subpixels SP can include pixel circuit PXC and light-emitting element LD. Pixel circuit PXC can include first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6 and seventh transistor T7, and storage capacitor Cst.

[0083] The first electrode of the light-emitting element LD can be electrically connected to the fourth node N4, and the second electrode of the light-emitting element LD can be electrically connected to the fourth power wiring PL4. The light-emitting element LD can generate light of a specific brightness in response to the amount of current (or drive current) supplied from the first transistor T1. In one or more embodiments, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer.

[0084] A first transistor T1 (or driving transistor) may be electrically connected between a first power wiring PL1 and a first electrode of a light-emitting element LD. The first transistor T1 may include a gate electrode electrically connected to a first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power wiring PL1 through the light-emitting element LD to the fourth power wiring PL4 based on the voltage of the first node N1. A first power voltage VDD may be applied to the first power wiring PL1, and a second power voltage VSS may be applied to the fourth power wiring PL4. The first power voltage VDD may be set to a voltage higher than the second power voltage VSS.

[0085] The second transistor T2 can be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the i-th first scan line S1i (or the first scan line). The second transistor T2 can be turned on when the first scan signal GW[i] (e.g., a low-level first scan signal) is supplied to the i-th first scan line S1i to electrically connect the second node N2 to the j-th data line Dj. When both the first transistor T1 and the third transistor T3 are on, the second transistor T2 can send the data signal from the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0086] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be electrically connected to the i-th first scan line S1i. The third transistor T3 can be turned on when the first scan signal GW[i] is supplied to the i-th first scan line S1i. When the third transistor T3 is turned on, the first transistor T1 can be in the form of a diode connection.

[0087] The fourth transistor T4 can be electrically connected between the first node N1 and the second power wiring PL2. The gate electrode of the fourth transistor T4 can be electrically connected to the i-th second scan line S2i (or the second scan line). The first initialization power voltage Vint1 can be applied to the second power wiring PL2. The fourth transistor T4 can be turned on by the second scan signal GI[i] supplied to the i-th second scan line S2i. When the fourth transistor T4 is turned on, the first initialization power voltage Vint1 can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0088] The fifth transistor T5 can be electrically connected between the first power wiring PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be electrically connected to the i-th light-emitting control line Ei (or the light-emitting control line). The sixth transistor T6 can be electrically connected between the third node N3 and the light-emitting element LD (or the fourth node N4). The gate electrode of the sixth transistor T6 can be electrically connected to the i-th light-emitting control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off when the light-emitting control signal EM[i] (e.g., a high-level light-emitting control signal EM[i]) is supplied to the i-th light-emitting control line Ei.

[0089] A seventh transistor T7 can be electrically connected between the first electrode (i.e., the fourth node N4) of the light-emitting element LD and the third power wiring PL3. The gate electrode of the seventh transistor T7 can be electrically connected to the i-th third scan line S3i. A second initialization power voltage Vint2 can be applied to the third power wiring PL3. According to one or more embodiments, the second initialization power voltage Vint2 can be the same as or different from the first initialization power voltage Vint1. The seventh transistor T7 can be turned on by the third scan signal GB[i] supplied to the i-th third scan line S3i to supply the second initialization power voltage Vint2 to the first electrode of the light-emitting element LD.

[0090] The storage capacitor Cst can be connected or formed between the first power wiring PL1 and the first node N1.

[0091] In one or more embodiments, the pixel circuit PXC may include P-type (class) transistors and / or N-type (class) transistors. Both the third transistor T3 and the fourth transistor T4 may be formed as oxide semiconductor transistors comprising one or more oxide semiconductors. For example, both the third transistor T3 and the fourth transistor T4 may be N-type (class) oxide semiconductor transistors and may include an oxide semiconductor layer as an active layer, but this disclosure is not limited thereto. Oxide semiconductor transistors can be processed at low temperatures and may have lower charge mobility than polysilicon semiconductor transistors. For example, oxide semiconductor transistors exhibit excellent or suitable cutoff current characteristics. Therefore, leakage current in the third transistor T3 and the fourth transistor T4 can be minimized or reduced.

[0092] The remaining transistors (e.g., first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, and seventh transistor T7) can be formed as polycrystalline silicon transistors including silicon semiconductors, and each can include a polycrystalline silicon semiconductor layer as an active layer. For example, the active layer can be formed using a low-temperature polycrystalline silicon process (e.g., low-temperature polycrystalline silicon (LTPS) process). For example, the polycrystalline silicon transistor can be a P-type (or similar) polycrystalline silicon transistor. Polycrystalline silicon semiconductor transistors can have a fast response rate, making them suitable for use in switching elements where fast switching is desired or required.

[0093] Figure 4A This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels in PXL.

[0094] Reference Figure 1 and Figure 4A Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged on the first direction DR1.

[0095] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0096] The first emission region EMA1 can be derived from the emission structure (see, for example, ...). Figure 5 The "EMS" in the diagram refers to the region of the EMS that emits light corresponding to the first sub-pixel SP1. The second emitting region EMA2 can be the region of the EMS that emits light corresponding to the second sub-pixel SP2. The third emitting region EMA3 can be the region of the EMS that emits light corresponding to the third sub-pixel SP3.

[0097] Figure 4B This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels in PXL.

[0098] Reference Figure 1 and Figure 4B Pixel PXL' may include a first sub-pixel SP1', a second sub-pixel SP2', and a third sub-pixel SP3'.

[0099] The first sub-pixel SP1' may include a first emission region EMA1' and a non-emission region NEA' surrounding the first emission region EMA1'. The second sub-pixel SP2' may include a second emission region EMA2' and a non-emission region NEA' surrounding the second emission region EMA2'. The third sub-pixel SP3' may include a third emission region EMA3' and a non-emission region NEA' surrounding the third emission region EMA3'.

[0100] When viewed on a third-party DR3 (e.g., in a planar view), the first subpixel SP1' to the third subpixel SP3' may have, but are not limited to, a square shape.

[0101] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged on the second direction DR2. The third sub-pixel SP3' can be arranged on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0102] The second sub-pixel SP2' may have an area larger than the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than the second sub-pixel SP2'. Therefore, the second emission region EMA2' may have an area larger than the first emission region EMA1', and the third emission region EMA3' may have an area larger than the second emission region EMA2'. However, this disclosure is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area as each other, and the third sub-pixel SP3' may have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' can be varied and modified according to one or more embodiments.

[0103] Figure 4C This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic planar view of one of the pixels in PXL.

[0104] Reference Figure 1 and Figure 4C The first sub-pixel SP1'' may include a first emission region EMA1'' and a non-emission region NEA'' surrounding the first emission region EMA1''. The second sub-pixel SP2'' may include a second emission region EMA2'' and a non-emission region NEA'' surrounding the second emission region EMA2''. The third sub-pixel SP3'' may include a third emission region EMA3'' and a non-emission region NEA'' surrounding the third emission region EMA3''.

[0105] When viewed on a third-party DR3 (e.g., in a planar view), the first subpixel SP1'' to the third subpixel SP3'' can have a polygonal shape. For example, as Figure 4C As shown, the shapes of the first sub-pixel SP1'' to the third sub-pixel SP3'' can be hexagonal.

[0106] When viewed from a third-party perspective on DR3 (e.g., in a plan view), the first emission region EMA1'' to the third emission region EMA3'' may have a circular shape. However, this disclosure is not limited thereto. For example, each of the first emission region EMA1'' to the third emission region EMA3'' may have a polygonal shape.

[0107] The first sub-pixel SP1'' and the third sub-pixel SP3'' can be arranged on the first direction DR1. The second sub-pixel SP2'' can be arranged relative to the first sub-pixel SP1'' in an oblique direction (or obliquely) at an acute angle based on the second direction DR2.

[0108] Figure 4A , Figure 4B and Figure 4C The arrangement of subpixels shown is an example, and this disclosure is not limited thereto. Each pixel may include two or more subpixels, the subpixels may be arranged in one or more suitable ways, each of the subpixels may have multiple shapes, and each of the emission regions of the subpixels may also have multiple shapes.

[0109] Figure 5 It is according to one or more embodiments of this disclosure along Figure 4A A schematic cross-sectional view taken from line I-I'.

[0110] exist Figure 5 In the illustration, for ease of explanation, the cross-sectional structure (or stacked structure) of the display device DD is briefly shown by focusing on the pixels PXL formed on the substrate SUB, and the thickness direction of the substrate SUB is indicated as the third direction DR3.

[0111] Reference Figure 1 , Figure 4A and Figure 5 The display device DD may include at least one or more pixels PXL arranged in the display area DA of the substrate SUB.

[0112] Pixel PXL may include at least one sub-pixel SP. For example, pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In one or more embodiments, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0113] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE.

[0114] The substrate SUB may include a transparent insulating material to allow light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0115] The pixel circuit layer PCL and the display element layer DPL may be arranged to overlap each other on one side of the substrate SUB.

[0116] At least one insulating layer may be arranged in the pixel circuit layer PCL. For example, the insulating layer may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a via layer VIA that are sequentially stacked on the substrate SUB along a third direction DR3. The insulating layer arranged in the pixel circuit layer PCL is not limited to the embodiments described above, and other insulating layers may be added.

[0117] The buffer layer BFL may be arranged over the entire area on the substrate SUB. The buffer layer BFL may prevent or reduce the diffusion of impurities into circuit elements (e.g., transistors) constituting the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating film including an inorganic material. The buffer layer BFL may include silicon nitride (Si x N y , where, for example, 0 < x ≤ 3 and 0 < y ≤ 4), silicon oxide (SiO x , where, for example, 0 < x ≤ 2), silicon oxynitride (SiO x N y , where, for example, 0 < x ≤ 2 and 0 < y ≤ 4), and aluminum oxide (Al x O y , where, for example, 0 < x ≤ 2 and 0 < y ≤ 3)) or at least one of them. The buffer layer BFL may be provided as a single-layer film, but may also be provided as a multi-layer film having at least two or more layers. If the buffer layer BFL is provided as a multi-layer, each layer may be formed of the same material or different materials. In one or more embodiments, the buffer layer BFL may not be provided depending on the material of the substrate SUB and the processing conditions.

[0118] The gate insulating layer GI may be arranged over the entire area on the buffer layer BFL. The gate insulating layer GI may include the same material as the buffer layer BFL described above, or the gate insulating layer GI may include a suitable (or selected) material from the materials listed above as components of the buffer layer BFL. For example, the gate insulating layer GI may be an inorganic insulating film including an inorganic material.

[0119] The interlayer insulating layer (ILD) may be disposed and / or formed throughout the entire region of the gate insulating layer (GI). The interlayer insulating layer (ILD) may include the same material as the buffer layer (BFL), or the interlayer insulating layer (ILD) may include one or more suitable (or selected) materials from the materials listed above as components of the buffer layer (BFL).

[0120] The via layer (VIA) can be disposed and / or formed throughout the entire area of ​​the interlayer insulating layer (ILD). The via layer (VIA) can be an inorganic insulating film comprising inorganic materials or an organic insulating film comprising organic materials. The inorganic insulating film can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The organic insulating film can include at least one of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In one or more embodiments, the via layer (VIA) can be an organic insulating film comprising organic materials.

[0121] The via layer (VIA) can be partially opened to include vias. These vias can be connection points for electrically connecting the pixel circuitry (PXC) and the light-emitting element (LD) of each sub-pixel (SP).

[0122] In the pixel circuit layer (PCL), circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3 can be arranged. For example, transistor T_SP1 of the first sub-pixel SP1, transistor T_SP2 of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be arranged in the pixel circuit layer (PCL). Transistor T_SP1 of the first sub-pixel SP1 can be one of the transistors included in the pixel circuit PXC of the first sub-pixel SP1, transistor T_SP2 of the second sub-pixel SP2 can be one of the transistors included in the pixel circuit PXC of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the pixel circuit PXC of the third sub-pixel SP3. Figure 5 In the diagram, for clarity and simplicity, one transistor in each sub-pixel SP is shown, and... Figure 5 The remaining circuit components are not provided.

[0123] The transistor T_SP1 of the first sub-pixel SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0124] The gate electrode GE can be disposed on the gate insulating layer GI and covered by the interlayer insulating layer ILD. For example, the gate electrode GE can be a gate conductive layer positioned between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE can be stacked with a portion of the semiconductor pattern SCP. For example, the gate electrode GE can be stacked with the active layer of the semiconductor pattern SCP.

[0125] A semiconductor pattern SCP can be disposed and / or formed on a buffer layer BFL. The semiconductor pattern SCP can be a semiconductor layer comprising polycrystalline silicon, amorphous silicon, and / or oxide semiconductors (e.g., composed of polycrystalline silicon, amorphous silicon, and / or oxide semiconductors). The semiconductor pattern SCP may include an active layer, a first contact region, and a second contact region. The active layer, the first contact region, and the second contact region may include undoped or doped semiconductor layers. For example, the first and second contact regions may include doped semiconductor layers, and the active layer may include an undoped semiconductor layer.

[0126] The active layer of the semiconductor pattern SCP is a region that can be a channel region, superimposed on the gate electrode GE. A first contact area of ​​the semiconductor pattern SCP can contact one end of the active layer. This first contact area can be electrically connected to a first terminal EL1. A second contact area of ​​the semiconductor pattern SCP can contact the other end of the active layer. This second contact area can be electrically connected to a second terminal EL2.

[0127] The first terminal EL1 may be disposed on and / or formed on the interlayer insulating layer ILD. For example, the first terminal EL1 may be formed by a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The first terminal EL1 may contact the first contact area of ​​the semiconductor pattern SCP through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0128] The second terminal EL2 may be disposed and / or formed on the interlayer insulating layer ILD and arranged to be spaced apart and / or separated from the first terminal EL1 (e.g., spaced apart or separated). The second terminal EL2 may be formed from a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The second terminal EL2 may contact the second contact area of ​​the semiconductor pattern SCP through another contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0129] According to one or more embodiments, the lower metal layer BML may be arranged on the bottom of the transistor T_SP1 of the first sub-pixel SP1 described above.

[0130] The lower metal layer BML can be a first conductive layer positioned between the substrate SUB and the buffer layer BFL. In one or more embodiments, the lower metal layer BML can be electrically connected to the transistor T_SP1 of the first sub-pixel SP1 to increase the driving range of a specific voltage supplied to the gate electrode GE.

[0131] Since the gate electrode GE, the first terminal EL1, and the second terminal EL2 are electrically connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be configured as one of the transistors in the pixel circuit PXC that constitutes the first sub-pixel SP1.

[0132] Each of the transistors T_SP2 and T_SP3 of the second sub-pixel SP2 and the third sub-pixel SP3 can be constructed to be substantially the same as the transistor T_SP1 of the first sub-pixel SP1.

[0133] As described above, the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0134] On top of the pixel circuit layer PCL, the display element layer DPL can be arranged. The display element layer DPL may include a first anode electrode AE1, a second anode electrode AE2 and a third anode electrode AE3, a pixel defining layer PDL, an emission structure EMS and a cathode electrode CE.

[0135] On the pixel circuit layer PCL (or via layer VIA), the first anode electrode AE1 to the third anode electrode AE3 can each be arranged on the first sub-pixel SP1 to the third sub-pixel SP3 (above). For example, the first anode electrode AE1 can be arranged on the via layer VIA of the first sub-pixel SP1, the second anode electrode AE2 can be arranged on the via layer VIA of the second sub-pixel SP2, and the third anode electrode AE3 can be arranged on the via layer VIA of the third sub-pixel SP3.

[0136] Each of the first anode electrodes AE1 to the third anode electrode AE3 can be electrically connected to a circuit element arranged in the pixel circuit layer PCL through a via of the via layer VIA. For example, the first anode electrode AE1 can be electrically connected to the transistor T_SP1 of the first sub-pixel SP1 through the first via VIH1 of the via layer VIA, the second anode electrode AE2 can be electrically connected to the transistor T_SP2 of the second sub-pixel SP2 through the second via VIH2 of the via layer VIA, and the third anode electrode AE3 can be electrically connected to the transistor T_SP3 of the third sub-pixel SP3 through the third via VIH3 of the via layer VIA.

[0137] In one or more embodiments, when viewed on DR3 by a third party, each of the first anode electrode AE1 to the third anode electrode AE3 may have the same characteristics as... Figure 4A The first emitting region EMA1 to the third emitting region EMA3 have similar shapes. For example, when viewed in a third-direction DR3, the first anode electrode AE1 may have a shape similar to the first emitting region EMA1, the second anode electrode AE2 may have a shape similar to the second emitting region EMA2 when viewed in a third-direction DR3, and the third anode electrode AE3 may have a shape similar to the third emitting region EMA3 when viewed in a third-direction DR3, but this disclosure is not limited thereto.

[0138] Each of the first anode electrodes AE1 to the third anode electrode AE3 can be electrically connected to the corresponding pixel circuit PXC to receive drive current. The first anode electrodes AE1 to the third anode electrode AE3 can be, but is not limited to, opaque conductive materials capable of reflecting light. According to one or more embodiments, the first anode electrodes AE1 to the third anode electrode AE3 can include transparent conductive materials.

[0139] A pixel defining layer (PDL) can be positioned on first anode electrodes AE1 to third anode electrodes AE3. The PDL may include openings OP that expose portions of the first anode electrode AE1, a portion of the second anode electrode AE2, and a portion of the third anode electrode AE3, respectively. The PDL may be a structure that defines (or divides) the emission region of each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the PDL may define a first emission region EMA1 of the first sub-pixel SP1, a second emission region EMA2 of the second sub-pixel SP2, and a third emission region EMA3 of the third sub-pixel SP3.

[0140] The pixel defining layer (PDL) can be formed from an organic insulating film comprising organic materials. Organic materials may include acrylic resins, epoxy resins, phenolic resins, polyamide resins, and / or polyimide resins. According to one or more embodiments, the pixel defining layer (PDL) may include a light-absorbing material or be treated with a light absorber to absorb light from the outside. For example, the pixel defining layer (PDL) may include a carbon-based black pigment. However, this disclosure is not limited thereto.

[0141] The pixel-limiting layer (PDL) can protrude from the via layer (VIA) on the third-direction DR3.

[0142] The emission structure EMS can be disposed on the first anode electrode AE1 to the third anode electrode AE3 exposed through the opening OP of the pixel defining layer PDL. The emission structure EMS may include, but is not limited to, a light-emitting layer configured to generate light, an electron transport unit configured to transport electrons, and a hole transport unit configured to transport holes.

[0143] The emission structure EMS fills the opening OP of the pixel-defining layer PDL and can also be disposed on top of the pixel-defining layer PDL, but this disclosure is not limited thereto. The emission structure EMS can be formed by processes such as vacuum deposition and inkjet printing.

[0144] The cathode electrode CE can be disposed on the emitting structure EMS. The cathode electrode CE can be a common layer disposed together in the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can be disposed in the form of a plate covering the entire area of ​​the display area DA. The cathode electrode CE can be used as a semi-reflective mirror that allows light emitted from the emitting structure EMS to be partially transmitted and partially reflected.

[0145] The cathode electrode CE can be a thin metal layer with a thickness sufficient to allow light emitted from the emitting structure EMS to penetrate it. The cathode electrode CE can be formed of a metallic material or a transparent conductive material to have a relatively reduced thickness. In one or more embodiments, the cathode electrode CE may include at least one of a variety of transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In one or more embodiments, the cathode electrode CE may include at least one of magnesium, silver, and mixtures thereof (e.g., any suitable mixture). However, the material of the cathode electrode CE is not limited to the embodiments described above.

[0146] The first anode electrode AE1, the portion of the emitting structure EMS superimposed on the first anode electrode AE1, and the portion of the cathode electrode CE superimposed on the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, the portion of the emitting structure EMS superimposed on the second anode electrode AE2, and the portion of the cathode electrode CE superimposed on the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, the portion of the emitting structure EMS superimposed on the third anode electrode AE3, and the portion of the cathode electrode CE superimposed on the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0147] The display element layer (DPL) may further include a capping layer (CPL) disposed on the cathode electrode (CE). The capping layer (CPL) can improve external luminous efficiency through constructive interference. The capping layer (CPL) may include organic materials, inorganic materials, or composite materials including both organic and inorganic materials. In one or more embodiments, the capping layer (CPL) may be omitted.

[0148] A thin-film encapsulation layer (TFE) can be disposed on the display element layer (DPL). The TFE can cover the display element layer (DPL). The TFE can be configured to prevent or reduce the possibility of oxygen and / or moisture penetrating into the display element layer (DPL) (e.g., protecting the display element layer (DPL) from the effects of oxygen and / or moisture). In one or more embodiments, the TFE can include a structure in which one or more inorganic films and one or more organic films are stacked alternately. For example, the inorganic films can include silicon nitride, silicon oxide, and / or silicon oxynitride. For example, the organic films can include one or more organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene oxide resins, polyphenylene sulfide resins, and benzocyclobutene. However, the materials in the organic and inorganic films of the TFE are not limited thereto.

[0149] According to one or more embodiments, the pixel PXL may further include an upper substrate disposed on the thin-film encapsulation layer TFE, and an intermediary layer CTL disposed between the thin-film encapsulation layer TFE and the upper substrate. The upper substrate may be positioned on (or bonded to) the thin-film encapsulation layer TFE by an adhesive process.

[0150] An intermediary layer CTL may be disposed and / or formed on the thin-film encapsulation layer TFE. The intermediary layer CTL may include an adhesive material to enhance the adhesion between the thin-film encapsulation layer TFE and the upper substrate. The intermediary layer CTL may also include a filler comprising an insulating material having insulating and adhesive properties. According to one or more embodiments, the intermediary layer CTL may be used as a planarization layer to mitigate steps caused by the construction of the structure located beneath it.

[0151] The upper substrate can be positioned on the intermediary layer CTL. The upper substrate may include a color filter layer CFL and a color conversion layer CCL formed by a substantially continuous process on one side of the substrate layer BSL (e.g., formed by a substantially continuous process on the side facing the thin-film encapsulation layer TFE). The upper substrate can be bonded to the thin-film encapsulation layer TFE via the intermediary layer CTL. The upper substrate may include the substrate layer BSL, the color filter layer CFL, the first insulating layer INS1, the color conversion layer CCL, and the second insulating layer INS2, sequentially stacked in a direction opposite to the third direction DR3.

[0152] The substrate layer (BSL) can be a rigid or flexible substrate, and its material or properties are not specifically limited. The substrate layer (BSL) can be formed of the same material as the substrate (SUB), or the substrate layer (BSL) can be formed of a different material than the substrate (SUB).

[0153] The color filter layer CFL can be set and / or formed on one side of the substrate layer BSL.

[0154] A color filter layer (CFL) can be configured to filter light emitted from an emission structure (EMS) and selectively output light or light of a color within a wavelength range corresponding to each sub-pixel (SP). The CFL may include color filters (CF) corresponding to first sub-pixels SP1 through SP3. For example, the CFL may include a first color filter (CF1) corresponding to the first sub-pixel SP1, a second color filter (CF2) corresponding to the second sub-pixel SP2, and a third color filter (CF3) corresponding to the third sub-pixel SP3. Each of the first color filters (CF1) through the third color filter (CF3) allows light within a wavelength range corresponding to the corresponding sub-pixel SP to pass through. For example, the first color filter (CF1) allows red light to pass through, the second color filter (CF2) allows green light to pass through, and the third color filter (CF3) allows blue light to pass through.

[0155] The first light-blocking pattern LBP1 can be positioned between adjacent color filters CF.

[0156] A first light-shielding pattern LBP1 may be positioned on one side of the substrate layer BSL to correspond to the pixel defining layer PDL. The first light-shielding pattern LBP1 may include a light-shielding material to prevent light leakage between each of the first emitting regions EMA1 to the third emitting regions EMA3 and adjacent emitting regions. In one or more embodiments, the first light-shielding pattern LBP1 may prevent or reduce the mixing of light emitted from each of the first sub-pixels SP1 to the third sub-pixels SP3 positioned adjacent to each other. According to one or more embodiments, the first light-shielding pattern LBP1 may not be provided.

[0157] A first insulating layer INS1 may be provided and / or formed on the color filter layer CFL in the direction opposite to the third-party direction DR3 (e.g., in the direction opposite to the third-party direction DR3). The first insulating layer INS1 may serve as a protective layer covering the color filter layer CFL to protect it, but this disclosure is not limited thereto. The first insulating layer INS1 may be an inorganic insulating film comprising inorganic materials or an organic insulating film comprising organic materials. According to one or more embodiments, the first insulating layer INS1 may not be provided.

[0158] A color conversion layer CCL may be disposed and / or formed on one side of the first insulating layer INS1 (e.g., the side facing the thin film encapsulation layer TFE).

[0159] The color conversion layer (CCL) may include a first color conversion pattern (CCP1), a second color conversion pattern (CCP2), a light scattering pattern (LSP), and a second light-blocking pattern (LBP2).

[0160] The first color conversion pattern CCP1 may be positioned on one side of the first insulating layer INS1 to correspond to the emission structure EMS of the first sub-pixel SP1, and may include first color conversion particles QD1 that convert light emitted from the emission structure EMS into red light. In one or more embodiments, the first color conversion pattern CCP1 may include a plurality of first color conversion particles QD1 dispersed in a set or predetermined matrix material (such as a matrix resin). The content (e.g., amount) of the first color conversion particles QD1 in the first color conversion pattern CCP1 may be approximately 10% to 60%, but this disclosure is not limited thereto.

[0161] The second color conversion pattern CCP2 may be positioned on one side of the first insulating layer INS1 to correspond to the emission structure EMS of the second sub-pixel SP2, and may include second color conversion particles QD2 that convert light emitted from the emission structure EMS into green light with excellent or suitable color reproducibility. In one or more embodiments, the second color conversion pattern CCP2 may include a plurality of second color conversion particles QD2 dispersed in a set or predetermined matrix material (such as a matrix resin). The content (e.g., amount) of the second color conversion particles QD2 in the second color conversion pattern CCP2 may be approximately 10% to 60%, but this disclosure is not limited thereto.

[0162] The light scattering pattern LSP can be positioned on one side of the first insulating layer INS1 to correspond to the emission structure EMS of the third sub-pixel SP3, and can be a transparent layer (or transparent window) that transmits light emitted from the emission structure EMS as is. The light scattering pattern LSP may include scattering particles SCT to scatter light emitted from the emission structure EMS in various directions.

[0163] The second light-shielding pattern LBP2 (or dam) can be arranged on one side of the first insulating layer INS1 to correspond to the pixel defining layer PDL (or the first light-shielding pattern LBP1). The second light-shielding pattern LBP2 can be a structure that defines the formation site of the first color conversion pattern CCP1, the formation site of the second color conversion pattern CCP2, and the formation site of the light scattering pattern LSP.

[0164] The second light-shielding pattern LBP2 may include at least one light-shielding material and / or reflective material, or the second light-shielding pattern LBP2 may include the same material as the first light-shielding pattern LBP1.

[0165] A second insulating layer INS2 may be disposed and / or formed on the side of the color conversion layer CCL opposite to the third direction DR3. In one or more embodiments, the second insulating layer INS2 may serve as a protective layer to protect the color conversion layer CCL by covering it, but this disclosure is not limited thereto. The second insulating layer INS2 may be an inorganic insulating film comprising inorganic materials or an organic insulating film comprising organic materials.

[0166] As described above, since the color conversion layer CCL and the color filter layer CFL are arranged on top of the thin film encapsulation layer TFE, the luminous efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 can be further improved by emitting light after converting the light emitted from each of the emission structures EMS of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 into light with excellent or suitable color reproducibility.

[0167] Figure 6 This illustrates one or more embodiments according to the present disclosure, including... Figure 5 A schematic cross-sectional view of the emission structure EMS in one of the first light-emitting elements LD1 to the third light-emitting element LD3.

[0168] Reference Figure 5 and Figure 6 The transmitting structure EMS can have a series structure in which a first transmitting unit EU1 and a second transmitting unit EU2 are stacked. The transmitting structure EMS can be constructed as follows: Figure 5 The first light-emitting element LD1 to the third light-emitting element LD3 are basically the same.

[0169] Each of the first emitting unit EU1 and the second emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0170] Depending on expectation and / or need, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer and / or an electron delay layer. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different structures.

[0171] Depending on expectation and / or need, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer and / or a hole delay layer. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same structure or different structures from each other.

[0172] An intermediate layer (or connecting layer), which can be configured in the form of a charge generation layer CGL, can be arranged between the first emitter unit EU1 and the second emitter unit EU2 to connect the first emitter unit EU1 and the second emitter unit EU2 to each other. Hereinafter, the charge generation layer CGL is referred to as the intermediate layer. In one or more embodiments, the intermediate layer CGL can have a stacked structure of p-doped layers and n-doped layers. For example, the p-doped layer can include p-type (or p-like) dopants such as hexaazatriphenylhexanitrile (HAT-CN), tetracyanoquinone dimethyl ether (TCNQ), and / or 2-(7-dicyanomethylene-1,3,4,5,6,8,9,10-octafluoro-7H-pyrene-2-ylidene)-malonadionitrile (NDP-9), and the n-doped layer can include alkali metals, alkaline earth metals, lanthanides, and / or combinations thereof (e.g., any suitable combination). However, the structure (or material) of the intermediate layer CGL is not limited to the embodiments described above. In one or more embodiments, the intermediate layer CGL is capable of being conductive by comprising a material having relatively high charge conductivity (or charge mobility) compared to the first emitter unit EU1 and the second emitter unit EU2 of the emitter structure EMS.

[0173] In one or more embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of different colors, but are not limited thereto. According to one or more embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color.

[0174] In one or more embodiments described above, the transmitting structure EMS is described as a series structure in which a first transmitting unit EU1 and a second transmitting unit EU2 are stacked, but this disclosure is not limited thereto. According to one or more embodiments, the transmitting structure EMS can be configured as a series structure in which three transmitting units are stacked.

[0175] Figure 7This illustrates one or more embodiments according to the present disclosure. Figure 1 A schematic plan view of the display area DA. Figure 8 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view taken from line II-II'. Figure 9 According to one or more embodiments of this disclosure Figure 8 An enlarged schematic cross-sectional view of region EA, and Figure 10 This illustrates one or more embodiments according to the present disclosure. Figure 7 A schematic perspective view of the via layer (VIA) and pixel-defining layer (PDL). Figure 8 For the sake of clarity and brevity, no references are provided. Figure 5 The description of the upper base.

[0176] exist Figures 7 to 10 In order to avoid repetition, embodiments will be described based on differences from one or more embodiments described above.

[0177] Reference Figure 1 and Figures 7 to 10 The display area DA can be divided into pixel rows R1 and R2. Pixel rows R1 and R2 can be arranged in a second direction DR2 by extending along a first direction DR1.

[0178] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged in the display area DA. The second sub-pixel SP2 can be positioned in the first column and the second column of the first pixel row R1 (positioned throughout the first column and the second column of the first pixel row R1), the first sub-pixel SP1 can be positioned in the first column of the second pixel row R2, and the third sub-pixel SP3 can be positioned in the second column of the second pixel row R2.

[0179] The first sub-pixel SP1 may include a first emitting region EMA1, the second sub-pixel SP2 may include a second emitting region EMA2, and the third sub-pixel SP3 may include a third emitting region EMA3. A non-emitting region NEA may be disposed around the first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3. A pixel definition layer PDL may be disposed within the non-emitting region NEA. The first sub-pixel SP1 may emit light of a first color, the second sub-pixel SP2 may emit light of a second color, and the third sub-pixel SP3 may emit light of a third color. The first color of light may be red, the second color of light may be green, and the third color of light may be blue, but this disclosure is not limited thereto.

[0180] First sub-pixels SP1 and third sub-pixels SP3 can be arranged on a first direction DR1. For each of the first sub-pixels SP1 and third sub-pixels SP3, a second sub-pixel SP2 can be arranged in the opposite direction to the second direction DR2 (e.g., the opposite direction of the second direction DR2). The first sub-pixel SP1 can have an area larger than the third sub-pixel SP3, and the second sub-pixel SP2 can have an area larger than the first sub-pixel SP1. Therefore, the first emission region EMA1 can have an area larger than the third emission region EMA3, and the second emission region EMA2 can have an area larger than the first emission region EMA1.

[0181] In one or more embodiments, each of the first sub-pixel SP1 to the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE.

[0182] In one or more embodiments, the via layer VIA included in the pixel circuit layer PCL may include a recessed pattern RP in a region of the non-emitting region NEA. The recessed pattern RP may be formed by the via layer VIA recessed on a third-direction DR3 in a direction facing (e.g., toward) the substrate SUB. For example, the recessed pattern RP may be a stepped region from one side of the via layer VIA (e.g., the upper surface of the via layer VIA) toward the substrate SUB. The via layer VIA including the recessed pattern RP may have a smaller thickness than a via layer VIA without the recessed pattern RP. In one or more embodiments, the via layer VIA may be an organic film comprising an organic material.

[0183] The recessed pattern RP of the via layer VIA can be located in a region of the non-emitting region NEA (e.g., located in the non-emitting region NEA between adjacent sub-pixels). The recessed pattern RP can include a first recessed pattern RP1 and a second recessed pattern RP2. The first recessed pattern RP1 and the second recessed pattern RP2 can extend in different directions from each other in a planar view. For example, the first recessed pattern RP1 can extend in a second direction DR2, and the second recessed pattern RP2 can extend in a first direction DR1.

[0184] Multiple first recessed patterns RP1 can be provided. For example, the first recessed pattern RP1 can extend in the second direction DR2 in the plan view and include multiple first recessed patterns RP1 arranged along the first direction DR1 intersecting the second direction DR2.

[0185] Multiple second recessed patterns RP2 can be provided. For example, the second recessed patterns RP2 can extend in the first direction DR1 in the plan view and include multiple second recessed patterns RP2 arranged along the second direction DR2 intersecting the first direction DR1.

[0186] A first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 may be disposed on a via layer VIA including a recessed pattern RP. The first anode electrode AE1 to the third anode electrode AE3 may be arranged spaced apart from each other and / or separated (e.g., spaced apart or separated). The first anode electrode AE1 to the third anode electrode AE3 may be disposed on the top surface of the via layer VIA so as not to overlap with the recessed pattern RP of the via layer VIA.

[0187] The via layer VIA can be disposed in the non-emitting region NEA, and the pixel defining layer PDL can be disposed on the first anode electrode AE1 to the third anode electrode AE3. The pixel defining layer PDL may include multiple openings (including, for example, referenced) Figure 5 (The described opening OP). For example, the pixel defining layer PDL may include a first opening OP1, a second opening OP2, a third opening OP3, a fourth opening OP4, and a fifth opening OP5. In one or more embodiments, the pixel defining layer PDL may be an organic film comprising organic materials.

[0188] The first opening OP1 can be a light-emitting opening defining a first emitting region EMA1, the second opening OP2 can be a light-emitting opening defining a second emitting region EMA2, and the third opening OP3 can be a light-emitting opening defining a third emitting region EMA3. The first opening OP1 of the pixel-defining layer PDL can expose a portion of the first anode electrode AE1, the second opening OP2 of the pixel-defining layer PDL can expose a portion of the second anode electrode AE2, and the third opening OP3 of the pixel-defining layer PDL can expose a portion of the third anode electrode AE3.

[0189] The fourth opening OP4 and the fifth opening OP5 can be dummy openings (DOPs) located in the non-emitting region (NEA). The dummy openings (DOPs) can include a first dummy opening (DOP1) and a second dummy opening (DOP2). The fourth opening OP4 and the fifth opening OP5 can be superimposed on the recessed patterns RP1 and RP2 of the via layer (VIA), respectively. The fourth opening OP4 and the fifth opening OP5 can be arranged to be spaced apart and / or separated (e.g., spaced apart or separated).

[0190] The fourth opening OP4 (or the first dummy opening DOP1) can be located in the non-emitting region NEA between the second sub-pixel SP2 and the first sub-pixel SP1, and in the non-emitting region NEA between the second sub-pixel SP2 and the third sub-pixel SP3. The fourth opening OP4 can extend in the first direction DR1 in the non-emitting region NEA between the second sub-pixel SP2 and the first sub-pixel SP1, and in the non-emitting region NEA between the second sub-pixel SP2 and the third sub-pixel SP3.

[0191] The fifth opening OP5 (or the second dummy opening DOP2) can be located in the non-emitting region NEA between the first sub-pixel SP1 and the third sub-pixel SP3. The fifth opening OP5 can extend in the non-emitting region NEA between the first sub-pixel SP1 and the third sub-pixel SP3 along the second direction DR2, which intersects with the first direction DR1. The fourth opening OP4 and the fifth opening OP5 can each extend in different directions.

[0192] In a planar view, the recessed pattern RP of the via layer VIA and the dummy opening DOP of the pixel limiting layer PDL can intersect (overlay). For example, the first recessed pattern RP1 of the via layer VIA and the fourth opening OP4 (or the first dummy opening DOP1) of the pixel limiting layer PDL can intersect (overlay) each other, and the second recessed pattern RP2 of the via layer VIA and the fifth opening OP5 (or the second dummy opening DOP2) of the pixel limiting layer PDL can intersect (overlay) each other. The fourth opening OP4 can intersect (overlay) with multiple first recessed patterns RP1, and the fifth opening OP5 can intersect (overlay) with multiple second recessed patterns RP2.

[0193] The two ends ED1 of the pixel defining layer PDL (e.g., the first ends ED1 of the pixel defining layer PDL on opposite sides) can be disposed on the first recessed pattern RP1 of the via layer VIA, and the fourth opening OP4 (or the first dummy opening DOP1) of the pixel defining layer PDL is located between the ends ED1 (e.g., the first ends ED1 of the pixel defining layer PDL on opposite sides can define the fourth opening OP4 (or the first dummy opening DOP1) of the pixel defining layer PDL). For example, the two ends ED1 of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can be disposed on a plurality of first recessed patterns RP1, and the fourth opening OP4 of the pixel defining layer PDL is located between the ends ED1 (e.g., defining the fourth opening OP4). The two ends ED1 of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can contact a portion of the first recessed pattern RP1 of the via layer VIA. The ends ED1 on both sides of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can contact the first recessed pattern RP1 of the via layer VIA to construct a first trench TRCH1 in the non-emitting region NEA, and a fourth opening OP4 is positioned between the ends ED1 (e.g., defining the fourth opening OP4). At this time, the boundary point BD between the upper surface of the via layer VIA and the first recessed pattern RP1 (see, for example, Figure 9The pixel-defining layer (PDL) can be covered. For example, the ends ED1 on both sides of the pixel-defining layer (PDL) (e.g., the first ends ED1 on opposite sides of the pixel-defining layer (PDL)) can be arranged in the first recessed pattern RP1 of the via layer (VIA), and the fourth opening OP4 is placed between the ends ED1. This configuration can define the first trench TRCH1 in the non-emitting region (NEA), and the boundary point BD between the upper surface of the via layer (VIA) and the first recessed pattern RP1 is covered by the pixel-defining layer (PDL).

[0194] The ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can be disposed on the second recessed pattern RP2 of the via layer VIA, and the fifth opening OP5 (or the second dummy opening DOP2) of the pixel defining layer PDL is located between the ends ED2 (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL can define the fifth opening OP5 (or the second dummy opening DOP2) of the pixel defining layer PDL). For example, the ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can be disposed on a plurality of second recessed patterns RP2, and the fifth opening OP5 of the pixel defining layer PDL is located between the ends ED2 (e.g., defining the fifth opening OP5). The ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can contact a portion of the second recessed pattern RP2 of the via layer VIA. The ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can contact the second recessed pattern RP2 of the via layer VIA to construct a second trench TRCH2 in the non-emitting region NEA, and a fifth opening OP5 is positioned between the ends ED2 (e.g., defining the fifth opening OP5). At this time, the boundary point BD between the upper surface of the via layer VIA and the second recessed pattern RP2 (see, for example, Figure 9 The pixel-defining layer (PDL) can be covered. For example, the ends ED2 on both sides of the pixel-defining layer (PDL) (e.g., the second ends ED2 on opposite sides of the pixel-defining layer (PDL)) can be arranged in the second recessed pattern RP2 of the via layer (VIA), and the fifth opening OP5 is located between the ends ED2. This configuration can define the second trench TRCH2 in the non-emitting region (NEA), and the boundary point BD between the upper surface of the via layer (VIA) and the second recessed pattern RP2 is covered by the pixel-defining layer (PDL).

[0195] The first trench TRCH1 can be formed in the region where the fourth opening OP4 of the pixel-defining layer PDL and the first recessed pattern RP1 of the via layer VIA intersect (overlap) in the non-emitting region NEA. The second trench TRCH2 can be formed in the region where the fifth opening OP5 of the pixel-defining layer PDL and the second recessed pattern RP2 of the via layer VIA intersect (overlap) in the non-emitting region NEA.

[0196] The emission structure EMS can be disposed on the first anode electrode AE1 to the third anode electrode AE3 and the pixel defining layer PDL. The emission structure EMS may include a first emission unit EU1 and a second emission unit EU2. The emission structure EMS may also include an intermediate layer CGL disposed between the first emission unit EU1 and the second emission unit EU2. In one or more embodiments, each of the first emission unit EU1 and the second emission unit EU2 may include a light-emitting layer that generates light according to an applied current. The first emission unit EU1 may be associated with a reference... Figure 6 The first transmitting unit EU1 described is identical, and the second transmitting unit EU2 may be identical to the reference unit. Figure 6 The second launch unit EU2 described is the same.

[0197] Both the first emitting unit EU1 and the second emitting unit EU2 may include a charge transport unit, a light-emitting layer, an electron transport unit, and a buffer layer comprising a material having a relatively low charge conductivity (or charge mobility) compared to the intermediate layer CGL. In one or more embodiments, the first emitting unit EU1 and the second emitting unit EU2 may include a material having relatively high insulating properties compared to the intermediate layer CGL. In such embodiments, even if the first emitting unit EU1 and the second emitting unit EU2 are connected to each other at the first trench TRCH1 and the second trench TRCH2 (above), no current can be transmitted to adjacent sub-pixels.

[0198] The first emission unit EU1 can be arranged on the pixel defining layer PDL and the anode electrode in the non-emission region NEA of adjacent sub-pixels. In the non-emission region NEA, the first emission unit EU1 can include a break (or opening) separated from each other at a first trench TRCH1 and a second trench TRCH2 located in the boundary region between adjacent sub-pixels. The break can be defined by portions in the first trench TRCH1 and the second trench TRCH2 where the first emission unit EU1 is broken (and / or discontinuously formed). In such embodiments, the first emission units EU1 of adjacent sub-pixels can be separated from each other. For example, as... Figure 8As shown, the first emission unit EU1 at the second sub-pixel SP2 can be separated from the first emission unit EU1 at the first sub-pixel SP1, and the first emission unit EU1 at the first sub-pixel SP1 can be separated from the first emission unit EU1 at the third sub-pixel SP3.

[0199] The intermediate layer CGL can be disposed on the first transmitting unit EU1. The intermediate layer CGL may include disconnected portions separated at the first trench TRCH1 and the second trench TRCH2, respectively. For example, as Figure 8 As shown, the intermediate layer CGL at the second sub-pixel SP2 can be separated from the intermediate layer CGL at the first sub-pixel SP1, and the intermediate layer CGL at the first sub-pixel SP1 can be separated from the intermediate layer CGL at the third sub-pixel SP3.

[0200] The second emission unit EU2 can be arranged on the intermediate layer CGL. The second emission unit EU2 can be formed on the intermediate layer CGL to have a relatively high thickness. Therefore, the second emission unit EU2 does not need to be interrupted in the non-emission region NEA (i.e., the boundary region between adjacent sub-pixels). For example, as... Figure 8 As shown, the second emission unit EU2 at the second sub-pixel SP2, the second emission unit EU2 at the first sub-pixel SP1, and the second emission unit EU2 at the third sub-pixel SP3 can be connected to each other. According to one or more embodiments, at least a portion of the second emission unit EU2 at one of two adjacent sub-pixels and at least a portion of the second emission unit EU2 at the other adjacent sub-pixel can be disconnected in the first trench TRCH1 and / or the second trench TRCH2. For example, the lower surface of the second emission unit EU2 at an adjacent sub-pixel (e.g., the side contacting the intermediate layer CGL) can be disconnected in the first trench TRCH1 and the second trench TRCH2, respectively, and the upper surface of the second emission unit EU2 on the third-direction DR3 facing the lower surface (e.g., opposite to the lower surface) (e.g., the side contacting the cathode electrode CE) can be connected to each other. Therefore, the second emission unit EU2 may not be disconnected in the first trench TRCH1 and the second trench TRCH2.

[0201] A cathode electrode CE can be disposed on a second emitting unit EU2. The cathode electrode CE can be formed of a metal comprising a conductive material. The second emitting unit EU2, disposed at the bottom of the cathode electrode CE, can be formed to have a relatively larger thickness than the first emitting unit EU1. The thickness of the second emitting unit EU2 can be the gap between the intermediate layer CGL and the cathode electrode CE. For example, the thickness of the second emitting unit EU2 corresponding to the gap between the intermediate layer CGL and the cathode electrode CE can be greater than the thickness of the first emitting unit EU1. This is to prevent or reduce defects caused by short circuits with the conductive intermediate layer CGL due to the cathode electrode CE comprising a material with high charge conductivity (or charge mobility), while preventing or reducing the possibility of the cathode electrode CE disconnecting due to steps of components located below it (e.g., the intermediate layer CGL and the first emitting unit EU1). Due to the large thickness of the second emitting unit EU2, the gap between the cathode electrode CE and the intermediate layer CGL can be further ensured, thereby preventing or reducing defects caused by short circuits between the cathode electrode CE and the intermediate layer CGL. In one or more embodiments, due to the second emitting unit EU2, the steps of the components positioned at the bottom are flattened, thereby improving the step coverage of the cathode electrode CE disposed on the second emitting unit EU2, thus preventing or reducing the possibility of the cathode electrode CE failing due to being cut off at the first trench TRCH1 and the second trench TRCH2 (e.g., disconnected at the first trench TRCH1 and the second trench TRCH2). For example, the cathode electrode CE may be disposed on the second emitting unit EU2 having a greater thickness than the first emitting unit EU1. This thickness, corresponding to the gap between the intermediate layer CGL and the cathode electrode CE, helps prevent defects caused by short circuits with the conductive intermediate layer CGL. The increased thickness of the second emitting unit EU2 ensures the gap, reduces the possibility of short circuits, and improves the step coverage of the cathode electrode CE, thereby preventing or reducing the possibility of disconnection at the first trench TRCH1 and the second trench TRCH2.

[0202] In one or more embodiments, a first gap VD1 may be formed in a first trench TRCH1, and a second gap VD2 may be formed in a second trench TRCH2. The first gap VD1 may be formed by some construction of a disconnected emitter structure EMS in the first trench TRCH1 and the remaining connected portions of the emitter structure EMS. The second gap VD2 may be formed by some construction of a disconnected emitter structure EMS in the second trench TRCH2 and the remaining connected portions of the emitter structure EMS. For example, the first gap VD1 may be surrounded by a first recessed pattern RP1 of the via layer VIA, end points ED1 on both sides of the pixel defining layer PDL that place the fourth opening OP4 (or the first dummy opening DOP1) therebetween (e.g., the first end point ED1 on the opposite side of the pixel defining layer PDL), a first emitter unit EU1, an intermediate layer CGL, and a second emitter unit EU2. The second gap VD2 can be surrounded by the second recessed pattern RP2 of the via layer VIA, the ends ED2 of the pixel limiting layer PDL on both sides where the fifth opening OP5 (or the second dummy opening DOP2) is placed (e.g., the second end ED2 on the opposite side of the pixel limiting layer PDL), the first emission unit EU1, the intermediate layer CGL and the second emission unit EU2.

[0203] According to one or more embodiments described above, in the non-emissive region NEA between the second sub-pixel SP2 and the first sub-pixel SP1, and in the non-emissive region NEA between the second sub-pixel SP2 and the third sub-pixel SP3, because the first recessed pattern RP1 of the via layer VIA and the fourth opening OP4 (or the first dummy opening DOP1) of the pixel defining layer PDL intersect (overlap), the ends ED1 on both sides of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can be positioned on the first recessed pattern RP1, and the fourth opening OP4 is placed between the ends ED1. In one or more embodiments, the first recessed pattern RP1 is recessed in the direction from the upper surface of the via layer VIA toward the substrate SUB to have a recessed shape, and the ends ED1 on both sides of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can be arranged on the first recessed pattern RP1 to have a raised shape. Therefore, the step inflection point can occur at the contact point between the first recessed pattern RP1 and the ends ED1 on both sides of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL). Due to the step inflection point, the inclination of the two sides of the pixel defining layer PDL that place the fourth opening OP4 therebetween (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can be increased. In other words, the first ends ED1 on opposite sides of the pixel defining layer PDL that define the fourth opening OP4 can have an increased angle relative to the substrate SUB. If the tilt angle of the two sides of the pixel-defining layer PDL where the fourth opening OP4 is located (e.g., at the first end ED1 on the opposite side of the pixel-defining layer PDL) increases (e.g., when the tilt angle of the two sides of the pixel-defining layer PDL where the fourth opening OP4 is located (e.g., at the first end ED1 on the opposite side of the pixel-defining layer PDL) increases), some structures (e.g., layers) of the emission structure EMS arranged on the pixel-defining layer PDL (e.g., electrical connections of the intermediate layer CGL) can be easily disrupted (e.g., disconnected), causing the intermediate layer CGL to have a high-resistance structure between adjacent sub-pixels. Therefore, in operating the display device (see, for example, Figure 1When “DD” is used, the current flowing out to neighboring sub-pixels through the layers included in the emission structure EMS can be reduced for each of the first sub-pixels SP1 to the third sub-pixel SP3. For example, in the non-emission region NEA between the second sub-pixel SP2 and the first sub-pixel SP1, and between the second sub-pixel SP2 and the third sub-pixel SP3, the ends ED1 on both sides of the pixel defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel defining layer PDL) can be positioned on the first recessed pattern RP1 of the via layer VIA, and the fourth opening OP4 is placed between the ends ED1. This arrangement can create step inflection points, increasing the tilt of the pixel defining layer PDL. Therefore, the electrical connection of the intermediate layer CGL can be easily disrupted, resulting in a high-resistivity structure between adjacent sub-pixels and reducing the current outflow from each sub-pixel.

[0204] In one or more embodiments, according to one or more embodiments described above, because the second recessed pattern RP2 of the via layer VIA and the fifth opening OP5 (or second dummy opening DOP2) of the pixel defining layer PDL intersect (overlap) in the non-emitting region NEA between the first sub-pixel SP1 and the third sub-pixel SP3, the ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can be positioned on the second recessed pattern RP2, and the fifth opening OP5 is disposed between the ends ED2. In one or more embodiments, the second recessed pattern RP2 is recessed in the direction from the upper surface of the via layer VIA to the substrate SUB to have a recessed shape, and the ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) are arranged on the second recessed pattern RP2 to have a raised shape. Therefore, the step inflection point can occur at the contact point between the second recessed pattern RP2 and the ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL). Due to the step inflection point, the inclination of the two sides of the pixel defining layer PDL that place the fifth opening OP5 therebetween (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can be increased. In other words, the second ends ED2 on opposite sides of the pixel defining layer PDL that define the fifth opening OP5 can have an increased angle relative to the substrate SUB. If the tilt angle of the two sides of the pixel-defining layer PDL where the fifth opening OP5 is located (e.g., at the second end ED2 on the opposite side of the pixel-defining layer PDL) increases (e.g., when the tilt angle of the two sides of the pixel-defining layer PDL where the fifth opening OP5 is located (e.g., at the second end ED2 on the opposite side of the pixel-defining layer PDL) increases), some structures (e.g., layers) of the emission structure EMS arranged on the pixel-defining layer PDL (e.g., electrical connections of the intermediate layer CGL) can be easily cut off (e.g., destroyed or disconnected), so that the intermediate layer CGL can have a high-resistance structure between adjacent sub-pixels. Therefore, during DD operation of the display device, the current flowing out to the adjacent sub-pixel through the layers included in the emission structure EMS from each of the first sub-pixel SP1 to the third sub-pixel SP3 can be reduced. For example, in the non-emitting region NEA between the first sub-pixel SP1 and the third sub-pixel SP3, the ends ED2 on both sides of the pixel defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel defining layer PDL) can be positioned on the second recessed pattern RP2 of the via layer VIA, and the fifth opening OP5 is placed between the second ends ED2. This arrangement can create a step inflection point, increasing the tilt of the pixel defining layer PDL.Therefore, the electrical connections of the intermediate CGL layer can be easily disrupted, resulting in a high-resistivity structure between adjacent sub-pixels and reducing the current outflow from each sub-pixel.

[0205] Figures 11 to 15 Is with Figure 7 Line II-II' corresponds to a schematic cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0206] exist Figure 7 and Figures 11 to 15 For ease of explanation, redundant descriptions of one or more of the above embodiments may be omitted.

[0207] Reference Figure 7 and Figure 11 A via layer (VIA) is formed on the interlayer insulating layer (ILD). For example, a via layer (VIA) is formed on top of the interlayer insulating layer (ILD) of an adjacent sub-pixel.

[0208] A via layer (VIA) is formed on an interlayer insulating layer (ILD) using a photolithography process with a mask. For example, a substrate material for the via layer (VIA) is coated onto the ILD, exposed using a mask, and then developed to form the via layer (VIA). During the exposure process, the amount of light is adjusted to form a first recessed pattern RP1 and a second recessed pattern RP2.

[0209] In the plan view, the first recessed pattern RP1 can extend in the second direction DR2, and the second recessed pattern RP2 can extend in the first direction DR1. Multiple first recessed patterns RP1 and multiple second recessed patterns RP2 can be provided.

[0210] Reference Figure 7 and Figure 12 A first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 are formed on the via layer VIA. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be arranged to be spaced apart from each other (e.g., spaced apart or separated) on the upper surface of the via layer VIA.

[0211] Reference Figure 7 and Figure 13 A pixel defining layer (PDL) is formed on the first anode electrode AE1 to the third anode electrode AE3 and the via layer VIA. For example, the pixel defining layer (PDL) can be formed on the first anode electrode AE1, the second anode electrode AE2, the third anode electrode AE3 and the via layer VIA.

[0212] The pixel definition layer (PDL) may include light-emitting apertures and dummy apertures (DOPs). For example, the light-emitting apertures may include a first aperture OP1 forming a first emission region EMA1 of a first sub-pixel SP1, a second aperture OP2 forming a second emission region EMA2 of a second sub-pixel SP2, and a third aperture OP3 forming a third emission region EMA3 of a third sub-pixel SP3. The dummy apertures (DOPs) may include a fourth aperture OP4 (or a first dummy aperture DOP1) and a fifth aperture OP5 (or a second dummy aperture DOP2) located in the area surrounding (between) the first emission region EMA1 and the third emission region EMA3 outside the emission region NEA.

[0213] The first opening OP1 can expose a portion of the first anode electrode AE1, the second opening OP2 can expose a portion of the second anode electrode AE2, and the third opening OP3 can expose a portion of the third anode electrode AE3. The fourth opening OP4 can be superimposed with the first recessed pattern RP1 of the via layer VIA, and the fifth opening OP5 can be superimposed with the second recessed pattern RP2 of the via layer VIA.

[0214] In the plan view, the fourth opening OP4 may extend in the first direction DR1 and intersect (overlay) with a plurality of first recessed patterns RP1. In the region between adjacent sub-pixels of the non-emitting region NEA, the first trench TRCH1 may be formed as the fourth opening OP4 of the pixel defining layer PDL, and each of the first recessed patterns RP1 of the via layer VIA may intersect (overlay) with the fourth opening OP4 (e.g., the first trench TRCH1).

[0215] In the plan view, the fifth opening OP5 may extend in the second direction DR2 and intersect (overlay) with a plurality of second recessed patterns RP2. In the region between adjacent sub-pixels of the non-emitting region NEA, the second trench TRCH2 may be formed as the fifth opening OP5 of the pixel defining layer PDL, and each of the second recessed patterns RP2 of the via layer VIA may intersect (overlay) with the fifth opening OP5 (e.g., the second trench TRCH2).

[0216] The two ends ED1 of the pixel-defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel-defining layer PDL) can contact the first recessed pattern RP1, and the fourth opening OP4 is located between the ends ED1. The two ends ED2 of the pixel-defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel-defining layer PDL) can contact the second recessed pattern RP2, and the fifth opening OP5 is located between the ends ED2. A step inflection point may appear at the contact point between each of the first recessed pattern RP1 and the two ends ED1 of the pixel-defining layer PDL (e.g., the first ends ED1 on opposite sides of the pixel-defining layer PDL). A step inflection point may appear at the contact point between each of the second recessed pattern RP2 and the two ends ED2 of the pixel-defining layer PDL (e.g., the second ends ED2 on opposite sides of the pixel-defining layer PDL). Due to the step inflection point, the tilt (angle) of the pixel-defining layer PDL between the two sides (e.g., the first ends ED1 and the second ends ED2) where the fourth opening OP4 and the fifth opening OP5 are located can be increased.

[0217] Reference Figure 7 and Figure 14 An emission structure EMS is formed on the pixel-defined layer (PDL). For example, the emission structure EMS may include a first emission unit EU1, an intermediate layer CGL, and a second emission unit EU2 sequentially stacked on a third-direction DR3. Each of the first emission unit EU1 and the intermediate layer CGL may have a break in a first trench TRCH1 and a second trench TRCH2. The second emission unit EU2 may not be broken in the first trench TRCH1 and the second trench TRCH2.

[0218] Reference Figure 7 and Figure 15 A cathode electrode CE is formed on the emission structure EMS. For example, the cathode electrode CE can be a common layer shared by adjacent sub-pixels (e.g., first sub-pixels SP1 to third sub-pixels SP3).

[0219] Subsequently, it can be formed sequentially. Figure 8 The remaining structures shown (e.g., the cover layer CPL and the thin film encapsulation layer TFE).

[0220] Figures 16 to 18 Each is a schematic plan view illustrating a region of the display area DA of a display device according to one or more embodiments of the present disclosure.

[0221] exist Figures 16 to 18 In order to avoid repetition, embodiments will be described based on differences from one or more embodiments described above.

[0222] Reference Figure 16The via layer VIA may include a first recessed pattern RP1 and a second recessed pattern RP2 located in a non-emitting region NEA between adjacent sub-pixels. The pixel defining layer PDL may be located in the non-emitting region NEA to define a first emitting region EMA1 to a third emitting region EMA3.

[0223] The pixel-defined layer (PDL) may include a fourth opening OP4 (or a first dummy opening DOP1) and a fifth opening OP5 (or a second dummy opening DOP2) located in a non-emitting region (NEA) between adjacent subpixels. The fourth opening OP4 may extend in a first direction DR1 and intersect (overlay) with a first recessed pattern RP1 of the via layer (VIA). The fifth opening OP5 may extend in a second direction DR2 and intersect (overlay) with a second recessed pattern RP2 of the via layer (VIA). In one or more embodiments, the fourth opening OP4 and the fifth opening OP5 may be connected to form a "T" shape in a planar view.

[0224] Reference Figure 17 The pixel-defined layer (PDL) may include a first dummy opening DOP1 (or a fourth opening OP4) and a second dummy opening DOP2 (or a fifth opening OP5) located in the region between adjacent sub-pixels of the non-emitting region NEA. The first dummy opening DOP1 and the second dummy opening DOP2 may each extend in different directions.

[0225] In one or more embodiments, the first dummy opening DOP1 may include 1-1 sub-dummy opening OP4_1, 1-2 sub-dummy opening OP4_2, and 1-3 sub-dummy opening OP4_3. The 1-1 sub-dummy opening OP4_1, 1-2 sub-dummy opening OP4_2, and 1-3 sub-dummy opening OP4_3 are spaced apart and / or separated from each other (e.g., spaced apart or separated) and extend in the first direction DR1. The 1-1 sub-dummy opening OP4_1 may intersect (overlay) with a first recessed pattern RP1 of the via layer VIA. Each of the 1-2 sub-dummy openings OP4_2 and 1-3 sub-dummy openings OP4_3 may intersect (overlay) with a plurality of first recessed patterns RP1 of the via layer VIA.

[0226] Reference Figure 18 The via layer VIA may include a first recessed pattern RP1 and a second recessed pattern RP2 located in the region between adjacent sub-pixels of the non-emitting region NEA.

[0227] The first recessed pattern RP1 of the via layer VIA can extend in the second direction DR2, and multiple first recessed patterns RP1 can be provided. Each of the multiple first recessed patterns RP1 can intersect (overlay) with the corresponding sub-dummy openings in the 1-1 sub-dummy openings OP4_1 to 1-3 sub-dummy openings OP4_3 of the pixel definition layer PDL. The second recessed pattern RP2 of the via layer VIA can extend in the second direction DR2 and is provided in a straight line between the first emission region EMA1 and the third emission region EMA3 (or provided in the region between the first sub-pixel SP1 and the third sub-pixel SP3 in the non-emission region NEA).

[0228] The pixel-defined layer (PDL) may include a second dummy opening (DOP2) (or a fifth opening (OP5)) located in the region between the first sub-pixel SP1 and the third sub-pixel SP3 in the non-emitting region (NEA). The second dummy opening (DOP2) may include a plurality of second sub-dummy openings extending along the first direction DR1. For example, the second dummy opening (DOP2) may extend along the first direction DR1 and include sub-dummy openings OP5_1 (2-1), OP5_2 (2-2), OP5_3 (2-3), and OP5_4 (2-4) arranged along the second direction DR2.

[0229] Sub-dummy openings OP5_1 (2-1), OP5_2 (2-2), OP5_3 (2-3), and OP5_4 (2-4) can intersect (overlay) with the second recessed pattern RP2 of the via layer VIA, which is arranged in a straight line. Sub-dummy openings OP5_1 (2-1), OP5_2 (2-2), OP5_3 (2-3), and OP5_4 (2-4) can extend in substantially the same direction as the first dummy opening DOP1.

[0230] Figure 19 This is a schematic plan view showing the display area DA of a display device according to one or more embodiments of the present disclosure.

[0231] exist Figure 19 In order to avoid repetition, embodiments will be described based on differences from one or more of the above embodiments.

[0232] Reference Figure 19 The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, arranged along the first direction DR1, can be arranged in the display area DA. The first sub-pixel SP1 to the third sub-pixel SP3 can be positioned in substantially the same pixel row.

[0233] In the non-emitting region NEA, in the area between adjacent sub-pixels, the recessed pattern RP of the via layer VIA can be located. For example, the recessed pattern RP of the via layer VIA can be located in the area of ​​the non-emitting region NEA between the first sub-pixel SP1 and the second sub-pixel SP2, and in the area of ​​the non-emitting region NEA between the second sub-pixel SP2 and the third sub-pixel SP3.

[0234] The pixel-defining layer (PDL) can be set in the non-emitting region (NEA) between adjacent sub-pixels. The PDL may include a first opening OP1 corresponding to the first emitting region EMA, a second opening OP2 corresponding to the second emitting region EMA2, and a third opening OP3 corresponding to the third emitting region EMA3.

[0235] The pixel-defining layer (PDL) may include dummy openings (DOPs) located in the region between adjacent sub-pixels of the non-emitting region (NEA). For example, the PDL may include a first dummy opening (DOP1) (or a fourth opening (OP4) located in the region between a first sub-pixel SP1 and a second sub-pixel SP2 in the non-emitting region (NEA), and a second dummy opening (DOP2) (or a fifth opening (OP5)) located in the region between a second sub-pixel SP2 and a third sub-pixel SP3 in the non-emitting region (NEA). Each of the first dummy opening (DOP1) and the second dummy opening (DOP2) may expose a portion of the via layer (VIA).

[0236] In one or more embodiments, the first dummy opening DOP1 and the second dummy opening DOP2 may extend in the second direction DR2 in the plan view. Each of the first dummy opening DOP1 and the second dummy opening DOP2 may intersect (overlay) the recessed pattern RP of the via layer VIA. In such an embodiment, the two sides of the pixel defining layer PDL that place the first dummy opening DOP1 therebetween (e.g., the first end ED1 on the opposite side of the pixel defining layer PDL) and the two sides of the pixel defining layer PDL that place the second dummy opening DOP2 therebetween (e.g., the second end ED2 on the opposite side of the pixel defining layer PDL) may be arranged on the corresponding recessed pattern RP to contact the recessed pattern RP. Therefore, a step inflection point can appear at the contact point between the recessed pattern RP and the ends on both sides of the pixel defining layer PDL (e.g., the first end ED1 and the second end ED2 on opposite sides of the pixel defining layer PDL), causing an increase in the tilt (angle) of the two sides of the pixel defining layer PDL where the dummy opening DOP is located (e.g., the first end ED1 and the second end ED2 on opposite sides of the pixel defining layer PDL). For example, the first dummy opening DOP1 and the second dummy opening DOP2 can extend in the second direction DR2 and intersect (overlay) with the recessed pattern RP of the via layer VIA. In such an embodiment, the ends ED1 and ED2 on both sides of the pixel defining layer PDL can be arranged on the corresponding recessed pattern RP, and the dummy openings DOP1 and DOP2 are located between the ends ED1 and ED2, respectively. This arrangement can create a step inflection point, increasing the tilt of the pixel defining layer PDL.

[0237] The display device according to the embodiments is applicable to various types of electronic devices. In the embodiments, the electronic device includes the display device described above, and in addition to the display device, it also includes other modules or devices with additional functions.

[0238] Figure 20 This is a block diagram of the electronic device 10 according to an embodiment. (Refer to...) Figure 20 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0239] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0240] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0241] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power module and generates power to operate the electronic device 10.

[0242] At least one of the components described above for electronic device 10 may be included in the display device according to the embodiments described above. Additionally, in terms of function, some of the various modules included in a single module may be included in the display device, and other modules may be disposed separately from the display device. For example, display module 11 may be included in the display device, while processor 12, memory 13, and power module 14 may not be included in the display device but may be disposed separately in electronic device 10.

[0243] Figure 21 Schematic diagrams of various embodiments of the electronic device are shown.

[0244] Reference Figure 21 Various types of electronic devices in embodiments of the application display device may include electronic devices that display images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), wearable electronic devices that include display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and automotive electronic devices 10_3 that include display modules (such as central information displays (CIDs) and interior mirror displays located on the dashboard, center instrument panel, and dashboard of a vehicle).

[0245] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0246] Furthermore, when describing embodiments of this disclosure, the word "may" refers to "one or more embodiments of this disclosure".

[0247] As used herein, the terms “substantially,” “about,” and similar terms are used as approximations rather than as terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. “Substantially” as used herein includes the stated value and means: within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0248] Furthermore, any numerical range disclosed and / or recorded herein is intended to include all subranges with the same numerical precision contained within the recorded range. For example, the range “1.0 to 10.0” is intended to include all subranges between the recorded minimum value of 1.0 and the recorded maximum value of 10.0 (and includes both the recorded minimum value of 1.0 and the recorded maximum value of 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit recorded herein is intended to include all lower numerical limits contained therein, while any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly record any subranges included within the range expressly recorded herein.

[0249] The light-emitting devices, electronic devices, fabrication devices, or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of the device can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0250] In view of the whole of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0251] It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, unless specifically indicated otherwise, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. It will be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: Base; Multiple sub-pixels on the substrate; A via layer, on the substrate, and defining a recessed pattern recessed in a direction toward the substrate; and A pixel defining layer defines an emission region, and a via layer is located in a non-emission region surrounding the emission region. The pixel defining layer defines a light-emitting opening corresponding to the emitting region and a dummy opening exposing a portion of the via layer in the non-emitting region. In the plane, the recessed pattern of the via layer and the dummy opening of the pixel defining layer overlap each other.

2. The display device according to claim 1, characterized in that, The sub-pixel includes: a first sub-pixel that emits light of a first color; a second sub-pixel that emits light of a second color; and a third sub-pixel that emits light of a third color. The emission region includes: a first emission region defining the first sub-pixel; a second emission region defining the second sub-pixel; and a third emission region defining the third sub-pixel.

3. The display device according to claim 2, Its features are, in, The dummy opening includes: A first dummy opening extends in a first direction in the non-emissive region between the first sub-pixel and the second sub-pixel, and in the non-emissive region between the second sub-pixel and the third sub-pixel; and The second dummy opening extends in the non-emission region between the first sub-pixel and the third sub-pixel in a second direction intersecting the first direction, and The recessed pattern includes: The first recessed pattern extends in the second direction and overlaps with the first dummy opening; as well as The second recessed pattern extends in the first direction and overlaps with the second dummy opening.

4. The display device according to claim 3, characterized in that, The first dummy opening and the second dummy opening are spaced apart from each other.

5. The display device according to claim 3, characterized in that, The first dummy opening and the second dummy opening are connected.

6. The display device according to claim 3, characterized in that: The pixel defining layer has a plurality of first ends at opposite sides of the pixel defining layer defining the first dummy opening between the plurality of first ends, and in the first recessed pattern; and The pixel defining layer has a plurality of second ends at opposite sides of the pixel defining layer defining a second dummy opening between the plurality of second ends, and in the second recessed pattern.

7. The display device according to claim 2, characterized in that, The dummy opening includes: A first dummy opening extends in a first direction in the non-emissive region between the first sub-pixel and the second sub-pixel, and in the non-emissive region between the second sub-pixel and the third sub-pixel; and The second dummy opening extends in the first direction within the non-emission region between the first sub-pixel and the third sub-pixel, and The second dummy opening includes a plurality of second sub-dummy openings that extend in the first direction and are arranged along a second direction that intersects the first direction.

8. The display device according to claim 2, characterized in that, The dummy opening includes: A first dummy opening extends in the non-emissive region between the first sub-pixel and the second sub-pixel in a second direction; and The second dummy opening extends in the second direction within the non-emission region between the second sub-pixel and the third sub-pixel, and The recessed pattern extends in a first direction intersecting the second direction and overlaps with each of the first dummy opening and the second dummy opening.

9. A display device, characterized in that, The display device includes: Base; A first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are on the substrate; A via layer, on the substrate, and defining a recessed pattern recessed in a direction toward the substrate; and A pixel defining layer is located on the via layer in a non-emitting region, and defines a first emitting region of the first sub-pixel, a second emitting region of the second sub-pixel, and a third emitting region of the third sub-pixel. The pixel defining layer defines a first opening corresponding to the first emission region, a second opening corresponding to the second emission region, a third opening corresponding to the third emission region, and a dummy opening exposing a portion of the via layer in the non-emission region. In the plane, the recessed pattern of the via layer and the dummy opening of the pixel defining layer overlap each other.

10. An electronic device, characterized in that, The electronic device includes: a display device, the display device comprising: Base; Sub-pixels, on the substrate; A via layer, on the substrate, and defining a recessed pattern recessed in a direction toward the substrate; and A pixel defining layer defines an emission region, and a via layer is located in a non-emission region surrounding the emission region. The pixel defining layer defines a light-emitting opening corresponding to the emitting region and a dummy opening exposing a portion of the via layer in the non-emitting region. In the plane, the recessed pattern of the via layer and the dummy opening of the pixel defining layer overlap each other.

Images