Communication systems with auxiliary master and auxiliary call support functionality

Abstract

A device with auxiliary master functionality in a communication system that has the following features: a node transceiver (104') comprising an upstream transceiver circuit arrangement (132) for receiving a signal transmitted via two upstream wires of a two-wire bus (106) from an upstream master node transceiver (102) and a downstream transceiver circuit arrangement (131) for receiving a signal transmitted via two downstream wires of the two-wire bus (106) from a downstream slave node transceiver (104), and the node transceiver (104') being selectively operable as a slave or master; a processing device (109) that is communicatively coupled to the node transceiver (104'), wherein the processing device (109) is configured to provide a signal to the node transceiver (104') to cause the node transceiver (104') to operate as a slave or master, and wherein the processing device (109) is configured to set itself up as a host for the communication system when the node transceiver (104') operates as master.

Description

background

[0001] As electronic components have become smaller and performance expectations have increased, more components are now contained in previously uninstrumented or less instrumented devices. In some environments, the communication infrastructure used to exchange signals between these components (e.g., in a vehicle) required thick and heavy bundles of cables.

[0002] US 2016 / 0034417A1 discloses systems and techniques for distributed audio coordination over a two-wire communication bus, in which a master node and multiple slave nodes are connected in a daisy-chain configuration. The system provides bidirectional synchronous data, clock, and synchronization signals over the bus. A slave device includes circuitry to receive a synchronization control frame, audio data, and parameters for a dynamics processor, and to derive timing information from the control frame. The master node generates downstream signals and a clock for synchronous data transmission, while the system allows downstream traffic, upstream traffic, and power transmission over the same twisted pair of wires. Slave nodes can selectively forward or process data.

[0003] US 2017 / 0220502A1 describes systems and methods for general-purpose input / output (GPIO)-to-GPIO communication in a multi-node network with a daisy-chain topology. The system comprises a master node and multiple slave nodes connected via a two-wire bus that provides bidirectional synchronous data, clock and synchronization signals, and power over the same lines. The disclosed node transceivers support mapping GPIO pins to virtual ports to communicate state changes over the bus without host intervention and can also be configured in a bus-monitor mode, in which an upstream transceiver monitors bus traffic and forwards it to a protocol analyzer, while the downstream transceiver is disabled.

[0004] US 2009 / 0021955A1 discloses a control network for an LED-based lighting system in a transit vehicle, comprising a master node and several slave nodes connected via a digital communication bus, preferably in a daisy-chain configuration. The network discloses a redundant backup control mechanism in which the slave nodes connected to the data bus monitor the bus and wait for periodic signals from the master node. If a slave node does not receive a signal from the master within an expected time period, it detects a failure and can initiate steps to take over the functionality of the master node. Each slave node can be programmed with a different waiting time to avoid conflicts when assuming the master function.

[0005] US 2009 / 0235001A1 describes a communication system with a master-slave structure comprising a first master unit, a second master unit, and at least one slave unit, connected, for example, via a two-wire structure. To continue data transmission in the event of a connection failure, the second master unit (backup master) is configured to be inserted into a data transmission chain extending from the first master unit to the slave unit. For this purpose, the second master unit has a master coupling unit that, in a first operating mode (normal operation), disconnects a control unit from the transmitting and receiving units and, in a second operating mode (when reception from the first master unit is interrupted), connects them to take over data transmission on the structure and automatically reconfigure the data transmission path. Brief description of the drawings

[0006] The embodiments will be easily understood in conjunction with the accompanying drawings and the following detailed description. To simplify this description, identical reference numerals denote identical structural elements. The embodiments are illustrated in the figures of the accompanying drawings as examples and are not limited to this. Fig. Figure 1 is a block diagram of an illustrative two-wire communication system according to various embodiments. Fig. 2 is a block diagram of a node transceiver according to various embodiments, which is located in a node of the system of Fig. It may contain 1. Fig. Figure 3 is a diagram of a part of a synchronization control frame according to various embodiments, which is used for communication in the system of Fig. 1 is used. Fig. 4 is a diagram of a superframe according to various embodiments, which is used for communication in the system of Fig. 1 is used. Fig. Figure 5 illustrates example formats for a synchronization control frame according to different embodiments, in different operating modes of the system. Fig. 1. Fig. Figure 6 illustrates example formats for a synchronization response frame according to different embodiments, in different operating modes of the system. Fig. 1. Fig. Figure 7 is a block diagram of various components of the bus protocol circuit arrangement of Fig. 2, according to various embodiments. Fig. Figures 8-11 illustrate examples of information exchange along a two-wire bus according to different embodiments of the bus protocols described herein. Fig. Figure 12 illustrates a ring topology for the two-wire bus and a unidirectional communication scheme on it, according to various embodiments. Fig. 13 is a block diagram of a device that acts as a node or host in the system of Fig. 1 can serve, according to various embodiments. Fig. Figure 14 is a block diagram of a communication system with auxiliary master functionality, according to various embodiments. Fig. Figure 15 is a flowchart of a procedure for providing the auxiliary master functionality in the system of Fig. 14, according to various embodiments. Fig. Figure 16 illustrates a specific example of a part of the communication system of Fig. 14, according to various embodiments. Fig. Figure 17 is a flowchart of a procedure for providing the auxiliary master functionality in the system of Fig. 16, according to various embodiments. Fig. Figure 18 is a schematic illustration of an exemplary implementation of the in Fig. 16 illustrated parts of the communication system, according to different embodiments. Fig. Figure 19 is a block diagram of a communication system with auxiliary call support functionality, according to various embodiments. Fig. Figure 20 is a flowchart of a procedure for providing the help call support functionality in the system of Fig. 19, according to various embodiments. Fig. Figure 21 illustrates a specific example of a part of the communication system of Fig. 19, according to various embodiments. Fig. Figure 22 is a flowchart of a procedure for providing the help call support functionality in the system of Fig. 21, according to various embodiments. Fig. Figure 23 is a schematic illustration of an exemplary implementation of the in Fig. 21 illustrated part of the communication system, according to different embodiments. Fig. 24A and Fig. Figure 24B illustrates an exemplary communication system with auxiliary call support functionality under various operating conditions, according to different embodiments. Fig. 25A and Fig. Figure 25B illustrates another exemplary communication system with auxiliary call support functionality under various operating conditions, according to different embodiments. Detailed description

[0007] This document discloses systems and techniques for auxiliary master functionality. In some embodiments, a communication system with auxiliary master functionality may include a master node coupled to several downstream slave nodes, wherein at least one of the slave nodes can perform master node functions when the master node is disconnected from the system.

[0008] The following detailed description refers to the accompanying drawings, which form part thereof, where identical reference numerals consistently denote identical parts and where embodiments that may be employed are shown for illustrative purposes. It is understood that other embodiments may be used and structural and logical modifications may be made without deviating from the scope of protection of this disclosure. Accordingly, the following detailed description is not to be interpreted in a limiting sense.

[0009] Various operations may be described as several discrete actions or in a manner that is extremely helpful in understanding the claimed subject matter. However, the order of the description should not be interpreted as implying that these operations are necessarily dependent on the order in which they are presented. In particular, these operations may not be performed in the order in which they are presented. Described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed, and / or described operations may be omitted in additional embodiments.

[0010] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0011] Various components may be referred to herein or illustrated herein in the singular (e.g., a "processor", a "peripheral device", etc.), this simply to facilitate discussion, and any element referred to in the singular may contain several such elements, according to the teachings herein.

[0012] The description uses the phrases "in one embodiment" or "in embodiments," each referring to one or more of the same or different embodiments. Furthermore, the terms "having," "including," "containing," and the like, as used with reference to the present disclosure, are synonymous. As used herein, the term "circuit arrangements" may refer to, be part of, or include: an application-specific integrated circuit (ASIC), an electronic circuit, and an optical circuit; a processor (shared, dedicated, or in a group) and / or memory (shared, dedicated, or in a group) executing one or more software or firmware programs; a combinational logic circuit; and / or other suitable hardware providing the described functionality.

[0013] Fig. Figure 1 is a block diagram of an illustrative half-duplex two-wire communication system 100 according to various embodiments. The system 100 comprises a host 110, a master node 102, and at least one slave node 104. Fig. Figure 1 illustrates three slave nodes (0, 1, and 2). The representation of three slave nodes is shown in Figure 104. Fig. 1 is merely for illustrative purposes and the system 100 can, depending on requirements, have one, two or more slave nodes 104.

[0014] The master node 102 can communicate with the slave nodes 104 via a two-wire bus 106. The bus 106 can have various two-wire bus links between adjacent nodes along the bus 106 to connect the nodes along the bus 106 in a daisy-chain manner. As shown in Fig. As illustrated in Figure 1, the bus 106 can, for example, have the following: a link that couples the master node 102 to the slave node 0, a link that couples the slave node 0 to the slave node 1, and a link that couples the slave node 1 to the slave node 2. In some embodiments, the links of the bus 106 can each be formed from a single twisted pair of wire (e.g., an unshielded twisted pair). In some embodiments, the links of the bus 106 can each be formed from a coaxial cable (where, for example, the core provides the "positive" line and the shield provides the "negative" line, or vice versa). The two-wire bus links together provide a complete electrical path (e.g., a forward and a return current path), so that no additional ground or voltage source lines are required.

[0015] The host 110 may include a processor that programs the master node 102 and acts as the output and receiver of various user data transmitted along the bus 106. In some embodiments, the host 110 may, for example, be or include a microcontroller. In particular, the host 110 may be the master of Inter-Integrated Circuit Sound (I2S) communications taking place along the bus 106. The host 110 may communicate with the master node 102 via an I2S / Time-Division Multiplex (TDM) bus and / or an Inter-Integrated Circuit (I2C) bus. In some embodiments, the master node 102 may be a transceiver (e.g., the one described below with reference to Fig. The master node 102 (discussed as two transceiver nodes 120) is located within the same housing as the host 110. The master node 102 can be programmed by the host 110 via the I2C bus for configuration and readout purposes and can be configured to generate clock, synchronization, and framing for all slave nodes 104. In some embodiments, an extension of the I2C control bus between the host 110 and the master node 102 can be embedded in the data streams transmitted via bus 106. This allows the host 110 direct access to registers and status information for one or more slave nodes 104, as well as enabling I2C-to-I2C communication over a distance to allow the host 110 to control the devices 108. In embodiments where the system 100 is contained in a vehicle, the host 110 and / or the master node 102 may be contained in a head unit of the vehicle.

[0016] The master node 102 can generate "downstream" signals (e.g., data signals, power signals, etc., transmitted from the master node 102 along the bus 106) and receive "upstream" signals (e.g., transmitted to the master node 102 along the bus 106). The master node 102 can provide a clock signal for synchronous data transmission over the bus 106. As used here, "synchronous data" can include data that is continuously streamed to / from the same node along the bus 106 with a fixed time interval between two successive transmissions (e.g., audio signals). In some embodiments, the clock signal provided by the master node 102 can be derived from an I2S input provided to the master node 102 by the host 110.A slave node 104 can be an addressable network connection point representing a possible destination for data frames transmitted downstream or upstream on bus 106. A slave node 104 can also represent a possible source of downstream or upstream data frames. The system 100 can allow control information and other data to be transmitted in both directions from one node to the next over bus 106. One or more of the slave nodes 104 can also be powered by signals transmitted over bus 106.

[0017] In particular, both the master node 102 and the slave nodes 104 can have a positive upstream port (designated as "AP"), a negative upstream port (designated as "AN"), a positive downstream port (designated as "BP"), and a negative downstream port (designated as "BN"). The positive and negative downstream ports of a node can be connected to the positive and negative upstream ports, respectively, of the adjacent downstream node. As shown in Fig. As shown in Figure 1, the master node 102 can have positive and negative upstream connections, although these connections may not be used; in other embodiments, the master node 102 may not have positive and negative upstream connections. The last slave node 104 along the bus 106 (the slave node 2 in Figure 1) Fig. 1) may have positive and negative downstream connections, although these connections may not be used; in other embodiments, the last slave node 104 may not have positive and negative downstream connections.

[0018] As discussed in detail below, the master node 102 can periodically send a synchronization control frame downstream, optionally along with data intended for one or more of the slave nodes 104. For example, the master node 102 can send a synchronization control frame every 1024 bits (representing a superframe) at a frequency of 48 kHz, resulting in an effective bit rate on bus 106 of 49.152 Mbps. Other rates are supported, including, for example, 44.1 kHz. The synchronization control frame allows the slave nodes 104 to identify the beginning of each superframe and, in combination with physical layer coding / signaling, also allows each slave node 104 to derive its internal operating clock from bus 106.The synchronization control frame can include a preamble to signal the start of synchronization, as well as control fields that allow various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing to registers on slave node 104), transmission of I2C information, remote control of certain general-purpose input / output (GPIO) pins on slave node 104, and other services. A portion of the synchronization control frame following the preamble and payload can be scrambled to reduce the likelihood of information in the synchronization control frame being mistaken for a new preamble and to flatten the spectrum of associated electromagnetic emissions.

[0019] The synchronization control frame can be passed between slave node 104 (optionally together with other data that may come from the master node 102, but may also or additionally come from one or more upstream slave nodes 104 or from a slave node 104 itself) until it reaches the last slave node 104 (i.e., slave node 2 in Fig. 1) reached by the last slave node 104, which has been configured by the master node 102 or which has identified itself as the last slave node 104. Upon receiving the synchronization control frame, the last slave node 104 can transmit a synchronization response frame, followed by any data it is authorized to transmit (e.g., 24-bit audio sampling in a designated timeslot). The synchronization response frame can be propagated upstream between slave nodes 104 (optionally along with data from downstream slave nodes 104), and each slave node 104 can, based on the synchronization response frame, identify a timeslot, if any, in which it is authorized to transmit.

[0020] In some embodiments, one or more of the slave nodes 104 in the system 100 can be coupled to and communicate with a peripheral device 108. For example, as discussed below, a slave node 104 can be configured to read and / or write data to / from the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, and / or I2C protocols. Although the singular reference is made here to the “peripheral device 108,” this is for the sake of simplicity, and a single slave node 104 can be coupled to no peripheral device, one peripheral device, or multiple peripheral devices.Examples of peripheral devices that may be included in peripheral device 108 include a digital signal processor (DSP), a field-programmable gate array (FPGA), an ASIC, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a codec, a microphone, a microphone array, a loudspeaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an environmental condition sensor (e.g., a temperature, humidity, and / or gas sensor), a wired or wireless communications transceiver, a display device (e.g., a touchscreen display), a user interface component (e.g., a button, a rotary dial, or other control), a camera (e.g., a video camera), a storage device, or any other suitable device that transmits and / or receives data.A number of examples of different peripheral device configurations are discussed in detail here.

[0021] In some embodiments, the peripheral device 108 may include any device configured for Inter-Integrated Circuit Sound (I2S) communication; the peripheral device 108 may communicate with the associated slave node 104 via the I2S protocol. In some embodiments, the peripheral device 108 may include any device configured for Inter-Integrated Circuit (I2C) communication; the peripheral device 108 may communicate with the associated slave node 104 via the I2C protocol. In some embodiments, a slave node 104 may not be coupled to any peripheral device 108.

[0022] A slave node 104 and its associated peripheral device 108 can be contained in separate enclosures and coupled via a wired or wireless communication link, or they can be contained in a common enclosure. For example, a loudspeaker connected as a peripheral device 108 can be located together with the hardware for an associated slave node 104 in one enclosure (e.g., the one shown below with reference to Fig. 2 discussed node transceivers 120), so that the hardware for the associated slave node 104 is contained within a housing that includes other speaker components. The same can be true for any type of peripheral device 108.

[0023] As discussed above, host 110 can communicate with and control master node 102 using multi-channel I2S and I2C communication protocols. Specifically, host 110 can transfer data via I2S to a frame buffer (not illustrated) in master node 102, and master node 102 can read data from the frame buffer and transmit the data along bus 106. Similarly, master node 102 can store data received via bus 106 in the frame buffer and then transmit the data to host 110 via I2S.

[0024] Each slave node 104 can have internal control registers that can be configured through communications from the master node 102. Several such registers are discussed in detail below. Each slave node 104 can receive downstream data and forward the data downstream. Each slave node 104 can receive and / or generate upstream data and / or forward data upstream and / or add data to an upstream transaction.

[0025] Communications along bus 106 can take place in periodic superframes. Each superframe can begin with a downstream synchronization control frame; can be divided into periods of downstream transmission (also called "downstream parts"), upstream transmission (also called "upstream parts"), and no transmission (during which bus 106 is not driven); and end just before the transmission of another downstream synchronization control frame. The master node 102 can be programmed (by the host 110) with a number of downstream parts to transmit to one or more of the slave nodes 104, and with a number of upstream parts to receive from one or more of the slave nodes 104.Each slave node 104 can be programmed (by the master node 102) with a number of downstream parts to transmit data down the bus 106, a number of downstream parts to receive data, a number of upstream parts to transmit data up the bus 106, and a number of upstream parts in which the slave node 104 can transmit data received by the slave node 104 from the associated peripheral device 108. Communication along the bus 106 is described in more detail below with reference to the... Fig. 2-12 discussed.

[0026] Both the master node 102 and the slave nodes 104 can have a transceiver to manage communication between components of the system 100. Fig. Figure 2 is a block diagram of a node-transmitter 120, according to various embodiments, which is located in a node (e.g. the master node 102 or a slave node 104) of the system 100 of Fig. 1 may be included. In some embodiments, a node transceiver 120 may be included in each of the nodes of the system 100, and a control signal may be provided to the node transceiver 120 via a master (MSTR) pin to indicate whether the node transceiver 120 should function as a master (e.g., when the MSTR pin is set high) or as a slave (e.g., when the MSTR pin is set low).

[0027] The node transceiver 120 can include an upstream differential signaling (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 can be connected to the above with reference to Fig. The positive and negative upstream connections discussed above can be connected, and the downstream DS transceiver 124 can be connected to the above with reference to Fig. The positive and negative downstream connections discussed in section 1 are coupled. In some embodiments, the upstream DS transceiver 122 can be a low-voltage DS (LVDS) transceiver and the downstream DS transceiver 124 can be an LVDS transceiver. Each node in the system 100 can be AC-coupled to the bus 106 and data signals can be transmitted along the bus 106 (e.g. via the upstream DS transceiver 122 and / or the downstream DS transceiver 124) using a predetermined form of DS (e.g. LVDS or multipoint LVDS (MLVDS) or similar signaling) with appropriate encoding to provide timing information over the bus 106 (e.g., differential Manchester encoding, biphase marker encoding, Manchester encoding, NRZI (Non-Return-to-Zero, Inverted) encoding with run-length limitation or any other suitable encoding).

[0028] The upstream DS transceiver 122 and the downstream DS transceiver 124 can communicate with a bus protocol circuit arrangement 126, and the bus protocol circuit arrangement 126 can communicate with, among other things, a phase-locked loop (PLL) 128 and a voltage regulator circuit arrangement 130. When the node transceiver 120 is powered up, the voltage regulator circuit arrangement 130 can output a "power supply good" signal, which is used by the PLL 128 as a power-up reset.

[0029] As noted above, one or more slave nodes 104 in the system 100 can simultaneously receive power transmitted over the bus 106 along with data. For power sharing (which is optional, since some of the slave nodes 104 may be configured to operate solely on a local power supply), the master node 102 can apply a DC bias to the bus link between the master node 102 and slave node 0 (e.g., by connecting one of the downstream terminals to a voltage source provided by a voltage regulator and the other downstream terminal to ground). The DC bias can be a predetermined voltage, such as 5 V, 8 V, the voltage of a car battery, or a higher voltage. Each subsequent slave node 104 can selectively tap its upstream bus link to gain power (e.g., using the voltage regulator circuit arrangement 130).This power can be used to power the slave node 104 itself (and optionally one or more peripheral devices 108 coupled to the slave node 104). A slave node 104 can also selectively bias the downstream bus link for the next slave node 104 in the sequence, either with the power gained from the upstream bus link or from a local power supply. For example, slave node 0 can use the DC bias on the upstream bus link 106 to gain power for slave node 0 itself and / or for one or more associated peripheral devices 108, and / or slave node 0 can gain power from its upstream bus link 106 to bias its downstream bus link 106.

[0030] Accordingly, in some embodiments of System 100, each node can provide power to subsequent downstream nodes via a downstream bus link. Powering nodes can be performed in a sequenced manner. For example, after discovering and configuring Slave Node 0 via bus 106, Master Node 102 can instruct Slave Node 0 to supply power to its downstream bus link 106 to provide power to Slave Node 1; after Slave Node 1 has been discovered and configured, Master Node 102 can instruct Slave Node 1 to supply power to its downstream bus link 106 to provide power to Slave Node 2 (and so on for additional Slave Nodes 104 connected to bus 106).In some embodiments, one or more of the slave nodes 104 can be powered locally, instead of or in addition to being powered by their upstream bus link. In some such embodiments, the local power source for a given slave node 104 can be used to supply power to one or more downstream slave nodes.

[0031] In some embodiments, the upstream bus interface circuit arrangement 132 can be arranged between the upstream DS transceiver 122 and the voltage regulator circuit arrangement 130, and the downstream bus interface circuit arrangement 131 can be arranged between the downstream DS transceiver 124 and the voltage regulator circuit arrangement 130. Since each link of the bus 106 can carry AC (signal) and DC (power) components, the upstream bus interface circuit arrangement 132 and the downstream bus interface circuit arrangement 131 can separate the AC and DC components, with the AC components being supplied to the upstream DS transceiver 122 and the downstream DS transceiver 124, and the DC components being supplied to the voltage regulator circuit arrangement 130.AC couplings on the line side of the upstream DS transceiver 122 and the downstream DS transceiver 124 essentially isolate the transceivers 122 and 124 from the DC component on the line to enable bidirectional high-speed communications. As discussed above, the DC component can be tapped for power, and the upstream bus interface circuit arrangement 132 and the downstream bus interface circuit arrangement 131 can incorporate a ferrite core, a common-mode choke, or an inductor to reduce, for example, the AC component supplied to the voltage regulator circuit arrangement 130.In some embodiments, the upstream bus interface circuit arrangement 132 may be contained in the upstream DS transceiver 122 and / or the downstream bus interface circuit arrangement 131 may be contained in the downstream DS transceiver 124; in other embodiments, the filter circuit arrangement may be located outside the transceivers 122 and 124.

[0032] The node transceiver 120 can include a transceiver 127 for I2S, TDM, and PDM communication between the node transceiver 120 and an external device 155. Although the singular reference here to the "external device 155" is used for simplicity of illustration, multiple external devices can communicate with the node transceiver 120 via the I2S / TDM / PDM transceiver 127. As is technically known, the I2S protocol is used to transmit pulse-code modulated (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used here, "I2S / TDM" can refer to an extension of the I2S stereo (2-channel) content to multiple channels using TDM. As is technically known, PDM can be used in sigma-delta converters, and in particular, the PDM format can represent an oversampled 1-bit sigma-delta ADC signal before decimation.The PDM format is frequently used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 can communicate with the bus protocol circuit arrangement 126 and the pins for communication with the external device 155. Six pins, BCLK, SYNC, DTX[1:0] and DRX[1:0], are available. Fig. Figure 2 illustrates that the BCLK pin can be used for an I2S bit clock, the SYNC pin can be used for an I2S frame synchronization signal, and the DTX[1:0] and DRX[1:0] pins are used to transmit and receive data channels, respectively. Although in Fig. As two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are illustrated, any desired number of receive and / or transmit pins can be used.

[0033] If the node transceiver 120 is contained in the master node 102, the external device 155 can have the host 110, and the I2S / TDM / PDM transceiver 127 can provide an I2S slave (with respect to BCLK and SYNC) that can receive data from and send data to the host 110 synchronously with an I2S interface clock from the host 110. In particular, an I2S frame synchronization signal can be received as an input from the host 110 at the SYNC pin, and the PLL 128 can use the signal to generate clocks. If the node transceiver 120 is contained in a slave node 104, the external device 155 can have one or more peripheral devices 108 and the I2S / TDM / PDM transceiver 127 can provide an I2S clock master (for BCLK and SYNC) that can control the I2S communication with the peripheral device 108.In particular, the I2S / TDM / PDM transceiver 127 can provide an I2S frame synchronization signal at the SYNC pin as an output. Registers in the node transceiver 120 can determine which and how many I2S / TDM channels are transmitted as data slots over the bus 106. A TDM mode (TDMMODE) register in the node transceiver 120 can store a value indicating how many TDM channels fit between successive SYNC pulses on a TDM transmit or receive pin. Along with the knowledge of the channel size, the node transceiver 120 can automatically adjust the BCLK rate to match the number of bits within the sampling time (e.g., 48 kHz).

[0034] The node transceiver 120 can include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. Although the singular reference here to the "external device 157" is used for simplicity of illustration, multiple external devices can communicate with the node transceiver 120 via the I2C transceiver 129. As is known technically, the I2C protocol uses clock (SCL) and data (SDA) lines to provide data transfer. The I2C transceiver 129 can communicate with the bus protocol circuit arrangement 126 and has pins for communication with the external device 157. Four pins, ADR1, ADR2, SDA, and SCL, are available in Fig. Figure 2 illustrates this; ADR1 and ADR2 can be used to modify the I2C addresses used by node transceiver 120 when node transceiver 120 acts as an I2C slave (e.g., when contained within master node 102), and SDA and SCL are used for serial I2C data and serial I2C clock signals, respectively. When node transceiver 120 is contained within master node 102, external device 157 can contain host 110, and I2C transceiver 129 can provide an I2C slave capable of receiving programming instructions from host 110. In particular, a serial I2C clock signal can be received as an input from host 110 for register accesses at the SCL pin.If the node transceiver 120 is contained in a slave node 104, the external device 157 can have a peripheral device 108, and the I2C transceiver 129 can provide an I2C master to allow the I2C transceiver to program one or more peripheral devices according to instructions provided by the host 110 and transmitted to the node transceiver 120 via the bus 106. In particular, the I2C transceiver 129 can provide a serial I2C clock signal at the SCL pin as an output.

[0035] The node transceiver 120 can have an interrupt request (IRQ) pin that communicates with the bus protocol circuitry 126. If the node transceiver 120 is contained in the master node 102 via the I2C transceiver 129, the bus protocol circuitry 126 can deliver event-driven interrupt requests to the host 110 via the IRQ pin. If the node transceiver 120 is contained in a slave node 104 (e.g., if the MSTR pin is set low), the IRQ pin can function as a GPIO pin with interrupt request capability. In addition to the functions described in Fig. 2 other pins shown (e.g. as discussed below).

[0036] System 100 can operate in any number of different operating modes. Each node on bus 106 can have a register indicating which operating mode is currently active. Descriptions of examples of different operating modes that can be implemented follow. In a standby mode, bus activity is reduced to enable overall power savings; the only traffic required is minimal downstream preamble to keep each node's PLLs (e.g., PLL 128) synchronized. Read and write operations over bus 106 are not supported in standby mode. In a discovery mode, the master node 102 can send predefined signals along bus 106 and wait for appropriate responses to map the topology of slave nodes 104 distributed along bus 106.In normal operating mode, full register access to and from the slave nodes 104 and to and from the peripheral devices 108 via bus 106 is available. Normal mode can be globally configured by the host 110 with or without synchronous upstream and downstream data.

[0037] Fig. Figure 3 is a diagram of a portion of a synchronization control frame 180 according to various embodiments, which is used for communication in the system 100. In particular, the synchronization control frame 180 can be used for data clock recovery and PLL synchronization, as discussed below. As noted above, communications can be time-division multiplexed into downstream and upstream portions, since communications can occur in both directions over the bus 106. In a downstream portion, a synchronization control frame and downstream data can be transmitted from the master node 102, whereas in an upstream portion, a synchronization response frame and upstream data can be transmitted from each of the slave nodes 104 to the master node 102. The synchronization control frame 180 can include a preamble 182 and control data 184.Each slave node 104 can be trained to use the preamble 182 of the received synchronization control frame 180 as a time base for supplying the PLL 128. To enable this, a preamble 182 does not follow the "rules" of valid control data 184 and can therefore be immediately distinguished from the control data 184.

[0038] In some embodiments, communication along bus 106 can be encoded, for example, using a clock-first, zero-transition differential Manchester coding scheme. According to such a coding scheme, each bit time begins with a clock transition. If the data value is zero, the encoded signal transitions again in the middle of the bit time. If the data value is one, the encoded signal does not transition again. The in Fig. The preamble 182 illustrated in Figure 5 may violate the encoding protocol (e.g., by having clock transitions that do not occur at the beginning of bit times 5, 7, and 8), meaning that preamble 182 may not match a legal (e.g., correctly encoded) pattern for control data 184. Additionally, preamble 182 cannot be reproduced by assuming a legal pattern for control data 184 and forcing bus 106 high or low for a single bit time or for a multi-bit time period. The in Fig. The 5 illustrated preamble 182 is merely illustrative and the synchronization control frame 180 may have different preambles 182 in any suitable manner which may violate the encoding used by the control data 184.

[0039] The bus protocol circuit arrangement 126 can include a differential Manchester decoder circuit arrangement running on a clock recovered from bus 106, which detects the synchronization control frame 180 in order to send a frame sync indicator to the PLL 128. In this way, the synchronization control frame 180 can be detected without using a system clock or a faster-running oversampling clock. Consequently, the slave nodes 104 can receive a PLL synchronization signal from bus 106 without requiring a crystal clock source at the slave nodes 104.

[0040] As noted above, communications along bus 106 can occur in periodic superframes. Fig. Figure 4 is a diagram of a Superframe 190, according to various embodiments. As in Fig. As shown in Figure 4, a superframe can begin with a synchronization control frame 180. When the synchronization control frame 180 is used as a timing source for the PLL 128, the frequency at which superframes communicate (“the superframe frequency”) can be the same as the synchronization signal frequency. In some embodiments where audio data is transmitted along the bus 106, the superframe frequency can be the same as the audio sampling frequency used in the system 100 (e.g., either 48 kHz or 44.1 kHz), although any suitable superframe frequency may be used. Each superframe 190 can be divided into periods of downstream transmission 192, periods of upstream transmission 194, and periods of no transmission 196 (e.g., when the bus 106 is not driven).

[0041] In Fig. Figure 4 shows the superframe 190 with an initial period of a downstream transmission 192 and a subsequent period of an upstream transmission 194. The downstream transmission period 192 can include a synchronization control frame 180 and X downstream data slots 198, where X can be zero. Essentially, all signals on the bus 106 can be line-coded and a synchronization signal is passed downstream from the master node 102 to the last slave node 104 in the form of the synchronization preamble 182 in the synchronization control frame 180, as discussed above. Synchronous downstream TDM data can be contained in the X downstream data slots 198 following the synchronization control frame 180. The downstream data slots 198 can have equal widths. As discussed above, the PLL 128 can provide the clock signal that a node uses to time communications over bus 106.In some embodiments where the bus 106 is used to transmit audio data, the PLL 128 can operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe).

[0042] The upstream transmission period 194 can include a synchronization response frame 197 and Y upstream data slots 199, where Y can be zero. In some embodiments, each slave node 104 can consume a portion of the downstream data slots 198. The last slave node (e.g., slave node 2 in Fig. 1) can respond (after a predetermined response time stored in a register of the last slave node) with a synchronization response frame 197. Synchronous upstream TDM data can be added by any slave node 104 directly after the synchronization response frame 197 into the upstream data slots 199. The upstream data slots 199 can have equal widths. A slave node 104 that is not the last slave node (e.g., slave nodes 0 and 1 in Fig. 1) can replace the received synchronization response frame 197 with its own upstream response if a read operation of one of its registers has been requested in the synchronization control frame 180 of the superframe 190, or if a remote I2C read operation has been requested in the synchronization control frame 180 of the superframe 190.

[0043] As discussed above, the synchronization control frame 180 can initiate any downstream transmission. In some embodiments, the synchronization control frame 180 can have a length of 64 bits, although any other suitable length may be used. The synchronization control frame 180 can, as noted above, begin with the preamble 182. In some embodiments, when the synchronization control frame 180 is forwarded by a slave node 104 to a downstream slave node 104, the preamble 182 can be generated by the transmitting slave node 104 instead of being forwarded.

[0044] The control data 184 of the synchronization control frame 180 can have fields containing data used to control transactions over bus 106. Examples of these fields are discussed below, and some embodiments are described in Fig. 5 illustrates. In particular illustrates Fig. Five example formats for the synchronization control frame 180 in normal mode, I2C mode, and discovery mode, according to various embodiments. In some embodiments, a different preamble 182 or a completely different synchronization control frame 180 can be used in standby mode, so that the slave nodes 104 do not have to receive the entire synchronization control frame 180 until a transition to normal mode is sent.

[0045] In some embodiments, the synchronization control frame 180 can include a counter (CNT) field. The CNT field can have any suitable length (e.g., 2 bits) and can be incremented from the value used in the previous superframe (modulo the length of the field). A slave node 104 that receives an unexpected CNT value can be programmed to return an interrupt.

[0046] In some embodiments, the synchronization control frame 180 may include a Node Addressing Mode (NAM) field. The NAM field can be of any suitable length (e.g., 2 bits) and can be used to control access to registers of a slave node 104 via the bus 106. In normal mode, registers of a slave node 104 can be read and / or written to, based on the ID of the slave node 104 and the address of the register. Broadcast transactions are write operations that should be performed by every slave node 104. In some embodiments, the NAM field can provide four node addressing modes, including "None" (e.g., data not addressed to any specific slave node 104), "Normal" (e.g., data unicasted to a specific slave node 104 specified in the address field discussed below), "Broadcast" (e.g.,(addressed to all slave nodes 104) and "discovery".

[0047] In some embodiments, the synchronization control frame 180 can include an I2C field. The I2C field can be of any suitable length (e.g., 1 bit) and can be used to indicate that the period of a downstream transmission 192 contains an I2C transaction. The I2C field can indicate that the host 110 has provided instructions to remotely access a peripheral device 108 that acts as an I2C slave with respect to an associated slave node 104.

[0048] In some embodiments, the synchronization control frame 180 may include a node field. The node field may be of any suitable length (e.g., 4 bits) and may be used to specify which slave node is addressed for normal access and I2C access. In discovery mode, this field may be used to program an identifier for a newly discovered slave node 104 in a node ID register of the slave node 104. Each slave node 104 in the system 100 may be assigned a unique ID when the slave node 104 is discovered by the master node 102, as discussed below. In some embodiments, the master node 102 does not have a node ID, whereas in other embodiments, the master node 102 may have a node ID. In some embodiments, the slave node 104 (e.g., slave node 0) attached to the master node 102 on the bus 106 is Fig. 1) The slave node will be 0, and each subsequent slave node (104) will have a number that is 1 higher than that of the preceding slave node. However, this is merely for illustrative purposes, and any suitable slave node identification system can be used.

[0049] In some embodiments, the synchronization control frame 180 may include a read / write (RW) field. The RW field may be of any suitable length (e.g., 1 bit) and may be used to control whether normal accesses are read operations (e.g., RW==1) or write operations (e.g., RW==0).

[0050] In some embodiments, the synchronization control frame 180 can include an address field. The address field can be of any suitable length (e.g., 8 bits) and can be used to address specific registers of a slave node 104 over the bus 106. For I2C transactions, the address field can be replaced by I2C control values, such as START / STOP, WAIT, RW, and DATA VLD. For discovery transactions, the address field can have a predetermined value (e.g., as in Fig. 5 illustrated).

[0051] In some embodiments, the synchronization control frame 180 can include a data field. The data field can be of any suitable length (e.g., 8 bits) and can be used for normal, I2C, and broadcast write operations. The RESPCYCS value, multiplied by 4, can be used to determine how many cycles a newly discovered node should wait between the start of receiving the synchronization control frame 180 and the start of transmitting the synchronization response frame 197. If the NAM field specifies the discovery mode, the node address and data fields discussed below can be encoded as a RESPCYCS value which, when multiplied by a suitable optional multiplier (e.g., 4), specifies the time in bits from the end of the synchronization control frame 180 to the start of the synchronization response frame 197.This allows a newly discovered slave node 104 to determine the appropriate time slot for upstream transmission.

[0052] In some embodiments, the synchronization control frame 180 may include a Cyclic Redundancy Check (CRC) field. The CRC field may be of any suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the control data 184 of the synchronization control frame 180 following the preamble 182. In some embodiments, the CRC may be calculated according to the CCITT CRC error detection scheme.

[0053] In some embodiments, at least part of the synchronization control frame 180 between the preamble 182 and the CRC field can be scrambled to reduce the probability that a bit sequence in this interval periodically matches the preamble 182 (and thus can be misinterpreted by the slave node 104 as the start of a new superframe 190), as well as to reduce electromagnetic emissions as noted above. In some such embodiments, the CNT field of the synchronization control frame 180 can be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Several embodiments of the system 100 described herein can omit scrambling.

[0054] Other techniques can be used to ensure that preamble 182 can be uniquely identified by slave node 104, or to reduce the probability of preamble 182 occurring elsewhere in the synchronization control frame 180, in addition to or instead of techniques such as scrambling and / or error coding, as discussed above. For example, a longer synchronization sequence can be used to reduce the probability that a specific encoding of the rest of the synchronization control frame 180 will match it. Additionally or alternatively, the rest of the synchronization control frame can be structured so that the synchronization sequence cannot occur, such as by placing fixed "0" or "1" values ​​on appropriate bits.

[0055] The master node 102 can send read and write requests to the slave node 104, including both requests specific to communication on bus 106 and I2C requests. For example, the master node 102 can send read and write requests (specified using the RW field) to one or more designated slave nodes 104 (using the NAM and Node fields) and can indicate whether the request is for the bus 106-specific slave node 104, an I2C request for the slave node 104, or an I2C request to be forwarded to an I2C-compatible peripheral device 108 that is connected to the slave node 104 via one or more of its I2C ports.

[0056] Turning to upstream communication, the synchronization response frame 197 can initiate any upstream transmission. In some embodiments, the synchronization response frame 197 can have a length of 64 bits, although any suitable length can be used. The synchronization response frame 197 can also include a preamble, as discussed above with reference to the preamble 182 of the synchronization control frame 180, followed by a data portion. At the end of a downstream transmission, the last slave node 104 on the bus 106 can wait until the RESPCYCS counter has expired and then begin upstreaming a synchronization response frame 197. If an upstream slave node 104 has been targeted by a normal read or write transaction, a slave node 104 can generate its own synchronization response frame 197 and replace the one received from downstream.If any slave node 104 does not see a synchronization response frame 197 from a downstream slave node 104 at the expected time, the slave node 104 will generate its own synchronization response frame 197 and begin transmitting it upstream.

[0057] The data portion of the synchronization response frame 197 can contain fields that hold data used to communicate response information back to the master node 102. Examples of these fields are discussed below, and some embodiments are shown in Fig. 6 illustrates. In particular illustrates Fig. 6 Example formats for the synchronization response frame 197 in normal mode, I2C mode and discovery mode, according to different embodiments.

[0058] In some embodiments, the synchronization response frame 197 may contain a counter (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be used to transmit the value of the CNT field in the previously received synchronization control frame 180.

[0059] In some embodiments, the synchronization response frame 197 may include an acknowledgment (ACK) field. The ACK field may be of any suitable length (e.g., 2 bits) and may be used by a slave node 104 to acknowledge a command received in the previous synchronization control frame 180 when that slave node 104 generates the synchronization response frame 197. Exemplary indicators that may be communicated in the ACK field include Wait, Acknowledge, Nonacknowledge (NACK), and Retry. In some embodiments, the ACK field may be sized such that an acknowledgment is transmitted by a slave node 104 that it has received and processed a broadcast message (e.g., by transmitting a broadcast acknowledgment to the master node 102).In some such embodiments, a slave node 104 can also indicate whether the slave node 104 has data to transmit (which can be used, for example, for demand-based upstream transmissions, such as non-TDM inputs from a keypad or touchscreen, or for prioritized upstream transmissions, such as when the slave node 104 wants to report an error or emergency condition).

[0060] In some embodiments, the synchronization response frame 197 can contain an I2C field. The I2C field can have any suitable length (e.g., 1 bit) and can be used to transmit the value of the I2C field in the previously received synchronization control frame 180.

[0061] In some embodiments, the synchronization response frame 197 may contain a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to transmit the ID of the slave node 104 that generates the synchronization response frame 197.

[0062] In some embodiments, the synchronization response frame 197 may contain a data field. The data field may be of any suitable length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the slave node 104 that generates the synchronization response frame 197. For discovery transactions, the data field may contain the value of the RESPCYCS field in the previously received synchronization control frame 180.If the ACK field indicates a NACK, or if the synchronization response frame 197 responds to a broadcast transaction, the data field may contain a Broadcast Acknowledgement (BA) indicator (in which the last slave node 104 can indicate whether the broadcast write was received without errors), a Discovery Error (DER) indicator (which indicates whether a newly discovered slave node 104 in a discovery transaction matches an existing slave node 104), and a CRC Error (CER) indicator (which indicates whether a NACK was caused by a CRC error).

[0063] In some embodiments, the synchronization response frame 197 may include a CRC field. The CRC field may be of any suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the portion of the synchronization response frame 197 between the preamble and the CRC field.

[0064] In some embodiments, the synchronization response frame 197 may contain an interrupt request (IRQ) field. The IRQ field may be of any suitable length (e.g., 1 bit) and may be used to indicate that an interrupt has been signaled by a slave node 104.

[0065] In some embodiments, the synchronization response frame 197 may contain an IRQ node (IRQNODE) ​​field. The IRQNODE field may be of any suitable length (e.g., 4 bits) and may be used to transmit the ID of the slave node 104 that signaled the interrupt presented by the IRQ field. In some embodiments, the slave node 104 will insert its own ID into the IRQNODE field to generate the IRQ field.

[0066] In some embodiments, the synchronization response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any suitable length (e.g., 4 bits) and may be used to transmit a CRC value for the IRQ field and the IRQNODE field.

[0067] In some embodiments, the synchronization response frame 197 may contain an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits of the synchronization response frame 197 (e.g., the last 10 bits). As discussed above, the interrupt-related fields may have their own CRC protection in the form of a CRC-4 (and thus not be protected by the preceding CRC field). Any slave node 104 that needs to signal an interrupt to the master node 102 will insert its interrupt information into these fields. In some embodiments, a slave node 104 with a pending interrupt may have a higher priority than any slave node 104 further downstream that also has a pending interrupt. The last slave node 104 along the bus 106 (e.g., slave node 2 in Fig. 1) can always populate these interrupt fields. If the last slave node 104 has no pending interrupt, the last slave node 104 can set the IRQ bit to 0 and the IRQNODE field to its node ID and provide the correct CRC-4 value. For convenience, a synchronization response frame 197 transmitting an interrupt can be referred to here as an "interrupt frame".

[0068] In some embodiments, at least part of the synchronization response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce emissions. In some such embodiments, the CNT field of the synchronization response frame 197 may be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Several embodiments of the system 100 described herein may omit scrambling.

[0069] Other techniques can be used to ensure that preamble 182 can be uniquely identified by the slave nodes 104, or to reduce the probability of preamble 182 occurring elsewhere in the synchronization response frame 197, in addition to or instead of techniques such as scrambling and / or error coding, as discussed above. For example, a longer synchronization sequence can be used to reduce the probability that a specific encoding of the remainder of the synchronization response frame 180 will match it. Additionally or alternatively, the remainder of the synchronization response frame can be structured so that the synchronization sequence cannot occur, such as by placing fixed "0" or "1" values ​​on appropriate bits.

[0070] Fig. Figure 7 is a block diagram of the bus protocol circuit arrangement 126. Fig. 2, according to various embodiments. The bus protocol circuit arrangement 126 may include a control circuit arrangement 154 for controlling the operation of the node transceiver 120 according to the protocol for the bus 106 described herein. In particular, the control circuit arrangement 154 may control the generation of synchronization frames for transmission (e.g., synchronization control frames or synchronization response frames, as discussed above), the processing of received synchronization frames, and the performance of control operations specified in received synchronization control frames. The control circuit arrangement 154 may include programmable registers, as discussed below. The control circuit arrangement 154 may generate and receive synchronization control frames appropriately based on received messages (e.g.,associated with a synchronization control frame if the bus protocol circuit arrangement 126 is contained in a slave node 104, or by an I2C device if the bus protocol circuit arrangement 126 is contained in a master node 102) and adapt the framing to the different operating modes (e.g. normal, discovery, standby, etc.).

[0071] When the node transceiver 120 prepares data for transmission along the bus 106, the preamble circuit arrangement 156 can be configured to generate preambles for synchronization frames for transmission and to receive preambles of received synchronization frames. In some embodiments, a preamble of the downstream synchronization control frame can be sent by the master node 102 every 1024 bits. As discussed above, one or more slave nodes 104 can synchronize to the preamble of the downstream synchronization control frame and generate local phase-aligned master clocks from the preamble.

[0072] A CRC insertion circuit arrangement 158 ​​can be configured to generate one or more CRCs for synchronization frames for transmission. A framing / compression circuit arrangement 160 can be configured to accept incoming data from the I2S / TDM / PDM transceiver 127 (e.g., from a frame buffer associated with the transceiver 127) and / or the I2C transceiver 129, optionally compress the data, and optionally generate parity check bits or error correction codes (ECC) for the data. A multiplexer (MUX) 162 can multiplex a preamble from the preamble circuit arrangement 156, the synchronization frames, and the data into a single transmission stream. In some embodiments, the transmission stream can be scrambled by a scrambling circuit arrangement 164 prior to transmission.

[0073] In some embodiments, for example, the framing / compression circuit arrangement 160 can apply a floating-point compression scheme. In such an embodiment, the control circuit arrangement 154 can transmit 3 bits to indicate how many repeated sign bits are present in the number, followed by a sign bit and N-4 bits of data, where N is the size of the data to be transmitted over the bus 106. The use of data compression can be configured by the master node 102 if desired.

[0074] In some embodiments, the received stream entering the node transceiver 120 can be demultiplexed by the design circuit arrangement 166. A demultiplexer (DEMUX) 168 can demultiplex the preamble, synchronization frames, and data from the received stream. The CRC check circuit arrangement 159 on the receive side can check the received synchronization frames for correct CRC. If the CRC check circuit arrangement 159 identifies a CRC failure in an incoming synchronization control frame 180, the control circuit arrangement 154 can be notified of the failure and will not execute any control commands in the control data 184 of the synchronization control frame 180.If the CRC check circuit arrangement 159 identifies a CRC failure in an incoming synchronization response frame 197, the control circuit arrangement 154 can be notified of the failure and can generate an interrupt to transmit to the host 110 in an interrupt frame. A deframing / decompression circuit arrangement 170 can accept received data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction - double error detection (SECDED)), optionally decompress the data, and write the received data to the I2S / TDM / PDM transceiver 127 (e.g., a frame buffer associated with the transceiver 127) and / or the I2C transceiver 129.

[0075] As discussed above, upstream and downstream data can be transmitted in TDM data slots within a superframe 190 along bus 106. The control circuit assembly 154 can have registers dedicated to managing these data slots on bus 106, several examples of which are discussed below. If the control circuit assembly 154 is contained in a master node 102, the values ​​in these registers can be programmed into the control circuit assembly 154 by the host 110. If the control circuit assembly 154 is contained in a slave node 104, the values ​​in these registers can be programmed into the control circuit assembly 154 by the master node 102.

[0076] In some embodiments, the control circuit arrangement 154 may include a downstream slot (DNSLOTS) register. If the node transceiver 120 is contained in the master node 102, this register may hold the value of the total number of downstream data slots. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the master node 102. In a slave node 104, this register may define the number of data slots passed downstream to the next slave node 104 before or after the addition of locally generated downstream slots, as discussed in more detail below with reference to LDNSLOTS.

[0077] In some embodiments, the control circuit arrangement 154 may include a local downstream slot (LDNSLOTS) register. This register may be unused in the master node 102. In a slave node 104, this register may define the number of data slots that the slave node 104 will use and not forward. Alternatively, this register may define the number of slots that the slave node 104 can contribute to the downstream data link 106.

[0078] In some embodiments, the control circuit arrangement 154 may include an upstream slot (UPSLOTS) register. In the master node 102, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots used for I2S / TDM transmission by the I2S / TDM / PDM transceiver 127 in the master node 102. In a slave node 104, this register may define the number of data slots that are forwarded upstream before the slave node 104 begins adding its own data.

[0079] In some embodiments, the control circuit arrangement 154 may include a local upstream slot (LUPSLOTS) register. This register may be unused in the master node 102. In a slave node 104, this register may define the number of data slots that the slave node 104 will add to the data received downstream before sending it upstream. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the slave node 104.

[0080] In some embodiments, the control circuit arrangement 154 may include a broadcast downstream slot (BCDNSLOTS) register. This register may be unused in the master node 102. In a slave node 104, this register may define the number of broadcast data slots. In some embodiments, broadcast data slots always appear at the beginning of the data field. The data in the broadcast data slots may be used by multiple slave nodes 104 and may be forwarded downstream by all slave nodes 104, whether they are used or not.

[0081] In some embodiments, the control circuit arrangement 154 may include a slot format (SLOTFMT) register. This register defines the format of data for upstream and downstream transmissions. The data size for the I2S / TDM / PDM transceiver 127 may also be determined by this register. In some embodiments, valid data sizes include 8, 12, 16, 20, 24, 28, and 32 bits. This register may also include bits to enable floating-point compression for downstream and upstream traffic. When floating-point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size over the bus 106. All nodes in the system 100 may have the same SLOTFMT values ​​when data slots are enabled, and the nodes may be programmed by a broadcast write operation so that all nodes are updated with the same value.

[0082] The Fig. Figures 8-11 illustrate examples of information exchange along bus 106, according to different embodiments of the bus protocols described herein. In particular, the Fig. 8-11 Embodiments in which each slave node 104 is coupled to one or more loudspeakers and / or one or more microphones as the peripheral device 108. This is merely illustrative, since any desired arrangement of the peripheral device 108 can be coupled to any specific slave node 104 according to the techniques described herein.

[0083] First, illustrate Fig. 8 Signaling and timing considerations for bidirectional communication on bus 106, according to various embodiments. The in Fig. The eight slave nodes 104 shown have different numbers of sensor / actuator elements, and consequently, different amounts of data can be sent to or received from the different slave nodes 104. In particular, slave node 1 has two elements, slave node 4 has four elements, and slave node 5 has three elements, so that the data transmitted by the master node 102 has two time slots for slave node 1, four time slots for slave node 4, and three time slots for slave node 5. Similarly, slave node 0 has three elements, slave node 2 has three elements, slave node 3 has three elements, slave node 6 has one element, and slave node 7 has four elements, so that the data transmitted upstream by these slave nodes 104 has the corresponding number of time slots.It should be noted that there need not be a one-to-one correlation between elements and time slots. For example, a microphone array with three microphones contained in the peripheral device 108 may include a DSP that combines signals from these three microphones (and possibly also information received from the master node 102 or from other slave nodes 104) to create a single data sample which, depending on the type of processing, may correspond to a single time slot or to multiple time slots.

[0084] In Fig. 8. The master node 102 transmits a synchronization control frame (SCF), followed by data for loudspeakers (SD) coupled to the specific slave nodes 104. Each subsequent slave node 104 forwards the SCF and also forwards at least any data intended for downstream slave nodes 104. A specific slave node 104 may forward all data or may remove data specific to that slave node 104. When the last slave node 104 receives the SCF, it transmits the synchronization response frame (SRF), optionally followed by any data that the slave node 104 is authorized to transmit. Each subsequent slave node 104 forwards the SRF along with any data from downstream slave nodes 104 and optionally inserts data from one or more microphones that are coupled to the special slave nodes 104 (MD). In the example of Fig. 8 The master node sends 102 data to the slave nodes 1, 4 and 5 (in Fig. 8 represented as active speakers) and receives data from slave nodes 7, 6, 3, 2 and 0 (in Fig. 8 represented as microphone arrays).

[0085] Fig. Figure 9 schematically illustrates the dynamic removal of data from a downstream transmission and the insertion of data into an upstream transmission, from the perspective of the downstream DS transmit-receiver 124, according to various embodiments. Fig. 9 is transmitted by the master node 102, just like in Fig. 8, an SCF, followed by data for slave nodes 1, 4, and 5 (SD) in reverse order (e.g., data for slave node 5 is followed by data for slave node 4, data for slave node 1 is followed by data for slave node 5, and so on) (see the line labeled MASTER). When slave node 1 receives this transmission, it removes its own data and forwards only the SCF, followed by the data for slave nodes 5 and 4, to slave node 2. Slave nodes 2 and 3 forward the data unchanged (see the line labeled SLAVE 2), so the data forwarded by slave node 1 is received by slave node 4 (see the line labeled SLAVE 3). Slave node 4 removes its own data and forwards only the SCF, followed by the data for slave node 5, to slave node 5, and slave node 5 similarly removes its own data and forwards only the SCF to slave node 6.Slave node 6 forwards the SCF to slave node 7 (see the line labeled SLAVE 6).

[0086] At this point, slave node 7 transmits the SRF, followed by its data (see the line labeled SLAVE 6), to slave node 6. Slave node 6 forwards the SRF, along with the data from slave node 7 and its own data, to slave node 5. Slave node 5, in turn, forwards the SRF, along with the data from slave nodes 7 and 6, to slave node 4. Slave node 4 has no additional data to add, so it simply forwards the data to slave node 3 (see the line labeled SLAVE 3), which forwards the data, along with its own data, to slave node 2 (see the line labeled SLAVE 2). Slave node 2, in turn, forwards the data, along with its own data, to slave node 1. Slave node 1 has no data to add, so it forwards the data to slave node 0, which forwards the data along with its own data.As a result, the master node 102 receives the SRF, followed by the data from the slave nodes 7, 6, 3, 2 and 0 (see the row labeled MASTER).

[0087] Fig. Figure 10 illustrates another example of dynamically removing data from a downstream transmission and inserting data into an upstream transmission, from the perspective of the downstream DS transmit-receiver 124, as shown in Fig. 9, although in Fig. 10. The slave nodes 104 are coupled to both sensors and actuators as the peripheral device 108, so that the master node 102 sends data downstream to all of the slave nodes 104 and receives data back from all of the slave nodes 104. The data is also in Fig. 10 are ordered based on the node address for which they are intended or from which they originate. The data slot labeled "Y" can be used for data integrity checking or data correction.

[0088] Fig. Figure 11 illustrates another example of dynamically removing data from a downstream transmission and inserting data into an upstream transmission, from the perspective of the downstream DS transmit-receiver 124, as shown in Fig. 9, although the data in Fig. 11. Downstream and upstream data are transmitted sequentially instead of in reverse order. Buffering in each slave node 104 allows for selective adding, removing, and / or forwarding of data.

[0089] As discussed above, each slave node 104 can remove data from downstream or upstream transmissions and / or add data to downstream or upstream transmissions. Thus, the master node 102, for example, can transmit a separate data probe to each of a number of slave nodes 104, and each such slave node 104 can remove its data probe and forward only the data intended for downstream slaves. Conversely, a slave node 104 can receive data from a downstream slave node 104 and forward the data along with additional data. One advantage of transmitting as little information as necessary is to reduce the total amount of power consumed by the system 100.

[0090] System 100 can also support broadcast transmissions (and multicast transmissions) from the master node 102 to the slave nodes 104, specifically through a configuration of the downstream slot utilization of the slave nodes 104. Each slave node 104 can process the broadcast transmission and forward it to the next slave node 104, although a specific slave node 104 can "consume" the broadcast message (i.e., not forward the broadcast transmission to the next slave node 104).

[0091] System 100 can also support upstream transmissions (e.g., from a dedicated slave node 104 to one or more other slave nodes 104). Such upstream transmissions can include unicast, multicast, and / or broadcast upstream transmissions. With upstream addressing, as discussed above with regard to downstream transmissions, a slave node 104 can determine whether or not to remove data from an upstream transmission and / or whether or not to forward an upstream transmission to the next upstream slave node 104, based on the configuration of the upstream slot usage of the slave nodes 104. Thus, for example, data can be forwarded by a dedicated slave node 104 to one or more other slave nodes 104 in addition to or instead of forwarding the data to the master node 102. Such slave-slave relationships can be configured, for example, via the master node 102.

[0092] Thus, in various embodiments, the slave nodes 104 can operate as active / intelligent repeater nodes with the ability to selectively forward, discard, and add information. The slave nodes 104 can generally perform such functions without necessarily decoding / examining all of the data, since each slave node 104 knows the relevant timeslot(s) within which it receives / transmits data and can therefore remove data from or add data to a timeslot. Despite not having to decode / examine all data, the slave nodes 104 can typically re-clock the data they transmit / forward. This can improve the robustness of the system 100.

[0093] In some embodiments, the bus 106 can be configured for unidirectional communication in a ring topology. Fig. Figure 12 illustrates, for example, an arrangement 1200 of the master node 102 and four slave nodes 104 in a ring topology and illustrates signaling and timing considerations for unidirectional communication in the arrangement 1200, according to various embodiments. In such embodiments, the node transceivers 120 can have a receive-only transceiver (MASTER IN) and a transmit-only transceiver (MASTER OUT) instead of two bidirectional transceivers for upstream and downstream communication. In the one shown in Fig. In the illustrated data link synchronization scheme 12, the master node 102 transmits an SCF 180, optionally followed by "downstream" data 1202, for the three loudspeakers coupled to different slave nodes 104 (the data for the different loudspeakers can be arranged in any suitable order, as above with reference to the Fig. (discussed in 8-11), and each subsequent slave node 104 forwards the synchronization control frame 180 together with any "upstream" data from previous slave nodes 104 and its own "upstream" data to provide "upstream" data 1204 (e.g., the data from the eight different microphones can be arranged in any suitable order, as above with reference to the Fig. Discussed in sections 8-11).

[0094] As described herein, data can be communicated between elements of the system 100 in any number of ways. In some embodiments, data can be sent as part of a set of synchronous data slots upstream by a slave node 104 (e.g., using data slots 199) or downstream by a slave node 104 or a master node 102 (e.g., using data slots 198). The amount of such data can be adjusted by changing the number of bits in a data slot or by including additional data slots. Data can also be communicated in the system 100 by inclusion in a synchronization control frame 180 or a synchronization response frame 197. Data communicated in this way can be I2C control data from the host 110 (with a response from a peripheral device 108 associated with a slave node 104); Accesses to registers of slave node 104 (e.g.for the discovery and configuration of slots and interfaces), which may include a write access from the host 110 / master node 102 to a slave node 104 and a read access from a slave node 104 to the host 110 / master node 102; and include event signaling via interrupts from a peripheral device 108 to the host 110. In some embodiments, GPIO pins may be used to transmit information from a slave node 104 to the master node 102 (e.g., by the master node 102 querying the GPIO pins via I2C or by a node transceiver 120 of a slave node 104 generating an interrupt on an interrupt request pin). In some such embodiments, for example, a host 110 can send information via I2C to the master node 102, and then the master node 102 can send this information to the slave via the GPIO pins.Any data types discussed herein as being transmitted via bus 106 may be transmitted using any one or more of these communication paths. Further data types and data communication techniques within system 100 may be disclosed herein.

[0095] Embodiments of the present disclosure can be implemented in a system using any suitable hardware and / or software to configure it as desired. Fig. Figure 13 schematically illustrates a device 1300 that can serve as a host or a node (e.g., a host 110, a master node 102, or a slave node 104) in the system 100, according to various embodiments. A number of components are shown in Fig. 13 is illustrated as contained in the device 1300, but one or more of these components may be omitted or duplicated as is appropriate for the application.

[0096] In addition, in various embodiments, the device 1300 may not have one or more of the features described in Fig. Figure 13 illustrates the components, but the device 1300 may have an interface circuit arrangement for coupling with one or more of the components. For example, the device 1300 may not have a display device 1306, but may have a display device interface circuit arrangement (e.g., a connector and a driver circuit arrangement) to which a display device 1306 can be coupled. In another set of examples, the device 1300 may not have an audio input device 1324 or an audio output device 1308, but may have an audio input or audio output device interface circuit arrangement (e.g., a connector and a support circuit arrangement) to which an audio input device 1324 or an audio output device 1308 can be coupled.

[0097] The device 1300 may include the node transceiver 120, according to any embodiment disclosed herein, for managing communication along the bus 106 when the device 1300 is coupled to the bus 106. The device 1300 may include a processing device 1302 (e.g., one or more processing devices), which may be contained within the node transceiver 120 or be separate from the node transceiver 120. As used herein, the term "processing device" may refer to any device or part of a device that processes electronic data from registers and / or a memory to transform such electronic data into other electronic data that can be stored in registers and / or a memory.The processing device 1302 can comprise one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors, or any other suitable processing devices. The device 1300 can comprise a memory 1304, which in turn can comprise one or more memory devices, such as non-persistent memory (e.g., dynamic random-access memory (DRAM)), persistent memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk.

[0098] In some embodiments, the memory 1304 can be used to store a working copy and a permanent copy of programming instructions to cause the device 1300 to perform any suitable techniques disclosed herein. In some embodiments, machine-accessible media (including non-volatile, computer-readable storage media), methods, systems, and devices for performing the techniques described above are illustrative examples of embodiments disclosed herein for communication over a two-wire bus. For example, a computer-readable medium (e.g., the memory 1304) can contain instructions stored thereon which, when executed by one or more of the processing devices included in the processing device 1302, cause the device 1300 to perform any techniques disclosed herein.

[0099] In some embodiments, the device 1300 may include another communication chip 1312 (e.g., one or more communication chips). The communication chip 1312 may, for example, be configured to manage wireless communications for the transfer of data to and from the device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data over a non-solid medium by means of modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although this may be the case in some embodiments.

[0100] The 1312 communication chip can implement any of a number of wireless standards or protocols, including, but not limited to, standards of the Institute for Electrical and Electronic Engineers (IEEE), including WiFi (IEEE 802.11 family), IEEE 802.16 standards (e.g. IEEE 802.16-2005 Supplement), Long-Term Evolution (LTE) project along with any additions, updates and / or revisions (e.g. Advanced LTE project, Ultra-Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The one or more 1312 communication chips can operate in a network according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE. The one or more 1312 communication chips can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The one or more 1312 communication chips can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as according to any other wireless protocols referred to as 3G, 4G, 5G, and beyond.The communication chip 1312 can operate according to other wireless protocols in other embodiments. The device 1300 can have an antenna 1322 to enable wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0101] In some embodiments, the 1312 communication chip can manage wired communications using a protocol other than the one described herein for bus 106. Wired communications can include electrical, optical, or any other suitable communication protocols. Examples of wired communication protocols that can be enabled by the 1312 communication chip include Ethernet, Controller Area Network (CAN), I2C, Media Oriented System Transport (MOST), or any other suitable wired communication protocols.

[0102] As noted above, the 1312 communication chip can contain multiple communication chips. For example, a first 1312 communication chip can be dedicated to shorter-range wireless communications, such as WiFi or Bluetooth, and a second 1312 communication chip can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first 1312 communication chip can be dedicated to wireless communications and a second 1312 communication chip can be dedicated to wired communications.

[0103] The device 1300 can include a battery / power circuit arrangement 1314. The battery / power circuit arrangement 1314 can include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit arrangements for coupling components of the device 1300 to a power source separate from the device 1300 (e.g., AC mains power supply, voltage provided by a car battery, etc.). For example, the battery / power circuit arrangement 1314 can include the upstream bus interface circuit arrangement 132 and the downstream bus interface circuit arrangement 131, which are described above with reference to Fig. 2 were discussed, and could be loaded via the bias on bus 106.

[0104] The device 1300 can include a display device 1306 (or a corresponding interface circuit arrangement, as discussed above). The display device 1306 can, for example, include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0105] The device 1300 can include an audio output device 1308 (or a corresponding interface circuit arrangement, as discussed above). The audio output device 1308 can include any device that produces an audible indicator, such as a loudspeaker, headphones, or earphones.

[0106] The device 1300 can include an audio input device 1324 (or a corresponding interface circuit arrangement, as discussed above). The audio input device 1324 can include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a digital musical instrument interface (MIDI) output).

[0107] The device 1300 can include a GPS device 1318 (or a corresponding interface circuit arrangement, as discussed above). The GPS device 1318 can communicate with a satellite-based system and, as is known in the art, can receive a location data for the device 1300.

[0108] The device 1300 may include another output device 1310 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. In addition, any suitable peripheral devices 108 discussed herein may be included in the other output device 1310.

[0109] The device 1300 may include another input device 1320 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 1320 may include an accelerometer, a gyroscope, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, or a radio frequency identification (RFID) reader. In addition, any suitable sensors or peripheral devices 108 discussed herein may be included in the other input device 1320.

[0110] Any suitable display, input, output, communication, or storage devices from those described above with reference to device 1300 may serve as the peripheral device 108 in the system 100. Alternatively or additionally, suitable display, input, output, communication, or storage devices from those described above with reference to device 1300 may be included in a host (e.g., host 110) or a node (e.g., a master node 102 or a slave node 104).

[0111] As noted above, in some embodiments, the System 100 can be a single-master, multiple-slave system, in which the master node 102 configures and manages the System 100 using a bus 106 (which may, for example, have a single differential wire pair). Digital synchronous data (e.g., audio data), control information, and / or power can be transmitted over this bus 106. The System 100 can also provide a multi-channel I2S / TDM link between nodes. However, if the system 100 has a single master node 102, the operation of the system 100 may be subject to a risk of failure if the master node 102 is rendered inoperable (e.g., if the host device 110 fails or the transceiver 120 of the master node 102 fails) or is disconnected from the rest of the system 100 (e.g., by an interruption in the bus 106 between the master node 102 and the slave nodes 104).As used herein, the phrase “the master node 102 is disconnected” can be used to refer in any way where the master node 102 is no longer able to control the operation of the system 100 (e.g., when the master node 102 is inoperative, when the bus 106 between the master node 102 and another part of the system 100 is inoperative, etc.).

[0112] This document discloses arrangements and techniques in which one or more of the slave nodes 104 function as an auxiliary master node if the master node 102 is unable to control the system 100. Such a dual-function slave node 104 is referred to herein as an "auxiliary master node 104'"; slave nodes 104 that are not auxiliary master nodes 104' are referred to herein as slave nodes 104-2, 104-3, ..., 104-N. Although several of the accompanying drawings illustrate a single auxiliary master node 104' in a communication system 100, this is for the sake of simplicity, and a system 100 may have multiple auxiliary master nodes 104' (for example, to provide multiple levels of redundancy).For example, if the communication system 100 is used in a vehicle, several different auxiliary master nodes 104' can be located at different positions within the vehicle in case a collision renders part of the communication system 100 inoperable. Furthermore, although several of the accompanying drawings illustrate the auxiliary master node 104' as being "adjacent" to the master node 102 along the bus 106, this is for the sake of simplicity, and in some embodiments, one or more slave nodes 104 can be located between the master node 102 and the auxiliary master node 104' along the bus 106.

[0113] Fig. Figure 14 is a block diagram of a communication system 100 that includes an auxiliary master node 104'. In particular, the communication system 100 includes a host 110 in communication with a master node 102 (e.g., according to any of the above with reference to Fig. The communication system 100 comprises an auxiliary master node 104' (which functions as a slave node when the master node 102 is connected) and one or more additional slave nodes 104 (including a final slave node 104-N). The nodes 102 / 104 are daisy-chained together by links of a two-wire bus 106, according to any of the embodiments discussed herein. The communication system 100 also includes a processing device 109, which can function as an auxiliary host (in place of the host 110) for the auxiliary master node 104' when the master node 102 is disconnected. The processing device 109 can be a peripheral device 108 associated with the auxiliary master node 104'. In some embodiments, the processing device 109 can be a microcontroller or a DSP.

[0114] The processing device 109 can communicate with the auxiliary master node 104' according to any of the embodiments discussed herein with respect to communication between the host 110 and the master node 102, and some specific examples are discussed in more detail below. If the master node 102 is disconnected, then the auxiliary master node 104' can act as a master node and the processing device 109 can act as a host to continue the operation of the communication system 100 (e.g., to avoid interference with a telephone call or Bluetooth connection, to maintain audio content, to maintain the delivery of a radio program, or to enable the making of emergency calls, as discussed further below). The subsystem controlled by the auxiliary master node 104' (e.g.,(if the master node 102 is disconnected) may be referred to herein as the auxiliary system 140 and may include the auxiliary master node 104' and additional slave nodes 104 downstream from the auxiliary master node 104'.

[0115] Any slave node 104 in a system 100 can be an auxiliary master node 104'. An auxiliary master node 104' can be trained to perform operations that the master node 102 is also trained to perform, but that the slave nodes 102-2 are not. For example, an auxiliary master node 104' can be trained to perform a full discovery along bus 106. An auxiliary master node 104' can also be trained to detect when the master node 102 is disconnected from system 100, to configure and run system 100 until the master node 102 is reconnected, and to detect the reconnection of the master node 102. In some embodiments, the configuration of an auxiliary master node 104' as a slave node or as a master node can be controlled by the processing device 109; a number of such embodiments are discussed below.

[0116] Fig. Figure 15 is a flowchart of a procedure 1400 for providing the auxiliary master functionality in the communication system 100 of Fig. 14, according to various embodiments. The method 1400 can be carried out by the processing device 109 (in communication with the auxiliary master node 104').

[0117] At 1402, the processing device 109 can start in a powered-off or reset state. The processing device 109 can remain in this state until power is supplied to it or a reset of the processing device 109 is completed. At that point, the processing device 109 can transition to 1404 and be powered on (e.g., load program instructions to perform the remaining operations of procedure 1400). After powering on at 1404, the processing device 109 can determine whether a voltage bias exists on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104' (e.g., the link of the two-wire bus 106 that "points" to the master node 102). The presence of this bias can indicate whether the master node 102 is connected or not. If the bias is not present, the master node 102 can be disconnected, and vice versa.If processing device 109 determines that the bias is present on the upstream link of bus 106, processing device 109 can proceed to 1406 and either 1) configure itself for slave node operation and assume that the auxiliary master node 104' is configured as a slave by master node 102 via bus link 106, or 2) communicate with the auxiliary master node 104' to configure it as a slave device. After configuring processing device 109 for slave operation at 1406, if processing device 109 determines that the bias is no longer present on the upstream link of bus 106, processing device 109 can proceed to 1402 and be reset.On the other hand, after configuring the processing device 109' as a slave at 1406, the processing device 109 can determine whether the auxiliary master node 104' has been discovered by the master node 102 and, if so, can enter a wait state 1408. In wait state 1408 (or any of the wait states disclosed herein), the processing device 109 can perform slave node processing as desired. The discovery of the auxiliary master node 104' by the master node 102 can be signaled to the processing device 109 by the auxiliary master node 104' (e.g., using an I / O pin of the auxiliary master node 104', as discussed below).In some embodiments, the signaling to the processing device indicating that the auxiliary master node 104' has been detected by the master node 102 can be used to trigger the transition from the off / reset state 1402 to the power-up state 1404, instead of or in addition to the upstream bus bias triggering this transition.

[0118] The processing device 109 can remain in the wait state 1408 until a normal shutdown command is received or upstream communication along bus 106 is lost. In some embodiments, a normal shutdown command can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109). If a normal shutdown command is received by the processing device 109 while it is in the wait state 1408, the processing device 109 can proceed to the powered-off / reset state 1402 and shut down.

[0119] If upstream communication is lost while the processing device 109 is in standby state 1408, the processing device 109 can proceed to configure itself as a host device at 1412. The processing device 109 can also proceed to configure itself as a host device at 1412 if, after starting up at 1404, the processing device 109 determines that there is no voltage bias on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104'. In some embodiments, a normal configuration change request can be provided to the processing device 109 from the host 110 / master node 102 via the bus 106 and the auxiliary master node 104' while the processing device 109 is in standby state 1408 (e.g.,by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104 and the processing device 109). If a normal configuration change request is received by the processing device 109 while it is in wait state 1408, the processing device 109 can proceed to 1412 and be reconfigured as a host.

[0120] After configuring itself as a host at 1412, the processing device 109 can communicate with the auxiliary master node 104' to configure the auxiliary master node 104' as a master device at 1414. The processing device 109 can then initiate the discovery of downstream slave node 104 at 1416 (of the auxiliary system 140) according to any of the techniques disclosed herein and then enter a wait state 1418. While in wait state 1418, if the processing device 109 determines that the upstream bus bias is present, the processing device 109 can proceed to the off / reset state 1402 and be reset, or can proceed to 1406 to reconfigure itself for slave node operation and can reconfigure the auxiliary master node 104' as a slave.

[0121] Although the startup of the processing device 109 is illustrated in several of the accompanying figures as occurring in a single stage, the startup of the processing device 109 can be performed via several different operating stages in any of the accompanying embodiments. For example, a first startup stage can be performed at 1404, while a second startup stage can take place at 1406 or 1412. The presence of a bus bias can be used to determine which of the second stages of startup operations is to be performed (e.g., 1406 if an upstream bus bias is present, and 1412 if the upstream bus bias is not present).

[0122] Fig. Figure 16 illustrates an exemplary implementation of part of the communication system 100 of Fig. 14. In particular, illustrates Fig. 16 an example of the auxiliary master node 104' (including a node transceiver 120 and an associated circuit arrangement), an example of the associated processing device 109 and exemplary interconnections between these. In Fig. 16 The auxiliary master node 104' comprises a node transceiver 120 (which may take the form of any of the node transceivers 120 disclosed herein), a bus bias detection circuit arrangement 111, an upstream bus interface circuit arrangement 132, a downstream bus interface circuit arrangement 131, and a power supply 115. The input voltage (Vin) to the power supply 115 may be provided by a battery 113-1 contained in the auxiliary master node 104' or by an external battery 113-2. In some embodiments, the battery 113-1 may be charged (e.g., trickle-charged) by the bias on the bus 106.The bus bias detection circuit arrangement 111 can be coupled to the upstream link of the two-wire bus 106 and can be configured to provide two distinct outputs: a "bus bias present" logic signal indicating whether or not a voltage bias exists between the two wires of the upstream link 106, and the "bus bias" voltage itself. The bus bias voltage can be supplied to the voltage input of the power supply 115 as shown (e.g., to allow the node transceiver 120 to power itself using the bus bias, if present). The power supply 115 can thus derive its input voltage from the bus bias and / or battery 113-1 and / or battery 113-2. The voltage output (Vout) from the power supply 115 can be received at a voltage input (Vin) of the node transmitter-receiver 120 and at a voltage input (Vin) of the processing device 109.In some embodiments, the power supply 115 may have one or more voltage regulators to generate different output voltages (e.g., also for the downstream bias or other peripheral devices in the node).

[0123] The upstream bus interface circuit arrangement 132 can be arranged between the bus bias detection circuit arrangement 111 and the upstream terminals (AP and AN) of the node transceiver 120. As discussed above, the upstream bus interface circuit arrangement 132 can terminate the bus bias, filter the differential signal provided via the bus 106, and provide protection against electromagnetic compatibility (EMC) and electrostatic discharge (ESD). The downstream bus interface circuit arrangement 131 can be arranged between the downstream terminals (BP and BN) of the node transceiver 120 and the downstream link of the two-wire bus 106 and can take the form of any of the embodiments disclosed herein.As discussed above, the downstream bus interface circuit arrangement 131 can combine the differential signal with the bus bias for transmission over bus 106, filter the differential signal provided over bus 106, and provide EMC and ESD protection.

[0124] Power supply 115 can also have an enable input that controls whether or not it provides a voltage output (Vout). The enable input of power supply 115 can be coupled to the "bus bias present" signal from bus bias detection circuitry 111 and to a "maintain" output of processing device 109. Processing device 109 generates the maintain output when it receives an indication from bus bias detection circuitry 111 that bus bias is present (i.e., via the "bus bias present" signal received at processing device 109). As discussed above, when the bus bias is removed, processing device 109 can be configured as a host, and the auxiliary master node 104 can be configured as a master device.Thus, the power supply 115 can be enabled to generate an output voltage when the bus bias is present (e.g., when the auxiliary master node 104' is operating as a slave), or the processing device generates a suitable sustain output (e.g., when the auxiliary master node 104' is operating as a master).

[0125] The processing device 109 can have an input (“Current Config.”) for receiving an indicator of the current configuration of the auxiliary master node 104’ from an output (“Configured as Slave”) of the node transceiver 120. In particular, the node transceiver 120 can use the “Configured as Slave” output to indicate to the processing device 109 whether the node transceiver 120 is currently configured as a slave or as a master. For example, the “Current Config.” and “Configured as Slave” inputs / outputs can be part of a GPIO, SPI, or I2C interface (e.g., including the node transceiver 129 discussed above) through which configuration information can be transferred. If the processing device 109 receives an indication that the node transceiver 120 is not currently configured as a slave (e.g.If the node transceiver 120 is not detected as a slave device, the processing device 109 can provide a maintain output to the power supply 115. In some embodiments, if the processing device 109 receives an indication that the node transceiver 120 is currently configured as a slave (e.g., detected as a slave device, as discussed above), the processing device 109 may not provide a maintain output to the power supply 115, whereas in other embodiments, the processing device 109 may provide a maintain output to the power supply 115 regardless of whether the node transceiver 120 is configured as a slave or as a master.In some embodiments, the processing device 109 can cease providing a sustain output to the power supply 115 when the processing device 109 undergoes a normal shutdown or otherwise wishes to shut down the auxiliary master node 104'.

[0126] The processing device 109 can have an output (“Reconfigure Node Transceiver”) for providing signals to an input (“Update Config”) of the node transceiver 120 to cause the node transceiver 120 to configure itself as a master or a slave. For example, the “Reconfigure Node Transceiver” and “Update Config” inputs / outputs can be part of a GPIO, SPI, or I2C interface (e.g., including the node transceiver 129 discussed above) through which configuration information can be transferred. The processing device 109 can cause the node transceiver 120 to reconfigure itself based on the “Bus Bias Present” signal received by the processing device 109 (e.g., as above with reference to Fig. 15 discussed).

[0127] Fig. Figure 17 is a flowchart of a procedure 1500 for providing the auxiliary master functionality in the communication system 100 of Fig. 16, according to various embodiments. The method 1500 can be carried out by the processing device 109 (in communication with the auxiliary master node 104') of Fig. 17 will be executed.

[0128] At 1502, the processing device 109 can start in a powered-off or reset state. The processing device 109 can remain in this state until power is supplied to it or a reset of the processing device 109 is completed. At that point, the processing device 109 can transition to 1504 and be powered on (e.g., load program instructions to perform the remaining operations of procedure 1500). After powering on at 1504, the processing device 109 can determine whether a voltage bias is present on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104' (e.g., the link of the two-wire bus 106 that "points" to the master node 102) via the "bus bias present" output of the bus bias detection circuit arrangement 111.The presence of this bias can indicate whether master node 102 is connected or not; if the bias is not present, master node 102 may be disconnected, and vice versa. If the processing device 109 determines that bias is present on the upstream link of bus 106 (via the "bus bias present" signal), the processing device 109 can proceed to 1506 and either 1) configure itself for slave node operation and assume that the auxiliary master node 104' is configured as a slave by the master node 102 via bus link 106, or 2) communicate with the node transceiver 120 to configure the node transceiver 120 as a slave device (via the "reconfigure node transceiver" output of the processing device 109 and the "update config" input of the node transceiver 120), and can output a maintain signal to the power supply 115.After configuring the processing device 109 for slave operation at 1506, if the processing device 109 determines that the bias on the upstream link of bus 106 is no longer present (via the "Bus bias present" signal), the processing device 109 can proceed to 1510 and stop outputting the maintain signal, and then proceed to 1502 to be reset. Otherwise, after configuring the processing device 109 as a slave at 1506, the processing device 109 can determine whether the node transceiver 120 has been discovered by the master node 102 (e.g., via the "Configured as slave" output from node transceiver 120, received at the "Current config." input of the processing device 109), and if so, it can enter a wait state 1508.

[0129] The processing device 109 can remain in the waiting state 1508 until a normal shutdown command is received or upstream communication along bus 106 is lost. In some embodiments, a normal shutdown command can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109). If a normal shutdown command is received by the processing device 109 while it is in standby state 1408, the processing device 109 can stop outputting the sustain signal at 1510 and then proceed to the off / reset state 1502 to be shut down.

[0130] If upstream communication is lost while the processing device 109 is in standby state 1508 (e.g., via the "Configured as Slave" output from node transceiver 120, which is received at the "Current Config." input of the processing device 109), the processing device 109 can proceed to configure itself as a host device at 1512 and can continue to provide a maintain signal to the power supply 115. The processing device 109 can also proceed to configure itself as a host device at 1512 and can output a maintain signal if, after starting up at 1504, the processing device 109 determines that there is no voltage bias on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104'.After configuring itself as a host at 1512, the processing device 109 can communicate with the node transceiver to configure the node transceiver 120 as a master device at 1514 (via the "Reconfigure Node Transceiver" output of the processing device 109 and the "Update Config" input of the node transceiver 120). The processing device 109 can then initiate the discovery of downstream slave node 104 at 1516 (of the auxiliary system 140) according to any of the techniques disclosed herein and then enter a wait state at 1518. While in the waiting state 1518, if the processing device 109 determines that the upstream bus bias is present, the processing device 109 can stop outputting the sustain signal at 1536 and proceed to the off / reset state 1502 to be reset.In some embodiments, the detection of the bus bias in standby state 1518 can cause the processing device 109 to advance to state 1506 while continuing to output the maintain signal. In some embodiments, only an external event (e.g., pressing a push button) allows the processing device 109 to advance from standby state 1518 to state 1502 (or any other state). Fig. Figure 18 illustrates a special embodiment of the Fig. 16 illustrated part of the communication system 100. Fig. Figure 18 illustrates specific embodiments of the bus bias detection circuit arrangement 111 and the power supply 115. In the embodiment of Fig. 18. Battery 113-1 can be a "backup" battery associated with the auxiliary master node 104, while the "external" battery 113-2 can be the "main" battery of the communication system 100 (e.g., a primary battery in a vehicle). The node transceiver 120 and the processing device 109 can communicate via an I2C or SPI interface and can also communicate via I2S / TDM I / O pins to provide the "Reconfigure Node Transceiver," "Current Config," "Update Config," and "Configured as Slave" connections. The processing device 109 can set the IO1 output high to generate the sustain signal (and set the IO1 output low to stop the sustain signal), and the IO5 input of the processing device 109 can be forced high by the master node 102 when the node transceiver 120 is configured and discovered as a slave.

[0131] In some embodiments, the Auxiliary System 140 can also provide an Auxiliary Call Assistance Functionality. As used herein, “Auxiliary Call Assistance Functionality” refers to the ability of the Auxiliary System 140 to enable a telephone call or other external communication to be made when the Master Node 102 is disconnected. For example, in a vehicle environment, the Master Node 102 and the Host 110 may be located in a vehicle head unit and together may provide a call assistance function under normal operating conditions. If a collision occurs or the head unit is otherwise damaged, causing the Master Node 102 to disconnect, the Auxiliary Call Assistance Functionality can enable a telephone call (e.g., an emergency call) to be made by the Auxiliary System 140.Although several of the Auxiliary Call Support Systems disclosed herein relate to the ability to make “telephone calls”, the Auxiliary Call Support Systems and Techniques disclosed herein can be used to provide any type of Auxiliary Messaging or External Communications functionality (e.g., SMS (Short Message Service) messages, etc.). This Messaging functionality may include wireless communication (e.g., a telephone call or SMS message may be wirelessly transferred between Communications System 100 and a cell-based or other wireless network).

[0132] Fig. Figure 19 is a block diagram of a communication system 100 with auxiliary call support functionality. A number of the elements of Fig. 19 will be combined with the communication system 100 by Fig. 14 used; these elements can be any of those herein with reference to Fig. The 14 forms discussed will be adopted and will not be repeated for the sake of clarity. In the communication system of Fig. 19 The host 110 can be coupled with call hardware 153 (which may include, for example, a modem, an antenna, analog or digital microphones, loudspeakers, ADCs, DACs, and / or any other suitable device for providing telephone functionality). Auxiliary call hardware 163 and 161 can be coupled with the auxiliary master node 104 or one or more of the slave nodes 104. The auxiliary call hardware 163 and 161 can be peripheral devices 108 for their associated nodes. The auxiliary call hardware 163 and 161 can individually include any of the exemplary elements discussed above with reference to the call hardware 153.During normal operation of the communication system 100, the call hardware 153 (together with any desired elements of the auxiliary call hardware 163 and 161) can make telephone calls; when the master node 102 is disconnected (and therefore the call hardware 153 is no longer available to make telephone calls), the auxiliary call hardware 163 and 161 can make telephone calls on the auxiliary system 140.For example, the call hardware 153 may have speakers, the auxiliary call hardware 163 may have a modem and speakers, and the auxiliary call hardware 161 may have one or more microphones. During normal operation, the speakers of the call hardware 153, the modem of the auxiliary call hardware 163, and the microphones of the auxiliary call hardware 161 can be used together to make telephone calls, while the auxiliary call hardware 163 and 161 can be used together to make telephone calls when the master node 102 is disconnected. In some embodiments, none of the slave nodes 104 are associated with any call hardware 157, and instead, the auxiliary call hardware 163 itself has all the hardware elements required to make a telephone call.

[0133] Auxiliary call hardware can be located at a different node than the auxiliary master node 104' and can be accessed via bus 106. Telephone numbers and other communication-related data can also be stored on another slave node 104, which is linked to the auxiliary master node 104' via bus 106. For example, a Bluetooth device can automatically initiate a call to the last dialed telephone number. Telephone numbers and other communication-related data can be presented directly to or to the auxiliary call hardware, or they can reside within the auxiliary call hardware (e.g., without the involvement of the auxiliary host).

[0134] Fig. Figure 20 is a flowchart of a procedure 1550 for providing the auxiliary call support functionality in the communication system 100 of Fig. 19, according to various embodiments. The method 1550 can be carried out by the processing device 109 (in communication with the auxiliary master node 104').

[0135] At 1552, the processing device 109 can start in a powered-off or reset state. The processing device 109 can remain in this state until power is supplied to it or a reset of the processing device 109 is completed. At that time, the processing device 109 can transition to 1554 and be started up (e.g., load program instructions to perform the remaining operations of procedure 1550). After starting up at 1554, the processing device 109 can determine whether a voltage bias is present on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104' (e.g., the link of the two-wire bus 106 that "points" to the master node 102). The presence of this bias can indicate whether the master node 102 is connected or not. If the bias is not present, the master node 102 can be disconnected, and vice versa.If processing device 109 determines that the bias is present on the upstream link of bus 106, processing device 109 can proceed to 1556 and either 1) configure itself for slave node operation and assume that the auxiliary master node 104' is configured as a slave by master node 102 via bus link 106, or 2) communicate with the auxiliary master node 104' to configure it as a slave device. After configuring processing device 109' for slave operation at 1556, if processing device 109 determines that the bias is no longer present on the upstream link of bus 106, processing device 109 can proceed to 1552 and be reset.On the other hand, after configuring processing device 109' as a slave, processing device 109 can determine at 1556 whether the auxiliary master node 104' has been discovered by master node 102, and if so, it can enter a wait state 1558. The discovery of the auxiliary master node 104' by master node 102 can be signaled to processing device 109 by the auxiliary master node 104' (e.g., using an I / O pin of the auxiliary master node 104', as discussed below). In some embodiments, the signaling to the processing device indicating that the auxiliary master node 104' has been detected by the master node 102 can be used to trigger the transition from the off / reset state 1552 to the power-up state 1554, instead of or in addition to the upstream bus bias triggering this transition.

[0136] The processing device 109 can remain in wait state 1558 until a normal shutdown command is received, a call initiation signal is received, the host 110 initiates a call using the auxiliary call hardware 163 (associated with the auxiliary master node 104'), or upstream communication along bus 106 is lost. In some embodiments, a normal shutdown command can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109).If a normal shutdown command is received by the processing device 109 while it is in standby state 1558, the processing device 109 can proceed to the off / reset state 1552 and shut down. In some embodiments, a normal configuration change request can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' while the processing device 109 is in standby state 1558 (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109).If a normal configuration change request is received by processing device 109 while it is in wait state 1558, processing device 109 can proceed to 1562 and reconfigure itself as a host.

[0137] In standby state 1558, if an emergency signal is received or an eCall button is pressed, the processing unit 109 can retrieve an emergency number (which is stored in memory or otherwise accessible to the processing unit 109). The emergency number might be 911, for example, in the United States. An emergency signal can be generated automatically by other hardware in the event of an emergency. In a vehicle environment, for example, an emergency signal can be generated by the vehicle after the airbags have deployed and transmitted to the processing unit 109 via a CAN bus or another secondary control bus (e.g., an emergency sensor or signal wire, not shown). An eCall button can also be manually pressed by a user to initiate the dialing of the emergency number.In standby state 1558, if a concierge button is pressed, the processing device 109 can retrieve a concierge number (which may be stored in memory or otherwise accessible to the processing device 109). The concierge number may be associated with a specialized service for providing amenities and assistance; in a vehicle environment, for example, dialing the concierge number may access a service that provides, among other things, flight bookings, hotel reservations, on-site assistance, weather information, mechanical maintenance, and / or insurance claim assistance. A concierge button may be manually pressed by a user to trigger dialing of the concierge number. Although special types of call-triggering events (e.g., emergency signals, emergency call buttons, and concierge call buttons) are included in the system, the concierge number may not be automatically dialed. Fig. Figures 20 and others of the accompanying figures illustrate this; these are simply examples and any other suitable call triggering events (e.g., automatic or manual) can be used.

[0138] After retrieving the emergency number (at 1570) or the concierge number (at 1572), the processing device 109 can signal the retrieval of the number to host 110 at 1574 (e.g., by sending a message to host 110 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109) and then wait for a response from host 110 at 1576 (e.g., by sending a message to the processing device 109 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109). If host 110 successfully indicates that the call should be initiated, the processing device 109 can make the call to the retrieved number at 1578.Procedure 1550 further illustrates that when the processing device 109 is in the wait state 1558, the processing device can receive an instruction from the host 110 to make a call to any specified number (e.g., by sending a message to the processing device 109 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109), and then the processing device 109 can proceed to make the call to 1578. When the call made to 1578 ends, the processing device 109 can return to the wait state 1558.

[0139] If host 110 does not respond while processing device 109 is waiting for a response from host 110 at 1576, or if upstream communication is lost while processing device 109 is in wait state 1558 or call state 1578 (e.g., during an emergency call), processing device 109 can proceed to configure itself as a host device at 1562. Processing device 109 can also proceed to configure itself as a host device at 1562 if, after powering up at 1554, processing device 109 determines that there is no voltage bias on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104'. After configuring itself as a host at 1562, the processing device 109 can communicate with the auxiliary master node 104' to configure the auxiliary master node 104' at 1564 as a master device.The processing device 109 can then initiate the discovery of downstream slave node 104 at 1566 (of the auxiliary system 140) according to any of the techniques disclosed herein and then enter a wait state 1568. While in wait state 1568, if the processing device 109 determines that the upstream bus bias is present, the processing device 109 can proceed to the off / reset state 1552 and be reset, or it can proceed to 1556 to reconfigure itself for slave node operation and can reconfigure the auxiliary master node 104' as a slave.

[0140] In standby state 1568, if an emergency signal is received or an eCall button is pressed, the processing device 109 can retrieve an emergency number (which is stored, for example, in memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above. In standby state 1558, if a concierge button is pressed, the processing device 109 can retrieve a concierge number (which is stored, for example, in memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above. After retrieving the emergency number (at 1580) or the concierge number (at 1582), the processing device 109 can place the call to the retrieved number at 1584. When the call made at 1584 ends, the processing device 109 can enter the off / reset state 1552 and be reset.In alternative embodiments, when the call made at 1584 ends, the processing device 109 can return to the waiting state 1568.

[0141] In alternative embodiments, the processing device 109 can move directly from 1570 to 1562 and then be reset, or it can reconfigure the auxiliary master node 104' to function as a slave.

[0142] Fig. Figure 21 illustrates an exemplary implementation of part of the communication system 100 of Fig. 19. In particular, illustrates Fig. 21 an example of the auxiliary master node 104' (including a node transceiver 120 and an associated circuit arrangement), an example of the associated processing device 109 and exemplary interconnections between these. A number of the elements of Fig. 21 will be combined with the communication system 100 by Fig. 16 used; these elements can be any of those herein with reference to Fig. The 16 forms discussed will be adopted and will not be repeated for the sake of clarity.

[0143] In the embodiment of Fig. 21 The enable input of the power supply 115 can be coupled with the "bus bias present" signal from the bus bias detection circuit arrangement 111, with the "maintain" output of the processing device 109, and with call trigger signals (e.g., emergency signal, eCall button, and concierge button). This allows the power supply 115 to generate an output voltage when the bus bias is present (e.g., when the auxiliary master node 104' is operating as a slave), the processing device to generate a suitable maintain output (e.g., when the auxiliary master node 104' is operating as a master), or a call trigger signal to be received.

[0144] The processing device 109 of Fig. 21 can have call inputs (“CALL”) that can receive various call initiation signals (e.g., emergency signal, eCall button, and concierge button) and, in response to these signals, support or control the process of making telephone calls, as described above with reference to Fig. 20 discussed. The call inputs can be, for example, any suitable I / O pins of the processing device 109.

[0145] Fig. Figure 22 is a flowchart of a procedure 1600 for providing the auxiliary master functionality in the communication system 100 of Fig. 21, according to various embodiments. The method 1600 can be carried out by the processing device 109 (in communication with the auxiliary master node 104') of Fig. 21 will be executed.

[0146] At 1602, the processing device 109 can start in a powered-off or reset state. The processing device 109 can remain in this state until power is supplied to it or a reset of the processing device 109 is completed. At that time, the processing device 109 can transition to 1604 and be powered on (e.g., load program instructions to perform the remaining operations of procedure 1500). After powering on at 1604, the processing device 109 can determine whether a voltage bias is present on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104' (e.g., the link of the two-wire bus 106 that "points" to the master node 102) via the "bus bias present" output of the bus bias detection circuit arrangement 111.The presence of this bias can indicate whether master node 102 is connected or not; if the bias is not present, master node 102 may be disconnected, and vice versa. If the processing device 109 determines that bias is present on the upstream link of bus 106 (via the "bus bias present" signal), the processing device 109 can proceed to 1606 and either 1) configure itself for slave node operation and assume that the auxiliary master node 104' is configured as a slave by the master node 102 via bus link 106, or 2) communicate with the auxiliary master node 104' to configure the auxiliary master node 104' as a slave device (via the "reconfigure node transceiver" output of the processing device 109 and the "update config" input of the node transceiver 120), and can output a maintain signal to the power supply 115.After configuring the processing device 109 for slave operation at 1606, if the processing device 109 determines that the bias on the upstream link of bus 106 is no longer present (via the "Bus bias present" signal), the processing device 109 can proceed to 1610 and stop outputting the maintain signal, and then proceed to 1602 to be reset. Alternatively, after configuring the processing device 109 for slave operation at 1606, the processing device 109 can determine whether the node transceiver 120 has been discovered by the master node 102 (e.g., via the "Configured as slave" output from node transceiver 120, received at the "Current config." input of the processing device 109), and if so, it can enter a wait state 1608.

[0147] The processing device 109 can remain in wait state 1608 until a normal shutdown command is received, a call initiation signal is received, the host 110 initiates a call using the auxiliary call hardware 163 (associated with the auxiliary master node 104'), or upstream communication along bus 106 is lost. In some embodiments, a normal shutdown command can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109).If a normal shutdown command is received by the processing device 109 while it is in the wait state 1608, the processing device 109 can proceed to state 1610 and stop outputting the sustain signal, and then proceed to the off / reset state 1602 to be shut down. In some embodiments, a normal configuration change request can be provided to the processing device 109 from the host 110 / master node 102 via bus 106 and the auxiliary master node 104' while the processing device 109 is in the wait state 1658 (e.g., by sending a message to the processing device 109 using mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109).If a normal configuration change request is received by the processing device 109 while it is in standby state 1658, the processing device 109 can proceed to 1662 and reconfigure itself as a host while continuing to provide a sustain signal to the power supply 115.

[0148] In standby state 1608, if an emergency signal is received (e.g., via the CALL inputs of the processing device 109) or if an emergency call ("eCall") button is pressed (e.g., via the CALL inputs of the processing device 109), the processing device 109 can retrieve an emergency number (which is, for example, stored in a memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above. In standby state 1608, if a concierge button is pressed (e.g., via the CALL inputs of the processing device 109), the processing device 109 can retrieve a concierge number (which is, for example, stored in a memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above.After retrieving the emergency number (at 1620) or the concierge number (at 1622), the processing device 109 can signal the retrieval of the number to host 110 at 1624 (e.g., by sending a message to host 110 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109) and then wait at 1626 for a response from host 110 (e.g., by sending a message to the processing device 109 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109). If host 110 successfully indicates that the call should be initiated, the processing device 109 can make the call to the retrieved number at 1628.Procedure 1600 further illustrates that when the processing device 109 is in the wait state 1608, the processing device can receive an instruction from the host 110 to make a call to any specified number (e.g., by sending a message to the processing device 109 using the mailbox functionality over an I2C connection between the auxiliary master node 104' and the processing device 109), and then the processing device 109 can proceed to make the call to 1628. When the call made to 1628 ends, the processing device 109 can return to the wait state 1608.

[0149] If host 110 does not respond while processing device 109 is waiting for a response from host 110 at 1626, or if upstream communication is lost (e.g., via the "Configured as Slave" output from node transceiver 120, which is received at the "Current Config." input of processing device 109), while processing device 109 is in wait state 1608 or call state 1628, processing device 109 can proceed to configure itself as a host device at 1612 and can continue providing a maintain signal to power supply 115.The processing device 109 can also proceed to configure itself as a host device at 1612 and can output a maintain signal if, after powering up at 1604, the processing device 109 determines that there is no voltage bias on the upstream link of the two-wire bus 106 coupled to the auxiliary master node 104'. After configuring itself as a host at 1612, the processing device 109 can communicate with the node transceiver 120 to configure the node transceiver 120 as a master device at 1614 (via the "Reconfigure Node Transceiver" output of the processing device 109 and the "Update Config" input of the node transceiver 120).The processing device 109 can then initiate the discovery of downstream slave node 104 at 1616 (of the auxiliary system 140) according to any of the techniques disclosed herein and then enter a wait state 1618. While in wait state 1618, if the processing device 109 determines that the upstream bus bias is present, the processing device 109 can proceed to the off / reset state 1602, or it can proceed to 1606 to reconfigure itself for slave node operation and can reconfigure the auxiliary master node 104' as a slave (while continuing to output the sustain signal for the power supply 115).

[0150] In standby state 1618, if an emergency signal is received or if an emergency call ("eCall") button is pressed (e.g., via the CALL inputs of the processing device 109), the processing device 109 can retrieve an emergency number (which is, for example, stored in memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above. In standby state 1618, if a concierge button is pressed, the processing device 109 can retrieve a concierge number (which is, for example, stored in memory or otherwise accessible to the processing device 109), according to any of the embodiments discussed above. After retrieving the emergency number (at 1630) or the concierge number (at 1632), the processing device 109 can place the call to the retrieved number at 1634.When the call made at 1634 ends, the processing device 109 can enter the off / reset state 1602 and be reset. In alternative embodiments, when the call made at 1634 ends, the processing device 109 can return to the standby state 1618.

[0151] In some embodiments, the detection of a bus bias in standby state 1618 can cause the processing device 109 to advance to 1606 while continuing to output the sustain signal. In some embodiments, an external event (e.g., actuation of a push button or the absence of a bus bias) can cause the processing device 109 to advance from standby state 1618 to 1602 (or any other state). In some embodiments, the processing device 109 can advance directly from 1620 to 1612 and be reset, or it can reconfigure the auxiliary master node 104' to function as a slave while continuing to output the sustain signal for the power supply 115.

[0152] Fig. 23 illustrates a special embodiment of the Fig. 21 illustrated parts of the communication system 100. A number of the elements of Fig. 23 will be combined with the communication system 100 by Fig. 18 used; these elements can be any of those herein with reference to Fig. The 18 forms discussed will be used and will not be repeated for the sake of clarity. Signal lines for the emergency signal and the eCall button signal are in Fig. Figure 23 shows the diagram, but an analog signal line for a concierge key signal has been omitted for the sake of clarity. The processing device 109 can set the IO1 output high to generate the sustain signal (and set the IO1 output low to stop the sustain signal), and the IO5 input of the processing device 109 can go high when the node transceiver 120 is configured and discovered as a slave. Changes in the IO2 and IO3 signals can be translated by the processing device 109 into messages for the host 110 (e.g., interrupts, control messages, GPIO-to-GPIO signals, etc.).

[0153] The call hardware 153 and the auxiliary call hardware 163 and 161 can take any number of forms. Fig. Figure 24 illustrates an exemplary communication system 100 with auxiliary call support functionality. In particular, it illustrates Fig. 24A a communication system 100 under normal conditions (i.e. when the master node 102 is connected) and Fig. Figure 24B illustrates communication system 100 under auxiliary operating conditions (i.e., when the master node 102 is disconnected). Communication system 100 of Fig. 24 features a main unit 123, which includes the master node 102 and the host 110 (which may take any of the forms disclosed herein). The main unit 123 can perform speech processing operations during normal operation. The call hardware 153 associated with the master node 102 / host 110 has one or more loudspeakers, as shown. The communication system 100 of Fig. 24 also features an auxiliary master node 104' communicating with a processing device 109 (via an I2S / TDM interface) and communicating with a set of auxiliary call hardware 163, including an amplifier 121 (which may, for example, include one or more ADCs, DACs, codecs, etc.), a modem / antenna 119, one or more loudspeakers, and one or more microphones (e.g., analog or digital microphones), as shown. The communication system 100 of Fig. 24 also features one or more slave nodes 104 with auxiliary call hardware 161, which includes additional microphones (e.g., analog or digital microphones). To the left of the two-wire communication bus 106, the master node 120, the auxiliary master node 104, and the slave nodes 104 can be coupled, as shown.

[0154] During the in Fig. 24A depicted normal operation can include calls made in accordance with the procedures of Fig. 20 and Fig. 22, using the microphones of the auxiliary call hardware 161, the modem / antenna 119 of the auxiliary call hardware 163, and the speakers of the call hardware 153. During the in Fig. The auxiliary operating mode shown in 24B can be used for calls made according to the procedures of Fig. 20 and Fig. 22, the modem / antenna 119, the loudspeakers and microphones of the auxiliary call hardware 163 are used. In some embodiments, during normal operating mode, calls made according to the procedures of Fig. 20 and Fig. 22, using the microphones and speakers of the auxiliary call hardware 163 and the modem / antenna 119 of the auxiliary call hardware 163 under the control of the main unit 123 (i.e., the host 110 and the master node 102).

[0155] Fig. Figure 25 illustrates another exemplary communication system 100 with auxiliary call support functionality. In particular, it illustrates Fig. 25A a communication system 100 under normal conditions (i.e. when the master node 102 is connected) and Fig. Figure 25B illustrates communication system 100 under auxiliary operating conditions (i.e., when the master node 102 is disconnected). Communication system 100 of Fig. 25 features a main unit 123 containing the master node 102 and the host 110 (which may take any of the forms disclosed herein). The call hardware 153 associated with the master node 102 / host 110 has one or more loudspeakers, as shown. The communication system 100 of Fig. 25 also features an auxiliary master node 104' communicating with a processing device 109 (via an I2S / TDM interface) and communicating with a set of auxiliary call hardware 163, including an amplifier 121, a modem / antenna 119, and one or more loudspeakers, as shown. The communication system 100 of Fig. 25 also features one or more slave nodes 104 with auxiliary call hardware 161, which includes additional microphones. To the left of the two-wire communication bus 106, the master node 102, the auxiliary master node 104, and the slave nodes 104 can be coupled, as shown.

[0156] During the in Fig. 25A depicted normal operation can include calls made in accordance with the procedures of Fig. 20 and Fig. 22, using the microphones of the auxiliary call hardware 161, the modem / antenna 119 of the auxiliary call hardware 163, and the speakers of the call hardware 153. During the in Fig. The auxiliary operating mode shown in section 25B can be used for calls made according to the procedures of Fig. 20 and Fig. 22, the modem / antenna 119 and the speakers of the auxiliary call hardware 163, as well as the microphones of the auxiliary call hardware 161, can be used. In some embodiments, during normal operating mode, calls made according to the procedures of Fig. 20 and Fig. 22, the loudspeakers of the auxiliary call hardware 163 and the modem / antenna 119 of the auxiliary call hardware 163 are used under the control of the main unit 123 (i.e., the host 110 and the master node 102).

[0157] In summary, systems and techniques for auxiliary master and / or auxiliary call support functionality are disclosed. In some embodiments, for example, a communication system with auxiliary master functionality may have a master node coupled to several downstream slave nodes, wherein at least one of the slave nodes can perform master node functions when the master node is disconnected from the system.

[0158] The following paragraphs provide examples of various embodiments disclosed herein.

[0159] Example 1 is a device with auxiliary master functionality in a communication system, comprising: a node transceiver, wherein the node transceiver has an upstream transceiver circuit arrangement for receiving a signal transmitted over two upstream wires of a two-wire bus from an upstream master node transceiver, and a downstream transceiver circuit arrangement for receiving a signal transmitted over two downstream wires of the two-wire bus from a downstream slave node transceiver; wherein the node transceiver is to operate as a slave when communication with the master node transceiver is functional, and the node transceiver is to (1) selectively operate as a slave or as a master, or (2) operate as a master when communication with the master node transceiver is not functional or is not desired (e.g.,(if it is preferred that an emergency call should never involve the master node transceiver).

[0160] Example 2 includes the subject matter of Example 1 and further specifies that the node transceiver should operate as a slave when the upstream transceiver circuitry receives a voltage bias between the two upstream wires of the two-wire bus, and that the node transceiver should operate as a master when the upstream transceiver circuitry does not receive a voltage bias between the two upstream wires of the two-wire bus.

[0161] Example 3 includes the subject matter of Example 1 and further includes: a processing device that is communicatively coupled to the node transceiver, wherein the processing device is to detect whether communication with the master node transceiver is functional and is to provide a signal to the node transceiver to cause the node transceiver to operate as a slave or as a master, depending on whether communication with the master node transceiver is functional.

[0162] Example 4 includes the subject matter of Example 3 and further specifies that the processing device is communicatively coupled to the node transceiver via an Inter-Integrated Circuit Sound (I2S) / Time Division Multiplex (TDM) bus, a Serial Peripheral Interface (SPI) bus or an Inter-Integrated Circuit (I2C) bus.

[0163] Example 5 includes the subject matter of one of Examples 3-4 and further specifies that the processing device should configure itself as a host for the communication system when communication with the master node transceiver is not functional or is not desired.

[0164] Example 6 includes the subject matter of one of Examples 3-5 and further specifies that the processing device shall also receive a signal indicating wireless communication to be initiated when communication with the master node transceiver is not functioning or is not desired, and shall initiate wireless communication in response to the signal.

[0165] Example 7 includes the subject matter of Example 6 and further specifies that the signal indicating wireless communication is an emergency signal.

[0166] Example 8 includes the subject of Example 7 and further specifies that the signal indicating wireless communication is received via a Controller Area Network (CAN) bus.

[0167] Example 9 includes the subject matter of Example 6 and further specifies that the signal indicating wireless communication is triggered by a manual call button.

[0168] Example 10 includes the subject matter of Example 6 and further specifies that the signal indicating wireless communication is triggered by a concierge call button.

[0169] Example 11 includes the subject matter of any of Examples 6-10 and further includes: a modem coupled to the processing device to carry out wireless communication.

[0170] Example 12 includes the subject of Example 11 and further includes the following: an antenna coupled to the modem.

[0171] Example 13 includes the subject matter of one of Examples 6-12 and further includes: a microphone communicatively coupled to the node transceiver, wherein the wireless communication is a telephone call and the outgoing data for the telephone call is to be provided by the microphone.

[0172] Example 14 includes the subject of Example 13 and further specifies that the microphone is communicatively coupled to the node transceiver at least partially by means of an Inter-Integrated-Circuit-Sound(I2S) / Time-Division-Multiplex(TDM) bus or a Pulse-Density Modulation(PDM) interface.

[0173] Example 15 includes the subject matter of one of Examples 6-14 and further specifies that the node transceiver is a first node transceiver, wherein the first node transceiver has a downstream transceiver circuit arrangement for receiving a signal transmitted over two downstream wires of the two-wire bus from a second node transceiver, the wireless communication is a telephone call, and outgoing data for the telephone call is to be provided by a microphone communicatively coupled to the second node transceiver.

[0174] Example 16 includes the subject matter of one of Examples 6-15 and further includes: a loudspeaker communicatively coupled to the node transceiver, wherein incoming data is to be output through the loudspeaker for wireless communication.

[0175] Example 17 includes the subject of Example 16 and further specifies that the loudspeaker is communicatively coupled to the node transceiver at least partially by means of an Inter-Integrated-Circuit-Sound(I2S) / Time-Division Multiplex(TDM) bus.

[0176] Example 18 includes the subject matter of one of Examples 1-17 and further specifies that the master node transceiver is located in a main unit of a vehicle.

[0177] Example 19 includes the subject matter of one of Examples 1-18 and further specifies that the master node transceiver is coupled to a host device.

[0178] Example 20 includes the subject of one of Examples 1-19 and further specifies that the node transceiver is located in a vehicle.

[0179] Example 21 is an auxiliary master device in a communication system comprising: a slave node transceiver, wherein the slave node transceiver has an upstream transceiver circuit arrangement for receiving a signal transmitted over two upstream wires of a two-wire bus from an upstream master node transceiver, and wherein the master node transceiver is coupled to a host device for the communication system;and a processing device that is communicatively coupled to the slave node transceiver, wherein the processing device is to detect whether communication between the slave node transceiver and the master node transceiver is functional, and if the communication is not functional, cause the slave node transceiver to act as an auxiliary master, and cause the processing device to act as an auxiliary host.

[0180] Example 22 includes the subject matter of Example 21 and further specifies that the processing device is to detect that communication between the slave node transceiver and the master node transceiver is functioning when the upstream transceiver circuit arrangement receives a voltage bias between the two upstream wires of the two-wire bus, and that the processing device is to detect that communication between the slave node transceiver and the master node transceiver is not functioning when the upstream transceiver circuit arrangement does not receive a voltage bias between the two upstream wires of the two-wire bus.

[0181] Example 23 includes the subject matter of one of Examples 21-22 and further specifies that the host device shall make and receive telephone calls using data received and transmitted over the two-wire bus when communication between the slave node transceiver and the master node transceiver is functioning, and the auxiliary host shall make and receive telephone calls when communication between the slave node transceiver and the master node transceiver is not functioning.

[0182] Example 24 includes the subject matter of one of Examples 21-23 and further specifies that the processing device is communicatively coupled to the slave node transceiver by means of an Inter-Integrated-Circuit-Sound(I2S) / Time-Division Multiplex(TDM) bus.

[0183] Example 25 includes the subject matter of one of Examples 21-24 and further specifies that the processing device shall receive a signal indicating a telephone call to be initiated when communication between the slave node transceiver and the master node transceiver is not functioning, and shall initiate the telephone call in response to the signal.

[0184] Example 26 includes the subject matter of Example 25 and further specifies that the signal indicating a telephone call is an emergency signal.

[0185] Example 27 includes the subject of Example 26 and further specifies that the signal indicating a telephone call is received via a Controller Area Network (CAN) bus.

[0186] Example 28 includes the subject of one of Examples 26-27 and further specifies that the signal indicating a telephone call is triggered by an airbag deployment.

[0187] Example 29 includes the subject matter of Example 25 and further specifies that the signal indicating a telephone call is triggered by a manual call button.

[0188] Example 30 includes the subject matter of Example 25 and further specifies that the signal indicating a telephone call is triggered by a concierge call button.

[0189] Example 31 includes the subject matter of one of Examples 25-30 and further includes: a modem coupled to the processing device to make the telephone call.

[0190] Example 32 includes the subject matter of Example 31 and further includes: an antenna coupled to the modem, wherein the telephone call is a wireless telephone call.

[0191] Example 33 includes the subject matter of one of Examples 25-32 and further includes: a microphone communicatively coupled to the slave node transceiver, the microphone being intended to provide outgoing data for the telephone call.

[0192] Example 34 includes the subject of Example 33 and further specifies that the microphone is communicatively coupled to the slave node transceiver at least partially by means of an Inter-Integrated-Circuit-Sound(I2S) / Time-Division-Multiplex(TDM) bus or a Pulse-Density Modulation(PDM) interface.

[0193] Example 35 includes the subject matter of one of Examples 25-34 and further specifies that the slave node transceiver is a first slave node transceiver, wherein the first slave node transceiver has a downstream transceiver circuit arrangement for receiving a signal transmitted over two downstream wires of the two-wire bus from a second slave node transceiver, and outgoing data for the telephone call is to be provided by a microphone communicatively coupled to the second slave node transceiver.

[0194] Example 36 includes the subject matter of one of Examples 25-35 and further includes: a loudspeaker that is communicatively coupled to the slave node transceiver, wherein incoming data for the telephone call is to be output through the loudspeaker.

[0195] Example 37 includes the subject of Example 36 and further specifies that the loudspeaker is communicatively coupled to the slave node transceiver at least partially by means of an Inter-Integrated-Circuit-Sound(I2S) / Time-Division Multiplex(TDM) bus.

[0196] Example 38 includes the subject matter of one of Examples 21-37 and further specifies that the master node transceiver is located in a main unit of a vehicle.

[0197] Example 39 includes the subject matter of one of Examples 21-38 and further specifies that the master node transceiver is coupled to a host device.

[0198] Example 40 includes the subject of one of Examples 21-39 and further includes the following: the master node transceiver.

[0199] Example 41 includes the subject of one of Examples 21-40 and further includes the following: the host device.

[0200] Example 42 is a method for operating as an auxiliary master in a daisy-chained two-wire communication system, comprising: receiving, by a processing device coupled to a slave node, an indication that a master node of the two-wire communication system has been disconnected; and in response to the indication, causing, by the processing device, the slave node to perform master functions for an auxiliary part of the two-wire communication system.

[0201] Example 43 includes the subject matter of Example 42 and further includes: receiving, by the processing device, an indication that the master node has been reconnected; and in response to the indication that the master node has been reconnected, causing, by the processing device, the slave node to cease performing the master functions.

[0202] Example 44 includes the subject matter of one of Examples 42-43 and further specifies that the indication that the master node has been disconnected includes a detection of no voltage bias on any part of the two-wire communication system between the master node and the slave node.

[0203] Example 45 includes the subject matter of one of Examples 42 and 44 and further includes: in response to the indication, causing the processing device to perform host functions for the auxiliary part of the two-wire communication system.

[0204] Example 46 includes the subject matter of any of Examples 42-45 and further includes: after causing the slave node to perform master functions, receiving, by the processing device, a signal indicating wireless communication to be initiated; and causing, by the processing device, the wireless communication to be initiated.

[0205] Example 47 includes the subject matter of Example 46 and further specifies that the signal includes an emergency signal, the pressing of a manual call button, or the pressing of a concierge button.

[0206] Example 48 is a communication system with auxiliary master functionality, including a master node coupled to several downstream slave nodes, wherein at least one of the slave nodes can perform master node functions when the master node is disconnected from the communication system.

[0207] Example 49 includes the subject matter of Example 48 and further specifies that a processing device coupled to at least one of the slave nodes shall perform a discovery of the at least one of the slave nodes when the master node is disconnected from the communication system.

[0208] Example 50 includes the subject matter of one of Examples 48-49 and further specifies that at least one of the slave nodes should cease performing master node functions when the master node is reconnected to the communication system.

[0209] Example 51 is a communication system with auxiliary master functionality, according to any of the embodiments disclosed herein.

[0210] Example 52 is a communication system with auxiliary call support functionality, according to any of the embodiments disclosed herein.

[0211] Example 53 is a method for using a slave node as an auxiliary master in a communication system, according to any of the embodiments disclosed herein.

[0212] Example 54 is a communication system including means for auxiliary master functionality, according to any of the embodiments disclosed herein.

[0213] Example 55 is a communication system including means for carrying out any of the methods disclosed herein.

Claims

[1] Device with auxiliary master functionality in a communication system, which has the following features: a node transceiver (104') comprising an upstream transceiver circuit arrangement (132) for receiving a signal transmitted via two upstream wires of a two-wire bus (106) from an upstream master node transceiver (102) and a downstream transceiver circuit arrangement (131) for receiving a signal transmitted via two downstream wires of the two-wire bus (106) from a downstream slave node transceiver (104), and the node transceiver (104') being selectively operable as a slave or master; a processing device (109) that is communicatively coupled to the node transceiver (104'), wherein the processing device (109) is configured to provide a signal to the node transceiver (104') to cause the node transceiver (104') to operate as a slave or master, and wherein the processing device (109) is configured to set itself up as a host for the communication system when the node transceiver (104') operates as master. [2] Device according to claim 1, wherein the node transceiver (104') operates as a slave when communication with the master node transceiver (102) is functional, and wherein the node transceiver (104') operates as a master when communication with the master node transceiver (102) is not functional. [3] Device according to claim 1, wherein the node transceiver (104') operates as a slave when the upstream transceiver circuit arrangement (132) receives a voltage bias between the two upstream wires of the two-wire bus (106), and wherein the node transceiver (104') operates as a master when the upstream transceiver circuit arrangement (132) does not receive a voltage bias between the two upstream wires of the two-wire bus (106). [4] Device according to claim 1, wherein the processing device (109) is further configured to detect whether communication with the master node transceiver (102) is functional and to provide a signal to the node transceiver (104') to operate as a slave or as a master, depending on whether communication with the master node transceiver (102) is functional. [5] Device according to claim 1, wherein the processing device (109) is further configured to receive a signal indicating a wireless communication to be initiated when the node transceiver (104') is operating as master, and to initiate wireless communication in response to the signal. [6] Device according to claim 5, wherein the wireless communication-indicating signal is an emergency signal or is triggered by a manual call button or a concierge call button. [7] Device according to claim 1, wherein the processing device (109) receives a signal indicating a telephone call to be initiated when the node transceiver (104') is operating as master, and initiates the telephone call in response to the signal. [8] Device according to claim 7, further comprising: a microphone communicatively coupled to the node transceiver (104'), the microphone being configured to provide outgoing data for the telephone call. [9] Device according to claim 7 or 8, further comprising: a loudspeaker communicatively coupled to the node transceiver (104'), the loudspeaker being configured to output incoming data of the telephone call. [10] Device with auxiliary master functionality in a communication system, which has the following features: a slave node transceiver (104'), wherein the slave node transceiver (104') comprises an upstream transceiver circuit arrangement (132) for receiving a signal transmitted via two upstream wires of a two-wire bus (106) from an upstream master node transceiver (102), and wherein the master node transceiver (102) is coupled to a host device (110) for the communication system; and a processing device (109) that is coupled to the slave node transceiver (104') for communication, wherein the processing device (109) is configured to detect whether communication between the slave node transceiver (104') and the master node transceiver (102) is functional, and, if the communication is not functional, to cause the slave node transceiver (104') to act as an auxiliary master and the processing device (109) to act as an auxiliary host. [11] Device according to claim 10, wherein the processing device (109) is configured to receive a signal indicating a telephone call to be initiated when communication between the slave node transceiver (104') and the master node transceiver (102) is not functioning, and to initiate the telephone call in response to the signal. [12] Device according to claim 11, further comprising: a microphone that is coupled to the slave node transceiver (104') for communication, with outgoing data for the telephone call being provided through the microphone. [13] Device according to claim 11 or 12, wherein the slave node transceiver (104') is a first slave node transceiver, wherein the first slave node transceiver has a downstream transceiver circuit arrangement (132) for receiving a signal transmitted via two downstream wires of the two-wire bus (106) from a second slave node transceiver, and outgoing data for the telephone call is to be provided by a microphone that is communicatively coupled to the second slave node transceiver. [14] Device according to any one of claims 11 to 13, further comprising: a loudspeaker that is coupled to the slave node transceiver (104') for communication, with incoming data for the telephone call being output through the loudspeaker. [15] Device according to any one of claims 10 to 14, wherein the master node transceiver (102) is located in a main unit of a vehicle. [16] Device according to any one of claims 10 to 15, wherein the master node transceiver (102) is coupled to a host device (110). [17] Device according to any one of claims 10 to 16, wherein the device comprises the master node transceiver (102) or the host device (110). [18] Method for operating as an auxiliary master in a daisy-chained two-wire communication system comprising: Received, by a processing device (109) coupled to a slave node (104'), an indication that a master node (102) of the daisy-chained two-wire communication system has been disconnected; in response to the indication, instigation by the processing device (109) that the slave node (104') performs master functions for an auxiliary part of the daisy-chained two-wire communication system; and in response to the indication, the processing device (109) causes the processing device (109) to perform host functions for the auxiliary part of the two-wire communication system. [19] The method of claim 18, further comprising: Received, by the processing device (109), an indication that the master node (102) has been reconnected; and In response to the indication that the master node (102) has been reconnected, cause the processing device (109) to cause the slave node (104') to stop performing the master functions. [20] The method of claim 18 or 19, further comprising: after initiating the slave node (104') to perform master functions, receiving, by the processing device (109), a signal indicating a wireless communication to be initiated; and Causing the processing device (109) to initiate wireless communication.

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