ACTIVE PEN

Abstract

Active pen, which includes the following: a first and a second electrode, which are provided in different positions; a transmission circuit that uses a booster circuit to induce a change in the first electrode in order to transmit a downlink signal; a receiving circuit which uses the second electrode to detect an uplink signal; and a blocking filter (26, 26a-e) which prevents a change in a potential of the first electrode from affecting a potential of the uplink signal detected by the receiving circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention

[0001] The present invention relates to an active stylus, and more particularly to an active stylus that performs both transmission and reception. 2. Description of the state of the art

[0002] There is a known active pin configured to receive an uplink signal transmitted by a sensor controller and transmit a downlink signal to the sensor controller. Examples of this type of active pin are disclosed in Japanese Patent Publication No. 6059410 (hereinafter referred to as "Patent Document 1").

[0003] Patent Document 1 discloses various active styluses, and a dual-mode stylus among them is an active stylus that supports both a first communication method of two-way communication and a second communication method of one-way communication from the active stylus to a sensor controller. The dual-mode stylus is configured to operate in the first communication method when the dual-mode stylus receives an uplink signal and to operate in the second communication method when the dual-mode stylus detects a stylus touch operation without receiving an uplink signal.

[0004] Examples of the communication method of the active pen are disclosed in each of International Publication No. WO 2017 / 029836 A1 (hereinafter referred to as “Patent Document 2”), International Publication No. WO 2015 / 111159 A1 (hereinafter referred to as “Patent Document 3”), US Patent No. 8,536,471 B2 (hereinafter referred to as “Patent Document 4”), and US Patent Application Publication No. US 2012 / 0105362 A1 (hereinafter referred to as “Patent Document 5”).

[0005] The dual-mode pin described in Patent Document 1 is configured to perform the reception of the uplink signal and the transmission of the downlink signal in a time-division manner. However, when the transmission and reception are performed in a time-division manner, the uplink signal may not be received while the downlink signal is being transmitted (for example, for a period of about 4 ms). Due to this, the reception of the uplink signal may be delayed, and the start of operation in the first communication process may also be delayed. Therefore, an improvement is necessary.

[0006] US 2020 / 0026369 A1 discloses a sensor controller connected to a sensor electrode to detect positions of one or more active pins depending on the charge induced on the sensor electrode.

[0007] US 2020 / 0050296 A1 discloses a stylus comprising a tip electrode, a tail portion provided on a tail side of the housing and comprising a tail electrode, a power circuit provided in the housing, a first transmission circuit that, in operation, receives power from the power circuit and generates a first downlink signal that is transmitted through the tip electrode to an outside of the housing, a second transmission circuit that, in operation, receives power from the power circuit and generates a second downlink signal that is transmitted through the tail electrode to the outside of the housing, wherein the second downlink signal is different from the first downlink signal, and a control circuit that, in operation, controls the first transmission circuit and the second transmission circuit according to a plurality of transmission modes.

[0008] US2019 / 0196642A1 discloses a touchscreen controller, a touchscreen system including the touchscreen controller, and a method for operating the touchscreen controller. SUMMARY OF THE INVENTION

[0009] An object of the present invention is to provide an active pin that can prevent a delay in receiving an uplink signal.

[0010] A first aspect of the present invention provides an active stylus comprising first and second electrodes provided at different positions, a transmitting circuit using a booster circuit for causing a change in the first electrode to thereby transmit a downlink signal, a receiving circuit using the second electrode to detect an uplink signal, and a notch filter preventing a change in a potential of the first electrode from affecting a potential of the uplink signal detected by the receiving circuit.

[0011] According to the first aspect of the present invention, the active pin can perform the reception of the uplink signal and the transmission of the downlink signal simultaneously, rather than in a time-divided manner. Therefore, this can prevent a delay in the reception of the uplink signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a configuration of a position detection system according to an embodiment of the present invention; Fig. 2 is a state transition diagram of a Fig. 1 illustrated integrated circuit; Fig. 3 is a diagram explaining operations of an active pen and a sensor controller with respect to a case where the sensor controller is a sensor controller supporting a first communication method; Fig. 4 is a diagram explaining operations of the active pen and the sensor controller with respect to a case where the sensor controller is a sensor controller supporting a second communication method; Fig. Figure 5 schematically shows a configuration in the Fig. 1 illustrated active pen; Fig. 6 shows a configuration of a Fig. 5 as a first example of a notch filter; Fig. Figure 7 shows results of a simulation of signals obtained by using the configuration of Fig. 6 is carried out; Fig. 8 illustrates a configuration of a receiving circuit provided in the integrated circuit for receiving an uplink signal based on an edge signal obtained by extracting only edges of the uplink signal; Fig. 9A - 9C show an example of an output signal FO generated by the Fig. 8 illustrated receiving circuit; Fig. 10 shows a configuration of a notch filter as a second example of the Fig. 5 illustrates the blocking filter; Fig. 11 presents results of a simulation of signals obtained by using the configuration of Fig. 10 is carried out; Fig. 12 presents results of a simulation of signals obtained by using the configuration of Fig. 10 is carried out; Fig. 13 shows a configuration of a notch filter as a third example of the Fig. 5 illustrates the blocking filter 26; Fig. 14 presents results of a simulation of signals obtained by using the configuration of Fig. 13 is carried out; Fig. 15 shows a configuration of a notch filter as a fourth example of the Fig. 5 illustrates the blocking filter; Fig. 16A - 16D show results of a simulation of signals obtained by using the configuration of Fig. 15 is carried out, and Fig. 17 shows a configuration of a notch filter as a fifth example of the Fig. 5 illustrates the blocking filter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Preferred embodiments of the present invention will now be described in detail with reference to the attached drawings.

[0013] Fig. Fig. 1 depicts a configuration of a position detection system 1 according to an embodiment of the present invention. As shown in Fig. As illustrated in Figure 1, the position detection system 1 includes an active pen 2 and an electronic device 3, which is a position detection device configured to detect the active pen 2. Examples of the electronic device 3 include a tablet computer and a device including a digitizer.

[0014] The electronic device 3 has a touch surface 3a, a sensor electrode group 30 arranged just below the touch surface 3a, a sensor controller 31 connected to the sensor electrode group 30, and a host processor 32 that controls each component of the sensor controller 31 including these components. The sensor controller 31 is an integrated circuit having a function for communicating with the active stylus 2 via the sensor electrode group 30 to derive the position of the active stylus 2 on the touch surface 3a, acquiring data from the active stylus 2, and respectively providing the derived position and the acquired data to the host processor 32. The host processor 32 is a central processing unit of the electronic device 3, and the host processor 32 can execute various programs, including a drawing application.The drawing application is a program having a function for generating digital ink based on the position and data provided by the sensor controller 31, storing the digital ink in a memory of the electronic device 3, and displaying the digital ink on a display.

[0015] A capacitance CX is generated between the active stylus 2 and the sensor electrode group 30 when the active stylus 2 is close to the touch surface 3a. The sensor controller 31 can exchange charge with the active stylus 2 (form a capacitive bond therewith) via the capacitance CX, thereby communicating with the active stylus 2.

[0016] The active stylus 2 is an active capacitive stylus (dual stylus) that supports both a first communication method, which is a two-way communication, and a second communication method, which is a one-way communication, from the active stylus 2 to the sensor controller 31. The first communication method is, for example, a communication method (AES 2.0 system) described in Patent Document 2, and the second communication method is, for example, a communication method (AES 1.0 system) described in Patent Document 3, a communication method described in Patent Document 4, or a communication method described in Patent Document 5.

[0017] Hereinafter, a signal transmitted from the sensor controller 31 to the active pin 2 is referred to as an uplink signal US, and a signal transmitted from the active pin 2 to the sensor controller 31 is referred to as a downlink signal DS. The uplink signal US has a pulse wave (square wave) in which transmission bits are distributed by a chip sequence (spreading codes) of a predetermined chip length. The chip length of an uplink signal US1 (=pulse period of the uplink signal US1) is, for example, a period such as 1 and 2 μs, and the edge period (rise period or fall period) is, for example, 10 ns. In AES 2.0, the pulse period of the pulse wave after Manchester coding is 2 μs.On the other hand, the downlink signal DS comprises a pulse wave (square wave) or a signal based on a sine wave (the signal comprises a sinusoidal signal at a predetermined frequency and a signal obtained by modulating the sinusoidal signal). Details of the downlink signal DS will be described later.

[0018] As in Fig. As illustrated in Figure 1, the active stylus 2 includes a core body 20, a stylus tip electrode 21 (first electrode), a ring electrode 22 (second electrode), a pressure sensor 23, a battery 24, an integrated circuit 25, and a barrier filter 26. The core body 20 is a member constituting a stylus axis of the active stylus 2. A front end of the core body 20 constitutes a stylus tip of the active stylus 2, and a rear end is in contact with the pressure sensor 23. The stylus tip electrode 21 and the ring electrode 22 are conductors provided at different positions. The stylus tip electrode 21 is disposed at the stylus tip of the active stylus 2, and the ring electrode 22 is disposed to surround the core body 20 at a position closer to the central portion of the active stylus 2 than the stylus tip electrode 21.

[0019] The pressure sensor 23 is a sensor that detects the pressure exerted on the front end of the core body 20. The pressure detected by the pressure sensor 23 is provided as a pin pressure value to the integrated circuit 25. The battery 24 plays a role in providing the necessary power for the operation of the integrated circuit 25.

[0020] The integrated circuit 25 is an integrated circuit that includes various circuits such as a booster circuit, a transmission circuit, a reception circuit, and a processing circuit. The transmission circuit is connected to the pen tip electrode 21 and the ring electrode 22, and the transmission circuit plays a role in using the booster circuit to cause a change in the pen tip electrode 21 or the ring electrode 22, thereby transmitting the downlink signal DS. The reception circuit is connected to the ring electrode 22, and the reception circuit plays a role in using the ring electrode 22 to perform a detection operation of the uplink signal US, thereby receiving the uplink signal US. The processing circuit generates a downlink signal DS and executes a process of causing the transmission circuit to transmit the generated downlink signal DS.In the case of performing the first communication method, the downlink signal DS is generated based on the uplink signal US received by the receiving circuit.

[0021] The notch filter 26 is a filter circuit interposed between the ring electrode 22 and the integrated circuit 25. Although the detailed configuration of the notch filter 26 will be described later, the notch filter 26 is a circuit provided to allow the detection of the uplink signal US using the ring electrode 22 and the transmission of the downlink signal DS from the pen tip electrode 21 at the same time.

[0022] Specifically, the potential boosted by the booster circuit for transmitting the downlink signal DS is 18 to 20 V, and the change in the potential of the pen tip electrode 21 associated with the transmission of the downlink signal DS also affects the receiving circuit. Due to this, the downlink signal DS is superimposed over the potential of the uplink signal US detected by the receiving circuit, and it is difficult to detect the uplink signal US at the same time as the transmission of the downlink signal DS. The reception strength of the uplink signal US is low when the active pen 2 is in a floating state in which the ring electrode 22 is far away from the sensor electrode group 30. Therefore, the detection of the uplink signal US becomes more difficult.The notch filter 26 plays a role in preventing the change in the potential of the pen tip electrode 21 associated with the transmission of the downlink signal DS from affecting the potential of the uplink signal US detected by the receiving circuit in the integrated circuit 25, thereby allowing the detection of the uplink signal US using the ring electrode 22 and the transmission of the downlink signal DS from the pen tip electrode 21 at the same time.

[0023] Fig. 2 is a state transition diagram of the integrated circuit 25. As in Fig. 2, the integrated circuit 25 is configured to operate in one of a search mode (first operating mode), a first mode (second operating mode), and a second mode.

[0024] The search mode is an operating mode in which the integrated circuit 25 has not yet detected the electronic device 3. The integrated circuit 25 is configured to first switch to the search mode when the power is turned on. The first and second modes are operating modes for the integrated circuit 25 to communicate with the sensor controller 31, which supports the first and second communication methods, respectively.

[0025] In the following description, the uplink signal US used in the first communication method is referred to as an uplink signal US1 in some cases. In the downlink signals DS used in the first communication method, the signal transmitted from the pen tip electrode 21 is referred to as a downlink signal DS1a in some cases, and the signal transmitted from the ring electrode 22 is referred to as a downlink signal DS1b in some cases. In the downlink signals DS used in the second communication method, the signal transmitted from the pen tip electrode 21 is referred to as a downlink signal DS2a in some cases, and the signal transmitted from the ring electrode 22 is referred to as a downlink signal DS2b in some cases.

[0026] The integrated circuit 25 in the search mode uses the ring electrode 22 to perform the detection operation of the uplink signal US1 and transmits the downlink signal DS2a from the pin tip electrode 21 (step S1). The detection operation and transmission are performed simultaneously rather than in a time-divided manner.

[0027] The integrated circuit 25, which has detected the uplink signal US1 in step S1, switches to the first mode (step S2) and starts communication using the first communication method. Specifically, the integrated circuit 25 first acquires a transmission and reception schedule of the uplink signal US1 and the downlink signals DS1a and DS1b based on the reception timing of the detected uplink signal US1. The integrated circuit 25 then transmits the downlink signals DS1a and DS1b according to the transmission and reception schedule (step S10), and when the reception timing of the uplink signal US1 arrives (step S11), the integrated circuit 25 performs the detection operation of the uplink signal US1 (step S12). The transmission in step S10 and the detection operation in step S12 are performed in a time-division manner.

[0028] Here, the uplink signal US1 is a signal modulated with a command indicating an instruction for the active pin 2. Further, the downlink signal DS1a is, for example, a signal including a position signal, which is an unmodulated pulse wave or sine wave, and a data signal modulated with data contained in the active pin 2.

[0029] The position signal is used by the sensor controller 31 to derive the position of the pen tip of the active pen 2. On the other hand, the data signal is used by the sensor controller 31 to acquire various types of data from the active pen 2. Regarding the data signal, the integrated circuit 25 is configured to acquire the data transmitted by the data signal according to the command included in the uplink signal US1 received from the sensor controller 31. In addition to the pen pressure value described above, the data thus acquired may include a pen ID stored in an internal memory of the integrated circuit 25 and switch information indicating an on / off state of a switch provided on the surface of the active pen 2.

[0030] The downlink signal DS1b includes only a position signal, which is an unmodulated pulse wave or sine wave. However, the frequency (pulse period) of the pulse wave or sine wave contained in the downlink signal DS1b differs from the frequency of the downlink signal DS1a. This is done so that the sensor controller 31, when receiving signals, can distinguish between the downlink signal DS1a and the downlink signal DS1b. The sensor controller 31 derives the position of the ring electrode 22 based on the downlink signal DS1b and derives the distance between the position of the ring electrode 22 and the position of the pen tip derived based on the position signal in the downlink signal DS1a, thereby detecting the inclination of the active pen 2.

[0031] If the integrated circuit 25 detects the uplink signal US1 due to the execution of the detection operation of the uplink signal US1 in step S12, the integrated circuit 25 maintains the first mode and returns to step S10 to transmit the downlink signals DS1a and DS1b (step S13). On the other hand, if the integrated circuit 25 does not detect the uplink signal US1, the integrated circuit 25 exits the first mode to return to the search mode and continues the process (step S14). Note that the integrated circuit 25 may be configured to exit the first mode to return to the search mode if the integrated circuit 25 fails to detect the uplink signal US1 for a predetermined number of times.

[0032] While the integrated circuit 25 is in the search mode, the integrated circuit 25 also monitors the pen pressure value. Based on the monitoring, if the integrated circuit 25 detects that the pen pressure value is higher than 0, the integrated circuit 25 determines that the pen tip of the active pen 2 has come into contact with the touch surface 3a (a pen touch has occurred) and switches to the second mode (step S3) to start communication of the second communication method.

[0033] More specifically, the integrated circuit 25 repeatedly transmits the downlink signals DS2a and DS2b (step S20) while increasing a variable count value by one each time (step S21).

[0034] Here, the downlink signals DS2a and DS2b are signals similar to the downlink signals DS1a and DS1b. The sensor controller 31 detects the position and inclination of the active pin 2 and acquires various types of data from the active pin 2 based on the downlink signals DS2a and DS2b, as in the case of the first communication method. However, there is no uplink signal US1, and the sensor controller 31 cannot request the data to be transmitted by the active pin 2.

[0035] When the variable count value reaches a predetermined value N, the integrated circuit 25 resets the variable count value to 1 (step S22) and performs a pen touch determination (step S23). In short, the pen touch determination is an act of determining whether the pen pressure value is 0 or not. The integrated circuit 25 determines that the active pen 2 is in the pen touch state when the pen pressure value is not 0, and determines that the active pen 2 is not in the pen touch state (is in the floating state) when the pen pressure value is 0. If the integrated circuit 25 determines that the active pen 2 is in the pen touch state, the integrated circuit 25 maintains the second mode and returns to step S20 to continue transmitting the downlink signals DS2a and DS2b (step S24).On the other hand, when the integrated circuit 25 determines that the active pen 2 is not in the pen touch state, the integrated circuit 25 exits the second mode to return to the search mode and continues the process (step S25).

[0036] Fig. 3 and Fig. 4 are diagrams explaining operations of the active pen 2 and the sensor controller 31. A Fig. 3 illustrates the sensor controller 31-1 that supports the first communication method, and a Fig. The sensor controller 31-2 illustrated in Figure 4 represents the sensor controller 31 that supports the second communication method. The operations of the active pin 2 and the sensor controller 31 will now be described in detail again with reference to Fig. 3 and Fig. 4 described.

[0037] First on Fig. 3, the integrated circuit 25, which has not yet detected the sensor controller 31, is in the search mode, and the integrated circuit 25 also detects the uplink signal US1 reaching the ring electrode 22 when the integrated circuit 25 transmits the downlink signal DS2a from the pen tip electrode 21. It should be noted that “R”, illustrated in Fig. 3, represents the detection operation (reception operation) of the signal. On the other hand, the sensor controller 31-1 transmits the uplink signal US1 at a predetermined time period UpIntv, and when the sensor controller 31-1 does not transmit the uplink signal US1, the sensor controller 31-1 performs the detection operation of the downlink signals DS1a and DS1b.

[0038] Once the active pin 2 enters a receivable range of the uplink signal US1 at a time t1 (“pin down”), the integrated circuit 25 receives the uplink signal US1 at the subsequent time t2. The integrated circuit 25, having received the uplink signal US1 in this way, switches to the first mode and then repeatedly performs the transmission of the downlink signals DS1a and DS1b and the detection operation of the uplink signal US1 in a time-divided manner according to the transmission and reception schedule determined by the reception time of the uplink signal US1. Although in Fig. 3, the integrated circuit 25 returns from the operation mode to the search mode when the integrated circuit 25 does not receive the uplink signal US 1 due to performing the detection operation of the uplink signal US 1.

[0039] Referring to Fig. 4, the integrated circuit 25, which has detected that the pen pressure value has dropped to 0 at a time t3 without receiving the uplink signal US1, switches to the second mode. The integrated circuit 25 repeatedly transmits the downlink signals DS2a and DS2b while the integrated circuit 25 is in the second mode. As soon as "pen-up" occurs at a time t4, the integrated circuit 25 leaves the second mode to return to the search mode at a time t5, which is a period T after a time t4. The duration of the period T is determined by the predetermined value N, illustrated in Fig. 2. The integrated circuit 25 continues the second mode without returning to the search mode if the state returns to the pen touch state during the period T.

[0040] Next, the notch filter 26, which allows the detection of the uplink signal US using the ring electrode 22 and the transmission of the downlink signal DS from the pen tip electrode 21 to be carried out at the same time, will be described in detail with reference to the drawings.

[0041] Fig. Figure 5 schematically illustrates a configuration in the active pin 2. As in Fig. As illustrated in Figure 5, the notch filter 26 is inserted into a wire connecting the ring electrode 22 and the integrated circuit 25. Therefore, the uplink signal US1 reaching the ring electrode 22 is provided to the integrated circuit 25 via the notch filter 26.

[0042] One in Fig. The capacitance CY illustrated in Figure 5 represents a parasitic capacitance generated between the pin tip electrode 21 and the wire connecting the pin tip electrode 21 to the integrated circuit 25, and the ring electrode 22 and the wire connecting the ring electrode 22 to the integrated circuit 25. Due to the parasitic capacitance CY, when the downlink signal DS2a is transmitted from the pin tip electrode 21 when the uplink signal US1 reaches the ring electrode 22, the downlink signal DS2a is superimposed over the uplink signal US1. The notch filter 26 plays a role in removing only the downlink signal DS2a from the uplink signal US1 over which the downlink signal DS2a has been superimposed, and providing only the uplink signal US1 to the integrated circuit 25.

[0043] Various configurations can be adopted for the specific configuration of the notch filter 26. Therefore, five types of notch filters 26a to 26e are illustrated, and each notch filter is described in detail.

[0044] Fig. 6 illustrates a configuration of the notch filter 26a as a first example of the notch filter 26. Fig. Figure 6 illustrates an example of a case where the downlink signal DS2a comprises a signal based on a sine wave at a predetermined frequency. Such a downlink signal DS2a is used, for example, in AES 1.0, and the predetermined frequency in this case is 1.8 MHz.

[0045] In Fig. 6 and the later described Fig. 10 and Fig. 13, the configurations of the active pin 2 and the sensor controller 31 are represented by equivalent circuits. Specifically, an oscillator V1 corresponds to the sensor controller 31 and generates the uplink signal US1. An oscillator V2 corresponds to the transmission circuit in the integrated circuit 25 and generates the downlink signal DS2a. The capacitance CX represents the capacitance formed between the ring electrode 22 and the sensor electrode group 30 (see Fig. 1). Capacitance C1 represents the capacitance formed between the ring electrode 22 and the wire connecting the ring electrode 22 to the integrated circuit 25, and a ground edge. A voltage Vring corresponds to the signal appearing at the ring electrode 22 (the uplink signal US1, over which the downlink signal DS2a is applied), and a voltage Vfiltout corresponds to an output signal of the notch filter 26. Although the circuit in the integrated circuit 25 supplied with the voltage Vfiltout is actually the receiving circuit, only a series circuit with capacitance C2 and resistor R1 is represented in a simplified manner in Fig. 6 and the later described Fig. 10 and Fig. 13. A voltage Vrxin corresponds to a signal received by the receiving circuit, which is supplied with the voltage Vfiltout.

[0046] The blocking filter 26a in the example of Fig. 6 includes a band-stop filter (notch filter) that blocks a specific frequency band including the predetermined frequency (the carrier frequency of the downlink signal DS2a). More specifically, the notch filter 26a, as shown in Fig. 6, a first circuit comprising two resistive elements having a resistance value R connected in series, in which the junction point of the two resistive elements is grounded via a capacitor having a capacitance value 2C. The notch filter 26a also comprises a second circuit comprising two capacitors having a capacitance value C connected in series, in which the junction point of the two capacitors is grounded via a resistive element having a resistance value R / 2. The first circuit and the second circuit are connected in parallel between the ring electrode 22 and the integrated circuit 25, and the capacitance value C and the resistance value R are set such that a notch frequency 1 / 2πCR is equal to the predetermined frequency.

[0047] Fig. Figure 7 shows results of a simulation of signals obtained by using the configuration of Fig. 6 is carried out. Fig. Figure 7 illustrates the uplink signal US1, the voltage Vring, the voltage Vfiltout, and the voltage Vrxin. In the simulation, the predetermined frequency is 1.8 MHz and the pulse period of the uplink signal US1 is 2 µs. The downlink signal DS2a, in the form not superimposed on the uplink signal US1, appears at the voltage Vring in the illustrated portion of a period X.

[0048] As in Fig. As illustrated in Figure 7, while the downlink signal DS2a is superimposed over the uplink signal US1 at voltage Vring, the uplink signal US1 appears independent at voltages Vfiltout and Vrxin. From the results, it can be understood that the notch filter 26a selectively blocks the downlink signal DS2a.

[0049] However, as can be seen from Fig. As can be understood from Figure 7, the uplink signal US1 appearing at the voltages Vfiltout and Vrxin is not the original pulse wave, but rather an edge signal obtained by extracting only the edges of the pulse wave. Therefore, the receiving circuit in the integrated circuit 25 must be able to receive the uplink signal US1 based on the edge signal. The configuration of the receiving circuit configured in this manner will now be described in detail.

[0050] Fig. Fig. 8 depicts the configuration of the receiving circuit provided in the integrated circuit 25 for receiving the uplink signal US1 based on the edge signal. As shown in Fig. 8, the integrated circuit 25 in this case comprises an amplifier circuit 40, a ΔΣ modulation unit 41, a pulse density detection unit 42, a gain control unit 43, an edge-matched filter 44, a pattern storage unit 45 and an uplink signal restoration unit 46.

[0051] The amplifier circuit 40 is a circuit which filters the voltage Vfiltout supplied by the Fig. 6, and provides an output signal DO to the ΔΣ modulation unit 41. The amplifier circuit 40 comprises a variable gain amplifier in which the gain factor can be controlled by the gain control unit 43.

[0052] The ΔΣ modulation unit 41 is a functional unit that uses at least two reference potentials VTP and VTN (VTP = -VTN > 0), which correspond to positive and negative, respectively, to perform a comparison for the output signal DO of the amplifier circuit 40 and performs a feedback process of the comparison result. As shown in Fig. As illustrated in Fig. 8, the ΔΣ modulation unit 41 includes a subtraction circuit 41a, an addition circuit 41b, a comparison circuit 41c, and delay circuits 41d and 41e.

[0053] The comparison circuit 41c is a circuit that compares an output signal IO of the addition circuit 41b and the reference potentials VTP and VTN. The comparison circuit 41c has three output terminals, including a comparison result output terminal, a positive-side output terminal (+1), and a negative-side output terminal (-1). A signal output from the comparison result output terminal among the output terminals provides an output signal CO of the ΔΣ modulation unit 41.

[0054] The operation of the comparison circuit 41c is as follows. When the output signal IO of the addition circuit 41b is higher than the reference potential VTP, the comparison circuit 41c outputs the output signal CO of +1, sets the potential of the positive-side output terminal to high, and sets the potential of the negative-side output terminal to low. When the output signal IO of the addition circuit 41b is lower than the reference potential VTN, the comparison circuit 41c outputs the output signal CO of -1, sets the potential of the negative-side output terminal to high, and sets the potential of the positive-side output terminal to low. In other cases, the comparison circuit 41c outputs the output signal CO of 0 and sets the potentials of the positive-side and negative-side output terminals to low.Due to the operation of the comparison circuit 41c, the output signal CO of the comparison circuit 41c is a ternary pulse signal having a value of either +1, 0 or -1.

[0055] The comparison circuit 41c is configured to operate within a time period shorter than the chip length of the chip sequence included in the uplink signal US1. Therefore, the output signal CO is a pulse signal comprising multiple chips (for example, four chips) for each chip of the chip sequence included in the uplink signal US1.

[0056] The delay circuit 41d is a circuit that multiplies the potential of the positive-side output terminal of the comparison circuit 41c by Δ and then feeds the signal back to the subtraction circuit 41a after delaying the signal by, for example, one clock (one chip of the output signal CO). Similarly, the delay circuit 41e is a circuit that multiplies the potential of the negative-side output terminal of the comparison circuit 41c by -Δ and then feeds the signal back to the subtraction circuit 41a after delaying the signal by, for example, one clock. It is recommended that the specific value of Δ be a value equal to the reference potential VTP.

[0057] The subtraction circuit 41a is a circuit that outputs a signal obtained by subtracting the potential corresponding to the output signals of the delay circuits 41d and 41e from the output signal DO of the amplifier circuit 40. Due to the subtraction, the potential level of the input signal of the addition circuit 41b falls when the output signal IO of the previous clock is higher than the reference potential VTP, and the potential level of the input signal of the addition circuit 41b rises when the output signal IO of the previous clock is lower than the reference potential VTN. This can achieve an advantageous effect that the potential level of the output signal IO of the addition circuit 41b can be limited within a certain range.

[0058] The addition circuit 41b is a circuit that outputs a signal obtained by integrating the output signals of the subtraction circuit 41a. The output signal IO of the addition circuit 41b is obtained by adding the output signal of the subtraction circuit 41a to the output signal of the addition circuit 41b of the previous clock.

[0059] The pulse density detection unit 42 is a functional unit that detects the pulse density of the output signal CO of the ΔΣ modulation unit 41 and informs the gain control unit 43 of the result. The gain control unit 43 plays a role in controlling the gain of the amplifier circuit 40 based on the pulse density notified by the pulse density detection unit 42, thereby preventing the output signal CO from becoming fixed due to the absolute value of the output signal DO becoming too large or too small.

[0060] The pattern storage unit 45 includes a memory circuit that stores, as a known pattern, a ternary chip sequence comprising a plurality of chips with values ​​of +1, 0, or 1 for each of a plurality of spreading codes (binary chip sequence) that can be used by the sensor controller 31 to transmit the uplink signal US.

[0061] The edge-matched filter 44 includes a first-in, first-out shift register capable of storing a chip sequence equivalent to the number of chips corresponding to a spreading code. Each time the edge-matched filter 44 detects a chip of the output signal CO of the ΔΣ modulation unit 41, the edge-matched filter 44 stores the chip in the shift register. Each time the edge-matched filter 44 stores a new chip, the edge-matched filter 44 calculates a correlation between the chip sequence currently stored in the shift register and each of the plurality of known patterns stored in the pattern storage unit 45. The edge-matched filter 44 sequentially provides the results as an output signal FO to the uplink signal restoration unit 46.

[0062] The uplink signal restoration unit 46 determines that the spreading code corresponding to the pattern used to calculate the output signal FO is detected when the output signal FO is equal to or greater than a predetermined value. The uplink signal restoration unit 46 then restores the uplink signal US1 based on the successively detected spreading codes. The integrated circuit 25 demodulates the thus restored uplink signal US to receive the command transmitted by the sensor controller 31.

[0063] Fig. 9A - 9C show an example of the output signal FO generated by the Fig. 8 illustrated receiving circuit is generated. Fig. 9A - 9C illustrate a case where the correlation is calculated by using a pattern corresponding to the chip sequence of the received uplink signal US1. Fig. Figure 9C illustrates a case where the voltage Vfiltout is input to the receiving circuit. For comparison, Fig. 9A shows a case in which an ideal uplink signal US without noise is input to the receiving circuit, and Fig. Figure 9B illustrates a case where the voltage Vring is input to the receiving circuit. From the Fig. 9A - 9C, it can be understood that by combining the Fig. 6 illustrated blocking filter 26a and the one in Fig. 8, the uplink signal US1 can be received correctly, as in the case where the ideal uplink signal US without noise is input to the receiving circuit.

[0064] Fig. 10 illustrates a configuration of the notch filter 26b as a second example of the notch filter 26. Fig. Figure 10 illustrates an example of a case where the downlink signal DS2a has a pulse wave. However, compared to the uplink signal US1, which also has a pulse wave, the pulse period of the downlink signal DS2a is significantly longer, and the duration of the edge period is also longer. Specifically, the pulse wave is, for example, 4 µs to 40 µs, and the edge period is, for example, 100 ns to 5 µs.

[0065] The notch filter 26b includes a high-pass filter 50 configured to pass the pulse wave (the first pulse wave) of the uplink signal US1 and to block the pulse wave (the second pulse wave) of the downlink signal DS2a. Specifically, it is recommended to Fig. 10 illustrates that the high-pass filter 50 comprises, for example, a CR filter including a capacitor with a capacitance value C, one end of which is connected to the ring electrode 22 and the other end to the integrated circuit 25, and a resistance element with a resistance value R connected between the other end of the capacitor and the ground flank. The capacitance value C and the resistance value R are set so that the notch filter 26b passes the uplink signal US1 and blocks the downlink signal DS2a.

[0066] Fig. 11 presents results of a simulation of signals obtained by using the configuration of Fig. 10 is carried out. Fig. Figure 11 illustrates the uplink signal US1, the downlink signal DS2a, the voltage Vring, and the voltage Vfiltout. In the example of Fig. 11, the pulse period of the uplink signal US1 is 2 µs, and the pulse period of the downlink signal DS2a is 40 µs. The duration of an edge period E1 of the uplink signal US1 is 10 ns, and the duration of an edge period E2 of the downlink signal DS2a is 2 µs.

[0067] As in Fig. As illustrated in Figure 11, the downlink signal DS2a is superimposed over the uplink signal US1 at the voltage Vring, and the downlink signal DS2a has essentially disappeared at the voltage Vfiltout. From the results, it can be understood that the notch filter 26b also selectively blocks the downlink signal DS2a. However, in the example of Fig. 11, the uplink signal US1 appearing at the voltage Vfiltout is not the original pulse wave, but an edge signal obtained by extracting only the edges of the pulse wave. Therefore, it is recommended that the receiving circuit in the integrated circuit 25 be the receiving circuit with the reference to Fig. 8 described configuration is as in the first example.

[0068] In case of using the blocking filter 26b with the Fig. In the configuration illustrated in Figure 10, it may be difficult to remove the downlink signal DS2a from the voltage Vring when the difference between the duration of the edge period E2 of the downlink signal DS2a and the duration of the edge period E1 of the uplink signal US1 is small. A specific example is described.

[0069] Fig. 12 presents results of a simulation of signals obtained by using the configuration of Fig. 10 as in Fig. 11 is carried out. The difference to Fig. 11 is that the duration of the edge period E2 of the downlink signal DS2a is 200 ns. As in Fig. As illustrated in Figure 12, in this case, edges of the downlink signal DS2a remain clearly at the voltage Vfiltout.

[0070] Fig. Figure 13 illustrates a configuration of the notch filter 26c as a third example of the notch filter 26. The notch filter 26c can be used to solve the problem of the notch filter 26b. The details will now be described.

[0071] The notch filter 26c has a mute circuit 51 on a rear stage of the Fig. 10. The muting circuit 51 includes a switching element SW and a clock circuit CLK connected between the other end of the capacitor of the high-pass filter 50 and the ground edge. The switching element SW has a non-inverting input terminal and an inverting input terminal. The switching element SW grounds the output end of the notch filter 26c when the difference between the potential of the non-inverting input terminal and the potential of the inverting input terminal is equal to or greater than a predetermined value, and otherwise, the switching element SW does not ground the output end. Further, the clock circuit CLK is configured to output a signal that is high during edge periods of the downlink signal DS2a and low during other periods. The clock circuit CLK provides the signal to the non-inverting input terminal of the switching element SW.The operation of the switching element SW and the clock circuit CLK mutes the output (= voltage Vfiltout) of the notch filter 26c in the edge periods of the downlink signal DS2a.

[0072] Fig. 14 presents results of a simulation of signals obtained by using the configuration of Fig. 13. The waveforms of the uplink signal US1 and the downlink signal DS2a are similar to the waveforms in the example of Fig. 12. As can be seen by comparing Fig. 14 and Fig. 12 can be understood, are in the example of Fig. 14, the edges of the downlink signal DS2a disappeared from the voltage Vfiltout. From the results, it can be understood that the muting circuit 51 plays a role in removing the downlink signal DS2a from the voltage Vring.

[0073] Here, a part of the pulse of the uplink signal US1 may be lost when using the mute circuit 51. Therefore, in the third example, as in the first and second examples, it is recommended that the receiving circuit in the integrated circuit 25 be the receiving circuit with the reference to Fig. 8. In this way, the correlation calculation by the edge-matched filter 44 can restore the uplink signal US1, and the uplink signal US1 can be correctly received even if the pulse of the uplink signal US1 is slightly lost due to the action of the muting circuit 51.

[0074] Fig. 15 depicts a configuration of the notch filter 26d as a fourth example of the notch filter 26. As in Fig. 15, the notch filter 26d comprises an amplification circuit 52 and a differential circuit 53.

[0075] The amplification circuit 52 is a circuit that outputs the downlink signal DS2a after controlling the amplitude of the downlink signal DS2a. The input end of the amplification circuit 52 is connected to the output end of the transmission circuit in the integrated circuit 25, and the output end is connected to the inverting input terminal of the differential circuit 53. The amplification circuit 52 plays a role in attenuating the amplitude of the downlink signal DS2a to a level equivalent to the amplitude of the downlink signal DS2a applied to the uplink signal US1 by the parasitic capacitance CY.

[0076] The differential circuit 53 is a circuit that outputs a signal after subtracting the output signal of the amplifying circuit 52 from the uplink signal US1 reaching the ring electrode 22. The non-inverting input terminal of the differential circuit 53 is connected to the ring electrode 22, and therefore, the uplink signal US1, across which the downlink signal DS2a is superimposed through the parasitic capacitance CY, is input to the non-inverting input terminal of the differential circuit 53. As described above, the output signal of the amplifying circuit 52 is the downlink signal DS2a with the amplitude attenuated to the level equivalent to the amplitude of the downlink signal DS2a superimposed on the uplink signal US1, and therefore, the output signal of the differential circuit 53 is the uplink signal US1 over which the downlink signal DS2a has not been superimposed.

[0077] Fig. 16A - 16D show results of a simulation of signals obtained by using the configuration of Fig. 15 is carried out. Fig. Figure 16A illustrates the uplink signal US1 generated by the sensor controller 31, and Fig. 16B to 16D illustrate signals which are respectively in the Fig. 15 illustrated nodes n1 to n3 appear. It should be noted that Fig. 16A-16D illustrate an example in which both the uplink signal US1 and the downlink signal DS2a have pulse waves, and the pulse period of the downlink signal DS2a is significantly longer than the pulse period of the uplink signal US1.

[0078] As from Fig. 16A-16D, the signal appearing in node n1 is a signal in which the uplink signal US1 generated by the sensor controller 31 and the downlink signal DS2a appearing in node n2 are superimposed. The signal appearing in node n3 is a signal having a waveform similar to the waveform of the original uplink signal US1 due to the removal of the downlink signal DS2a appearing in node n2 from the signal appearing in node n1. From the results, it can be understood that the notch filter 26d plays a role in removing the downlink signal DS2a from the signal reaching the ring electrode 22.

[0079] Although in the example of Fig. 15 and Fig. 16 is not taken into account, the uplink signal US1, which passes through the parasitic capacitance CY toward the pin tip electrode 21, is applied to the actual input of the amplification circuit 52. The components of the uplink signal US1 must be removed from the downlink signal DS2a in the notch filter 26 if the influence of the superposition cannot be ignored. In a fifth example described next, the notch filter 26 is described, which allows this removal.

[0080] Fig. 17 depicts a configuration of the notch filter 26e as a fifth example of the notch filter 26. As in Fig. 17, the notch filter 26e includes a finite impulse response (FIR) filter 54, a subtractor 55, and a feedback circuit 56.

[0081] The FIR filter 54 is a digital filter configured to extract only specific signal components. The FIR filter 54 in the notch filter 26e plays a role as a filter circuit that removes the components of the uplink signal US1 from the downlink signal DS2a output from the transmission circuit in the integrated circuit 25, and plays a role as an amplification circuit that outputs the downlink signal DS2a after controlling the amplitude of the downlink signal DS2a. Similar to the Fig. 15, the subtractor 55 is a differential circuit that outputs a signal after subtracting the output signal of the FIR filter 54 from the uplink signal US1 reaching the ring electrode 22.

[0082] The feedback circuit 56 is a circuit that controls the control amount of the amplitude of the downlink signal DS2a through the FIR filter 54 to reduce the amplitude of the output signal of the subtractor 55 (i.e., to reduce the output energy). Specifically, it is recommended to use a least mean squares (LMS) algorithm to control the value of each coefficient included in the transfer function of the FIR filter 54. Due to the control by the feedback circuit 56, the signal output from the FIR filter 54 is a signal close to a pure downlink signal DS2a, which does not include the components of the uplink signal US1. Therefore, according to the notch filter 26e, the downlink signal DS2a can be effectively removed from the signal reaching the ring electrode 22 even if the uplink signal US1 is applied across the input of the FIR filter 54 by the parasitic capacitance CY.

[0083] As described above, according to the active pin 2 of the present embodiments, the notch filter 26 is provided between the ring electrode 22 and the integrated circuit 25, and therefore, the reception of the uplink signal US1 and the transmission of the downlink signal DS2a can be performed simultaneously instead of in a time-divided manner. Therefore, this can prevent a delay in the reception of the uplink signal US1.

[0084] Furthermore, according to the active pin 2 of the present embodiment, the reception of the uplink signal US and the transmission of the downlink signal DS can be performed at the same time in the state (search mode) in which the sensor controller 31 is not yet detected and the transmission timing of the uplink signal US transmitted by the sensor controller 31 is not detected. On the other hand, the reception of the uplink signal US and the transmission of the downlink signal DS can be performed in a time-division manner in the state (first mode) in which the uplink signal US is detected and the transmission timing of the uplink signal US transmitted by the sensor controller 31 is detected. Therefore, the delay in receiving the uplink signal US can be prevented, and once the uplink signal US is detected, the uplink signal US can be detected with a small amount of noise.In addition, the downlink signal DS can be transmitted from both the pen tip electrode 21 and the ring electrode 22, and therefore the inclination of the active pen 2 can be used.

[0085] Although the preferred embodiments of the present invention have been described, the present invention is in no way limited to these embodiments, and it is obvious that the present invention can be embodied in various modes without departing from the scope of the present invention.

[0086] For example, although the case of using the uplink signal US1, which is a pulse signal, has been illustrated and described in the embodiments, the present invention can also be advantageously applied to a case of using the uplink signal US, which is a signal based on a sine wave. In a case of using the uplink signal US1, which is a pulse signal, Fig.6, in this case, the uplink signal US may be a signal based on a sine wave at a frequency not included in the specific frequency band blocked by the notch filter 26a.

[0087] Furthermore, although the example of fixing and inserting the notch filter 26 between the ring electrode 22 and the integrated circuit 25 has been described in the embodiments, a first route passing through the notch filter 26, a second route not passing through the notch filter 26, and a switch for switching between the routes may be provided. The integrated circuit 25 can control the switch to validate the first route in the case where the detection operation of the uplink signal US1 and the transmission of the downlink signal DS2a are performed at the same time (search mode), and to validate the second route in other cases (first and second modes).

[0088] In addition, although the example of applying the present invention to the active pin 2, which is a dual-mode pin, has been described in the embodiments, the present invention can also be widely applied to the active pin 2 which needs to transmit the downlink signal DS and receive the uplink signal US at the same time.

Claims

[1] Active pen, which includes: a first and a second electrode provided at different positions; a transmission circuit that uses a booster circuit to cause a change in the first electrode to thereby transmit a downlink signal; a receiving circuit that uses the second electrode to detect an uplink signal; and a notch filter (26, 26a-e) that prevents a change in a potential of the first electrode from affecting a potential of the uplink signal detected by the receiving circuit. [2] Active pen according to claim 1, wherein the downlink signal is a signal based on a sine wave at a predetermined frequency, and the notch filter (26, 26a-e) is a band-stop filter that blocks a specific frequency band including the predetermined frequency. [3] The active pen according to claim 1 or 2, wherein the uplink signal comprises a pulse wave. [4] An active pen according to any preceding claim, wherein the uplink signal is a signal based on a sine wave at a frequency not included in the specific frequency band. [5] An active stylus according to any preceding claim, wherein the uplink signal is a first pulse wave, the downlink signal is a second pulse wave in which a duration of an edge period differs from the first pulse wave, and the notch filter (26, 26a-e) is a high-pass filter (50) configured to pass the first pulse wave and block the second pulse wave. [6] An active pen according to any one of claims 1 to 4, wherein the uplink signal and the downlink signal are pulse waves, and the notch filter comprises: a high-pass filter (50) configured to pass the pulse wave contained in the uplink signal and to block the pulse wave contained in the downlink signal, and a muting circuit (51) that mutes an input to the receiving circuit in an edge period of the downlink signal. [7] An active pen according to claim 6, wherein the mute circuit (51) is provided between the high-pass filter (50) and the receiving circuit. [8] The active pen of claim 6 or 7, wherein the receiving circuit is configured to receive the uplink signal based on a correlation calculation. [9] Active pen according to one of claims 1 to 4, wherein the blocking filter comprises: an amplifying circuit (52) which outputs the downlink signal after controlling an amplitude of the downlink signal, and a differential circuit (53) that outputs a signal after subtracting the output signal of the amplifying circuit (52) from the uplink signal reaching the second electrode. [10] The active pen according to claim 9, wherein the notch filter (26, 26a-e) further comprises a feedback circuit (56) that controls a control amount of the amplitude of the downlink signal by the amplification circuit (52) to reduce an amplitude of the output signal of the differential circuit (53). [11] Active pen according to one of the preceding claims, further comprising: an integrated circuit (25) comprising the transmission circuit and the reception circuit, wherein the integrated circuit (25) controls the receiving circuit for detecting the uplink signal reaching the second electrode, while the transmitting circuit transmits the downlink signal from the first electrode.

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