Integrated circuit with deep conductors and shallow conductors in signal paths and methods for their fabrication

Abstract

The integrated circuit comprises: several deep first-layer traces and several shallow first-layer traces, each of the deep first-layer traces and the shallow first-layer traces being located in a first conductive layer above transistors on a substrate; several deep second-layer traces and several shallow second-layer traces, each of the deep second-layer traces and the shallow second-layer traces being located in a second conductive layer above the first conductive layer; and a conductor having a low-resistance section and a low-capacitance section, the low-resistance section being coupled to an output of a first active device, and the low-capacitance section being coupled to an input of a second active device;wherein the low-resistance section has at least one deep first-layer conductor and / or at least one deep second-layer conductor and excludes the shallow first-layer conductors and the shallow second-layer conductors; and wherein the low-capacitance section has at least one shallow first-layer conductor and / or at least one shallow second-layer conductor and excludes the deep first-layer conductors and the deep second-layer conductors.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over preliminary US application 63 / 148,883, filed on February 12, 2021, which is incorporated herein in its entirety by reference. BACKGROUND

[0002] The recent trend toward miniaturization of integrated circuits (ICs) has led to smaller devices that consume less power but offer higher functionality at faster speeds. This miniaturization process has also resulted in stricter design and manufacturing requirements, as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits, ensuring adherence to these standard design and manufacturing requirements. List of characters

[0003] Aspects of this disclosure are best understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a layout diagram of an integrated circuit according to some embodiments. Fig. 2A to Fig. 2D are cross-sectional views of the integrated circuit in Fig. 1 according to some embodiments. Fig. Figure 3A is a cross-sectional view of deep conduits and shallow conduits with labeled depth dimensions according to some embodiments. Fig. Figure 3B is a diagram of a resistance curve and capacitance plotted against changes in the depths of the conductor tracks, according to some embodiments. Fig. 4A to Fig. 4C are cross-sectional views of the integrated circuit in Fig. 1 according to some embodiments. Fig. Figure 5 is a layout diagram of an integrated circuit with a signal path formed by a combination of deep lines and shallow lines, according to some embodiments. Fig. 6A to Fig. 6F are layout diagrams of integrated circuits with signal paths formed with different configurations of the low-impedance section, the low-capacitance section and the mutation point according to some embodiments. Fig. Figure 7 is a layout diagram of an integrated circuit with multiple signal paths formed by combinations of deep traces and shallow traces, according to some embodiments. Fig. 8A to Fig. Figure 8B shows schematic diagrams of integrated circuits with multiple signal paths formed with combinations of deep traces and shallow traces, according to some embodiments. Fig. Figure 9 is a layout diagram of an integrated circuit with multiple signal paths formed with deep lines, according to some embodiments. Fig. Figure 10 is a flowchart of a process for manufacturing an integrated circuit according to some embodiments. Fig. Figure 11 is a flowchart of a process for manufacturing deep conduits and shallow conduits according to some embodiments. Fig. 12A to Fig. Figure 12E shows cross-sectional views of exemplary device structures according to some embodiments. Fig. Figure 13 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Fig. Figure 14 is a block diagram of a system for manufacturing an integrated circuit (IC) and an associated IC manufacturing process, according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the disclosed content. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting. Other components, values, operations, materials, arrangements, or the like are considered. For example, forming a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements can be formed between the first and second elements, so that the first and second elements need not be in direct contact.Furthermore, this disclosure may repeat reference numerals from the various examples. This repetition serves the purpose of simplicity and clarity and does not fundamentally prescribe a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "under," "below," "below," "above," "above," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass various orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may also be designed accordingly.

[0006] In some embodiments, an integrated circuit includes deep traces and shallow traces in both a first conductive layer and a second conductive layer. Selecting deep and shallow traces to construct different signal paths enables performance improvements for the integrated circuit. In some embodiments, the resistance-capacitance constant (RC constant) of the signal path from a first active device to a second active device is reduced. In some embodiments, the signal propagation delay in the signal path from a first active device to a second active device is reduced. In some embodiments, the signal path includes a mutation point between a low-resistance section of the signal path and a low-capacitance section of the signal path.In some embodiments, the signal path changes from a deep channel to a shallow channel at the mutation point. In some embodiments, the signal propagation delay in a signal path from a first active device to a second active device is reduced when a mutation point is selected from several mutation point candidates on the signal path.

[0007] Fig. Figure 1 is a layout diagram of an integrated circuit 100 according to some embodiments. Fig. 2A to Fig. 2D are cross-sectional views of the integrated circuit in Fig. 1 according to some embodiments. The integrated circuit 100 comprises deep first-layer conductors and flat first-layer conductors extending in the X direction. The integrated circuit 100 also comprises deep second-layer conductors and flat second-layer conductors extending in the Y direction. The deep first-layer conductors (111D, 112D, 113D, 115D, 117D, 118D, and 119D) and the flat first-layer conductors (111S, 112S, 117S, and 118S) are located in a first conductive layer. The deep second-layer conductors (123D and 128D) and the flat second-layer conductors (122S, 123S, 127S, and 128S) are located in a second conductive layer.

[0008] The integrated circuit 100 comprises a first active device D1 and a second active device D2. The output of the first active device D1 is electrically connected to an input of the second active device D2 via a conductive path 101. The conductive path 101 includes segments of the first layer deep trace 112D, the second layer deep trace 123D, the first layer deep trace 115D, the second layer deep trace 128D, and the first layer deep trace 118D. The via 1V1 electrically connects the first layer deep trace 112D to the second layer deep trace 123D. The via 1V2 electrically connects the second layer deep trace 123D to the first layer deep trace 115D. The via 1V3 electrically connects the first layer deep trace 115D to the second layer deep trace 128D.The via connection 1V4 electrically connects the deep trace 128D of the second layer to the deep trace 118D of the first layer. The output of the first active device D1 is electrically connected to the deep trace 112D of the first layer, and the input of the second active device D2 is electrically connected to the deep trace 118D of the first layer.

[0009] In Fig. 1. Conductor 101 includes the deep traces of the first layer and the deep traces of the second layer, while conductor 101 excludes the shallow traces of the first layer and the shallow traces of the second layer. That is, the shallow traces of the first layer and the shallow traces of the second layer are missing from conductor 101. The resistance value of a deep trace of the first layer per unit length is lower than the resistance value of a shallow trace of the first layer per unit length, while the capacitive value of a deep trace of the first layer per unit length is higher than the capacitive value of a shallow trace of the first layer per unit length.Similarly, the resistance value of a deep second-layer conductor per unit length is lower than the resistance value of a shallow second-layer conductor per unit length, while the capacitive value of a deep second-layer conductor per unit length is higher than the capacitive value of a shallow second-layer conductor per unit length. The geometric distinctions between the deep first-layer conductors and the shallow first-layer conductors are shown in the cross-sectional views of the diagram. Fig. 2A to Fig. Recognizable in 2D. The geometric distinctions between the deep conduits of the second layer and the shallow conduits of the second layer are visible in the cross-sectional views of the Fig. 2A to Fig. 2D also recognizable.

[0010] The cross-sectional views of the integrated circuit 100 in section planes, as defined by lines AA', BB' and CC' in Fig. 1 are specified in Fig. 2A, Fig. 2B and Fig. 2C is shown accordingly. Fig. 2A to Fig. In 2C, the deep conductors 111D and 112D of the first layer and the shallow conductors 111S and 112S of the first layer are deposited over an insulating layer 205. Each of the deep conductors 111D and 112D of the first layer extends into the interlayer dielectric 210 with a depth d1 along the Z-direction. Each of the shallow conductors of the first layer 111S and 112S extends into the interlayer dielectric 210 with a depth s1 along the Z-direction. The depth d1 of the deep conductors of the first layer is greater than the depth s1 of the shallow conductors of the first layer.

[0011] In Fig. 2A to Fig. 2C is the interlayer dielectric 220 deposited above the interlayer dielectric 210 and above the deep conductors of the first layer and the shallow conductors of the first layer. In Fig. In layer 2A, the flat conductor 122S of the second layer extends along the Y-direction and is embedded in the interlayer dielectric 220 with a depth of s2. Fig. In layer 2B, the deep conductor 123D of the second layer extends along the Y-direction and is embedded in the interlayer dielectric 220 with a depth d2. Furthermore, the deep conductor 123D of the second layer is electrically connected to the deep conductor 112D of the first layer via the via 1V1. Fig. 2C, the cross-sections of the deep conduits of the second layer and the shallow conduits of the second layer do not appear in the cross-sectional view along the section plane defined by line CC' in Fig. 1 is specified.

[0012] The cross-sectional view of the integrated circuit 100 in the section plane defined by the line PP' in Fig. 1 is specified, is in Fig. Displayed in 2D. Fig. In the second layer, the deep conductor 122D and the shallow conductors 122S and 123S of the second layer are deposited above the interlayer dielectric 210. The deep conductor 123D of the second layer extends into the interlayer dielectric 220 with a depth d2 along the Z-direction. Each of the shallow conductors of the second layer 122S and 123S extends into the interlayer dielectric 220 with a depth s2 along the Z-direction. The depth d2 of the deep conductors of the second layer is greater than the depth s2 of the shallow conductors of the second layer. Fig. The deep conductor 112D of the first layer extends along the X-direction and is embedded in the interlayer dielectric 210. The deep conductor 123D of the second layer is electrically connected to the deep conductor 112D of the first layer via the via 1V1.

[0013] In Fig. 2A to Fig. In 2D, the depths of the first layer's deep conductors and the first layer's shallow conductors are set based on the design specifications, and the depths of the second layer's deep conductors and the second layer's shallow conductors are also set based on the design specifications. The difference between the depth d1 of the first layer's deep conductors and the depth s1 of the first layer's shallow conductors refers to the resistance and capacitance values ​​between the deep and shallow conductors of the first layer. The difference between the depth d2 of the second layer's deep conductors and the depth s2 of the second layer's shallow conductors refers to the resistance and capacitance values ​​between the deep and shallow conductors of the second layer.The difference in depth between d1 and d2, as well as the difference in depth between s1 and s2, are also related to other design considerations. In some embodiments, d1 differs from d2. In some embodiments, d1 is the same as d2. In some embodiments, s1 differs from s2. In some embodiments, s1 is the same as s2.

[0014] Fig. Figure 3A is a cross-sectional view of deep conduits and shallow conduits with labeled depth dimensions according to some embodiments. Fig. Figure 3B is a diagram of a curve of specific resistance and capacitance plotted against the change in the depth of the conductor tracks, according to some embodiments. In the example of Fig. 3A are the deep conductors, labeled with the letter "A", which are modified from the uniform conductors in that the deep conductors extend further into the interlayer dielectric 210 than the uniform conductors, and the shallow conductors, labeled with the letter "B", which are modified from the uniform conductors in that the deep conductors extend less far into the interlayer dielectric 210 than the uniform conductors. The uniform conductors occur in designs where all conductor tracks in the interlayer dielectric 210 have the same depth "h". Fig. 3A to Fig. 3B, the depth “d” of the deep conduits and the depth “s” of the shallow conduits are compared with the depth “h” of the uniform conduits.

[0015] In Fig. In Figure 3B, curve 310D is a plot of the relative change in capacitance ΔCt as a function of the relative change in height LA ​​= (dh) / h of the deep conduit, and curve 320D is a plot of the relative change in resistance ΔRs as a function of the relative change in height LA ​​= (dh) / h of the deep conduit. As the depth of the deep conduit increases, the capacitance value in curve 310D increases, and the resistance value in curve 320D decreases. For example, if the depth of the deep conduit increases by 30%, the capacitance value in curve 310D increases by 14%, and the resistance value in curve 320D decreases by 30%. Consequently, as the depth of the deep conduit increases, the changes in capacitance and resistance cause a change in the RC constant of the deep conduit. In the example of Fig. 3B decreases the RC constant of a deep conduit by 20% per unit length when the depth of the deep conduit increases by 30%.

[0016] In Fig. In Figure 3B, curve 310S is a plot of the relative change in capacitance ΔCt as a function of the relative change in height LB=(sh) / h of the flat line, and curve 320S is a plot of the relative change in resistance ΔRs as a function of the relative change in height LB=(sh) / h of the flat line. As the depth of the flat line decreases, the capacitance value in curve 310S decreases and the resistance value in curve 320S increases. For example, if the depth of the flat line decreases by 30%, the capacitance value in curve 310S decreases by 16% and the resistance value in curve 320S increases by 65%. Consequently, as the depth of the flat line decreases, the changes in capacitance and resistance cause a change in the RC constant of the flat line. In the example of Fig. 3B The RC constant of a flat conductor increases by 39% per unit length when the depth of the flat conductor decreases by 30%.

[0017] In the example of Fig. 3B The RC constant of a deep trace is smaller than the RC constant of a shallow trace. In some embodiments, deep traces are selected to form signal paths that require reduced time delays due to the RC constant of the traces. In the embodiments from Fig. 1. The conductor path 101 between the first active device D1 and the second active device D2 is formed by the deep conductor 112D of the first layer, the deep conductor 123D of the second layer, the deep conductor 115D of the first layer, the deep conductor 128D of the second layer, and the deep conductor 118D of the first layer. It is expected that the conductor path 101 will have a smaller RC constant than the RC constant of an alternative path formed by a combination of the flat conductors of the first layer and / or the flat conductors of the second layer for connecting the first active device D1 to the second active device D2. On the other hand, it is expected that an alternative conductor path formed by a combination of the flat conductors of the first layer and / or the flat conductors of the second layer will have smaller stray capacitances.

[0018] Since the characteristics of a deep trace differ from those of a shallow trace, selecting the deep and shallow traces for different types of traces in an integrated circuit would allow for some performance improvements. In some embodiments, the traces of interest in an integrated system are ranked based on the delay time of each trace, and those with a delay time longer than a critical delay time are selected to form a list of selected traces for speed improvements. In some embodiments, the critical delay time is the delay time equal to zero idle time.Idle time is the time that one task can be delayed without delaying another task or affecting the completion of the overall task of a circuit system. In some embodiments, a selected path is formed from the list for speed improvements based on deep traces (e.g., trace 101 in [reference]). Fig. 1) In some embodiments, the automatic placement and routing (APR) program is configured to find deep first-layer traces and deep second-layer traces to form the selected path for speed improvements. In some embodiments, the APR program is also configured to find shallow first-layer traces and shallow second-layer traces to form one or more traces that are subject to stray capacitance reduction.

[0019] In Fig. 2A to Fig. In 2D, the deep conductors 111D to 112D of the first layer and the flat conductors 111S to 112S of the first layer are located in a first conductive layer above an insulating layer 205, and the deep conductor 123D of the second layer and the flat conductors 122S and 123S of the second layer are located in a second conductive layer above the first conductive layer.In some embodiments, the insulating layer 205 is an upper insulating layer manufactured in the front-end-of-line (FEOL) process, and the first conductive layer (with the deep first-layer conductors and the flat first-layer conductors) is a first metal layer Mo located directly above the fabricated transistors in the integrated circuit, while the second conductive layer (with the deep second-layer conductors and the flat second-layer conductors) is a second metal layer M1 located directly above the first metal layer Mo.

[0020] In some alternative embodiments, the insulating layer 205 is the layer of interlayer dielectric covering the first metal layer Mo, and the first conductive layer (with the deep conductors of the first layer and the flat conductors of the first layer) is a second metal layer M1 located immediately above the first metal layer Mo, while the second conductive layer (with the deep conductors of the second layer and the flat conductors of the second layer) is a third metal layer M2 located immediately above the second metal layer M1. In still some alternative embodiments, the first conductive layer and the second conductive layer are in Fig. 2A to Fig. 2D accordingly a fourth metal layer M3 and a third metal layer M2. In some alternative embodiments, the first conductive layer can be in Fig. 2A to Fig. 2D is a metal layer above the fourth metal layer M3, while the second conductive layer is in Fig. 2A to Fig. 2D is a metal layer above the third metal layer M2. Furthermore, in contrast to the embodiments from Fig. 2A to Fig. 2D, in which the second conductive layer is located above the first conductive layer, the second conductive layer in some alternative embodiments below the first conductive layer.

[0021] In Fig. 2A to Fig. Figure 2D shows two conductive layers, exhibiting both deep and shallow conductors. However, in some embodiments, the integrated circuit can be 100 in Fig. 1 also include additional conductive layers. Some of the additional conductive layers have both deep and shallow conductors, while some of the additional conductive layers of the integrated circuit 100 include only uniform conductors. In the embodiments as described in Fig. 4A to Fig. As shown in Figure 4C, there are, for example, three conductive layers that exhibit both deep and shallow conductions.

[0022] Fig. 4A to Fig. 4C are cross-sectional views of the integrated circuit in Fig. 1 according to some embodiments. The cross-sectional views in Fig. 4A to Fig. 4C lies accordingly in the same section planes as the cross-sectional views in Fig. 2A to Fig. 2C. The cross-sectional views in Fig. 4A to Fig. 4C and Fig. 2A to Fig. 2C exhibit the same first conductive layer and the same second conductive layer. In Fig. 4A to Fig. 4C and Fig. 2A to Fig. In 2C, the first conductive layer has the deep first-layer conductors 111D to 112D and the flat first-layer conductors 111S to 112S embedded in the interlayer dielectric 210, and the second conductive layer has the deep second-layer conductor 123D and the flat second-layer conductor 122S embedded in the interlayer dielectric 220. Fig. 4A to Fig. 4C also shows the third conductive layer. The third conductive layer has the deep third-layer conductors 431D to 432D and the shallow third-layer conductors 431S to 432S, which are embedded in the interlayer dielectric 430.

[0023] In some alternative embodiments, the stacking positions of the first conductive layer, the second conductive layer, and the third conductive layer differ from the stacking positions as described in Fig. 4A to Fig. 4C are shown. In some alternative embodiments, the third conductive layer is located, for example, between the first conductive layer and the second conductive layer. In some alternative embodiments, the third conductive layer is located both under the first conductive layer and under the second conductive layer. In contrast, the third conductive layer is located in Fig. 4A to Fig. 4C both above the first conductive layer and above the second conductive layer. Additionally, in some alternative embodiments, the third conductive layer is formed only with uniform conductors, while the third conductive layer in Fig. 4A to Fig. 4C is formed with both deep and shallow conductors. In some alternative embodiments, the third conductive layer, consisting only of uniform conductors, is located both beneath the first and second conductive layers. In some alternative embodiments, the third conductive layer, consisting only of uniform conductors, is located between the first and second conductive layers.

[0024] In some embodiments, the integrated circuit comprises 100 in Fig. 1 in addition to the three conductive layers that are in Fig. 4A to Fig. As shown in Figure 4C, there are also several conductive layers formed either with uniform conductors or with both deep and shallow conductors. In some alternative embodiments, at least two conductive layers are deposited between the first conductive layer and the second conductive layer. Each of the at least two conductive layers is formed either with uniform conductors or with both deep and shallow conductors. In some alternative embodiments, at least two conductive layers are deposited above the first conductive layer and the second conductive layer. In some alternative embodiments, at least two conductive layers are deposited below the first conductive layer and the second conductive layer.

[0025] In some embodiments, a signal path is formed with a combination of deep conductors in the first conductive layer, in the second conductive layer, and / or in other conductive layers to reduce the RC constant of the signal path. In some embodiments, a signal path is formed with a combination of shallow conductors in the first conductive layer, in the second conductive layer, and / or in other conductive layers to reduce stray capacitances at different segments of the signal path.In some embodiments, a signal guidance path connecting the output of a first active device to the input of a second active device is formed with a combination of the deep conductors and the shallow conductors in the various conductive layers to reduce the overall time delay of the signal propagation from the first active device to the second active device along the signal guidance path.

[0026] Fig. Figure 5 is a layout diagram of an integrated circuit 500 with a signal path formed by a combination of deep traces and flat traces, according to some embodiments. The integrated circuit 500 comprises deep first-layer traces and flat first-layer traces extending in the X direction. The integrated circuit 500 also comprises deep second-layer traces and flat second-layer traces extending in the Y direction. The deep first-layer traces (512D, 513D, 514D, 518D, and 519D) and the flat first-layer traces (512S, 517S, and 518S) are located in a first conductive layer. The deep conductors of the second layer (523D, 525D, 527D and 528D) and the shallow conductors of the second layer (522S, 523S, 526S and 527S) are located in a second conductive layer.

[0027] The integrated circuit 500 comprises a first active device D1 and a second active device D2. The output of the first active device D1 is electrically connected to the input of the second active device D2 by a conductor track comprising a low-resistance section 501 and a low-capacitance section 502. The low-resistance section 501 of the conductor track includes the deep traces of the first layer 512D and 514D and the deep traces of the second layer 523D and 525D. The low-capacitance section 502 of the conductor track includes the flat traces 517S and 518S of the first layer and the flat trace 527S of the second layer.In the low-resistance section 501, the deep conductor of the first layer 512D is electrically connected to the deep conductor of the second layer 523D via the via 5V1, the deep conductor of the second layer 523D is electrically connected to the deep conductor of the first layer 514D via the via 5V2, and the deep conductor of the first layer 514D is electrically connected to the deep conductor of the second layer 525D via the via 5V3. In the low-capacitance section 502, the flat conductor 517S of the first layer is electrically connected to the flat conductor 527S of the second layer via the via 5V5, and the flat conductor 527S of the second layer is electrically connected to the flat conductor 518S of the first layer via the via 5V6.

[0028] When the deep trace of the second layer 525D is electrically connected to the flat trace of the first layer 517S via the via 5V4, the low-resistance section 501 of the trace is electrically connected to the low-capacitance section 502 of the trace. The mutation point 5MP is located at the via 5V4 between the low-resistance section 501 and the low-capacitance section 502 of the trace. The low-resistance section 501 is electrically connected between the output of the first active device D1 and the mutation point 5MP, and the low-capacitance section 502 is electrically connected between the mutation point 5MP and the input of the second active device D2.

[0029] The low-impedance section 501, which has the deep lines, and the low-capacitance section 502, which has the shallow lines, are selected to increase the speed of the signals transmitted from the first active device D1 to the second active device D2, compared with the speed of the signals in some alternative designs in which the signal path from the first active device D1 to the second active device D2 is formed with uniform lines (which have a lesser depth than the deep lines, but a greater depth than the shallow lines).

[0030] In some embodiments, such as those described in Fig. 6A to Fig. As shown in Figure 6F, different configurations of the low-impedance section, the low-capacitance section, and the mutation point are compared to find an optimized configuration. In some embodiments, the optimized configuration is chosen to reduce the overall time delay of the signal propagation from the first active device to the second active device along the signal path. In some embodiments, the selection of the optimized configuration includes consideration of other factors besides the overall time delay, such as electromigration due to IR decay and cross-coupling due to stray capacitance.

[0031] Fig. 6A to Fig. Figure 6F are layout diagrams of integrated circuits with signal paths formed by different configurations of the low-impedance section, the low-capacitance section, and the mutation point, according to some embodiments. Each of the layout diagrams in Fig. 6A to Fig. 6F selects a different position on a signal path than the position for the mutation point. Based on the layout diagrams in Fig. 6A to Fig. Section 6F compares different configurations of the signal path with reference to the reduction of the signal propagation time from the first active device D1 to the second active device D2.

[0032] In an initial configuration, as it appears in Fig. As shown in Figure 6A, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601A and a low-capacitance section 602A. The low-resistance section 601A includes the deep trace 512D of the first layer. The low-capacitance section 602A includes the flat trace 522S of the second layer, the flat traces 614S of the first layer, the flat trace 625S of the second layer, the flat trace 517S of the first layer, the flat trace 527S of the second layer, and the flat trace 518S of the first layer (which are connected to each other by vias 6V2, 6V3, 6V4, 6V5, and 6V6, respectively). The mutation point 6MP is located at the via 6V1, which electrically connects the deep trace 512D of the first layer to the flat trace 522S of the second layer.The low-impedance section 601A is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602A is located between the mutation point 6MP and the input of the second active device D2.

[0033] In a second configuration, as seen in Fig. As shown in Figure 6B, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601B and a low-capacitance section 602B. The low-resistance section 601B includes the first-layer deep trace 512D and the second-layer deep trace 523D, which are connected by the via 6V1. The low-capacitance section 602B comprises the first-layer flat traces 614S, the second-layer flat trace 625S, the first-layer flat trace 517S, the second-layer flat trace 527S, and the first-layer flat trace 518S (which are connected by the vias 6V3, 6V4, 6V5, and 6V6, respectively). The mutation point 6MP is located at the via 6V2, which electrically connects the deep conductor 523D of the second layer to the flat conductors 614S of the first layer.The low-impedance section 601B is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602B is located between the mutation point 6MP and the input of the second active device D2.

[0034] In a third configuration, which is in Fig. As shown in Figure 6C, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601C and a low-capacitance section 602C. The low-resistance section 601C includes the first-layer deep trace 512D, the second-layer deep trace 523D, and the first-layer deep trace 514D (which are connected to each other by vias 6V1 and 6V2, respectively). The low-capacitance section 602C comprises the second-layer flat trace 625S, the first-layer flat trace 517S, the second-layer flat trace 527S, and the first-layer flat trace 518S (which are connected to each other by vias 6V4, 6V5, and 6V6, respectively). The mutation point 6MP is located at the via 6V3, which electrically connects the deep conductor 514D of the first layer to the flat conductor 625S of the second layer.The low-impedance section 601C is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602C is located between the mutation point 6MP and the input of the second active device D2.

[0035] In a fourth configuration, which is in Fig. As shown in Figure 6D, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601D and a low-capacitance section 602D. The low-resistance section 601D includes the first-layer deep trace 512D, the second-layer deep trace 523D, the first-layer deep trace 514D, and the second-layer deep trace 525D (which are connected to each other by vias 6V1, 6V2, and 6V3, respectively). The low-capacitance section 602D includes the first-layer flat trace 517S, the second-layer flat trace 527S, and the first-layer flat trace 518S (which are connected to each other by vias 6V5 and 6V6, respectively). The mutation point 6MP is located at the via 6V4, which electrically connects the deep conductor 525D of the second layer to the flat conductor 517S of the first layer.The low-impedance section 601D is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602D is located between the mutation point 6MP and the input of the second active device D2.

[0036] In a fifth configuration, which is in Fig. As shown in Figure 6E, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601E and a low-capacitance section 602E. The low-resistance section 601E includes the first-layer deep trace 512D, the second-layer deep trace 523D, the first-layer deep trace 514D, the second-layer deep trace 525D, and the first-layer deep trace 517D (which are connected to each other by vias 6V1, 6V2, 6V3, and 6V4, respectively). The low-capacitance section 602E includes the second-layer flat trace 527S and the first-layer flat trace 518S, which are electrically connected to each other by via 6V6. The mutation point 6MP is located at the via 6V5, which electrically connects the deep conductor 517D of the first layer to the flat conductor 527S of the second layer.The low-impedance section 601E is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602E is located between the mutation point 6MP and the input of the second active device D2.

[0037] In a sixth configuration, which is in Fig. As shown in Figure 6F, the conductor track from the first active device D1 to the second active device D2 comprises a low-resistance section 601F and a low-capacitance section 602F. The low-resistance section 601F includes the first-layer deep trace 512D, the second-layer deep trace 523D, the first-layer deep trace 514D, the second-layer deep trace 525D, the first-layer deep trace 517D, and the second-layer deep trace 527D (which are connected to each other by vias 6V1, 6V2, 6V3, 6V4, and 6V5, respectively). The low-capacitance section 602F includes the first-layer flat trace 518S. The mutation point 6MP is located at the via 6V6, which electrically connects the second-layer deep trace 527D to the first-layer flat trace 518S.The low-impedance section 601F is located between the output of the first active device D1 and the mutation point 6MP. The low-capacitance section 602F is located between the mutation point 6MP and the input of the second active device D2.

[0038] In some embodiments, the automatic placement and routing program (APR program) compares the total time delay of the signal propagation from the first active device D1 to the second active device D2 in each of the configurations in Fig. 6A to Fig. 6F, and the APR program then selects one of the configurations in Fig. 6A to Fig. 6F, which has the smallest overall signal propagation delay. The mutation point 6MP chosen by the APR program is located at one of the via connections (such as 6V1, 6V2, 6V3, 6V4, 6V5, or 6V6).

[0039] In some embodiments, several signal pathways share a common section of the signal pathways. The selection of the mutation point for each signal pathway is achieved by comparing the total signal propagation delay in each pathway with different configurations.

[0040] Fig. Figure 7 is a layout diagram of an integrated circuit 700 with multiple signal paths formed by combinations of deep traces and shallow traces, according to some embodiments. Fig. 7 The output of the first active device D1 is electrically connected to the input of the second active device D2 by a first conductor track comprising a low-resistance section 701 and a low-capacitance section 702, and the output of the first active device D1 is electrically connected to the input of the third active device D3 by a second conductor track comprising a low-resistance section 703 and a low-capacitance section 704.

[0041] In Fig. 7 is the low-resistance section 701 of the first conductor track in Fig. 7 identical to the low-resistance section 501 in Fig. 5. The low-capacity section 702 of the first conductor track in Fig. 7 is identical to the low-capacity section 502 in Fig. 5. The first mutation point 7MP1 for the first conductor track in Fig. 7 is located at the via connection 5V4. The low-resistance section 701 is electrically connected between the output of the first active device D1 and the first mutation point 7MP1, and the low-capacitance section 702 is electrically connected between the first mutation point 7MP1 and the input of the second active device D2.

[0042] In Fig. Section 703 of the second low-resistance trace comprises the first layer deep trace 512D, the second layer deep trace 523D, the first layer deep trace 514D, and the second layer deep trace 525D (connected accordingly by vias 5V1, 5V2, and 5V3). Section 704 of the second low-capacitance trace comprises the first layer flat trace 715S, the second layer flat trace 727S, and the first layer flat trace 718S (connected accordingly by vias 7V5 and 7V6). The second mutation point 7MP2 for the second trace in Fig. 7 is located at the via 7V4, which electrically connects the deep trace 525D of the second layer to the flat trace 715S of the first layer. The low-resistance section 703 is electrically connected between the output of the first active device D1 and the second mutation point 7MP2, and the low-capacitance section 704 is electrically connected between the second mutation point 7MP2 and the input of the third active device D3.

[0043] In Fig. 7. The first and second conductors share a common conductive path running from the output of the first active device D1 to the deep conductor 525D of the second layer, if the first conductor runs from the first active device D1 to the second active device D2 and the second conductor runs from the first active device D1 to the third active device D3. Here, the deep conductor 525D of the second layer is a fan-out node that branches the common conductor into the first and second conductors. The low-capacitance section 702 of the first conductor forms at least one section of a first branched conductor between the fan-out node and the input of the second active device D2.The low-capacitance section 704 of the second conductor trace forms at least one section of a second branched conductor trace between the fan-out node and the input of the third active device D3. The first branched conductor trace and the second branched conductor trace are each conductor traces that exclude the deep leads of the first layer and the deep leads of the second layer, respectively. In some embodiments, each branched conductor trace excludes not only deep leads in the first conductive layer and in the second conductive layer, but also deep leads in other conductive layers. In some embodiments, while each branched conductor trace excludes deep leads in the first conductive layer and in the second conductive layer, each branched conductor trace nevertheless includes deep leads in one or more other conductive layers.

[0044] In each of the conductor tracks from the first active device D1 to the second active device D2 in Fig. 1, Fig. 5 and Fig. 6A to Fig. In 6F, a mutation point is located between a low-resistance section of the conductor track and a low-capacitance section of the conductor track. In some embodiments, the mutation point is located at a via connection. In some embodiments, such as in each of the conductor tracks in Fig. 8A to Fig. 8B, the mutation point is a fan-out node that connects at least two branched traces, and each of the at least two branched traces includes a low-capacitance section of the trace.

[0045] Fig. 8A to Fig. Figure 8B shows schematic diagrams of integrated circuits with multiple signal paths formed by combinations of deep traces and shallow traces, according to some embodiments. Fig. 8A comprises a first conductor track from the first active device D1 to the second active device D2, consisting of a low-resistance section and a low-capacitance section. The low-resistance section of the first conductor track includes a deep first-layer trace 862D and a deep second-layer trace 872D, electrically connected by a via 8V67. The low-capacitance section of the first conductor track includes a flat first-layer trace 868S and a flat second-layer trace 878S, electrically connected by a via 8V76. The deep first-layer trace 862D and the flat first-layer trace 868S are located in a first conductive layer. The deep second-layer trace 872D and the flat second-layer trace 878S are located in a second conductive layer.In some embodiments, the integrated circuits comprise at least eight metal layers (from Mo to M7) above the top insulating layer, manufactured in a front-end-of-line (FEOL) process. The first conductive layer is the seventh metal layer, M6 (located above the other six metal layers, Mo to M5), and the second conductive layer is the eighth metal layer, M7 (located above the other seven metal layers, M to M6).

[0046] In Fig. 8A is the low-resistance section of the first conductor track electrically connected to the low-capacitance section of the first conductor track by the second-layer conductor 874. In some embodiments, the second-layer conductor 874 is a deep second-layer conductor. In some embodiments, the second-layer conductor 874 is a shallow second-layer conductor. In some embodiments, the second-layer conductor 874 is a uniform second-layer conductor (having a depth greater than that of a shallow second-layer conductor but less than that of a deep second-layer conductor). Fig. 8A, the second layer line 874, is a fan-out node. The first trace includes a first mutation point 8MP1 at the fan-out node between the low-resistance section and the low-capacitance section. The second trace, from the first active device D1 to the third active device D3, branches off from the first trace (which runs from the first active device D1 to the second active device D2) at the fan-out node (i.e., second layer line 874). The second trace includes a low-resistance section and a low-capacitance section. The low-resistance section is located between the first active device D1 and a second mutation point 8MP2 at the fan-out node. The low-capacitance section is located between the second mutation point 8MP2 and the input of the third active device D3.The low-resistance section of the second conductor track comprises the deep conductor 862D of the first layer and the deep conductor 872D of the second layer. The low-capacitance section of the second conductor track comprises a flat conductor 866S of the first layer and a flat conductor 876S of the second layer, which are electrically connected by a suitable via.

[0047] In some embodiments, the low-resistance section of the first conductor track, in addition to the deep conductor 862D of the first layer in the seventh metal layer M6 and the deep conductor 872D of the second layer in the eighth metal layer M7, also includes conductor tracks 822D, 832D, 842D, and 852D, which are electrically interconnected by the corresponding via connections 8V23, 8V34, and 8V45. Conductor track 852D is electrically connected to the deep conductor 862D of the first layer by the via connection 8V56. Conductor track 822D is electrically connected to the output of the first active device D1. In some embodiments, conductor track 822D is electrically connected to the output of the first active device D1 by some via connections and the conductor tracks in the first metal layer Mo and in the second metal layer M1 (which are not shown in the figure).In some embodiments, conductor 822D is a deep trace in the third metal layer M2, conductor 832D is a deep trace in the fourth metal layer M3, conductor 842D is a deep trace in the fifth metal layer M4, and conductor 852D is a deep trace in the sixth metal layer M5. In some embodiments, one or more of the conductors 822D, 832D, 842D, and 852D are not deep traces. In some embodiments, one or more of the conductors 822D, 832D, 842D, and 852D are flat traces or uniform traces.

[0048] In some embodiments, the low-capacitance section of the first conductor track connected to the second active device D2 includes, in addition to the first-layer flat conductor 868S in the seventh metal layer M6 and the second-layer flat conductor 978S in the eighth metal layer M7, conductor tracks 828S, 838S, 848S, and 858S, which are electrically interconnected by the corresponding via connections 8V32, 8V43, and 8V54, respectively. Conductor track 858S is electrically connected to the first-layer flat conductor 868S by the via connection 8V65. Conductor track 828S is electrically connected to the input of the second active device D2.In some embodiments, conductor 828S is electrically connected to the input of the second active device D2 via some via connections and some conductors in the first metal layer Mo and in the second metal layer M1 (not shown in the figure). In some embodiments, conductor 828S is a flat conductor in the third metal layer M2, conductor 838S is a flat conductor in the fourth metal layer M3, conductor 848S is a flat conductor in the fifth metal layer M4, and conductor 858S is a flat conductor in the sixth metal layer M5. In some embodiments, one or more of the conductors 828S, 838S, 848S, and 858S are not flat conductors. In some embodiments, one or more of the conductors 828S, 838S, 848S, and 858S are deep conductors or uniform conductors.

[0049] In some embodiments, the low-capacitance section of the second conductor track connected to the third active device D3 includes, in addition to the first-layer flat conductor 866S in the seventh metal layer M6 and the second-layer flat conductor 976S in the eighth metal layer M7, conductor tracks 826S, 836S, 846S, and 856S, which are electrically interconnected by various vias. Conductor track 856S is electrically connected to the first-layer flat conductor 866S by a corresponding via. Conductor track 826S is electrically connected to the input of the third active device D3. In some embodiments, conductor track 826S is electrically connected to the input of the third active device D3 by several vias and several conductor tracks in the first metal layer Mo and in the second metal layer M1.In some embodiments, conductor 826S is a flat trace in the third metal layer M2, conductor 836S is a flat trace in the fourth metal layer M3, conductor 846S is a flat trace in the fifth metal layer M4, and conductor 856S is a flat trace in the sixth metal layer M5. In some embodiments, one or more of the conductors 826S, 836S, 846S, and 856S are not flat traces. In some embodiments, one or more of the conductors 826S, 836S, 846S, and 856S are deep traces or uniform traces.

[0050] If the first conductor track from the first active device D1 to the second active device D2 is implemented with a low-resistance section and a low-capacitance section, the signal propagation delay along the first conductor track is reduced. In a specific example, as in Fig. As shown in Figure 8A, the signal propagation delay in the first conductor track with the low-resistance and low-capacitance sections is reduced by 5.4% compared to an alternative design where all conductors in the first conductor track are implemented as single lines. The 5.4% reduction is the sum of the individual reductions of 1.5%, 1.8%, 0.2%, 0.4%, 0.4%, and 1.1%, respectively, in metal layers M7, M6, M5, M4, M3, and M2.

[0051] In the specific example, as in Fig. As shown in Figure 8A, the deep second-layer trace 872D is located in the low-resistance section and the flat second-layer trace 878S is located in the low-capacitance section of the eighth metal layer M7. The reduction in time delay provided by the deep second-layer trace 872D and the flat second-layer trace 878S is 1.5%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8A, the deep second-layer trace 872D and the flat second-layer trace 878S are located in the low-capacitance section of the eighth metal layer M7. Fig. As shown in Figure 8A, the deep trace 862D of the first layer is located in the low-resistance section and the flat trace 868S of the first layer is located in the low-capacitance section of the seventh metal layer M6. The reduction in time delay achieved by the deep trace 862D and the flat trace 868S of the first layer is 1.8%, compared to the alternative design with uniform traces.

[0052] In the specific example, as in Fig. As shown in Figure 8A, the deep trace 852D and the flat trace 858S are located in the sixth metal layer M5. The reduction in time delay provided by the deep trace 852D and the flat trace 858S is 0.2%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8A, the deep trace 852D and the flat trace 858S reduce the time delay by 0.2% compared to the alternative design with uniform traces. Fig. As shown in Figure 8A, the deep trace 842D and the flat trace 848S are located in the fifth metal layer M4. The reduction in time delay achieved by the deep trace 842D and the flat trace 848S is 0.4%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8A, the deep trace 842D and the flat trace 848S are located in the fifth metal layer M4. Fig. As shown in Figure 8A, the deep trace 832D and the flat trace 838S are located in the fourth metal layer M3. The reduction in time delay achieved by the deep trace 832D and the flat trace 838S is 0.4%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8A, the deep trace 832D and the flat trace 838S are located in the fourth metal layer M3. Fig. As shown in Figure 8A, the deep trace 822D and the flat trace 828S are located in the third metal layer M2. The reduction in time delay achieved by the deep trace 822D and the flat trace 828S is 1.1%, compared to the alternative design with uniform traces.

[0053] In the embodiments from Fig. 8A includes the reduction of the signal propagation delay in the first conductor track and the contributions from the delay reductions in the metal layers M7, M6, M5, M4, M3, and M2. In some embodiments, such as the specific example in Fig. 8B, the reduction in signal propagation delay in the first conductor is dominated by the delay reductions in the first conductive layer and the second conductive layer if the low-resistance and low-capacitance sections of the first conductor implemented in the first and second conductive layers have a total length much greater than the total length of the conductors for the same path in all other conductive layers. Fig. 8B the first conductive layer is located in the ninth metal layer M8 and the second conductive layer is located in the tenth metal layer M9.

[0054] In Fig. 8B comprises the first conductor track from the first active device D1 to the second active device D2, consisting of a low-resistance section and a low-capacitance section. The low-resistance section of the first conductor track includes a first-layer deep trace 882D in the ninth metal layer M8 and a second-layer deep trace 892D in the tenth metal layer M9. The first-layer deep trace 882D and the second-layer deep trace 892D are electrically connected to each other via the via 8V89. The first-layer deep trace 882D in the low-resistance section is electrically connected to the output of the first active device D1 via the via 8V78 and other vias / traces in various metal layers (from Mo to M7).The first low-capacitance section of the conductor comprises a first-layer flat conductor 888S in the ninth metal layer M8 and a second-layer flat conductor 898S in the tenth metal layer M9. The first-layer flat conductor 888S and the second-layer flat conductor 898S are electrically connected to each other via the 8V98 via. The first-layer flat conductor 888S in the low-capacitance section is electrically connected to the input of the second active device D2 via the 8V78 via and further vias / traces in different metal layers (from Mo to M7).

[0055] In Fig. 8B is the low-resistance section of the first conductor track, electrically connected to the low-capacitance section of the first conductor track by the second-layer conductor 894. In some embodiments, the second-layer conductor 894 is a deep second-layer conductor. In some embodiments, the second-layer conductor 894 is a shallow second-layer conductor. In some embodiments, the second-layer conductor 894 is a uniform second-layer conductor. The second-layer conductor 894 is a fan-out node. The first conductor track (leading from the first active device D1 to the second active device D2) and the second conductor track (leading from the first active device D1 to the third active device D3) branch from each other at the fan-out node (i.e., the second-layer conductor 894).

[0056] In Fig. 8B, the second conductor track also includes a low-resistance section and a low-capacitance section. The low-resistance section is located between the first active device D1 and the second-layer trace 894. The low-capacitance section is located between the second-layer trace 894 and the third active device D3. The low-resistance section of the second conductor track includes the first-layer deep trace 882D and the second-layer deep trace 892D. The low-capacitance section of the second conductor track includes a first-layer flat trace 886S and a second-layer flat trace 896S, which are electrically connected by a suitable via.

[0057] In Fig. 8B The signal propagation delay along the first conductor track is reduced if the first conductor track from the first active device D1 to the second active device D2 is implemented with a low-resistance section and a low-capacitance section. In the specific example, as shown in Fig. As shown in Figure 8B, the reduction in signal propagation delay in the first conductor is dominated by the delay reductions in the ninth metal layer M8 and the tenth metal layer M9. In the specific example shown in Figure 8B, the reduction in signal propagation delay in the first conductor is dominated by the delay reductions in the ninth metal layer M8 and the tenth metal layer M9. Fig. As shown in Figure 8B, the reduction in time delay achieved by the deep trace 882D of the first layer and the shallow trace 888S of the first layer in the ninth metal layer M8 is 2.8%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8B, the time delay is reduced by 2.8%. Fig. As shown in Figure 8B, the reduction in time delay achieved by the deep trace 892D of the second layer and the shallow trace 898S of the second layer in the tenth metal layer M9 is 2.0%, compared to the alternative design with uniform traces. In the specific example shown in Figure 8B, the time delay is reduced by 2.0%. Fig. As shown in Figure 8B, the overall time delay of the signal propagation in the first conductor track is reduced by 4.7% compared to an alternative design where all conductor tracks in the first conductor track are implemented as uniform conductors.

[0058] In some embodiments, each of the traces in the first conductor is implemented as a deep trace if the total length of the first conductor from the first active device D1 to the second active device D2 is less than a predefined distance. In some embodiments, the value of the predefined distance used by the APR program is set by the user. In some embodiments, the value of the predefined distance used by the APR program is read from a database or a technology file.

[0059] In some embodiments, such as in Fig. As shown in Figure 9, the output of the first active device D1 is electrically coupled to several receiver devices (such as D2A, D2B, D2C, and D2D). In some embodiments, if the total length of a conductor track from the first active device D1 to each receiver device (such as D2A, D2B, D2C, or D2D) is less than a predetermined distance, the conductor tracks in all conductor tracks from the output of the first active device D1 to the several receiver devices D2A to D2D are implemented with deep conductors in at least two conductive layers. Fig. 9. The conductor traces branch from the first active device D1 to the multiple receiver devices D2A-D2D at the fan-out node, which is conductor 934D. The common section of the conductor traces from the first active device D1 to the multiple receiver devices D2A-D2D runs from the output of the first active device D1 to conductor 934D.

[0060] In Fig. The common section of the conductors comprises the first layer deep conductor 922D in the third metal layer M2 and the second layer deep conductor 932D in the fourth metal layer M3. The first layer deep conductor 922D and the second layer deep conductor 932D are electrically connected to each other by the via 9V23. The first layer deep conductor 922D is electrically connected to the output of the first active device D1 via various vias and conductors (which also include the second layer deep conductor 912D in M1). The common section of the conductors is electrically connected to the branched path to each receiver device (such as D2A, D2B, D2C, or D2D) by conductor 934D. Fig. 9 is the conductor track 934D implemented as a deep conductor in the fourth metal layer M3.

[0061] In Fig. 9 The branched path to each receiver device (such as D2A, D2B, D2C, or D2D) comprises a deep trace (929D, 928D, 927D, or 926D, respectively) in the third metal layer M2 and a deep trace (939D, 938D, 937D, or 936D, respectively) in the fourth metal layer M3. Each of the deep traces 939D, 938D, 937D, and 936D is electrically connected between the fan-out node (i.e., trace 934D) and one of the corresponding deep traces 929D, 928D, 927D, or 926D. Each of the deep lines 929D, 928D, 927D and 926D is electrically connected to the input of one of the corresponding receiver devices D2A, D2B, D2C or D2D through various via connections and various conductor tracks (such as through one of the corresponding deep lines 919D, 918D, 917D or 916D in the second metal layer M1).

[0062] In Fig. 9. The reduction in the time delay of the signal propagation in the conductor track to each receiver device is dominated by the time delay reductions in the third metal layer M2 and in the fourth metal layer M3 if the total length of the deep conductors in the metal layers M2 and M3 for the conductor track from the first active device D1 to a receiver device (such as D2A, D2B, D2C or D2D) is longer than the total length of the conductor tracks for the same conductor track in all other conductive layers.

[0063] In the specific example, as in Fig. As shown in Figure 9, the reduction in time delay due to the deep trace 922D in the third metal layer M2 is 2.7% and the reduction in time delay due to the deep trace 932D in the fourth metal layer M3 is 1.1%, compared to the alternative design with uniform traces. In the specific example, as shown in Fig. As shown in Figure 9, the reduction in time delay due to the deep trace (929D, 928D, 927D, or 926D) in the third metal layer M2 on a branched path is 0.2%, and the reduction in time delay due to the deep trace (939D, 938D, 937D, or 936D) in the fourth metal layer M3 on a branched path is -0.3%, compared to the alternative design with uniform traces. In the specific example, as shown in Fig. As shown in Figure 9, the overall time delay of the signal propagation in the conductor track from the first active device D1 to one of the receiver devices (such as D2A, D2B, D2C or D2D) is reduced by 3.7% compared to an alternative design in which all conductor tracks in the conductor path are implemented as uniform conductors.

[0064] Fig. Figure 10 is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments. The sequence in which the operations of method 1000 are performed is shown. Fig. The figures shown in Figure 10 are purely illustrative; the operations of Procedure 1000 can be performed in a different format than the one shown in Figure 10. Fig. The sequence shown in section 10 is to be carried out. It is understood that further operations may be performed before, during and / or after procedure 1000, which is described in Fig. 10 is shown, can be executed, and some other processes may only be briefly described herein.

[0065] In operation 1010 of method 1000, a conductor track is selected that connects a first active device to a second active device. In some embodiments, the selected conductor track is chosen for speed improvements because the selected conductor track has a delay time that is longer than a critical delay time when the selected conductor track is implemented with uniform conductors.

[0066] In operation 1015 of procedure 1000, the length of the conductor track in an APR program is compared to a predefined value. If the conductor track length is less than the predefined value, the process flow of procedure 1000 continues with operation 1018. Conversely, if the conductor track length is not less than the predefined value, the process flow of procedure 1000 continues with operation 1020.

[0067] In operation 1018 of procedure 1000, which follows the sequence of the "YES" decision from operation 1015, deep conductors for the conductor track are selected in at least two conductive layers. In the exemplary embodiments from Fig. 9. The conductor tracks in the metal layers M2 and M3 are implemented with deep conductors for all conductor tracks from the output of the first active device D1 to the multiple receiver devices D2A to D2D if the total length of a conductor track from the first active device D1 to each receiver device (such as D2A, D2B, D2C or D2D) is less than a predetermined distance.

[0068] In operation 1020 of procedure 1000, which follows the sequence of the "NO" decision from operation 1015, a group of mutation point candidates is generated. In the exemplary embodiments from Fig. 6A to Fig. 6F comprises the group of mutation point candidates the via connections 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6. In some exemplary embodiments, one or more mutation point candidates are located at a fan-out node. Examples of the fan-out node include the deep second-layer trace 525D in Fig. 7, line 874 of the second shift in Fig. 8A, or line 894 of the second layer in Fig. 8B.

[0069] In operation 1030 of procedure 1000, the time delays of signal propagation in the conductor track are evaluated for at least two mutation point candidates. In the exemplary embodiments of Fig. 6A to Fig. In 6F, the time delay of a signal propagation in the conductor track is evaluated for each of the situations when one of the via connections 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 is selected as a mutation point 6MP. In some embodiments, only some of the via connections 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 are evaluated for implementation as mutation points 6MP.

[0070] In operation 1040 of procedure 1000, a mutation point candidate with the smallest time delay is selected as the mutation point based on the time delays obtained in operation 1030. In the exemplary embodiments of Fig. 6A to Fig. 6F selects the mutation point candidate that exhibits the smallest time delay after each of the via connections 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 has been evaluated for implementation as mutation point 6MP. For example, if the via connection 6V4 is selected as mutation point 6MP, the trace from the first active device D1 to the second active device D2 has the smallest time delay. In the exemplary embodiments of Fig. 8A to Fig. 8B, the selected mutation point is located at a fan-out node (i.e., at line 874 of the second layer in Fig. 8A or line 894 of the second layer in Fig. 8B).

[0071] In some embodiments, after the mutation point has been selected, the layout structures for a section of the low-resistance trace and the layout structures for a section of the low-capacitance trace are generated by an APR program. The process then continues with operation 1050.

[0072] In operation 1050 of method 1000, a low-resistance section and a low-capacitance section of the conductor track are fabricated. The low-resistance section of the conductor track comprises one or more deep traces between the output of the first active device and the mutation point. The low-capacitance section of the conductor track comprises one or more shallow traces between the mutation point and the input of the second active device. In the exemplary embodiments of Fig. 6D comprises the low-resistance section 601D, fabricated in operation 1050, the deep conductor 512D of the first layer, the deep conductor 523D of the second layer, the deep conductor 514D of the first layer, and the deep conductor 525D of the second layer. In the exemplary embodiments of Fig. Section 6D comprises the low-capacity section 602D, manufactured in operation 1050, the first-layer flat conductor 517S, the second-layer flat conductor 527S, and the first-layer flat conductor 518S. In the exemplary embodiments of Fig. The low-impedance section 601D is located between the output of the first active device D1 and the mutation point 6MP, and the low-capacitance section 602D is located between the mutation point 6MP and the input of the second active device D2.

[0073] Fig. Figure 11 is a flowchart of a method 1100 for manufacturing at least one deep conduit and at least one shallow conduit according to some embodiments. The sequence in which the operations of method 1100 are performed in Fig. The figures shown in Figure 11 are purely illustrative; the operations of procedure 1100 can be performed in a different format than the one shown in Figure 11. Fig. The sequence shown in section 11 is to be executed. It is understood that further operations may be performed before, during, and / or after the sequence shown in section 11. Fig. The 11 procedures shown can be carried out in 1100, and some other processes can only be briefly described here.

[0074] Fig. 12A to Fig. Figure 12E are cross-sectional views of exemplary device structures that were manufactured during the operations of Method 1100 according to some embodiments. The cross-sectional views of the integrated circuit in Fig. 6F within the cutting planes MM' and NN' (correspondingly through the lines MM' and NN' in Fig. 6F specified) are in Fig. 12E is shown. In the cross-sectional view in the section plane NN' of Fig. In step 12E, the first layer's flat conductor 518S and the first layer's deep conductors 517D to 519D, embedded in the interlayer dielectric 210, are fabricated over an insulating layer 205. The depth of each first layer deep conductor (e.g., 517D, 518D, 519D) is greater than the depth of the first layer's flat conductor 518S. The interlayer dielectric 220 is deposited over the interlayer dielectric 210 and over the first layer's deep and flat conductors. The second layer's deep conductor 527D, extending along the Y-direction, is embedded in the interlayer dielectric 220. Furthermore, the deep conductor 527D of the second layer is electrically connected to the flat conductor 518S of the first layer via the via connection 6V6 and to the deep conductor 517D of the first layer via the via connection 6V5.

[0075] In the cross-sectional view in the section plane MM' of Fig. In step 12E, the flat conductor 518S of the first layer, embedded in the interlayer dielectric 210, is fabricated above the insulating layer 205. The interlayer dielectric 220 is deposited above the interlayer dielectric 210 and above the flat conductor 518S of the first layer. The flat conductors 526S to 527S of the second layer and the deep conductors 527D to 528D of the second layer are fabricated in the interlayer dielectric 220 above the interlayer dielectric 210. Furthermore, the deep conductor 527D of the second layer is electrically connected to the flat conductor 518S of the first layer via the via 6V6.

[0076] The procedure 1100 in Fig. 11 comprises operations 1110, 1120, 1130, 1140, 1150, 1160, and 1170. In operation 1110 of process 1100, a first insulating layer is deposited onto another base insulating layer. In some embodiments, the deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or another suitable deposition process. In some embodiments, the base insulating layer is an upper insulating layer fabricated in the front-end-of-line (FEOL) process. In some embodiments, the base insulating layer is one of the interlayer dielectric (ILD) layers fabricated after the FEOL process. In an exemplary embodiment, as described in Fig. As shown in Figure 12A, the interlayer dielectric 210 is deposited on the insulating layer 205.

[0077] In operation 1120 of method 1100, deep and shallow trenches are formed in the first insulation layer. In some embodiments, the structures of the deep and shallow trenches are defined by a mask layer fabricated above the first insulation layer using lithographic techniques. In some embodiments, the etching processes for forming the deep and shallow trenches include reactive ion deep etching or another suitable etching process. In an exemplary embodiment, as described in Fig. As shown in Figure 12A, a shallow trench 1218S and deep trenches 1217D to 1219D are formed in the interlayer dielectric 210.

[0078] In operation 1130 of method 1100, deep first-layer conduits are formed in the deep trenches and shallow first-layer conduits are formed in the shallow trenches. In some embodiments, metallic materials are deposited into the deep and shallow trenches, and a polishing process, such as a chemical-mechanical polishing (CMP) process, is subsequently performed to planarize and remove excess metallic materials. In some embodiments, the deposition processes for metallic materials include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or another suitable deposition process. In an exemplary embodiment, as shown in Fig. As shown in Figure 12B, the shallow conductors 518S of the first layer and the deep conductors 517D to 519D of the first layer are formed in the interlayer dielectric 210 after the metallic materials are placed in the shallow trenches 1218S and the deep trenches 1217D to 1219D (as shown in Figure 12B). Fig. 12A) are separated.

[0079] In operation 1140 of method 1100, a second insulating layer is deposited over the first insulating layer. In some embodiments, the deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or another suitable deposition process. In an exemplary embodiment, as shown in Fig. As shown in 12C, the interlayer dielectric 210 is deposited onto the interlayer dielectric 210.

[0080] In operation 1150 of method 1100, vias are formed in the second insulating layer. In operation 1160 of method 1100, deep and shallow trenches are formed in the second insulating layer. In some embodiments, the vias, deep trenches, and shallow trenches are formed in several steps of structure formation and etching processes. In some embodiments, the structure formation process includes forming a mask layer over the second insulating layer using lithographic techniques. In some embodiments, the etching processes for forming the vias, deep trenches, and shallow trenches include reactive ion deep etching or another suitable etching process. In an exemplary embodiment, as shown in Fig. Figure 12D shows the via openings 12V5 to 12V6, the shallow trenches 1226S to 1227S and the deep trenches 1227D to 1228D formed in the interlayer dielectric 220.

[0081] In operation 1170 of method 1100, metallic materials are deposited into the via holes, deep trenches, and shallow trenches, thereby forming correspondingly deep second-layer conductors and shallow second-layer conductors in the deep and shallow trenches of the second insulation layer. In an exemplary embodiment, as shown in Fig. As shown in Figure 12E, the flat conductors 526S to 527S of the second layer and the deep conductors 527D to 528D of the second layer are formed in the interlayer dielectric 220 after metallic materials are placed into the via holes 12V5 to 12V6 (in Fig. 12D) and in the shallow trenches 1226S to 1227S and the deep trenches 1227D to 1228D (in Fig. 12D). In addition, the via connections 6V5 are formed, which connects the deep trace of the second layer 527D to the deep trace of the first layer 517D, and the via connections 6V5, which connects the deep trace of the second layer 527D to the flat trace of the first layer 518S, are formed.

[0082] Fig. Figure 13 is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0083] In some embodiments, the EDA system 1300 includes an APR system. The methods described here for designing layout diagrams representing wire routing arrangements can be implemented according to one or more embodiments, for example, using the EDA system 1300 according to some embodiments.

[0084] In some embodiments, the EDA system 1300 is a multi-purpose computing device comprising a hardware processor 1302 and a non-transitory, computer-readable storage medium 1304. The storage medium 1304 is encoded, among other things, with memory and computer program code 1306, i.e., a set of executable instructions. The execution of instructions 1306 by the hardware processor 1302 constitutes (at least partially) an EDA tool that implements a section or all of the procedures described herein according to one or more embodiments (hereinafter referred to as the processes and / or procedures).

[0085] The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an I / O interface 1310 via bus 1308. A network interface 1312 is also electrically connected to the processor 1302 via bus 1308. The network interface 1312 is connected to a network 1314, so that the processor 1302 and the computer-readable storage medium 1304 are in the layer to connect to external elements via network 1314. The processor 1302 is configured to execute computer program code 1306, which is encoded in the computer-readable storage medium 1304, in order to cause the system 1300 to be usable for the execution of a section or all of the aforementioned processes and / or procedures.In one or more embodiments, the processor 1302 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0086] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or such apparatus or device). For example, a computer-readable storage medium 1304 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments that uses optical disks, the computer-readable storage medium 1304 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0087] In one or more embodiments, the storage medium 1304 stores computer program code 1306 configured to cause the system 1300 (where such an embodiment is (at least partially) the EDA tool) to be usable for executing a section or all of the processes and / or procedures mentioned. In one or more embodiments, the storage medium 1304 also stores information that facilitates the execution of a section or all of the processes and / or procedures mentioned. In one or more embodiments, the storage medium 1304 stores a library 1307 of standard cells, comprising such standard cells as disclosed herein. In one or more embodiments, the storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layouts disclosed herein.

[0088] The EDA system 1300 includes the I / O interface 1310. The I / O interface 1310 is coupled to the external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, a numeric keypad, a mouse, a trackball, a trackpad, a touchscreen, and / or cursor keys for transmitting information and commands to the processor 1302.

[0089] The EDA system 1300 also includes the network interface 1312, which is coupled to the processor 1302. The network interface 1312 allows the system 1300 to communicate with the network 1314, to which one or more other computer systems are connected. The network interface 1312 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, a section or all of the aforementioned processes and / or procedures are implemented in two or more systems 1300.

[0090] System 1300 is configured to receive information through I / O interface 1310. The information received through I / O interface 1310 includes one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1302. The information is transferred to processor 1302 via bus 1308. EDA system 1300 is also configured to receive information associated with a user interface (UI) through I / O interface 1310. This information is stored on computer-readable medium 1304 as a user interface (UI) 1342.

[0091] In some embodiments, a section or all of the aforementioned processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, a section or all of the aforementioned processes and / or methods are implemented as a software application that is part of another software application. In some embodiments, a section or all of the aforementioned processes and / or methods are implemented as a plugin for a software application. In some embodiments, at least one of the aforementioned processes and / or methods is implemented as a software application that is a section of an EDA tool. In some embodiments, a section or all of the aforementioned processes and / or methods are implemented as a software application that is used by the EDA System 1300.In some embodiments, a layout diagram comprising standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0092] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory, computer-readable recording medium. Examples of non-transitory, computer-readable recording media include, but are not limited to, external / removable and internal / built-in storage or working memory units, for example, one or more from an optical disc, such as a DVD, a magnetic disc, such as a hard drive, a semiconductor memory, such as a ROM, RAM, memory card, and the like.

[0093] Fig. Figure 14 is a block diagram of a system 1400 for the fabrication of an integrated circuit (IC) and an associated IC fabrication process according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the fabrication system 1400.

[0094] In Fig. The IC manufacturing system 1400 comprises entities such as a design house 1420, a mask house 1430, and an IC manufacturer / fabricator (“Fab”) 1450, which interact with each other in the design, development, and manufacturing cycles and / or services associated with the manufacture of an IC device 1460. The entities in the system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities, providing services to and / or receiving services from one or more of the other entities.In some embodiments, two or more from Design House 1420, Mask House 1430, and IC-Fab 1450 are owned by a single larger company. In some embodiments, two or more from Design House 1420, Mask House 1430, and IC-Fab 1450 coexist in a common facility and use common resources.

[0095] Design House (or Design Team) 1420 produces an IC design layout diagram 1422. The IC design layout diagram 1422 includes various geometric structures designed for an IC device 1460. The geometric structures correspond to structures made of metal, oxide, or semiconductor layers that represent the various components of the IC device 1460 to be manufactured. The different layers combine to form various IC features. For example, a section of the IC design layout diagram 1422 includes various IC features, such as an active region, a gate electrode, source and drain, metal traces or vias of an interlayer connection, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers deposited on the semiconductor substrate.Design House 1420 implements a correct design procedure to create the IC design layout diagram 1422. The design procedure includes one or more logic design, physical design, or location and route. The IC design layout diagram 1422 is represented in one or more data files containing information about the geometric structures. For example, the IC design layout diagram 1422 can be expressed in a GDSII or DFII file format.

[0096] The mask house 1430 comprises data preparation 1432 and mask production 1444. Mask house 1430 uses the IC design layout diagram 1422 to produce one or more masks 1445, which are to be used to manufacture the various layers of the IC device 1460 according to the IC design layout diagram 1422. Mask house 1430 performs mask data preparation 1432, in which the IC design layout diagram 1422 is translated into a representative data file (RDF). Mask data preparation 1432 provides the RDF for mask production 1444. Mask production 1444 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reed plate) 1445 or a semiconductor wafer 1453. The design layout diagram 1422 is manipulated by mask data preparation 1432 to meet certain properties of the mask writer and / or requirements of the IC fab 1450. Fig. Figure 14 illustrates mask data preparation 1432 and mask production 1444 as separate elements. In some embodiments, mask data preparation 1432 and mask production 1444 can be referred to collectively as mask data preparation.

[0097] In some embodiments, the mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. OPC adapts the IC design layout diagram 1422. In some embodiments, the mask data preparation 1432 includes further resolution enhancement techniques (RET), such as axis-shifted illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverted lithography technology (ILT) is also used, which OPC treats as an inverted imaging problem.

[0098] In some embodiments, the mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout diagram 1422, which has been subjected to the processes in OPC with a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 1422 to compensate for constraints during mask manufacturing 1444, which may undo a portion of the changes made by the OPC to satisfy the mask creation rules.

[0099] In some embodiments, the mask data preparation 1432 includes the lithography process check (LPC), which simulates processing performed by IC-Fab 1450 to fabricate the IC fixture 1460. LPC simulates this processing based on the IC design layout diagram 1422 to generate a simulated fabricated fixture, such as the IC fixture 1460. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools for fabricating the IC, and / or other aspects of the fabrication process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if the simulated manufactured device was created using LPC, and the simulated device is not close enough in shape to satisfy the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 1422.

[0100] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, data preparation 1432 includes additional features such as a logic operation (LOP) to modify the IC design layout diagram 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout diagram 1422 during data preparation 1432 can be performed in a variety of different sequences.

[0101] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a group of masks 1445 is fabricated based on the modified IC design layout diagram 1422. In some embodiments, mask fabrication 1444 includes performing one or more lithographic exposures based on the IC design layout diagram 1422. In some embodiments, an electron beam (e-beam) or a mechanism of multiple e-beams is used to form a structure on a mask (photomask or reticle) 1445 based on the modified IC design layout diagram 1422. The mask 1445 can be formed using various technologies. In some embodiments, the mask 1445 is formed using binary technology. In some embodiments, a mask structure comprises opaque regions and transparent regions. A beam of light, such as...An ultraviolet (UV) beam used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and passes through the transparent regions. In one example, a binary mask version of Mask 1445 comprises a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, Mask 1445 is formed using phase-shift technology. In a phase-shift mask (PSM) version of Mask 1445, various features in the structure formed on the phase-shift mask are configured to exhibit a correct phase difference to improve resolution and image quality. In various examples, the phase-shift mask can be an equalized PSM or an alternating PSM.The mask(s) produced by the mask fabrication process 1444 are used in several processes. For example, one or more such masks are used in an ion implantation process to form different doped regions in a semiconductor wafer 1453, in an etching process to form different etched regions in a semiconductor wafer 1453, and / or in other suitable processes.

[0102] IC-Fab 1450 is an IC manufacturing company that includes one or more manufacturing facilities for producing a variety of different IC products. In some configurations, IC-Fab 1450 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of several IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility provides the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry business.

[0103] The IC fabrication device 1450 comprises fabrication tools 1452 configured to perform various fabrication operations on semiconductor wafers 1453, such that the IC device 1460 is fabricated according to the mask(s), e.g., mask 1445. In various embodiments, the fabrication tools 1452 comprise one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other fabrication equipment located in the layer to perform one or more suitable fabrication processes, as discussed herein.

[0104] The IC-Fab 1450 uses one or more masks 1445, produced by the mask house 1430, to fabricate the IC device 1460. Thus, the IC-Fab 1450 uses, at least indirectly, the IC design layout diagram 1422 to fabricate the IC device 1460. In some embodiments, the semiconductor wafer 1453 is fabricated by the IC-Fab 1450 using one or more masks 1445 to form the IC device 1460. In some embodiments, the IC fabrication includes performing one or more lithographic exposures, at least indirectly, based on the IC design layout diagram 1422. The semiconductor wafer 1453 comprises a silicon substrate or other ordinary substrate having layers of material formed on it.The semiconductor wafer 1453 further comprises one or more different doped regions, dielectric features, multilevel interconnects and the like (which are formed in subsequent manufacturing steps).

[0105] Details an integrated circuit manufacturing system (IC manufacturing system) (e.g. System 1400 from Fig. 14), and an IC manufacturing process associated therewith, can be found, for example, in U.S. Patent No. 9,256,709, granted on February 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published on October 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published on February 6, 2014, and U.S. Patent No. 7,260,442, granted on August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0106] One aspect of this revelation relates to an integrated circuit. The integrated circuit comprises several deep first-layer traces and several flat first-layer traces. Each of the deep first-layer traces and the flat first-layer traces is located in a first conductive layer above transistors on a substrate. The integrated circuit also comprises several deep second-layer traces and several flat second-layer traces. Each of the deep second-layer traces and the flat second-layer traces is located in a second conductive layer above the first conductive layer.

[0107] Another aspect of this disclosure relates to an integrated circuit. The integrated circuit comprises several deep first-layer conductors and several flat first-layer conductors. Each of the deep first-layer conductors and the flat first-layer conductors is located in a first conductive layer. The integrated circuit also includes a conductor having a low-resistance section and a low-capacitance section. The low-resistance section is coupled to an output of a first active device. The low-capacitance section comprises at least one deep first-layer conductor and excludes the flat first-layer conductors. The low-capacitance section comprises at least one flat first-layer conductor and excludes the deep first-layer conductors.

[0108] Another aspect of this disclosure relates to a method. The method comprises fabricating deep first-layer conductors and flat first-layer conductors extending in a first direction within a first insulating layer. The method also comprises fabricating via connections between deep second-layer conductors and flat second-layer conductors within a second insulating layer. The deep second-layer conductors and the flat second-layer conductors extend in a second direction perpendicular to the first direction. One of the via connections either connects one of the deep second-layer conductors to one of the flat first-layer conductors or connects one of the flat second-layer conductors to one of the deep first-layer conductors.

[0109] The above describes features of several embodiments that will help those skilled in the field to better understand the aspects of this disclosure. Those skilled in the field should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. They should also understand that such corresponding designs do not deviate from the spirit and scope of this disclosure and that they can make various changes, substitutions, and modifications to it without deviating from the spirit and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 148883

[0001] US 9256709

[0105] US 20150278429

[0105] US 20140040838

[0105] US 7260442

[0105]

Claims

[1] Including an integrated circuit: several deep first-layer conductors and several shallow first-layer conductors, each of the deep first-layer conductors and the shallow first-layer conductors being located in a first conductive layer over transistors on a substrate; and several deep second-layer conductors and several shallow second-layer conductors, each of the deep second-layer conductors and the shallow second-layer conductors being located in a second conductive layer above the first conductive layer. [2] Integrated circuit according to claim 1, further comprising: a conductor track that has at least one deep conductor of the first layer and at least one deep conductor of the second layer, excluding the flat conductors of the first layer and the flat conductors of the second layer. [3] Integrated circuit according to claim 1, further comprising: a conductor track comprising a low-resistance section and a low-capacitance section, wherein the low-resistance section is coupled to an output of a first active device, and wherein the low-capacitance section is coupled to an input of a second active device; wherein the low-resistance section includes at least one deep first-layer conductor or at least one deep second-layer conductor and excludes the shallow first-layer conductors and the shallow second-layer conductors; and wherein the low-capacity section has at least one first-layer flat conductor or at least one second-layer flat conductor and excludes the first-layer deep conductors and the second-layer deep conductors. [4] Integrated circuit according to claim 3, wherein: the low-resistance section has at least one deep conductor of the first layer and at least one deep conductor of the second layer; and the low-capacity section has at least one flat conductor of the first layer and at least one flat conductor of the second layer. [5] Integrated circuit according to claim 3, wherein the low-resistance section is connected to the low-capacitance section by a via connection between the first conductive layer and the second conductive layer. [6] Integrated circuit according to claim 3, wherein the low-resistance section is connected to the low-capacitance section by a fan-out node. [7] Integrated circuit according to claim 6, further comprising: a third active device on the substrate; a branched conductor path between the fan-out node and an input of the third active device; and wherein the branched conductor track has at least one further flat conductor of the first layer or one further flat conductor of the second layer and excludes the deep conductors of the first layer and the deep conductors of the second layer. [8] Integrated circuit according to any one of claims 1 to 7, further comprising: several deep third-layer conductors and several shallow third-layer conductors, each of the deep third-layer conductors and the shallow third-layer conductors being located in a third conductive layer. [9] Integrated circuit according to claim 8, wherein the third conductive layer is located above the second conductive layer. [10] Integrated circuit according to claim 8, wherein the third conductive layer is located between the first conductive layer and the second conductive layer. [11] Integrated circuit according to claim 8, wherein the third conductive layer is located above the transistors but below the first conductive layer. [12] Integrated circuit according to any one of claims 1 to 11, further comprising: several conductive traces in a third conductive layer between the first conductive layer and the second conductive layer. [13] Including an integrated circuit: several deep first-layer conductors and several shallow first-layer conductors, each of the deep first-layer conductors and the shallow first-layer conductors being located in a first conductive layer; a conductor track comprising a low-resistance section and a low-capacitance section, wherein the low-resistance section is coupled to an output of a first active device, and wherein the low-capacitance section is coupled to an input of a second active device; wherein the low-resistance section includes at least one deep first-layer conductor and excludes the shallow first-layer conductors; and wherein the low-capacity section has at least one shallow first-layer conductor and excludes the deep first-layer conductors. [14] Integrated circuit according to claim 13, further comprising: several deep second-layer conductors and several shallow second-layer conductors, each of the deep second-layer conductors and the shallow second-layer conductors being located in a second conductive layer above the first conductive layer; wherein the low-resistance section also includes at least one deep second-layer conductor and excludes the shallow second-layer conductors; and where the low-capacity section also includes at least one shallow second-layer conductor and excludes the deep second-layer conductors. [15] Integrated circuit according to claim 14, wherein the low-resistance section and the low-capacitance section are connected to a via connection between the first conductive layer and the second conductive layer. [16] Integrated circuit according to any one of claims 13 to 15, wherein the low-resistance section and the low-capacitance section are connected to a fan-out node. [17] Procedure encompassing: Manufacturing of deep first-layer conduits and shallow first-layer conduits extending in a first direction within a first insulation layer; Fabrication of via connections, deep second-layer conductors and shallow second-layer conductors in a second insulating layer, wherein the deep second-layer conductors and the shallow second-layer conductors extend in a second direction perpendicular to the first direction; and wherein one of the via connections either connects one of the deep conductors of the second layer to one of the flat conductors of the first layer or connects one of the flat conductors of the second layer to one of the deep conductors of the first layer. [18] The method of claim 17, further comprising: Forming deep trenches for the deep conduits of the first layer and shallow trenches for the shallow conduits of the first layer in the first insulation layer. [19] Method according to claim 17 or 18, further comprising: Forming via openings in the second insulation layer for the via connections; and Forming deep trenches for the deep second-layer conduits and shallow trenches for the shallow second-layer conduits in the second insulation layer. [20] The method of claim 19, further comprising: Deposition of metallic materials in the via holes, deep trenches and shallow trenches.