Current-mode transconductance capacitance filter in a high-frequency digital-to-analog converter

Abstract

Filter stage system that features: a continuous-time baseband filter having a feedback loop utilizing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current; and a mirroring component that mirrors the filtered current to an output.

Description

TECHNICAL FIELD

[0001] The subject matter disclosure relates to an integrated radio frequency digital-to-analog converter (RF DAC), and more particularly to utilizing a current mode transconductance-capacitance filter to generate a filtered current and provide a path to reuse current between the filter and adjacent stages in a signal chain. BACKGROUND

[0002] Quantum computing generally involves the use of quantum mechanical phenomena to perform data and information processing functions. Quantum computing can be viewed as the opposite of classical computing, which generally operates on the basis of binary values ​​in transistors. That is, classical computers can operate on the basis of two ground states, which are either 0 or 1, whereas quantum computers operate on the basis of quantum bits, which exhibit a probabilistic superposition of both 0 and 1, can entangle multiple quantum bits, and can utilize perturbations. Quantum computing is currently emerging as a new model to solve a large group of problems that can be extremely challenging to perform on a conventional classical high-performance computer.The ability to generate variable-amplitude, low-distortion arbitrary waveforms is desirable in many contexts, including qubit control in quantum computing. In particular, high-frequency digital-to-analog converters (HFDACs) are valuable in a variety of applications, including wireless transmitters and qubit control pulses. The implementation of filters and the interface between the filter and the other elements of the signal chain are important in such designs. Continuous-time filters are well-suited for low-power, high-dynamic-range active filters. Current-mode signal processing is well-suited for low-distortion applications because it reduces voltage fluctuations at different nodes of interest.A conventional current-mode input filter using an operational amplifier has significant power consumption and is of limited use in high-frequency applications. SUMMARY

[0003] The following summary is intended to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify important or critical elements or to delineate the scope of any particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, computer-implemented methods enable an integrated radio frequency digital-to-analog converter (RF DAC), and more specifically, utilize a current-mode transconductance-capacitance filter to generate a filtered current and provide a path to reuse current between the filter and adjacent stages in a signal chain.

[0004] According to one embodiment, a system comprises a processor executing the following system-executable components stored in main memory: a high-frequency digital-to-analog converter (HFDAU) operating in current mode, and a continuous-time baseband filter having a feedback loop utilizing at least a first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current.

[0005] In an optional aspect, a mirroring component operating in current mode mirrors the filtered current to an output.

[0006] According to one embodiment, a method implemented by a system comprises: a high-frequency digital-to-analog converter for executing system-executable components to perform the following actions: operating in stream mode together with a baseband filter, wherein the inputs and outputs of system blocks are represented as streams.

[0007] In an optional aspect, the method implemented by a system further comprises associating, by the system, a current-mode mirroring component that mirrors the filtered current to an output, selectively choosing a mirroring ratio to achieve a variable gain with respect to a fine-tuned base step. DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a block diagram of an exemplary system implementation implementing an integrated digital-to-analog converter (DAC) using a current-mode signal path. Fig. Figure 2 illustrates an exemplary flow diagram of an integrated high-frequency digital-to-analog converter using a current-mode transconductance-capacitance filter. Fig. Figure 3 illustrates an example architecture of a signal chain of a high-frequency digital-to-analog converter (HF-DAC signal chain). Fig. Figure 4 illustrates an example architecture of a block-level view of the feedback-based transconductance capacitor baseband filter. Fig. Figure 5 illustrates an exemplary schematic drawing of an asymmetrical implementation of the filter at the transistor level. Fig. Figure 6 illustrates an exemplary implementation of the baseband filter at the transistor level. Fig. Figure 7 illustrates another exemplary drawing of an alternative filter arrangement of transistor-level embodiments. Fig. Figure 8 illustrates another exemplary drawing of an alternative filter arrangement of a transistor-level embodiment. Fig. 9 illustrates another exemplary drawing of an alternative filter arrangement of embodiments at the transistor level. Fig. 10 illustrates an exemplary drawing of a differential filter transfer function of one embodiment at the transistor level. Fig. Figure 11 illustrates an example of simulation results of the current mode transconductance-capacitance filter. Fig. Figure 12 illustrates an example of a schematic extension of an array-based system. Fig. Figure 13 illustrates an exemplary schematic representation of a cascaded extension of complementary stages. Fig. 14 illustrates a block diagram of an example, non-limiting operating environment that may enable one or more embodiments described herein. Fig. 15 illustrates a block diagram of an example, non-limiting operating environment according to one or more embodiments of the subject disclosure. Fig. 16 illustrates a block diagram of example, non-limiting abstraction layers according to one or more embodiments of the subject disclosure. DETAILED DESCRIPTION

[0008] The following detailed description is for purposes of illustration only and is not intended to limit embodiments and / or any application or uses of embodiments. Furthermore, there is no intention to be bound by any expressly or impliedly included information set forth in the "Summary" section above or the "Detailed Description" section. One or more embodiments will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It will be apparent, however, that the one or more embodiments may be practiced in various instances without these specific details.

[0009] The subject matter disclosure generally relates to systems and methods that implement a continuous current-mode path from the radio-frequency digital-to-analog converter (RF DAC) through an output, enabling the realization of a favorable set of tradeoffs regarding power consumption and distortion. The elements of a signal path are the RF DAC, baseband filter, mirrors, and an output stage. Advantages can be achieved by implementing an entire chain in current mode or by implementing subelements of the chain in current mode.

[0010] Embodiments integrate a high-frequency digital-to-analog converter by utilizing a current-mode transconductance-capacitance filter to generate a filtered current and provide a current reuse path between the filter and adjacent stages in a signal chain. Current-mode signal processing is well-suited for low-distortion applications because it reduces voltage fluctuations at various nodes of interest. However, conventional current-mode input filters using an operational amplifier consume a significant amount of power and are subject to limitations in high-frequency applications. Embodiments disclosed and claimed herein propose a promising solution to this problem by incorporating a current-mode signal path design into the implementation of an integrated digital-to-analog converter.Implementing an efficient current-mode filter stage offers several advantages in the context of a proposed RF DAC architecture with a continuous current-mode analog signal path, designed for low-power, low-distortion arbitrary waveform generation applications. It provides a path for current reuse between the filter and neighboring stages in the signal chain. It also avoids introducing additional current-to-voltage conversions in the signal path (such conversions can be included in the feedback path), which helps limit unwanted distortion products and is well-suited to small output amplitude requirements.

[0011] Quantum computing uses a qubit as its essential unit instead of a classical computing bit. A qubit (e.g., a binary quantum bit) is a quantum mechanical equivalent of a classical bit. While classical bits can only use one of two fundamental states (e.g., 0 or 1), qubits can use superpositions of these fundamental states (e.g., α|0〉 + β|1〉, where α and β are complex scalars such that |α| 2 + |β| 2= 1), which makes it possible for multiple qubits to theoretically contain exponentially more information than the same number of classical bits. Therefore, in theory, quantum computers (e.g., computers that use qubits instead of exclusively classical bits) can quickly solve problems that can be extremely difficult for classical computers. The bits of a classical computer are simply binary digits with a value of either 0 or 1. Almost any device with two unique states can serve to represent a classical bit: a switch, a valve, a magnet, a coil, or a similar binary-like state measure. Qubits involved in the mystery of quantum can occupy a superposition of the states 0 and 1. The point is not that the qubit can have an intermediate value such as 0.63; when the state of a qubit is measured, the result is either 0 or 1.But during the course of a computation, a qubit can act as if it were a mixture of states—for example, 63 percent 0 and 37 percent 1. General quantum programs require coordination of quantum and classical components of a computation. One way to think of general quantum programs is to identify processes and abstractions for specifying a quantum algorithm, converting the algorithm into an executable form, conducting an experiment or simulation, and analyzing the results. One idea that runs through these processes is that of intermediate representations. An intermediate representation (IR) of a computation is neither its description in a source language nor the target machine instructions, but something in between.Compilers can use multiple IRs during the process of compiling and optimizing a program. The input is source code describing a quantum algorithm and compile-time parameters. The output is a combined quantum / classical program expressed using a higher-level IR. One difference between a quantum computer and a classical computer is that a quantum computer is probabilistic; thus, measures of algorithm outputs provide a proper solution within an algorithm-specific confidence interval. The computation is then repeated until a satisfactory possible confidence of the solution can be achieved.

[0012] By processing information using the laws of quantum mechanics, quantum computers offer novel ways to perform computational tasks such as molecular calculations, optical photon computations, optimization, and much more. Many algorithms have been introduced to perform such computational tasks efficiently. In particular, high-frequency digital-to-analog converters are valuable in a variety of applications, including wireless transmitters and the realization of control pulses for qubits. A few problems arise in designs that use voltage-mode representations in a signal path that includes high dynamic range requirements at block interfaces, leading to nonlinear behavior and the generation of higher amplitude distortion products and independent power consumption per block, without the opportunity for energy efficiency that comes from power reuse.Thus, embodiments herein propose an efficient current-mode filter design in the implementation of an integrated RF DAC to develop low-distortion arbitrary waveform generation applications. This provides a path for reusing current between a filter and adjacent stages in a signal chain and avoiding the introduction of additional current-to-voltage conversions in a signal path (e.g., such conversions may be included in a feedback path), which helps limit unwanted distortion products and is well-matched with small output amplitude requirements.

[0013] Fig. 1 illustrates a block diagram of an exemplary system 100 that can access data and process that data using various depicted data processing components according to one or more embodiments described herein. The system 100 can enable a process of evaluating and identifying large amounts of various forms of data using machine learning and training a neural network or other type of model. The system 100 can also generate predictive recommendations for an individual level of context according to one or more embodiments described herein. Aspects of systems (e.g., system 100 and the like), devices, or processes discussed in this disclosure can form machine-executable components embodied within machines, e.g.,embodied in one or more computer-readable media associated with one or more machines. Such components, when executed by the one or more machines, e.g., computers, computing devices, virtual machines, etc., can cause the machines to perform operations described herein. For the sake of brevity, repeated description of similar elements employed in one or more embodiments described herein is omitted.

[0014] System 100 enables an integrated high-frequency digital-to-analog converter (HFDAU) that utilizes a current-mode signal path. Embodiments involve managing elements of a signal path, an HFDAU, a baseband filter, a mirror, and an output stage. Advantages can be achieved by implementing an entire chain in current mode or by implementing subelements of the chain in current mode.

[0015] System 100 may optionally include a server unit, one or more networks, and one or more devices (not shown). System 100 may also include or be associated with a current-mode high-frequency digital-to-analog converter 102 having a current-mode continuous-time baseband filter 104, with the input and output of the system blocks represented as streams. A mirroring component 106 mirrors the filtered stream to a current-mode output 108.

[0016] In one implementation, a continuous current-mode path from the high-frequency digital-to-analog converter via output 108 enables realization of low-power, low-distortion applications for generating arbitrary waveforms. The continuous-time baseband filter 104 includes a feedback loop utilizing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current.The mirroring component 106 mirrors the filtered current to the output 108, selectively changing a mirroring ratio to achieve a variable gain with respect to a fine base step.

[0017] System 100 may be any suitable computing device or set of computing devices connected for data transmission purposes to devices, non-limiting examples of which may include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated test system, a network storage device, a data transmission device, a web server device, a network connection device, a network forwarding device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device may be any device that can exchange information with system 100 and / or any other suitable devices that can utilize information provided by system 100.It should be understood that the system 100, components, models, or units may be equipped with data communication components (not shown) that may enable data communication between the system, components, models, units, etc., over one or more networks.

[0018] The various components of system 100 may be connected either directly or through one or more networks. Such networks may include wired networks and wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), non-limiting examples of which include cellular, WAN, Wireless Fidelity (Wi-Fi), Wi-Max, WLAN, radio communications, microwave communications, satellite communications, optical communications, sonic communications, or any other suitable communications technology. Furthermore, the aforementioned systems and / or devices have been described in terms of interaction between multiple components.It should be understood that such systems and components may include these components or subcomponents specified therein, some of the specified components or subcomponents, and / or additional components. Subcomponents may also be implemented as components interconnected with other components for data transfer purposes, rather than those included in higher-level components. Furthermore, one or more components and / or subcomponents may be combined into a single component that provides aggregate functionality. These components may also interact with one or more other components not specifically described herein for brevity, but known to those skilled in the art.

[0019] The subject computer processing systems, methods, apparatus, and / or computer program products may be used to solve new problems created by advances in technology, computer networks, the Internet, and the like.

[0020] In today's digital world, wireless data transmission applications represent one of the largest growth areas in electronics. Modern radio-frequency systems, such as superconducting quantum bit controllers, are based on a wideband multi-channel architecture. The use of vector signal generators with IQ modulators and analog synthesizers for RF signals is limited due to complex signal calibration and cost. Thus, digital-to-analog conversions are valuable for the practical implementation of signal processing, modulation, and signal generation. Furthermore, radio-frequency digital-to-analog converters (RF DACs) are valuable in a variety of applications, including wireless transmitters, implementing control pulses for qubits, and signal-to-noise ratio issues.In particular, HFDAU implementations can ideally aim for low distortion while minimizing power consumption. In general, these objectives provide scope for compromises during the design process. An HFDAU signal path implementation can include voltage-mode signals, current-mode signals, or a combination of both. Thus, embodiments propose a promising solution by introducing a current-mode signal path configuration in an integrated digital-to-analog converter. An efficient current-mode filter offers several advantages in the context of a proposed HFDAU architecture with an end-to-end current-mode analog signal path, designed for low-power, low-distortion arbitrary waveform generation applications. It provides a path for reusing power between a filter and neighboring stages in a signal chain.It also avoids introducing additional current-to-voltage conversions in the signal path (e.g., such conversions can be included in a feedback path), which mitigates unwanted distortion products and is well-matched with small output amplitude requirements.

[0021] Fig. 2 illustrates an example flowchart of an integrated high-frequency digital-to-analog converter using a current-mode transconductance-capacitance filter. As described in flowchart 200, a system includes a high-frequency digital-to-analog converter (HFDAU) using a current-mode baseband filter. At 202, a continuous-time baseband filter includes a feedback loop utilizing at least a first impedance node and at least a second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole. At 204, the continuous-time baseband filter generates a filtered current.At 206, a mirroring component selectively selects a mirroring ratio to achieve variable gain relative to a fine base step. At 208, a scaling component scales the feedback loop input current to enable coarse gain control. At 210, a monitor component monitors a scaled version of the input current to mitigate monitor distortion noise. A set of additional poles is placed between the continuous-time baseband filter and the mirroring component to enable higher-order filtering and mitigate degradation of the continuous-time baseband filter's stability. At 212, a subset of the plurality of cascaded continuous-time baseband filters provides low-pass, band-pass, or high-pass characteristics with corner frequencies, a quality factor, or gain control determined by digital control.The output from this continuous-time filter is current, and multiple such filters can easily be cascaded to create higher-order current-mode filters. A filter can provide low-pass, band-pass, or high-pass characteristics with corner frequencies, quality factor, and gain steps determined by digital control.

[0022] Wireless data transmission applications are challenging due to the speed and performance demands of modern data converters in the frequency domain. Fast digital-to-analog converters require fewer mixing and filtering stages to produce a high-performance output. Today's technological advances encounter many challenges when it comes to meeting increasing bandwidth demands in a congested frequency spectrum. This increases the complexity of the signal chain, as frequency planning impacts size, power, and performance requirements. The ability to leverage a frequency spectrum improves the user experience and enables new system capabilities. Radio frequency converters are used to convert microwave signals to lower or higher frequency ranges to achieve a wide range of processing options.Reducing the size and cost of telecommunications and military systems is driving the development of modern digital-to-analog converters to integrate more functionality into a single chip. Certain fast digital-to-analog converters integrate digital signal processing and conditioning functionality, such as filters, complex modulation, and numerically controlled oscillators. This enables direct generation of complex RF signals in an efficient and compact manner. In a conventional HFDAU architecture, information from one frequency is processed and translated to another frequency. Embodiments disclosed herein perform versatile signal processing at a low frequency and with reduced power consumption.

[0023] Fig. Figure 3 illustrates an exemplary architecture of a radio frequency digital-to-analog converter (HFDAU) signal chain. One method for generating complex signals is to modulate a carrier signal frequency by a local oscillator using a vector modulator. In RF applications, digital I and Q baseband signals are generated using arbitrary waveform generators (AWGs) that include one or more synchronized digital-to-analog converters. An HFDAU chain architecture 300 includes digital baseband signals BBI 302 and BBQ 304. Baseband multibit digital-to-analog converters (DAUs) 306 and 308 take digital bits and convert them to an analog signal depending on a signal's bandwidth and sampling clock frequency. This enables a stream output and provides a filtered amplified stream to mixers.Signals are processed through low-pass filters 306 and 308 to remove an out-of-band noise component originating from the digital-to-analog converter 300. The filtered signals are mixed and thus upconverted by mixers 310 and 312, using two carriers (LO-Q and LO-I) with perpendicular phases of 0 and 90 degrees of I and Q. Using a signal combiner 311, the resulting signals are combined to create a single-sideband signal representation. For example, if the function (x*y) needs to be implemented in a single-sideband representation, the variable x can be represented as a combination of 0 and 90 degrees, and the variable y can be represented as a combination of 0 and 90 degrees. These two variables can then be multiplied and added similarly to the dot product of two vectors. An output of this function is processed by a driver DRV 314.A matching network MN 316 is a component that typically consists of passive elements that do not introduce distortion. The matching network 316 converts a resistor 318 (e.g., 50 ohms) to an impedance required by the driver to maximize power transfer. An output 320 of these DACs is filtered, upconverted using I- and Q-channel mixers, and the resulting signal is combined and fed to a nominal load (e.g., 50 ohms) at output 320 via a driver and a matching network. The filter implementation and the interface between the filter and the other elements of the signal chain are important in such designs. Continuous-time filters are very well suited for implementing low-power active filters with a high dynamic range.Current-mode signal processing is well-suited for low-distortion applications because it reduces voltage fluctuations at various nodes of interest. However, a conventional current-mode input filter using an operational amplifier consumes considerable power and has limited use in high-frequency applications. Continuous-time gm-C filters typically provide a high input impedance, resulting in more distortion products. A gm-C filter is well-suited for high-frequency applications but is quite limited in terms of the dynamic range supported at the input, which is typically a voltage.

[0024] Fig. Figure 4 illustrates a block diagram of an exemplary architecture of a feedback-based transconductance capacitor baseband filter. The circuit architecture 400 has a DC supply V DD402. The circuit 400 consists of a buffer BUF 403 and a high impedance Z 404, which provides an output impedance of the load transistors. There are two transconductance blocks g m1 410 and g m2 412. The two capacitors C1 406 and C2 408 with arrows show that C1 and C2 can be controlled together or independently. The ratio of the transconductances and the capacitors determines the quality factor of the filter. The current diverting unit IBLD 416 is a current auxiliary unit that provides different bias currents so that the m1 410 and the buffer BUF 403. In a feedback loop, this would be the path via g m2 , Z, BUF, g m1 act using the following equation: Q=gm1c2gm2c1 where Q is the quality factor and is a ratio of similar quantities that are nearly constant over variations in process (P) and temperature (T). The Q factor can be adjusted by programming g m1 , g m2 , C1, C2 can be varied using a digital control. The feedback loop gain reduces distortion, and the bandwidth BW can be derived using the following equation: BW=12Πgm1gm2C1C2

[0025] A biasing strategy can be a sub-claim that optimizes the performance by taking the bias block with the constant g mand the bias current supplied from the bias current 1 / R (e.g., filter poles tracked). A continuous-time baseband filter takes input current and provides an output current, and internal feedback mechanisms are implemented as a combination of current-to-voltage and voltage-to-current conversion. The feedback loop uses at least one high-impedance node and at least one low-impedance node, with the high-impedance node providing a dominant pole and the low-impedance node providing a non-dominant pole. Pole splitting ensures stability, and the bias current provides a substantially constant separation between the dominant and non-dominant poles to maintain adequate phase margin.The loop uses a mirroring unit to mirror the filtered current to an output, and by changing a mirroring ratio, variable gain can be achieved with respect to a finely tuned base step. Coarse control of the gain can be achieved by scaling the input current within the feedback loop, and this auxiliary path can also be used as a path to monitor a scaled version of the input current without additional distortion. Additional poles can be placed between the filter core stage and the mirroring stage to achieve higher-order filtering without compromising the stability of the filter. This additional pole consumes no power and produces no distortion and can be implemented using a resistor and a capacitor.The output from this continuous-time filter is a current, and multiple such filters can easily be cascaded to create higher-order current-mode filters. A filter can provide low-pass, band-pass, or high-pass characteristics with corner frequencies, quality factors, and gain steps determined by digital control.

[0026] Fig. Figure 5 illustrates an exemplary drawing of an asymmetrical transistor-level implementation of filter 500. This embodiment may be one of the methods for constructing the filter. The transistors M PB 502 or M N1 504 can implement a DC offset compensation DAC. The filter 500 includes a gm-C filter with current mode input / output. A common mode input current 506 is fixed, and the output current 508 is controlled using drain / gate / source switching elements across M NMXprogrammed. This is a negative feedback loop consisting of M NC1 510 and M N2 512 and then M N1 504, with the three transistors located inside the loop. For the other two transistors M PB 502 and M NB514 are PMOS and NMOS bias transistors, respectively. The baseband filter contains a current-mode input along with a negative feedback loop. The feedback loop consists of two capacitors C1 516 and C2 518. C1 516 is associated with the dominant pole, to which node C1 is connected, and C2 518 is associated with a non-dominant pole. The feedback loop is connected to a dominant pole and a non-dominant pole. In this way, it provides room for optimization for phase margin and stability purposes. The dominant pole is formed by the output conductance of transistors, and the non-dominant pole is formed by the transconductance of transistors. The third pole is formed with a resistor R 520 and an input capacitance of unit M NMX522. This provides three poles, and the third pole can be realized without additional power consumption. The output is also a current i out 508, and it provides a filtering function and a gain function, the gain being i out / i in This filter 500 simultaneously provides the possibility of a low-pass or band-pass transfer function. By using current waveforms that are out / i in a transfer function can be derived which is a low-pass behavior. Otherwise, the transfer function of the current can be described by i(M NC1 ) / i inwhich would be a bandpass behavior. Thus, this filter 500 provides both behaviors simultaneously; it has two poles, which are complex conjugates of each other, and a real pole formed outside the loop is defined by the resistance and input capacitance of M NMX I1 524 and I2 526, which are connected using current mirrors across the networks V P 530 and V N2 532 are digitally programmable. M NC2 528 is used as an attenuator to account for the dynamic range of the input. This is a representation of an example structure. Changing from NMOS to PMOS could lead to another example representation.

[0027] Fig. Figure 6 illustrates another exemplary drawing of an asymmetrical implementation of a transistor-level filter architecture 600 that uses a DC voltage supply V DD 602. The filter 600 consists of two transistors M P1 604 and M P2 608. Z1 606 and Z2 610 represent capacitors associated with dominant and non-dominant poles. Z1 606 and Z2 610 can be represented using a series and parallel combination of at least one reactive element (e.g., capacitance, inductance). This feedback loop consists of transistors M PC1 612, M P2 604, M P1 608, which provide negative feedback using current-mode signaling. A transfer function of variables of the low-pass and high-pass filters H LP and H HP can be represented by: HLP(s)=iout,LPiin=−α(gm1gm2C1C2){s2+s(gm2C2)+(gm1gm2C1C2)} HHP(s)=iout,HPiin=s2+s(gm2C2){s2+s(gm2C2)+(gm1gm2C1C2)} where g m1 and g m2 Transconductances of transistors M P1 604 and M P2 608 represent. I in , i out represent input and output current, and the capacitance is represented as C1 and C2. HP and LP stand for low-pass and high-pass filters, respectively. α represents a ratio between the two transistors M PMY 614 and M P1 604. Pole positions are determined by a ratio G m of transconductance and capacitance, and a bias current can be provided so that G m can be constant, where G m and C can be calibrated independently or can also be supplied with bias current, whereby G m / C itself. The supply of bias current together with the filter 600 is also a unique selling point. The transistors M PMY 614 and M P1604 can be biased below a threshold or with a strong pulse, where one transistor can be biased below a threshold and the other transistor can receive a strong pulse. Similar permutations and combinations can be made with the transistors as described in the example above.

[0028] Fig. Figure 7 illustrates another exemplary drawing of an alternative filter arrangement of embodiments at the transistor level. There are many combinations of implementations of the baseband filter, and these embodiments propose one of such implementation methods. As shown in illustration 700A, g m represents the transconductance of the transistor and C represents the capacitor. The 700A architecture has a DC supply V DD702. In this configuration, an impedance Z2 706 is associated with the dominant pole, and Z1 704 is associated with the non-dominant pole. Furthermore, this configuration uses positive feedback using current-mode signaling. Another example of the embodiment is shown in illustration 700B. In this configuration, the impedance Z2 708 is between the gate and drain terminals of M P1 710. This results in a smaller pole, and Z1 712 is associated with the non-dominant pole. This configuration also uses positive feedback using current-mode signaling.

[0029] Fig. 8 illustrates another exemplary drawing of an alternative filter arrangement of a sample embodiment at the transistor level. Many combinations of implementations of the baseband filter exist, and these embodiments propose one of such implementation methods. As shown in illustration 800A, the impedance Z2 804 is associated with the dominant pole and Z1 802 is associated with the non-dominant pole. This configuration uses negative feedback using current-mode signaling. Similarly, the architecture shown in 800B illustrates that an additional current-mode signaling branch may be included within the feedback loop (M N1 " 806 and Z3 808). Depending on the scaling and polarity of the signal, the order of the filter can be increased.

[0030] Fig. 9 illustrates another exemplary drawing of an alternative filter arrangement of embodiments at the transistor level. Many combinations of implementations of the baseband filter exist, and these embodiments propose one of such implementation methods. As shown in illustration 900A, this configuration includes an impedance Z2 902 associated with the dominant pole, and Z1 904 associated with the non-dominant pole. This configuration employs negative feedback using current-mode signaling. The impedance Z3 906 is inserted within the loop to achieve higher-order filtering and consists of at least one passive element, where Z3 906 is connected to the gate of M N2904. Similarly, the illustration shown in 900B includes additional impedances, with an impedance Z2 908 associated with the dominant pole and Z1 910 associated with the non-dominant pole. This configuration employs positive feedback using current-mode signaling.

[0031] Fig. 10 illustrates an exemplary drawing of a differential filter transfer function of a sample transistor-level embodiment. Many combinations of baseband filter implementations exist, and these embodiments propose one of such implementation methods. As shown in illustration 1000A, this configuration includes an impedance Z2 1002 associated with the dominant pole and Z1 1004 associated with the non-dominant pole. This schematic is a differential filter with the transistors relocated to the differential side 1006. Furthermore, the illustration in 1000B shows a configuration where an impedance Z2 1008 is associated with the dominant pole and Z1 1010 is associated with the non-dominant pole. The additional series impedance at the input terminal provides neutralization and can reduce the loading on the drive circuit.A neutralization network consists of at least one passive element.

[0032] A novelty of this embodiment is the use of a continuous-time current-mode gm-C filter. This methodology can implement two poles within a feedback loop. The feedback loop can implement a complex pair of poles. The feedback provides linearization, resulting in low distortion. A real pole is implemented outside the loop. Furthermore, variable gain is implemented by using a plurality of current-mirroring elements and activating M of N elements to achieve the desired output current. The current can be split between a mixer and the output stage of the baseband filter, thereby reducing power consumption. Three poles can be implemented, while distortion occurs only at one transconductor stage.This concept can be extended by a seamless cascade of multiple current-mode filters with common-mode compatibility. The input stage can be shared with the previous stage's output to further reduce power consumption. The output stage can be shared with the next stage's input to further reduce power consumption. Complex filters can be implemented using delayed I and Q signals.

[0033] Fig. Figure 11 illustrates an example of simulation results for the current-mode transconductance-capacitance filter. The simulation shows a frequency response 1102 at the 3 dB cutoff frequency. The intermodulation results 1104 show the results varying based on the frequency spectrum on the x-axis. Loop stability relies on the varying frequency spectrum 1106 and the resulting output noise of this baseband filter 1108. From these simulations, it can be seen that this type of current-mode baseband filter is necessary for the general requirement of the correct control unit block in quantum applications. This can also be used in a general sense for any transmitter, such as a radio transmitter. The output results and the intermodulation results show that this filter provides a path for current reuse between the filter and any adjacent stages in the signal chain.It avoids introducing additional current-to-voltage conversions in the signal path, which helps limit unwanted distortion. It also meets the requirement for low output amplitudes.

[0034] Fig. Figure 12 illustrates an example of a schematic extension of an array-based system. As shown in illustration 1200, the input is fed with baseband signals I and Q, represented as BBI1 1202 and BBQ1 1204. This can also be extended to n signals BBI N 1206 and BBQ N1208. In this sequence, the filter element is shared by multiple channels. Given a current input and output, the current is taken from one filter and passed to another filter 1210 and 1212. Addition or subtraction 1214 can also be performed very simply at any of these interfaces to produce an output 1216 with a 50-ohm resistor. Another set of applications can also be implemented, using one filter in an array, one filter in a low-pass construct, and another filter with a bandpass response. In this way, it provides different types of signals to different sensors or qubits. Higher-order filtering can be realized by cascading a plurality of filters with common-mode compatibility.In addition, low-distortion multiphase filtering can be realized by cross-connecting quadrature phase filters.

[0035] Fig. Figure 13 illustrates an example schematic of a cascaded extension of complementary stages. The illustration in block 1300 shows how cascades can be created, where filter 1302 is a 3rd order filter, but can only accept the current of a 2nd order filter. This allows it to be in a loop. The output of an NMOS stage is directly connected 1304 to the input of a PMOS stage 1306. The filter shown in this illustration is a 3rd order filter, and the cascade is of 6th order, resulting in minimal power consumption and low distortion. The illustration is shown in a single-phase system, but the loop setup can also be done in other ways. Filter 1306 is also a 3rd order filter.Order, and two similar filters can be used to construct a higher-order filter without loss of dynamic range, making it easy to cascade these two filters. In previous embodiments, the OTA-based transimpedance filter was commonly used in wireless systems. This filter typically uses shunt-to-shunt feedback, but the gain and bandwidth requirements result in higher power consumption. Both a low-pass and band-pass transfer function can be implemented. The proposed structure can operate with only one high-impedance node in the feedback loop for a biquadratic function. Due to the lack of resistance, it is compact. The open-loop cascade structure with a common gate input is used in some cases, usually with a current-to-voltage converter.The proposed structure uses feedback to realize two complex poles, resulting in two real poles. This limited the reliability of the filter transfer function.

[0036] The current-mode solution provides a path for power reuse and low distortion, well-suited to the requirements of cryogenic waveform generation. A novel feature of these embodiments is the use of the transconductance capacitor (gm-C) filter. The main contribution is the realization of a gm-C filter that provides low input impedance. Conventional gm-C filters have high input impedance and typically provide an input voltage-to-output voltage transfer function. Implementation in commercially available CMOS technologies is entirely feasible. This circuit approach is useful for implementing CMOS analog circuits for generating control pulses to enable advanced scalability in future quantum computing systems.

[0037] In order to provide a context for the various aspects of the disclosed subject matter, Fig. 14 and the following discussion provide a general description of a suitable environment in which the various aspects of the disclosed subject matter may be implemented. Fig. Figure 14 illustrates a block diagram of an exemplary, non-limiting operating environment that may enable one or more embodiments described herein. For brevity, similar elements employed in other embodiments described herein are not repeated.

[0038] With reference to Fig. 14, a suitable operating environment 1400 for implementing various aspects of this disclosure may also include a computer 1412. Computer 1412 may also include a processing unit 1414, a system memory 1416, and a system bus 1418. System bus 1418 connects system components, including but not limited to system memory 1416, to processing unit 1414. Processing unit 1414 may be any of several available processors. Dual microprocessor and other multiprocessor architectures may also be utilized as processing unit 1414.The system bus 1418 may be any of several types of bus structures, including, but not limited to, the memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any variety of available bus structures, including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0039] System main memory 1416 may also include volatile memory 1420 and non-volatile memory 1422. The Basic Input / Output System (BIOS), which contains the basic routines for transferring data between elements within computer 1412, for example, during startup, is stored in non-volatile memory 1422. Computer 1412 may also include removable / non-removable, volatile / non-volatile computer storage media. Fig. For example, Figure 14 illustrates a disk storage 1424. Disk storage 1424 may also include, but is not limited to, devices such as a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 1424 may also include storage media separate from or in combination with other storage media. To enable connection of disk storage 1424 to system bus 1418, a removable or non-removable interface, such as interface 1426, is typically used. Fig. 14 also illustrates software that acts as an intermediary between users and the basic computer resources described in the appropriate operating environment 1400. Such software may also include, for example, an operating system 1428. The operating system 1428, which may be stored on disk storage 1424, is used to control and allocate resources of the computer 1412.

[0040] System applications 1430 utilize the management of resources by the operating system 1428 via program modules 1432 and program data 1434, stored, for example, either in the system main memory 1416 or on the disk storage 1424. It should be understood that this disclosure may be implemented with various operating systems or combinations of operating systems. A user inputs commands or information to the computer 1412 via an input device(s) 1436. Input devices 1436 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite reception antenna, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices are accessible via the system bus 1418 and the interface port(s).the interface ports 1438 are connected to the processing unit 1414. The interface port(s) 1438 include, for example, a serial port, a parallel port, a game port, and a Universal Serial Bus (USB). An output device(s) 1440 uses some of the same types of ports as the input device(s) 1436. Therefore, for example, a USB port may be used to provide input to the computer 1412 and to output data from the computer 1412 to an output device 1440. An output adapter 1442 is provided to illustrate that some output devices 1440, such as monitors, speakers, and printers, may be present here, in addition to other output devices 1440 that require special adapters.By way of illustration, and not limitation, output adapters 1442 include video and sound cards that provide a means of connection between output device 1440 and system bus 1418. Note that other devices and / or systems of devices, such as remote computers 1444, may provide both input and output capabilities.

[0041] Computer 1412 may operate in a networked environment using logical connections to one or more remote computers, such as remote computers 1444. Remote computers 1444 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device, or other conventional network node, and the like, and may further include many or all of the elements described in connection with computer 1412. For brevity, only a main memory unit 1446 is illustrated for remote computers 1444. The remote computer(s) 1444 is / are connected locally to computer 1412 via a network interface 1448 and then physically via a communications link 1450.The network interface 1448 includes wired and / or wireless data exchange networks such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, or are limited to, point-to-point connections, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variants thereof, packet-switched networks, and digital subscriber lines (DSL). The term "communication link" 1450 refers to the hardware / software used to connect the network interface 1448 to the system bus 1418. While the communication link 1450 is shown internal to the computer 1412 for illustrative clarity, it may also be external to the computer 1412.Hardware / software for connecting to the 1448 network interface may also include, to name a few examples, internal and external technologies such as modems, including standard telephone modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

[0042] With reference to Fig. 15, an illustrative cloud computing environment 1550 is depicted. As shown, the cloud computing environment 1550 includes one or more cloud computing nodes 1510 with which local computing devices used by cloud customers, such as a personal digital assistant (PDA) or mobile phone 1554A, a desktop computer 1554B, a notebook computer 1554C, and / or an automotive computer system 1554N, can exchange data. Although in Fig. 15, the cloud computing nodes 1510 may further comprise a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, etc.) with which local computing devices used by cloud customers can exchange data. The nodes 1510 may exchange data with each other. They may be physically or virtually grouped in one or more networks, such as a private cloud, community cloud, public cloud, or hybrid cloud described above, or a combination thereof (not shown). This enables the cloud computing environment 1550 to provide infrastructure, platforms, and / or software as services for which a cloud customer does not need to manage resources on a local computing device. It is understood that the types of Fig. 15 are intended to be merely illustrative, and that the computing nodes 1510 and the cloud computing environment 1550 may communicate with any type of computer-based device over any type of network and / or over any type of connection accessible over a network (e.g., using a web browser).

[0043] With reference to Fig. 16 shows a set of functional abstraction layers used by the cloud computing environment 1550 ( Fig. 15). It should be clear from the outset that the Fig. The components, layers, and functions shown in Figure 16 are intended to be illustrative only, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0044] A hardware and software layer 1660 includes hardware and software components. Examples of hardware components include: mainframe computers 1661; Reduced Instruction Set Computer (RISC)-based servers 1662; servers 1663; blade servers 1664; storage devices 1665; and networks and networking components 1666. In some embodiments, software components include network application server software 1667, quantum platform forwarding software 1668, and / or quantum software (in Fig. 16 not illustrated).

[0045] A virtualization layer 1670 provides an absorption layer from which the following examples of virtual devices may be deployed: virtual servers 1671; virtual storage 1672; virtual networks 1673, including virtual private networks; virtual applications and operating systems 1674; and virtual clients 1675.

[0046] In one example, a management layer 1680 may provide the functions described below. Resource provisioning 1681 provides for the dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Billing and pricing 1682 provides cost tracking while resources are used within the cloud computing environment, as well as billing and invoicing for the use of these resources. In one example, these resources may include application software licenses. Security provides identity verification of cloud customers and tasks, as well as protection for data and other resources. A user portal 1683 provides customers and system administrators with access to the cloud computing environment.Service Level Management (SLM) 1684 provides allocation and management of cloud computing resources so that the required service level is achieved. Service Level Agreement (SLA) planning and fulfillment 1685 provides advance planning and procurement of cloud computing resources for which future requirements are expected based on an SLA.

[0047] An operational load layer 1690 provides examples of functionalities for which the cloud computing environment may be utilized. Non-limiting examples of operational loads and functions that may be provided from this layer include: mapping and navigation 1691; lifecycle software development and management 1692; virtual classroom training delivery 1693; data analytics processing 1694; transaction processing 1695; and quantum state preparation software 1696.

[0048] The present invention may be a system, method, apparatus, and / or computer program product with any possible level of integration of technical details. The computer program product may comprise computer-readable storage medium(s) having computer-readable program instructions stored thereon for causing a processor to perform aspects of the present invention. The computer-readable storage medium may be a tangible entity on which instructions may be retained and stored for use by an instruction-executing device.The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium may also include the following: a removable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM).Flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, shall not be construed to include transient signals per se, such as radio waves or freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., pulses of light propagating through a fiber optic cable), or electrical signals transmitted over a cable.

[0049] Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing units or to an external computer or storage unit over a network, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic cables, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in the computing / processing unit receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing unit.Computer-readable program instructions for performing operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including, but not limited to, object-oriented programming languages ​​such as Smalltalk, C++, or the like, and procedural programming languages ​​such as the C programming language or similar programming languages.The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (for example, over the Internet using an Internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), that execute computer-readable program instructions may be configured to personalize the electronic circuit by utilizing state information of the computer-readable program instructions to perform aspects of the present invention.

[0050] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be appreciated that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, may be implemented using computer-readable program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, provide means for performing the functions described in a block(s) of the flowchart(s) and / or block diagram(s).to implement the functions / actions specified in the block diagrams. These computer-readable program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the computer-readable medium having instructions stored thereon comprises a product of manufacture that includes instructions that implement the function / action specified in a block(s) of the flowcharts and / or block diagrams.The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other devices to cause a series of operations to be performed on the computer, other programmable devices, or other devices to create a computer-implemented process, such that the instructions executing on the computer, other programmable devices, or devices implement the functions / acts specified in a block or blocks of the flowcharts and / or block diagrams.

[0051] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams may represent a control component, segment, or section of instructions comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions specified in the block may occur in a different order than indicated in the figures. For example, two blocks listed in succession may actually execute substantially concurrently, or the blocks may sometimes execute in reverse order depending on the functionality associated with the blocks.Furthermore, it may be noted that each block of the block diagrams and / or flowchart representations, as well as combinations of blocks in the block diagrams and / or flowchart representations, may be implemented using dedicated hardware-based systems for performing the specified functions or acts, or using combinations of dedicated hardware and dedicated computer instructions.

[0052] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product executing on a computer and / or computers, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Program modules generally include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will recognize that the computer-implemented methods of the invention may be practiced using other computer system configurations, including, but not limited to, computer systems having one or more processors, mini-data processing units, mainframe computers, and handheld data processing units (e.g.,PDA, telephone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects may also be practiced in distributed computing environments in which tasks are performed by remotely located processing units connected via a communications network. However, some, if not all, aspects of this disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located on both local and remote main memory units.

[0053] As used in this application, the terms "component," "system," "platform," "interface," etc., may refer to or include a computer-related entity or an entity associated with an operational machine having one or more particular functionalities. The entities disclosed herein may be either hardware, a combination of hardware and software, software, or software in execution. A component may be, for example, but not limited to, a process executing on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. For illustrative purposes, both an application executing on a server and the server may be a component.One or more components may reside within a process and / or thread of execution, and a component may reside on one computer and / or be distributed across two or more computers. In another example, respective components may execute from different computer-readable media on which different data structures are stored. The components may exchange data via local and / or remote processors, for example, according to a signal containing one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).As a further example, a component may be a device with a particular functionality provided by mechanical parts actuated by electrical or electronic circuits operated by a software or firmware application executed by a processor. In such a case, the processor may be located internally or externally to the device and may execute at least a portion of the software or firmware application. In another example, a component may be a device that provides a particular functionality via electronic circuits without mechanical parts, where the electronic components may include a processor or other means to execute software or firmware that confers at least a portion of the functionality of the electronic components.In one aspect, a component may emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

[0054] Furthermore, the term "or" should be understood to mean an inclusive "or" and not an exclusive "or". This means that, unless otherwise stated or evident from the context, the expression "X utilizes A or B" refers to any of the natural inclusive permutations. This means that if A is utilized by X; B is utilized by X; or X utilizes both A and B, then "X utilizes A or B" is satisfied under any of the above circumstances. Furthermore, the articles "a" and "an" as used in the description of the subject matter and in the accompanying drawings should generally be construed to mean "one or more" unless otherwise stated or evident from the context.As used herein, the terms "example" and / or "exemplary" are used to mean "serving as an example, specimen, or illustrative." For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspects or configurations described herein as "example" and / or "exemplary" are not necessarily to be construed as preferred or advantageous over other aspects or configurations, nor are they intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0055] As used in the description of the subject matter, the term “processor” can refer to substantially any computing device or devices, including, but not limited to, single-core processors; single-core processors with multi-threaded software execution capability; multi-core processors; multi-core processors with multi-threaded software execution capability; multi-core processors with hardware multi-threading technology; parallel platforms; and parallel platforms with shared distributed memory.Furthermore, the term "processor" may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), transistor or discrete gate logic, discrete hardware components, or any combination thereof configured to perform the functions described herein. Furthermore, processors may utilize nanoarchitectures such as, but not limited to, molecular or quantum dot transistors, switches, and gates to optimize space utilization or improve the performance of user devices. A processor may also be implemented as a combination of data processing units.In this disclosure, terms such as "store," "memory," "data storage," "database," "database," and essentially any other information storage components relevant to the operation and functionality of a component are used to refer to "memory components," units embodied in a "memory," or components that include memory. It should be understood that memory and / or memory components described herein may be either volatile memory or non-volatile memory, or such memory or memory components may include both volatile and non-volatile memory.By way of illustration, and not limitation, non-volatile memory may be read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random-access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory may include RAM that can act, for example, as an external cache. By way of illustration, and not limitation, RAM is available in many forms, for example, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).Furthermore, the memory components of computer-implemented systems or methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0056] The above description includes only examples of systems and computer-implemented methods. It is obviously not possible to describe every conceivable combination of components or computer-implemented methods to describe this disclosure, but those skilled in the art will recognize that many other combinations and variations of this disclosure are possible. Furthermore, to the extent that the terms "comprises," "includes," "has," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a similar manner that the term "comprising" is interpreted as "including" when used as a transitional word in a claim.

[0057] The descriptions of the various embodiments are intended to be illustrative, but are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will occur to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to explain the principles of the embodiments, the practical application, or technical improvement over existing technology, or to enable others of similar skill in the art to understand the embodiments disclosed herein.

Claims

[1] Filter stage system that has: a continuous-time baseband filter having a feedback loop utilizing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current; and a mirroring component that mirrors the filtered current to an output. [2] The system of claim 1, further comprising a scaling component that scales an input current of the feedback loop to enable coarse control of the gain. [3] The system of claim 2, further comprising a monitoring component that monitors a scaled version of the input stream to mitigate distortion disturbances. [4] The system of claim 1, wherein the continuous-time baseband filter is asymmetric. [5] The system of claim 1, wherein the continuous-time baseband filter is a differential filter. [6] The system of claim 4, wherein at least one of the continuous-time baseband filters, the mirroring component, the scaling component, or the monitoring component is a cryoelectronic component. [7] A method for quantum computing, comprising: Using a continuous-time baseband filter having a feedback loop comprising at least a first impedance node and uses at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current; and Using a mirroring component that mirrors the filtered stream to an output. [8] The method of claim 7, further comprising using the mirroring component to selectively change a mirroring ratio to achieve variable gain. [9] The method of claim 7, further comprising using a scaling component to scale an input current of the feedback loop to enable coarse control of the gain. [10] The method of claim 8, further comprising using a monitoring component to monitor a scaled version of the input stream to mitigate distortion disturbances. [11] The method of claim 7, further comprising using a set of additional poles placed between the continuous-time baseband filter and the reflection component to enable higher-order filtering and mitigate degradation of the stability of the continuous-time baseband filter. [12] The method of claim 7, further comprising using a plurality of cascaded continuous-time baseband filters. [13] The method of claim 7, further comprising using a subset of the plurality of cascaded continuous-time baseband filters to provide low-pass, band-pass, or high-pass characteristics with corner frequencies, a quality factor, or gain control determined by digital control. [14] The method of claim 7, further comprising the feedback loop using the following equations: Q=gm1gm2C2C1, BW=12πgm1gm2C1C2 where C 1,2 Capacitors are, g m1,2 Transconductors are, Q is the quality factor and BW is the bandwidth. [15] A computer program product, the computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the instructions being executable by a processor to cause the processor to: a continuous-time baseband filter having a feedback loop using at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current; and a mirroring component is used that mirrors the filtered current to an output.

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