Back-contacted solar cell and method for manufacturing a back-contacted solar cell

Abstract

The invention relates to a back-contacted solar cell (10) with features of claim 1 and a method for manufacturing such a back-contacted solar cell (10).

Description

[0001] The invention relates to a back-contacted solar cell having features of claim 1 and a method for producing a back-contacted solar cell having features of the independent claim.

[0002] In a back-contact solar cell, the electrodes of both polarities, as well as those for the emitter and base regions, are arranged on the back of the solar cell. The back of the solar cell is the side facing away from the sun during operation. Accordingly, the front of the solar cell is the side facing the sun.

[0003] Back-contact solar cells can generally achieve higher efficiencies than solar cells with electrodes of one polarity arranged on the front and electrodes of the opposite polarity arranged on the back. In back-contact solar cells, the front is not shaded by electrodes. To minimize resistance and recombination losses in back-contact solar cells, the electrodes of both polarities, and thus also the emitter and base regions, are arranged alternately at close intervals on the back.

[0004] Creating a multitude of closely spaced pn junctions is technically much more difficult to achieve than, for example, a conventional solar cell with contact on both sides and only a single large-area pn junction. The emitter and base regions arranged alternately on the back can be created, for example, using laser irradiation. In this process, n-type and p-type dopants are driven locally into a semiconductor substrate by melting the surface at different times and locations using laser irradiation, thus creating either a p-type or n-type doped region, depending on the dopant. Such a laser doping process is disclosed, for example, in DE 10 2013 219 564 A1. The described structuring of the back enables efficiencies of up to 24% due to low internal series resistances and high current efficiency.

[0005] Even higher efficiencies are essentially limited by recombination mechanisms in the base as well as at the highly doped, contacted, and non-contacted surfaces. Recombination in the base depends on the quality of the semiconductor substrate and can only be influenced to a limited extent during the further manufacturing process of the solar cell. Recombination mechanisms at the doped n- and p-type surfaces are only limited by Auger recombination in the non-contacted regions with good surface passivation, with Auger recombination increasing with the dopant concentration in the silicon. In contacted regions, where metal electrodes contact the silicon, contact with the metal leads to high interfacial recombination. During the manufacturing process, Auger recombination at the non-contacted surfaces can be reduced by minimizing doping.On the contacted surfaces, however, a high dopant concentration is advantageous, as this reduces contact resistance and interfacial recombination.

[0006] To counteract this discrepancy, the use of so-called passivating or charge carrier-selective contacts is known, see, for example, DE 10 2013 219 564 A1 or WO 2014 / 100 004 A1. The electrodes do not directly contact the crystalline silicon wafer, which serves as the absorber, but are separated by a thin dielectric layer, e.g., a silicon oxide layer. On the one hand, the silicon oxide layer passivates the silicon surface. On the other hand, the silicon oxide layer is so thin that charge carriers (especially electrons) can tunnel through the silicon oxide layer from the semiconductor into the electrode, or from the electrode into the semiconductor (depending on polarity). Therefore, the silicon oxide layer can be referred to as a tunnel layer through which charge carriers can tunnel. Small holes, e.g., in the nm (nanometer) range, can also be arranged in the tunnel layer to enable current flow.

[0007] To stimulate the charge carriers to tunnel, an electric field can be present in the tunnel layer. The electric field can be generated, for example, by a highly doped n- or p-type silicon on the tunnel layer. The doping of this highly doped silicon layer above the tunnel layer leads to band bending in the silicon base below the tunnel layer. This eliminates the need for traditional doping of the silicon base to create the pn junction. Because the silicon base is no longer doped, or at least only slightly doped, Auger recombination in the base decreases. The spatial separation of a metal / silicon interface of the electrodes from the silicon base also decreases interfacial recombination. Nevertheless, a low contact resistance can be achieved because the electrodes contact the highly doped silicon layer.Suitable doped silicon layers include, for example, amorphous, semi-crystalline or polycrystalline silicon layers with a thickness of 20 nm to 400 nm, which can be deposited using PECVD, LPCVD, APCVD or a PVD process.

[0008] Back-contact solar cells with charge-carrier-selective contacts of both polarities have so far achieved efficiencies of up to 26.7%. However, the production of such solar cells is very complex, as the two differently doped passivating contacts can only be applied using various complex masking and patterning steps. High precision and fine resolution of the masking and patterning are essential. The spacing between the charge-carrier-selective contacts of opposite polarities should not exceed the diffusion length of the free charge carriers. Large spacing can also lead to an increase in the internal series resistance due to the lateral current flow in the base.

[0009] The differently doped silicon layers of the charge-carrier-selective contacts can also be separated either by an undoped silicon layer or by a spatial separation, such as a trench or an interruption. Without such a separation, the junction between the differently doped layers exhibits a defect-rich pn junction, which limits the efficiency of the solar cell. Ideally, the separation should be as fine as possible, since a large separation area can be detrimental to the short-circuit current and open-circuit voltage.

[0010] WO 2023 / 110534 A1, DE 19819200 A1, CN 116417523 A and WO 2022 / 074091 A1 each disclose a solar cell having features of claim 1.

[0011] It is therefore an object of the present invention to provide a back-contacted solar cell and a method for producing a back-contacted solar cell, wherein the solar cell has the highest possible efficiency and can be produced cost-effectively and efficiently.

[0012] This object is achieved by the back-contacted solar cell having the features of claim 1. The back-contacted solar cell comprises a semiconductor substrate, a front side and a back side. The semiconductor substrate can comprise silicon or be formed from silicon. A plurality of first regions, a plurality of second regions and a plurality of third regions are arranged on the back of the solar cell. The first regions each comprise a first doped silicon layer. The second regions each comprise a second doped silicon layer. The doping of the first doped silicon layer and the doping of the second doped silicon layer can have different or opposite polarities. The first doped silicon layers and the second doped silicon layers are each amorphous, semi-crystalline or polycrystalline.The third regions are each formed without amorphous, semi-crystalline, or polycrystalline silicon. The first regions and the second regions are formed as passivating contacts. A first tunnel layer is arranged between the first doped silicon layers and the semiconductor substrate. A second tunnel layer is arranged between the second doped silicon layers and the semiconductor substrate.

[0013] A surface of the back side or the back side and the front side of the solar cell is at least partially, in particular completely, covered with a dielectric (passivating) layer. The dielectric layer can be formed as a layer stack, i.e. consist of several layers. The dielectric layer has a first interruption in the region of the first regions and a second interruption in the region of the second regions. The dielectric layer therefore has a plurality of first and a plurality of second interruptions, in particular on the back side of the solar cell. The solar cell has a plurality of first electrodes and a plurality of second electrodes. In each case, a first electrode contacts a first doped silicon layer through a first interruption. In particular, a first electrode can in each case contact the second silicon layer and / or the second tunnel layer in the respective first region.A second electrode contacts a second doped silicon layer through a second interruption.

[0014] The first regions are arranged on pedestal-like elevations of the semiconductor substrate. The elevations each have a cross-section that widens (or increases in size) in a first direction. In particular, the cross-section of the pedestal-like elevations can be trapezoidal.

[0015] This allows the third regions to be formed in a recessed region that widens transversely to the first direction, and thus virtually in the "shadow" (with respect to the first direction) of the first regions. The first doped silicon layers and the second doped silicon layers, in particular of the first and second regions, are therefore each separated from one another by the third regions. The third regions in particular form a step in the "shadow" of the first regions. This allows separate, differently doped, charge carrier-selective contacts to be implemented with a fine separation of a few micrometers and a high resolution without further complex structuring steps. This separation avoids a pn junction in both doped silicon layers, which would in particular limit the fill factor and thus also the efficiency.This makes it possible to create a solar cell with the highest possible efficiency that can be manufactured cost-effectively and efficiently.

[0016] In this case, the first direction refers to a direction pointing away from the back of the solar cell. The first direction is oriented perpendicular to the front and back of the solar cell.

[0017] The first doped silicon layers can be p-type (positive) or n-type (negative) layers. The second doped silicon layers can be p-type or n-type layers. The first doped layers and the second doped layers are amorphous, semi-crystalline, or polycrystalline and thus differ from the semiconductor substrate (or silicon base), which is crystalline, particularly monocrystalline.

[0018] The widening cross-section of the pedestal-like elevations can be implemented by undercutting (see below). This allows the third regions to be formed, which extend transversely to the first direction in a range of 0.5 µm to 20 µm (micrometers), in particular in a range of 1 µm to 10 µm, in which no (amorphous, semi-crystalline, or polycrystalline) silicon layer is arranged.

[0019] According to the invention, the third regions are formed as undercut regions.

[0020] This allows the third areas to be implemented using simple means.

[0021] According to a further development of the solar cell, the third regions can be undoped.

[0022] In this context, "undoped" means no additional (process-related) doping. An undoped layer has the same doping (type and concentration) as the semiconductor substrate. The semiconductor substrate can have a low doping, e.g., in the range of 5×10^16 cm-3. An "undoped" layer can therefore have the same low doping. Accordingly, doping means additional doping compared to the semiconductor substrate.

[0023] This allows the third regions to be implemented using simple means. In particular, it allows for a clear (undoped) separation between the doped first and / or second silicon layers.

[0024] According to a further development, the third regions can have a third doped silicon layer. The surface of the semiconductor substrate in the region of the third regions can thus be doped.

[0025] This can further improve the efficiency of the solar cell.

[0026] According to a further development of the solar cell, a fourth doped silicon layer can be arranged on the front side of the solar cell.

[0027] This can further improve the efficiency of the solar cell.

[0028] According to a further development of the solar cell, the semiconductor substrate, the first doped silicon layers, the second doped silicon layers, the third doped silicon layers, the fourth doped silicon layer and / or the third regions can have a doping according to one of the combinations according to Table 1. Table 1: semiconductor substrate First doped silicon layer Second doped silicon layer Third area or third doped silicon layer Front of the solar cell or fourth doped silicon layer n n p - p n n p - n n n p p p n n p n n n p n - p n p n - n n p n p p n p n n n p n p - p p n p - n p n p p p p n p n n p p n - p p p n - n p p n p p p p n n n p n p - - p n p - - p n p p - p n p n - p p n - - p p n - - p p n p - p p n n - n n p - - n n p - - n n p p - n n p n - n p n - - n p n - - n p n p - n p n n -

[0029] In the present case and in particular in Table 1, “p” means an additional positive doping compared to the semiconductor substrate, “n” means an additional negative doping compared to the semiconductor substrate, and “-” means no additional doping compared to the semiconductor substrate.

[0030] This allows the solar cell to be designed and implemented as flexibly as possible.

[0031] According to a further development of the solar cell, the first doped silicon layers, the second doped silicon layers, the first tunnel layers, and / or the second tunnel layers can each be formed free of perforations. The first and / or second tunnel layers can each be formed as closed layers. In particular, the first tunnel layers and / or the second tunnel layers are not perforated (or penetrated) or are only slightly perforated (or penetrated) by the first electrodes and / or the second electrodes.

[0032] This can further improve the efficiency of the solar cell.

[0033] According to a further development of the solar cell, the first doped silicon layers, the second doped silicon layers, the first tunnel layers, and / or the second tunnel layers can each be perforated by an aluminum-silicon eutectic. The aluminum-silicon eutectic can be arranged at the respective first electrode and / or at the respective second electrode.

[0034] This can further improve the efficiency of the solar cell.

[0035] According to a further development of the solar cell, the aluminum-silicon eutectic can be surrounded at least in regions by a fifth doped silicon layer. The fifth doped silicon layer can have a p-type doping, for example using aluminum, or an n-type doping. If an aluminum-silicon eutectic is arranged at each of the first electrodes and the second electrodes, the respective fifth doped silicon layer can have a polarity that corresponds to the respective polarity of the electrode. In particular, the fifth doped layers of the eutectics arranged at the first electrodes and the fifth doped layers of the eutectics arranged at the second electrodes can have opposite polarity.

[0036] This can further improve the efficiency of the solar cell and make manufacturing more cost-effective.

[0037] The above object is achieved by a method for producing a back-contacted solar cell according to the above embodiments with the features of the independent claim. The method comprises the steps: Providing a semiconductor substrate having a front side and a back side.

[0038] Forming a first tunnel layer on the back side of the semiconductor substrate.

[0039] Forming a first doped silicon layer of a first polarity on the first tunnel layer.

[0040] Forming an etch-stable barrier layer on the first doped silicon layer.

[0041] Removal of the etch-stable barrier layer in several etching areas.

[0042] Etching, in particular of the first doped silicon layer, the first tunnel layer, and the surface of the semiconductor substrate, in the etched regions. The etching, in particular of the etch-stable barrier layer, creates pedestal-like elevations on the semiconductor substrate with a cross-section widening in the first direction. The pedestal-like elevations thus extend out of the semiconductor substrate. The etching can be wet-chemical etching.

[0043] In particular, complete removal of the etch-stable barrier layer.

[0044] Formation of a second tunnel layer, particularly in the areas between the pedestal-like elevations of the semiconductor substrate.

[0045] Forming a second doped silicon layer with a second polarity opposite to the first, particularly in the regions between the pedestal-like elevations, wherein the second doped silicon layer is not formed in the third regions due to the widening cross-section of the pedestal-like elevations. Thus, the third regions do not contain any amorphous, semi-crystalline, or polycrystalline silicon.

[0046] Regarding the advantages achievable with the process, reference is made to the relevant explanations regarding the solar cell. The measures described in connection with the solar cell and / or those explained below can be used to further refine the process.

[0047] According to a further development of the method, the method may comprise the following steps: Forming the third doped silicon layers in the third regions and / or the fourth doped silicon layer on the front side by means of a furnace diffusion.

[0048] According to a further development of the method, the method may comprise the step: Removal of a silicate glass layer formed during furnace diffusion, for example phosphosilicate glass or borosilicate glass, in particular by (wet chemical) etching.

[0049] According to a further development of the method, the method may comprise the following steps: Forming the first and / or second electrodes and / or forming the aluminum-silicon eutectic at the first and / or second electrodes by using pastes or paste stacks, in particular wherein the pastes or paste stacks contain a p-type dopant, in particular aluminum, and / or an n-type dopant.

[0050] The method comprises, in particular, an anisotropic or isotropic wet-chemical etching of the first doped silicon layer, the first tunnel layer, and / or the semiconductor substrate. The wet-chemical etching can be performed after depositing or growing the first tunnel layer, the first doped silicon layer, depositing an etch barrier layer, and structuring the etch barrier layer, for example, by means of laser irradiation. The wet-chemical etching can, for example, remove approximately 0.5 µm to 20 µm, in particular 1 µm to 10 µm, (etch depth) of silicon along the first direction (i.e., perpendicular to the surface). This also results, regardless of whether the etching is carried out anisotropic or isotropic, in particular in undercutting the etch barrier and, if applicable, the first doped silicon layer (provided that the latter has a high etch stability due to its chemical properties).

[0051] The etch barrier layer can then be removed.

[0052] After growing a second tunnel layer, which passivates the exposed surface of the semiconductor substrate, the second doped silicon layer can be deposited, for example, using physical vapor deposition (PVD). Unlike conventional chemical vapor deposition processes (PECVD, LPCVD, APCVD), no or hardly any particles are deposited transversely to the first direction (i.e., on surfaces perpendicular to the particle deposition direction). In particular, no particles are deposited within undercut areas. This allows the formation of third regions that contain neither the first doped silicon layer nor the second doped silicon layer. The pn junction can thus be located exclusively in the semiconductor substrate (silicon wafer) and thus exhibit low recombination. This allows a high fill factor and high efficiency to be achieved.

[0053] In other words, when the first doped silicon layer is removed by post-chemical etching in areas without a barrier layer, the barrier layer is isotropic or anisotropic undercut. The deposition of the second doped silicon layer can be achieved using physical, directed, unidirectional vapor deposition. As a result, the second doped silicon layer is not deposited on all exposed surfaces on the back of the solar cell, but is interrupted at least in shadowed areas of the undercut. Therefore, no further process step is required to separate the first doped silicon layer in the first regions and the second doped silicon layer in the second regions (i.e., the two differently doped silicon layers).Furthermore, this separation (i.e., areas without the first and second doped silicon layers) extends over a width of a few micrometers (the sum of the etch depth and the under-etched area). This allows for ultrafine separation of charge carrier-selective contacts in the micrometer range.

[0054] Further features, details, and advantages of the invention will become apparent from the wording of the claims and from the following description of exemplary embodiments with reference to the drawings. They show: Fig. 1 shows a schematic cross section of a back-contacted solar cell according to a first embodiment; Fig. 2 shows a schematic cross section of the back-contacted solar cell according to a second embodiment; Fig. 3 shows a schematic cross section of the back-contacted solar cell according to a third embodiment; Fig.4 a scanning electron image of a first, second and third region of the solar cell according to the illustrations of Fig. 1 to 3; Fig. 5 to 16 show a method for producing a back-contacted solar cell according to a first embodiment and Fig. 17 to 28 show the method for producing a back-contacted solar cell according to a second embodiment.

[0055] In the following description and in the figures, corresponding components and elements bear the same reference symbols. For the sake of clarity, not all reference symbols are shown in all figures.

[0056] Fig.Figure 1 shows a schematic cross-section of a back-contacted solar cell 10 according to a first embodiment. In this example, the solar cell 10 comprises a crystalline n-type semiconductor substrate 12. In this example, the semiconductor substrate 12 forms a silicon base 12. This base 12 forms an absorber. In another embodiment, it may also be a crystalline p-type silicon base 12.

[0057] The solar cell 10 comprises a front side 14 and a back side 16. The front side 14 faces the sun during operation of the solar cell 10. In the illustrated embodiment, the front side 14 is textured. Arranged on the back side 16 of the solar cell 10 are a plurality of first regions 18, each with a first doped silicon layer 20, a plurality of second regions 22, each with a second doped silicon layer 24, and a plurality of third regions 26. In the present case, the second doped silicon layer 24 is arranged above the first doped silicon layer 20 in the first regions 10. However, the second doped silicon layer 24 arranged in the first regions 18 is not functional.

[0058] The first doped silicon layers 20 and the second doped silicon layers 24 are each amorphous, semi-crystalline, or polycrystalline. They thus differ from the (mono)crystalline silicon base 12 (or the semiconductor substrate 12). The third regions 26 each contain no amorphous, semi-crystalline, or polycrystalline silicon. A first tunnel layer 28 is arranged between the first doped silicon layer 20 and the semiconductor substrate 12. A second tunnel layer 30 is arranged between the second doped silicon layer 24 and the semiconductor substrate 12.

[0059] The first regions 18 and the second regions 22 are each formed as passivating contacts. In the present case, a surface of the rear side 16 and the front side 14 of the solar cell 10 is each at least partially, in particular completely, covered with a dielectric layer 32 or dielectric layer stack. The dielectric layer 32 is formed from two layers. The dielectric layer 32 can passivate the front side 14 and / or rear side 16, reduce reflections on the front side 14, and improve the light absorption of the solar cell 10. The dielectric layer 32 comprises, for example, aluminum oxide (AlOx), silicon oxide (SiOx), or silicon nitride (SiNx). The dielectric layer 32 can be formed as a layer stack (i.e., consisting of multiple layers).

[0060] The layer stack can consist of two or more layers, including, for example, AlOx, SiOx, and / or SiNx. Other layers for reducing reflection and / or improving passivation are also conceivable. The dielectric layer 32 or layer stack on the front side 14 and the dielectric layer 32 or layer stack on the back side 16 can be identical or different in structure.

[0061] The dielectric layer 32 has a first interruption 34 in the region of the first regions 18 and a second interruption 36 in the region of the second regions 22. The first interruption 34 can continue through the second doped silicon layer 24 in the first region 18 to the first doped silicon layer 20.

[0062] The solar cell 10 comprises a plurality of first electrodes 38 and a plurality of second electrodes 40. In each case, a first electrode 38 contacts a first doped silicon layer 20 through a first interruption 34. In each case, a first electrode 38 can penetrate the second doped silicon layer 24. It is also conceivable that the second doped silicon layer 24 can represent a (further) tunneling connection in the region of the first interruption 34. In each case, a second electrode 40 contacts a second doped silicon layer 24 through the second interruption 36. The first regions 18 are arranged on pedestal-like elevations 42 of the semiconductor substrate 12. The elevations 42 each have a cross-section that widens in a first direction 44. In other words, the cross-section of the elevations 42 tapers opposite to the first direction 44.

[0063] The third regions 26 can be formed as undercut regions. The third regions 26 can be formed undoped.

[0064] In the example, the front side 14 comprises a fourth doped silicon layer 48. This can comprise p-type doped silicon. The fourth silicon layer can form a so-called "front floating emitter" (FFE), since an emitter with a pn junction, i.e., with the opposite doping to that of the silicon base 12 or the semiconductor substrate 12, is formed. The fourth doped silicon layer 48 can be coated with a p-type dopant, for example, boron, in particular with a dopant concentration of approximately 5×10 17 cm -3 up to 1×10 20 cm -3 , preferably of about 5×10 18 cm -3 up to 5×10 19 cm -3 be endowed.

[0065] In a further embodiment, an n-type doping, in particular with a comparable or identical dopant concentration, can also be provided. In this case, the doping on the front side is referred to as a "front surface field" (FSF), i.e., a doping equal to the doping of the silicon base 12. The fourth doped silicon layer 48 can be coated with an n-type dopant, for example, phosphorus, in particular with a dopant concentration of approximately 5×10 17 cm -3 up to 1×10 20 cm -3 , preferably of about 5×10 18 cm -3 up to 5×10 19 cm -3 be endowed.

[0066] A surface of the rear side 16 can, for example, be textured over the entire surface or chemically polished over the entire surface. The surface of the rear side 16 can also comprise a combination of textured areas and polished areas. For example, the surface can be polished in the area of ​​the first areas 18 and textured in the area of ​​the second areas 22 (or vice versa). Chemical polishing can be applied to the surface after an anisotropic silicon etching, for example, with hot potassium hydroxide.

[0067] The first doped silicon layers 20 can comprise n-type doped polycrystalline silicon. The second doped silicon layers 24 can comprise p-type doped polycrystalline silicon. In the present case, a second doped silicon layer 24 is arranged in each of the first regions 18 above the first doped silicon layers 20 (with respect to the first direction 44). These second doped silicon layers 24, which are arranged in the first regions 18, are in particular non-functional.

[0068] In the present case, the first regions 18 and the second regions 22 are arranged alternately. A distance a between a center M1 of a first, in this case n-type doped, region 18 and a center M2 of a next, in this case n-type doped, first region 18 is, for example, between 300 µm and 3000 µm, preferably between 400 µm and 2000 µm. Accordingly, a distance between a center of a second, in this case p-type doped, region 22 and a center of a next, in this case p-type doped, second region is, for example, between 300 µm and 3000 µm, preferably between 400 µm and 2000 µm.

[0069] Across the area of ​​the rear side 16 of the solar cell, a ratio of the total area of ​​the p-type doped regions to the total area of ​​the n-type doped regions is in particular between 1:9 to 9:1, in particular 2:8 to 8:2, preferably between 3:7 to 7:3.

[0070] The alternating pattern of the first and second regions 18, 20 can, in principle, extend completely or at least approximately over the entire rear side 16 of the solar cell 10. However, the alternating pattern can also be interrupted locally, e.g., in regions where busbars are provided.

[0071] The layer thickness of the first doped silicon layers 20 and / or the second doped silicon layers 24 can be, for example, 20 nm to 400 nm. The first doped silicon layers 20 and the second doped silicon layers 24 can have the same layer thickness. It is also conceivable that the first doped silicon layers 20 and the second doped silicon layers 24 can have different layer thicknesses.

[0072] The first doped silicon layers 20 and / or the second doped silicon layers 24 can be coated with an n-type dopant, e.g. phosphorus, and with a dopant concentration of, for example, 1×10 19 cm -3 up to 1×10 21 cm -3 , preferably 5×10 19 cm -3 up to 2×10 20 cm -3 , be endowed.

[0073] The first and / or second tunnel layers 28, 30 can each be formed as a dielectric layer. The first and / or second tunnel layers 28, 30 can, for example, have a layer comprising silicon oxide (SiOx) or a layer comprising silicon oxynitride (SiON). The first and / or second tunnel layers 28, 30 can passivate the surface of the semiconductor substrate 12 (or the silicon base 12). The first and / or second tunnel layers 28, 30 can, for example, have a thickness of 0.5 nm to 4 nm. This enables, in particular, the tunneling of charge carriers.

[0074] The first and / or second tunnel layers 28, 30 can each be formed free of perforations. It is also conceivable for the first and / or second tunnel layers 28, 30 to have openings, so-called pinholes, in the nm range. This allows for ohmic contact to be established between the semiconductor substrate 12 (silicon base 12) and the first doped silicon layer 20 or the second doped silicon layer 24.

[0075] The first doped silicon layers 20, in particular in the first regions 18, and the second doped silicon layers 24, in particular in the second regions 22, are separated from one another by the third regions 26. The third regions 26 are formed from an under-etched silicon volume of the semiconductor substrate 12 or the silicon base 12. The third regions 26 can be formed from a first region 27 and a second region 29. The first region 27 can be oriented transversely (perpendicular) to the first direction 44, and the second region 29 can be inclined or angled to the first direction 44. It is also conceivable that the first regions 27 and the second regions 29 can each be inclined or angled to the first direction 44 (cf. Fig. 4).

[0076] In particular, there are no (or only minimal) amounts of the second doped silicon layer 24 in the third regions 26. There is therefore no pn junction between the first doped silicon layers 20, in particular the regions 18, and the second doped silicon layers 24, in particular the regions 22. In the first exemplary embodiment shown, the silicon base 12 (or the semiconductor substrate 12) is undoped in the third regions 26. The dopant concentration of the third regions 26 therefore corresponds in particular to the dopant concentration of the silicon base 12. The surface of the third regions 26 can be covered or passivated by means of a dielectric layer, in particular by means of the second tunnel layer 30. Additionally or alternatively, the surface of the third regions 26 can be covered with the dielectric layer 32 (or a dielectric layer stack). For this purpose, the dielectric layer 32 (ordielectric layer stack), in contrast to the second doped silicon layer 24, are formed undirected, and also include the third regions 26.

[0077] The dielectric layer 32 essentially serves to passivate the surface of the silicon base 12 (or the semiconductor substrate 12). On the one hand, the dielectric layer 32 serves as a hydrogen source to improve passivation with the first and second tunnel layers 28, 30, respectively; on the other hand, it can also saturate open bonds in the third regions 26 and improve passivation by means of a field effect. The dielectric layer 32 can also serve to optimize the optical properties of the solar cell 10, particularly when the solar cell 10 is used bifacially. The dielectric layer 32 comprises, for example, aluminum oxide (AlOx), silicon oxide (SiOx), and / or silicon nitride (SiNx). The dielectric layer 32 can consist of a layer stack comprising at least two layers, for example, comprising AlOx, SiNx, and / or SiNx. Other layers for reducing reflection and / or improving passivation are also conceivable.

[0078] In the example, the dielectric layer 32 covers almost the entire surface of the back side 16 and the front side 14.

[0079] The first and second interruptions 34, 36, which can be formed, for example, as openings, are provided in the dielectric layer 32 on the rear side 16. These first and second interruptions 34, 36 enable electrical contact between the respective first doped silicon layers 20 and the respective second doped silicon layers 24 and the corresponding first and second electrodes 38, 40, respectively. In other words, the first and second electrodes 38, 40 contact the first doped silicon layers 20 and the second doped silicon layers 24, respectively, through the first and second interruptions 34, 36, respectively.

[0080] For this purpose, in the first regions 18, the second doped silicon layers 24 and the second tunnel layers 30 can each also have an interruption in order to enable the contacting of the first electrodes 38 with the respective first doped silicon layer 20 (cf. Fig. 1). These interruptions can be designed analogously to the first and / or second interruptions 34, 36.

[0081] The first and / or second interruptions 34, 36 can, for example, be continuous or designed as round or square, linear, or segmented interruptions. Thus, correspondingly shaped contact surfaces can be provided for the first and second electrodes 38, 40, for example, point-shaped or circular contact surfaces or linear or segmented contact surfaces.

[0082] In the illustrated example, the first electrodes 38 contact the first doped silicon layers 20, which in this case are n-type doped. The first electrodes 38 can therefore also be referred to as negative electrodes. In the illustrated example, the second electrodes 40 contact the second doped silicon layers 24, which in this case are p-type doped. The second electrodes 40 can therefore also be referred to as positive electrodes.

[0083] The first and second (positive and negative) electrodes 38, 40 can consist of one or more metals, for example silver, copper, or aluminum. The first and second electrodes 38, 40 can be designed, for example, as a layer stack of silver and copper, in order, for example, to minimize the silver content of the metallization. In the present case, the respective first tunnel layer 28 is formed without interruption (as a closed layer) in the first region 18. In the present case, the respective second tunnel layer 30 is formed without interruption (as a closed layer) in the second region 22. It is also conceivable for the first and / or second tunnel layers 28, 30 to be formed with interruptions in the regions of the first and / or second interruptions 34, 36.

[0084] Fig.Figure 2 shows a schematic cross section of the back-contacted solar cell 10 according to a second embodiment. The second embodiment differs from the first, in Fig. 1 shown embodiment by the following: In particular, the surface of the semiconductor substrate 12 can be further doped in the third regions 26, so that the dopant concentration in the third regions 26 exceeds the dopant concentration of the semiconductor substrate 12. The third regions 26 here have a third doped silicon layer 46. Furthermore, the second tunnel layer 30 is not present or has been removed in the third regions 26. The third doped silicon layer 46 can, for example, be n-type or p-type doped. This additional doping (compared to the semiconductor substrate 12) can improve the passivation in the third regions 26. Depending on the doping of the third doped silicon layer 46, a pn junction can form to the first (e.g., p-type) doped silicon layer 20 or to the second (e.g., n-type) doped silicon layer 24.

[0085] Fig.Figure 3 shows a schematic cross section of the back-contacted solar cell 10 according to a third embodiment. The third embodiment differs from the second, in Fig. 2 shown, embodiment by the following: In the present case, the second electrodes 40 (e.g., formed as positive electrodes) are formed as alloying aluminum electrodes. In the region of the second interruptions 36 in the dielectric layer 32, there is an aluminum-silicon eutectic 50, which breaks through or penetrates the second doped silicon layer 24 and the second tunnel layer 30. The aluminum-silicon eutectic 50 is formed on the second electrodes 40 (or their underside). In the present case, the aluminum-silicon eutectic 50 is surrounded at least in sections by a fifth doped silicon layer 52. In other words, the silicon around the eutectic is doped. The doping can be aluminum doping. In the example with an n-type semiconductor substrate 12 (silicon base 12), an aluminum-doped emitter is formed, which surrounds the eutectic.In a further embodiment with a p-type semiconductor substrate 12, an aluminum-doped backside field (Al-BSF) can form at the interruptions.

[0086] It is also conceivable for the first electrodes 38 to also form a eutectic with a fifth doped silicon layer. The fifth doped silicon layer of the eutectic of the first electrodes 38 and the fifth doped silicon layer of the eutectic of the second electrodes 40 can have opposite polarity. The doping type of the respective eutectic can correspond to the polarity of the respective electrodes 38, 40 or to the respective first and / or second doped silicon layers 20, 24.

[0087] It is also conceivable that the above-described aluminum electrodes in combination with the first embodiment of the solar cell according to Fig. 1 are present.

[0088] The semiconductor substrate 12, the first doped silicon layers 20, the second doped silicon layers 24, the third doped silicon layers 46, the fourth doped silicon layer 48 and / or the third regions 26 of the solar cell 10 according to one of the three embodiments described above can each have a doping according to one of the combinations according to Table 1. Table 1: Semiconductor substrate 12 First doped silicon layer 20 Second doped silicon layer 24 Third region 26 or third doped silicon layer 46 Front side 14 of the solar cell 10 or fourth doped silicon layer 48 n n p - p n n p - n n n p p p n n p n n n p n - p n p n - n n p n p p n p n n n p n p - p p n p - n p n p p p p n p n n p p n - p p p n - n p p n p p p p n n n p n p - - p n p - p n p p - p n p n - p p n - - p p n - p p n p - p p n n - n n p - - n n p - - n n p p - n n p n - n p n - - n p n - - n p n p - n p n n -

[0089] Fig. Figure 4 shows a scanning electron image of a first, second, and third region 18, 22, 26 of the solar cell 10. This can be a solar cell 10 according to one of the three exemplary embodiments described above. The third regions 26 were produced in this case by undercutting.

[0090] In a unidirectional, directed deposition, e.g., physical vapor deposition, the particles can only be deposited on a free surface, i.e., outside the illustrated third region 26 (or outside the undercut region). The third region 26 therefore leads to an interruption of a unidirectionally deposited layer (e.g., the second doped silicon layer 24 (in Fig. 4 not shown)).

[0091] Fig. 5 to 16 show a method for producing a back-contacted solar cell 10 according to a first embodiment. Using the method shown, the solar cell 10 can be produced according to the above explanations, in particular according to the Fig. 1 shown first embodiment.

[0092] First, a semiconductor substrate 12 having a front side 54 and a back side 56 is provided. Fig.5 shows the semiconductor substrate 12 (or silicon wafer). The front side 54 of the semiconductor substrate 12 corresponds in particular to the front side 14 of the solar cell 10. Accordingly, the back side 56 of the semiconductor substrate 12 corresponds to the back side 16 of the solar cell 10. The first direction 44 is oriented perpendicular to the front side 54 and the back side 56 and points away from the back side 56. The deposition direction of the second doped silicon layer 24 by PVD corresponds in particular to the opposite direction of the first direction 44. In other words, the deposition direction of the second doped silicon layer 24 is oriented opposite to the first direction 44.

[0093] First, the semiconductor substrate 12 can be textured with an isotropic etch, particularly on the front side 54 and the back side 56. An additional etch prior to texturing to remove saw damage is possible. Other texturing methods are also conceivable.

[0094] The semiconductor substrate 12 can be subjected to full-surface diffusion, for example, furnace diffusion, to dope the surfaces, particularly on the front side 54 and back side 56. It can be doped with either a p-type or an n-type dopant, for example, boron or phosphorus. Thus, the fourth doped silicon layer 48 can be formed on the front side 14 of the solar cell 10. Depending on the doping, the dopant forms a so-called "front floating emitter" or a "front surface field." On the back side 56 of the semiconductor substrate 12, dopant can also diffuse to the surface and create an undesirable doping layer 49 (see FIG. Fig. 6).

[0095] During diffusion, e.g., furnace diffusion, a dopant-rich silicate glass, e.g., borosilicate glass (BSG) or phosphosilicate glass (PSG), can grow. This results in the formation of a silicate glass layer 62, particularly on the front side 54 and the back side 56 of the semiconductor substrate 12 (see FIG. Fig. 6). On the backside 56 of the semiconductor substrate 12, the doping layer 49 and the silicate glass layer 62 are undesirable and should be completely or at least partially suppressed or should be subsequently removed. Particularly for a solar cell 10 with a p-type semiconductor substrate 12, this diffusion step can also be skipped, so that the doping on the frontside 54 of the semiconductor substrate 12 (or on the frontside 14 of the solar cell 10) is not higher than the base doping of the semiconductor substrate 12.

[0096] Fig.7 shows a wet-chemical etching back of the back side 56 of the semiconductor substrate 12 (if necessary). This removes the doping layer 49 and the silicate glass layer 62. For example, the silicate glass layer 62 on the back side 56 can first be etched in an acidic, single-sided etching solution. A further alkaline etch etches only the exposed silicon on the back side 56 and removes the doping layer 49. The silicate glass layer 62 on the front side 54 of the semiconductor substrate 12 prevents the etching of the fourth doped silicon layer 48. The etching advantageously has an anisotropic effect, so that a planar surface is created on the back side 56 of the semiconductor substrate 12. An isotropic etch for a still textured back side 56 of the semiconductor substrate 12 is also conceivable.

[0097] Next, the first tunnel layer 28 is formed on the back side 56 of the semiconductor substrate 12 (see Fig.8). This can be grown or deposited. The thickness of the first tunnel layer 28 can be between 5 and 40 angstroms. The first tunnel layer 28 can be formed of silicon oxide. Other dielectric substances or materials that can serve for surface passivation are also conceivable if they allow charge carriers to pass through. The first tunnel layer 28 can also be grown or deposited on the front side 54 if necessary. However, the deposition on the front side 54 has no or only a decisive influence on the further process and is therefore not considered further.

[0098] The first doped silicon layer 20 is then formed on the first tunnel layer 28 (cf. Fig.9). This can be implemented by deposition. The thickness of the first doped silicon layer 20 can be between 20 nm and 400 nm. The first doped silicon layer 20 can have a dopant concentration in a range of 1×10 19 cm -3 and 1×10 21 cm -3The deposition of the first doped silicon layer 20 can be carried out, for example, using PVD, LPCVD, PECVD or APCVD. In this case, the first doped silicon layer 20 can also be deposited, at least partially at the edges, on the front side 54 of the semiconductor substrate 12. The first doped silicon layer 20 can be deposited in-situ doped or first deposited intrinsically and then doped ex-situ. During ex-situ doping, it should be noted that the silicate glass layer 62 on the front side 54 must at least partially serve as a diffusion barrier, in particular if the doping types of the first doped silicon layer 20 and the fourth doped silicon layer 48 are opposite. If the first doped silicon layer 20 is also deposited on the front side 54, it may have to be removed and / or taken into account in further process steps.

[0099] Next, an etch-stable barrier layer 58 is formed on the first doped silicon layer 20 (see Fig.10). This can be implemented by deposition. The barrier layer 58 can be formed, for example, from silicon nitride (SiNx), silicon oxide (SiOx), and / or silicon oxynitride (SiON). The barrier layer 58 can also be arranged as a layer stack comprising several layers on the rear side 56 of the semiconductor substrate 12. The barrier layer 58 serves as an etch barrier against alkaline etching in a further process step. In the case of ex-situ doping of the first doped silicon layer 20, the grown silicate glass from the furnace diffusion can, for example, also be used as the barrier layer 58. The barrier layer 58 can also cover the front side 54 completely or only partially, e.g., at the edges. Any barrier layer 58 on the front side 54 is not shown, but can be taken into account or removed in further process steps if necessary.

[0100] After the barrier layer 58 has been formed, it is removed in several etching areas 60 (cf. Fig. 11). This can be implemented, for example, by laser ablation. The ablation width can be between 50 µm and 2000 µm. The distance (center-to-center) between two etched regions 60 can be between 200 µm and 3000 µm. The ablation can be linear and result in a so-called "interdigitated" pattern. This pattern can be interrupted in regions of the current collecting bars of the solar cell 10. When removing the barrier layer 58 in the etched regions 60, the first doped silicon layer 20 and / or the first tunnel layer 28 can also be partially or completely removed. In addition, the semiconductor structure 12 on its rear side 56 can also be partially removed.

[0101] Subsequently, the etching regions 60 are etched, whereby the pedestal-like elevations 42 of the semiconductor substrate 12 are produced by the etching (cf. Fig.12). The first regions 18 are arranged on the elevations 42, and the second regions 22 are arranged between the elevations 42. In particular, the first doped silicon layer 20, the first tunnel layer 28, and partially the semiconductor substrate 12 on the rear side 56 in the second regions 22 are removed by etching. The etching can be carried out using an acidic or alkaline solution that removes the silicon isotropically or anisotropically. The barrier layer 58 (outside the etching regions 60) is not etched or is etched only very slowly, so that outside the etching regions 60, there is no etching of the first doped silicon layer 20, or only slight etching, aligned parallel to the first direction 44. The barrier layer 58, the first doped silicon layer 20, and the first tunnel layer 28 are undercut, creating the third regions 26, which are shaded along the first direction 44 (vertically).The depth of the etching areas 60 is determined by the etching depth and can be between 0.5 µm and 20 µm.

[0102] Etching can be performed in a single-sided process only on the back side 56. When using a batch process in which the semiconductor substrate 12 (or silicon wafer) is completely immersed in the etching agent with the front side 54 and the back side 56, the silicate glass layer 62 can serve as an etch barrier and prevent the etching of the semiconductor substrate 12 on the front side 54. If the first doped silicon layer 20 was also deposited on the front side 54 in a previous step, this can be etched until the underlying etch barrier in the form of the silicate glass layer 62 is exposed. If the barrier layer 58 was also deposited on the front side 54 in a previous step, it can be selectively removed from the front side 54 by an (acidic) etch, for example in a single-sided etch.This also applies if an etch-stable silicate glass has grown on the first doped silicon layer 20 during ex-situ doping.

[0103] The barrier layer 58 and / or the silicate glass layer 62 can then be completely removed (cf. Fig. 13). This can be achieved, for example, using an acidic solution. A purification step may follow.

[0104] In a next step, the second tunnel layer 30 can be formed (cf. Fig. 13). The second tunnel layer 30 can be formed by deposition or growth. The second tunnel layer 30 can be formed on the back side 56. Additionally, the second tunnel layer 30 can also be formed on the front side 54. The second tunnel layer 30 can saturate open bonds on the surface of the semiconductor substrate 12. The second tunnel layer 30 can have a layer thickness of 5 to 40 angstroms.

[0105] Subsequently, the second doped silicon layer 24 is formed (see Fig.14). The second doped silicon layer 24 can be formed by deposition. The second doped silicon layer 24 can be deposited using a directed process, for example, PVD. The second doped silicon layer 24 (e.g., p-type) has, in particular, a doping opposite to that of the first doped silicon layer 20 (e.g., n-type). Due to the cross-section of the pedestal-like elevations 42 widening in the first direction 44, the second doped silicon layer 24 is not formed in the third regions 26. The third regions 26 thus do not contain any amorphous, semi-crystalline, or polycrystalline silicon. In particular, due to the directed deposition (parallel and opposite to the first direction 44), no particles of the second doped silicon layer 24 are deposited in the third regions 26, since they are shaded.

[0106] Within the first regions 18, the second doped silicon layer 24 is deposited onto the second tunnel layer 30 and the underlying first doped silicon layer 20. The layer thickness of the second doped silicon layer 24 can be between 20 nm and 400 nm. The second doped silicon layer 24 can have a dopant concentration between 1×10 19 cm -3 and 2×10 20 cm -3 In particular, due to the directed deposition, the second doped silicon layer 24 is not deposited on the front side 54. A high-temperature step can follow to crystallize the first and / or second doped silicon layer 20, 24 and to activate the dopants in the first and / or second doped silicon layer 20, 24.

[0107] Next, a dielectric layer 32 may be deposited to passivate the surface of the front side 54 and the back side 56 (see Fig.15). The dielectric layer 32 can consist of one or more layers, for example of aluminum oxide, silicon oxide, and / or silicon nitride. In the present case, the dielectric layer 32 consists of two layers. The dielectric layer 32 on the front side 54 and the dielectric layer 32 on the back side 56 can be identical or different, in particular with different properties. The deposition process of the dielectric layer 32 can be preceded by a wet-chemical cleaning step. The hydrogen contained in the dielectric layer can serve to saturate open bonds on the surface of the semiconductor substrate 12, in particular in the first and second regions 18, 22 in which the first and second doped silicon layers 20, 24 are arranged, respectively. The dielectric layer 32 can also serve as an anti-reflective coating, in particular on the front side 54, and increase the light yield of the solar cell.

[0108] Subsequently, the first and second electrodes 38, 40 can be formed and / or applied (cf. Fig. 16). The first and / or second electrodes 38, 40 are arranged such that the first electrodes 38 each contact a first doped silicon layer 20 and the second electrodes 40 each contact a second doped silicon layer 24. The first electrodes 38 can each penetrate the second doped silicon layer 24 and the second tunnel layer 30 (in the first regions 18).

[0109] To contact the electrodes 38, 40, the dielectric layer 32 can have first and second interruptions 34, 36 at the corresponding locations. The interruptions 34, 36 can be created, for example, by local ablation, e.g., laser irradiation. Pastes can also be used to form the electrodes 38, 40. The first and / or second interruptions 34, 36 can also be created during firing of the pastes, in which the pastes locally dissolve the dielectric layer 32. The firing step can also have a positive effect on the passivation of the non-metallized surfaces, since the hydrogen contained in the dielectric layer 32 is mobilized during the high-temperature step, diffuses to the surfaces of the semiconductor substrate 12, and saturates open bonds there.

[0110] The first and / or second interruptions 34, 36 can be implemented as continuous lines or interrupted, in the form of round dots, squares, or segmented lines. The pastes can contain, for example, silver, copper, or aluminum as the conductive metal. After firing, the particles in the pastes sinter together and form the first and / or second electrodes 38, 40. The first and / or second electrodes 38, 40 can also comprise a layer stack (paste stack), for example of silver and copper. When using aluminum, the composition of the pastes can be selected so that the aluminum does not alloy with silicon, or only minimally so. Such a composition is suitable for both polarities.

[0111] The composition of the paste can also be selected so that during firing, the aluminum alloys with the silicon, and the resulting aluminum-silicon eutectic 50 penetrates the first and / or second doped silicon layer 20, 24. The aluminum can further dope the silicon and surround the eutectic 50, so that, depending on the polarity of the base, an Al-doped emitter or an Al-doped backside field can form. Such an alloying paste is particularly suitable for positive electrodes (see [Fig. 1]. Fig. 3). For negative electrodes, an n-type dopant can be added to the paste so that after the eutectic is formed, an n-type doped silicon surrounds the eutectic and the paste is suitable for forming the negative electrode.

[0112] Fig.17 to 28 show the method for producing a back-contacted solar cell 10 according to a second embodiment. Using the method shown, the solar cell 10 can be produced according to the above explanations, in particular according to the Fig. 2 shown first embodiment.

[0113] In a first step, the semiconductor substrate 12 is etched with an anisotropic etching agent to remove any sawing damage. This creates a planar front side 54 and a planar back side 56 of the semiconductor substrate 12 (see FIG. Fig. 17).

[0114] Next (analogous to the first embodiment of the method), the first tunnel layer 28, then the first doped silicon layer 20 and subsequently the barrier layer 58 are formed on the back side 56 of the semiconductor substrate 12 (cf. Fig.18-20). The first tunnel layer 28 can have a layer thickness of 5 to 40 angstroms, the first doped silicon layer 20 can have a layer thickness of 20 nm to 400 nm, and the barrier layer 58 can be formed analogously to the first exemplary embodiment of the method. The first tunnel layer 28 can also be grown thermally. The first tunnel layer 28, the first doped silicon layer 20, and / or the barrier layer 58 can completely cover the rear side 56 of the semiconductor substrate 12. The first tunnel layer 28, the first doped silicon layer 20, and / or the barrier layer 58 can each, or all together, partially cover the front side 54 of the semiconductor substrate 12, in particular only at the edges, or completely.

[0115] The first doped silicon layer 20 can be deposited in-situ doped, with a dopant concentration of 1×10 19 up to 2×10 20 cm -3, or first deposited intrinsically and then doped ex-situ, e.g., by means of furnace diffusion. If a silicate glass grows on the surface during furnace diffusion, this can optionally be used as a barrier layer 58. The doping of the first doped silicon layer 20 can comprise either n- or p-type doping according to Table 1. The barrier layer 23 can comprise a dielectric layer, for example SiOx, SiON, or SiNx, or a layer stack comprising several (such) layers.

[0116] Subsequently (analogous to the first embodiment of the method), the barrier layer 58 is removed locally so that etching regions 60 are formed (cf. Fig.21). This can be implemented, for example, by laser ablation. In this case, the first doped silicon layer 20 and / or the first tunnel layer 28 can also be at least partially or completely removed in the etching regions 60. Furthermore, the semiconductor substrate 12 (at its rear side 56) can be at least partially removed in the etching regions 60.

[0117] Thereafter, a wet-chemical etching step is carried out to remove (if still present) the first doped silicon layer 20 of the first tunnel layer 28 and partially the semiconductor substrate 12 (cf. Fig.22). Approximately 0.5 µm to 20 µm of the semiconductor substrate 12 can be removed in the etching areas 60. Etching with an alkaline silicon etching agent can be performed on one side only on the back side 56 or can also include the front side 54. The layers that may have been deposited on the front side 54 in the preceding process steps should also be etched, if necessary with an additional one-sided etching.

[0118] It is also conceivable to clean and / or etch the front side 54 in an earlier or later process step. By etching the front side 54, a textured surface of the front side 54 can be created. It is important that during etching on the back side 56, an under-etching of the barrier layer 58 and possibly the first doped silicon layer 20 occurs, so that an under-etched region is formed (i.e., the elevations 42 and the third regions 26 are formed). The third (under-etched) regions 26 are shaded along the first direction 44 (vertical) by the barrier layer 58 and the first doped silicon layer 20. The third (under-etched) regions 26 are formed regardless of whether an isotropic or anisotropic etch is used. In particular, with an isotropic etch, the surface of the third regions 26 can be textured and provided with an inclination, as in Fig. 4 shown.

[0119] After etching, the second tunnel layer 30 is formed by growth or deposition (see Fig. 23). The second tunnel layer 30 can have a layer thickness of 5 to 40 angstroms. The second tunnel layer 30 can be grown or deposited in an undirected manner, so that it can also be formed in the first, second, and third regions 18, 22, 26. The second tunnel layer 30 can also be formed on the front side 54.

[0120] Thereafter, the second doped silicon layer 24 is formed (see Fig.24). This can be implemented by means of directional deposition, for example, by means of physical vapor deposition (PVD). The second doped silicon layer 24 is deposited on the entire non-shaded surface on the backside 56 of the semiconductor substrate 12. The second doped silicon layer 24 is not deposited in the undercut, shaded third regions 26. The second doped silicon layer 24 is thus interrupted by the third regions 26. Within the second regions 22, the second doped silicon layer 24 is also not in contact with the first doped silicon layer 20.

[0121] The second doped silicon layer 24 can either be deposited in-situ doped or deposited intrinsically and then, for example, in a furnace diffusion (cf. Fig.25). A further layer can be deposited on the second doped silicon layer 24 by means of PVD, which can serve as a diffusion barrier in a subsequent (furnace) diffusion step. This can prevent further doping of the second doped silicon layer 24 during furnace diffusion. For example, in the third (under-etched) regions 26, a doping contrary to the second doped silicon layer 24 in the form of a third doped silicon layer 46 can form. The doping of the second doped silicon layer 24 should have the contrary doping of the first doped silicon layer 20 according to Table 1.

[0122] For the formation of a charge carrier-selective contact, a high-temperature step may be required which crystallizes the amorphous, semi-crystalline or polycrystalline silicon of the first doped silicon layer 20 and / or the second doped silicon layer 24 and activates the dopants. This crystallization can, for example, also take place in the furnace diffusion step described above, thereby avoiding the above-mentioned high-temperature step.

[0123] Fig.25 shows such a diffusion process of a dopant, for example boron or phosphorus, for forming the fourth doped silicon layer 48 on the front side 54. The polarity of the doping of the fourth doped silicon layer 48 is to be selected according to Table 1. It may prove advantageous if the back side 56 is also doped completely or at least partially in the same process step. In particular, in the third regions 26, the same or a similar doping as on the front side 54 forms. In other words, the third doped silicon layer 46 is formed. The second doped silicon layer 24 can either also be doped during this diffusion step if the second doped silicon layer 24 was deposited intrinsically or at least further doped if the second doped silicon layer 24 is not covered by a diffusion barrier.

[0124] The dopant concentration in the second doped silicon layer 24 may differ from the dopant concentration in the third regions 26 and the dopant concentration of the fourth doped silicon layer 48, since the diffusion rate in amorphous, semi-crystalline, or polycrystalline silicon is higher than in the monocrystalline semiconductor substrate 12. Furthermore, the second tunnel layer 30 may prevent or reduce the diffusion in the third regions 26 and on the front side 54, provided the second tunnel layer 30 is present there.

[0125] During the diffusion step, particularly during furnace diffusion, the silicate glass layer 62, for example a borosilicate glass (BSG) or a phosphosilicate glass (PSG), can grow on the front side 54 and the back side 56 (cf. Fig. 25). The Fig.The method step illustrated in Figure 25 can be omitted, particularly in the case of a p-type semiconductor substrate 12, so that no higher doping is formed on the front side 54 (and thus the fourth doped silicon layer 48) and in the third regions 26 (and thus the third doped silicon layer 46). In this case, the second doped silicon layer 24 can be deposited as in-situ doped.

[0126] In a further step, a wet-chemical cleaning can be carried out to remove the silicate glass layer 62 on the front side 54 and the back side 56 (cf. Fig.26). In an etching step, the second tunnel layer 30 in the third regions 26 (if present) can also be removed. The second tunnel layer 30 can be removed in the same etching step as the silicate glass layer 62. In other words, the second tunnel layer 30 and the silicate glass layer 62 can be removed together (or using the same etching process) (if present).

[0127] Fig. 27 and Fig. 28 illustrate the formation of the dielectric layer 32 on the front side 54 and the back side 56 (in this case consisting of two layers each), as well as the formation of the first and second electrodes 38, 40. These in the Fig. 27 and Fig. 28 steps shown correspond to the steps in the Fig. 15 and Fig. 16 shown steps of the first embodiment, are in particular identical thereto.

[0128] The individual steps of the two embodiments of the method described above can be combined and / or supplemented as desired.

Claims

[1] A back-contacted solar cell (10) comprising a semiconductor substrate (12), a front side (14) of the solar cell (10) and a back side (16) of the solar cell (10), wherein a plurality of first regions (18) each having a first doped silicon layer (20), a plurality of second regions (22) each having a second doped silicon layer (24) and a plurality of third regions (26) are arranged on the back side (16) of the solar cell (10), wherein the first doped silicon layers (20) and the second doped silicon layers (24) are each amorphous, semi-crystalline or polycrystalline, wherein the third regions (26) each contain no amorphous, semi-crystalline or polycrystalline silicon, wherein a first tunnel layer (28) is arranged between the first doped silicon layer (20) and the semiconductor substrate (12),wherein a second tunnel layer (30) is arranged between the second doped silicon layer (24) and the semiconductor substrate (12), wherein the first regions (18) and the second regions (22) are each formed as passivating contacts, wherein a surface of the rear side (16) or the rear side (16) and the front side (14) of the solar cell (10) is at least partially covered with a dielectric layer (32) or dielectric layer stack, wherein the dielectric layer (32) or layer stack comprises a first interruption (34) in the region of the first regions (18) and a second interruption (36) in the region of the second regions (22), wherein the solar cell (10) comprises a plurality of first electrodes (38) and a plurality of second electrodes (40), wherein a first electrode (38) contacts a first doped silicon layer (20) through a first interruption (34),wherein in each case a second electrode (40) contacts a second doped silicon layer (24) through a second interruption (36), wherein the first regions (18) are arranged on pedestal-like elevations (42) of the semiconductor substrate (12), wherein the elevations (42) each have a cross-section widening in a first direction (44), wherein the first direction (44) is a direction pointing away from the rear side (16) of the solar cell (10), wherein the third regions (26) are formed as undercut regions, wherein the second regions (22) are formed free of undercuts. [2] Back-contacted solar cell (10) according to claim 1, characterized by that the third regions (26) are undoped. [3] Back-contacted solar cell (10) according to claim 1 or 2, characterized by that the third regions (26) each have a third doped silicon layer (46). [4] Back-contacted solar cell (10) according to one of the preceding claims, characterized by that a fourth doped silicon layer (48) is arranged on the front side (14) of the solar cell (10). [5] Back-contacted solar cell (10) according to one of the preceding claims, characterized by that the semiconductor substrate (12), the first doped silicon layers (20), the second doped silicon layers (24), the third doped silicon layers (46), the fourth doped silicon layer (48) and / or the third regions (26) have a doping according to one of the combinations according to Table 1. [6] Back-contacted solar cell (10) according to one of the preceding claims, characterized by that the first doped silicon layers (20), the second doped silicon layers (24), the first tunnel layers (28) and / or the second tunnel layers (30) are each formed free of openings. [7] Back-contacted solar cell (10) according to one of claims 1 to 4, characterized by that the first doped silicon layers (20), the second doped silicon layers (24), the first tunnel layers (28) and / or the second tunnel layers (30) are each perforated by an aluminum-silicon eutectic (50), wherein the aluminum-silicon eutectic (50) is arranged on the respective first electrode (38) and / or on the respective second electrode (40). [8] Back-contacted solar cell (10) according to the preceding claim, characterized by in that the aluminum-silicon eutectic (50) is at least partially surrounded by a fifth doped silicon layer (52), wherein the fifth silicon layer (52) has a p-type doping or an n-type doping corresponding to the doping of the first or the second doped silicon layer (20, 24). [9] Method for producing a back-contacted solar cell (10) according to one of the preceding claims, comprising the steps: - Providing a semiconductor substrate (12) having a front side (54) and a back side (56); - forming a first tunnel layer (28) on the back side (56) of the semiconductor substrate (12); - forming a first doped silicon layer (20) of a first polarity on the first tunnel layer (28); - forming an etch-stable barrier layer (58) on the first doped silicon layer (20); - removing the etch-stable barrier layer (58) in several etching areas (60); - etching in the etching regions (60), wherein the etching produces pedestal-like elevations (42) of the semiconductor substrate (12) with a cross-section widening in the first direction (44); - forming a second tunnel layer (30), in particular in the regions between the pedestal-like elevations (42) of the semiconductor substrate (12); - forming a second doped silicon layer (24) with a second polarity which is opposite to the first polarity, in particular in the regions between the pedestal-like elevations (42), wherein no second doped silicon layer (24) is formed in the third regions (26) due to the widening cross section of the pedestal-like elevations (42). [10] Method according to claim 9, characterized by that the procedure includes the steps: - Forming the third doped silicon layers (46) in the third regions (26) and / or the fourth doped silicon layer (48) on the front side (54) by means of furnace diffusion. [11] Method according to the preceding claim, characterized by that the procedure comprises the step: - removing a silicate glass layer (62) formed during the furnace diffusion, in particular by etching. [12] Method according to one of claims 9 to 11, characterized by that the procedure includes the steps: - forming the first and / or second electrodes (38, 40) and / or forming the aluminum-silicon eutectic (50) on the first and / or second electrodes (38, 40) by using pastes or paste stacks, in particular wherein the pastes or paste stacks contain a p-type dopant, in particular aluminum, and / or an n-type dopant.

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