SELECTION OF PRIMARY AND SECONDARY ADMINISTRATIVE CONTROLS IN A MULTI-ADMINISTRATIVE CONTROL SYSTEM

Abstract

The examples described herein relate to a system. In some examples, the system includes an interface and a circuit arrangement coupled to the interface. In some examples, the circuit arrangement, when operating, is used to: select a primary management controller and a secondary management controller from among the multiple management controllers, based on the detection of multiple management controllers. In some examples, the primary management controller is intended to perform at least one different operation than the secondary management controller, wherein the primary management controller includes a baseboard management controller (BMC), the secondary management controller includes a BMC, and the multiple management controllers are located in at least one programmable network interface device and a host system.

Description

BACKGROUNDData centers include an array of computing platforms with numerous devices that execute software and firmware. Various schemes are available to manage computing platform configurations and monitor computing platform operations. Distributed Management Task Force (DMTF) Redfish® is an example suite of industry standard protocols and application program interfaces (APIs) for out-of-band configuration and management of servers, networks, storage devices, and device equipment. To make various changes to system configurations, control settings, and / or firmware (e.g., basic input output system (BIOS)), Redfish® protocols access a baseband management controller (BMC).A computing system may include a central processing unit (CPU) to perform computational operations and to utilize a BMC on the system to control the system to apply control and policies to the system. Intel® infrastructure processing units (IPUs) provide network connectivity and can execute processes as an alternative to using the CPU. IPUs may include BMCs that may supplement the computing system by providing another way to control and monitor a system, in addition to the BMC used by the CPU.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates an example system. FIG. 2 illustrates an example process. FIGS. 3A and 3B illustrate example network interface devices. FIG. 4 illustrates an example network interface device. FIG. 5 illustrates an example system.DETAILED DESCRIPTIONIn some cases, multiple BMCs may apply different and sometimes conflicting sets of policies, which may result in inconsistent behavior between different management controllers or live lock or dead lock due to the application of conflicting policies. Some examples described herein provide arbitration circuitry (e.g., circuitry and / or processor-executed software or firmware) to arbitration among multiple management controllers, such as management controllers on the computing system and the network interface device or other device (e.g., accelerator, graphics processing unit (GPU), memory device, and so forth), such that platform policies may be configured based on priority and a hierarchy may be applied to reduce a likelihood of inconsistent behavior between different management controllers or a live lock or dead lock due to application of conflicting policies. The arbitration circuitry may be validated as trusted to reduce risks of compromise of operation of servers by remote control, deployment of malware, implants of ransomware and firmware, and physical damage (e.g., bricking) of the server. Arbitration circuitry may discover various management controllers in a platform and authenticate management controllers based on an identification credential provided by the management controllers. To reduce a likelihood of conflicting or inconsistent commands from different management controllers, the arbitration circuitry may apply an arbitration scheme to select a management controller as a primary management controller and select a management controller as a secondary management controller, where primary and secondary management controllers perform different operations.FIG. 1 illustrates an example system. Platform 100 may include at least one host 110, network interface devices 120- 0 to 120- 1, and arbitration circuitry 130. The host 110 may include a management controller (MC) 112, memory and devices 114, processors 116, as well as other circuitry and software described at least with reference to FIGS. 3A, 3B, 4, and / or 5. Network interface device 120- 0 may include management controller (MC) 122- 0, computation 124- 0 (e.g., CPU, GPU, or other instruction-executing processor), direct memory access (DMA) circuitry (not shown), accelerator 126- 0, network interface 128- 0, as well as other circuitry and software described at least with reference to FIGS. 3A, 3B, 4, and / or 5. Similarly, network interface device 120- 1 may include an MC 122- 1, a computation 124- 0 (e.g., CPU, GPU, or other instruction-executing processor), a DMA circuitry (not shown), an accelerator 126- 1, a network interface 128- 1, as well as other circuitry and software described at least with reference to FIGS. 3A, 3B, 4, and / or 5.Although the examples shown for network interface devices 120- 0 and 120- 1 are similar, network interface devices 120- 0 and 120- 1 may include different components and execute different software. Different numbers of network interface devices may be connected to the host 110. The host 110 may be communicatively coupled to the network interface device 120- 0 and / or the network interface device 120- 1 via the host interface 129.The host interface 129 may communicate in a manner consistent with one or more of the following: Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCl), or other connection technologies. See, for example, PCIe (Peripheral Component Interconnect Express) Base Specification 1.0 (2002), as well as earlier versions, later versions, and variations thereof. See, for example, CXL (Compute Express Link) specification revision 2.0, version 0.7 (2019), as well as earlier versions, later versions, and variations thereof. See, for example, the UCIe-1.0 specification (2022), as well as earlier versions, later versions, and variations thereof.One or more of the management controllers 112, 122- 0, and 122- 1 may perform management and monitoring capabilities for system administrators to monitor operation of at least the host 110 (and devices connected thereto) and the network interface devices 120- 0 to 120- 1 using channels, including channels capable of communicating data (e.g., in-band channels) and out-of-band channels. Out-of-band channels may include packet flows or transmission media that communicate metadata and telemetry and may not communicate data. In some examples, one or more of the management controllers 112, 122- 0, and 122- 1 may be communicatively coupled to the host 110, and may be implemented as one or more of: board management controller (BMC), Intel® management or managementability engine (ME), or other devices.One or more of the management controllers 112, 122- 0, and 122- 1 may be configured to communicate with the arbitration circuitry 130, and the arbitration circuitry 130 may send signals to select a primary management controller and secondary management controllers from the management controllers 112, 122- 0, and 122- 1. Arbitration circuitry 130 may configure operations of primary and secondary management controllers and allowed outputs of primary and secondary management controllers, as described herein. Arbitration circuitry 130 may be implemented as one or more of: circuitry and / or processor-executed software or firmware. For example, arbitration circuitry 130 may send a signal to management controller 112 of host 110 to indicate that management controller 112 of host 110 is a primary or secondary management controller. For example, arbitration circuitry 130 may send a signal to management controller 122- 0 of network interface devices 120- 0 or send a signal to management controller 122- 1 of network interface devices 120- 1 to indicate that management controller 122- 0 or 122- 1 is a primary or secondary management controller.Arbitration circuitry 130 may be connected to host 110 via a printed circuit board connected to host 110 via a device interface or a server in the same data center as host 110. Arbitration circuitry 130 may be coupled to management controllers 112, 122- 0, and 122- 1 using a device interface (e.g., PCIe or CXL) or another interface (e.g., I2C or I3C).For example, at boot time of a core of the processors 116 (or after boot time), the management controllers 112, 122- 0, and 122- 1 may communicate with the arbitration circuitry 130 to access a credential of the arbitration circuitry 130, and one or more of the management controllers 112, 122- 0, and 122- 1 may communicate with the arbitration backend 150 to authenticate the arbitration circuitry 130. An identity credential may include a process address space identifier (PASID) or other value. For example, an evidence of identity may be based on a hash derived from a public and private key pair (e.g., Rivest-Shamir-Adheman (RSA), Elliptic Curve Cryptography (ECC), or other) or blockchain-based identities. Based on the attack of arbitration circuitry 130, management controllers 112, 122- 0, and 122- 1 may provide an associated credential to arbitration circuitry 130.Arbitration circuitry 130 may authenticate management controllers 112, 122- 0, and 122- 1 with trusted backend 150 based on a provided credential from management controllers 112, 122- 0, and 122- 1. The credential associated with the management controllers 112, 122- 0, and 122- 1 may be based on a PASID or a hash derived from a public and private key pair. In some examples, to authenticate arbitration circuitry 130 and management controllers 112, 122- 0, and 122- 1, technologies based on trusted computing group (TCG) device identifier composition engine (DICE) standards (e.g., DICE Attention Architecture Version 1.00 (2020) and previous versions, revisions, and variations thereof) may be utilized.Arbitration circuitry 130 may communicate with backend server 150 to access configuration 132 for platform 100. Based on configuration 132, arbitration circuitry 130 may specify actions that a particular management controller is allowed to perform. Based on configuration 132, arbitration circuitry 130 may assign a set of associated functionalities to management controllers 112, 122- 0, and / or 122- 1, and arbitration circuitry 130 may update the associated functionalities after the initial assignment out-of-band or in-band with data traffic.For example, the arbitration circuitry 130 may select one or more of the management controllers 112, 122- 0, and / or 122- 1 as primary management controller and secondary management controller(s) based on the configuration 132. Based on configuration 132, arbitration circuitry 130 may configure management controllers 112, 122- 0, and / or 122- 1 to disable or enable particular operations for authorized tenants. An example format of configuration 132 may be as shown in Table 1, however, configuration 132 may specify particular operations that a particular MC is allowed to perform. Table 1 Table 1MC 122-0, MC 122-1, MC 112MC 112 is primaryMC 122-0, MC 112MC 122-0 is primaryMC 122-1, MC 112MC 122-1 is primaryMC 122-0, MC 122-1MC 122-0 is primaryIf a particular MC is not identified in the configuration 132, the arbitration circuitry 130 does not assign primary or secondary MC roles to such an MC not identified in the configuration 132 and may issue a warning to an orchestrator or administrator.In some examples, a primary management controller may perform a set of operations including operations to manage the system and control critical features (e.g., ring 0 authentication type). Operations for managing the system and controlling critical features may include one or more of: performing power distribution across the various parts of the system, assigning power management of the host system and the at least one network interface device, configuring the operating frequency or power of cores of the host 110 and the network interface devices 120- 0 and 120- 1, memory management of the host system 110 and the network interface devices 120- 0 and 120- 1, controlling software updates of the host system 110 and the network interface devices 120- 0 and 120- 1, or controlling firmware updates of the host system 110 and the network interface devices 120- 0 and 120- 1.In some examples, a primary management controller may perform one or more of: retrieving server identification and asset information (e.g., health condition, temperature sensors and fans, power supply output levels, platform power consumption, and thresholds), input / output (I / O) infrastructure data (e.g., host network interface controller media access control (MAC) address(s)) for devices to be managed (e.g., Lights Out Management (LOM) devices), hard disk status or fault reporting, network-based discovery of a service endpoint, discovery of a system topology (e.g., rack, chassis, server, nodes), Reboot or power cycle servers with connected devices, change device booting order, set power thresholds, alert or event notifications, event log access, access to and configuring management control network settings, manage management control user accounts, or others.In some examples, after the selection of the primary management controller, the arbitration circuitry 130 may limit operations of the secondary management controller to detecting and monitoring the physical state of the platform 100 (e.g., power consumption, temperature, and so forth), the network, and sensors, and communicating such information to the primary management controller. The primary management controller may transmit such information to a system administrator. For example, the primary management controller and / or the secondary management controller may perform operations described at least with respect to Redfish® (e.g., Redfish Scalable Platforms Management API Specification Version 1.0 (2015), as well as earlier versions, later versions, and variations thereof).In some examples, primary and secondary management controllers may provide messages and commands to arbitration circuitry 130, and arbitration circuitry 130 may coalesce the data and provide a status update to system administrator or arbitration backend 150 for processing. The system administrator or arbitration backend 150 may determine an operating status of the host 110, such as software versions, firmware versions, power consumption, or temperature. The system administrator or arbitration backend 150 may modify software and firmware used by the host 110 and the network interface devices 120- 0 and 120- 1 based on received status updates.Arbitration circuitry 130 may function as a proxy for administration control outputs (e.g., configuration data and telemetry). Arbitration circuitry 130 may intercept or receive action requests from a particular management controller and test configuration 132 to determine whether the action requests are permitted. If the action is permitted, arbitration circuitry 130 may allow the request to go to the corresponding target device within platform 100. If the action is not permitted, arbitration circuitry 130 may reject the request (e.g., not forward the request to the target device) and communicate with backend 150 to trigger an error or indicate that an invalid request has been issued.Arbitration backend 150 may host and execute a trusted service responsible for providing configuration schemes (e.g., configuration 132) and providing attestation capabilities to authenticate management controllers and arbitration circuitry 130. The backend 150 may be positioned either in a host system in a data center edge or in the cloud.FIG. 2 illustrates an example process. The process may be performed by arbitration circuitry, a processor core (e.g., a core of processors 116), a management controller, or other circuitry, processor-executed software, or firmware, in some examples. At 202, detection of one or more management controllers connected to a platform may occur. For example, when booting a management controller, the management controller may indicate a device identifier via a bus or an interconnect. At 204, the detected management controller(s) may be authenticated. The attestation may include verification of the device identifier provided by a management controller. At 206, a configuration to be applied to one or more detected management controllers may be read. For example, the configuration may indicate certain roles of management controllers in a system, including specifying which management controller in the platform is to be a primary management controller and which management controller in the platform is to be a secondary management controller. At 208, based on the assessment of multiple management controllers, a primary management controller may be selected from the one or more detected management controllers. The selection of the primary management controller may be based on the configuration. At 210, one or more second management controllers may be selected from the one or more detected management controllers that are not selected as a primary management controller. However, if only a single management controller is detected, the single detected management controller may be selected as the primary management controller, and no secondary management controller is selected, and if the single management controller is authenticated, the single management controller may perform configured operations. Thereafter, commands and telemetry issued to one or more target devices may be provided by primary and secondary management controllers according to the configuration. It should be noted that the attestation of a management controller and the configuration of a management controller may be as a primary or secondary management controller at time intervals, in response to processor or platform booting, or in response to a request from a system administrator or orchestrator.FIG. 3A illustrates an example system. The host 300 may include processors, memory devices, device interfaces, as well as other circuitry, such as described with respect to one or more of FIGS. 3B, 4, and / or 5. Processors of the host 300 may execute software, such as applications (e.g., microservices, virtual machines (VMs), microVMs, containers, processes, threads, or other virtualized execution environments), operating system (OS), and device drivers. An OS or device driver may configure a network interface device or packet processing device 310 to utilize one or more control planes to communicate with the SDN (software defined networking) controller 350 over a network to configure operation of the one or more control planes.The packet processing device 310 may include multiple computing complexes, such as an acceleration compute complex (ACC) 320 and a management compute complex (MCC) 330, as well as packet processing circuitry 340 and network interface technologies for communicating with other devices over a network. The ACC 320 may be implemented as one or more of the following: a microprocessor, a processor, an accelerator, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or circuitry described with reference to at least FIGS. 3B, 4, and / or 5. Similarly, the MCC 330 may be implemented as one or more of the following: a microprocessor, a processor, an accelerator, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or circuitry described with reference to at least FIGS. 3B, 4, and / or 5. In some examples, the ACC 320 and the MCC 330 may be implemented as separate cores in one CPU, different cores in different CPUs, different processors in the same integrated circuit, different processors in different integrated circuits.As described herein, management controller 334 may store an encrypted device identifier and provide the device identifier to arbitration circuitry 342 to authenticate management controller 334. Management controller 334 may receive a configuration of operations to be performed from arbitration circuitry 342, such as when multiple management controllers are operating in one platform. The management controller 334 may perform operations according to the received configuration.The packet processing device 310 may be implemented as one or more of the following: a microprocessor, a processor, an accelerator, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or circuitry described at least with reference to FIGS. 3B, 4, and / or 5. Packet processing pipeline circuitry 340 may process packets as directed or configured by one or more control planes executed by multiple computational complexes. In some examples, ACC 320 and MCC 330 may execute respective control planes 322 and 332.The SDN controller 350 may update or reconfigure software executing on the ACC 320 (e.g., control plane 322 and / or control plane 332) by contents of packets received by the packet processing device 310. In some examples, the ACC 320 may execute a control plane operating system (OS) (e.g., Linux) and / or a control plane application 322 (e.g., user space or kernel modules) used by the SDN controller 350 to configure the operation of the packet processing pipeline 340. The control plane application 322 may include generic flow tables (GFT), ESXi, NSX, Kubernetes control plane software, application software for managing crypto configurations, programming protocol independent packet processors (P4) runtime daemon, destination specific daemon, container storage interface (CSI) agents, or remote direct memory access (RDMA) configuration agents.In some examples, the SDN controller 350 may communicate with the ACC 320 using a remote procedure call (RPC), such as google remote procedure call (gRP), or other service, and the ACC 320 may convert the request to a target specific protocol buffer (protocol buf) request to the MCC 330. The gRPC is a remote procedure invocation solution based on data packets sent between a client and a server. Although gRP is an example, other communication schemes may be used, such as, but not limited to, Java Remote Method Invocation, Moda-3, RPyC, Distributed Ruby, Erlang, Elixir, Action Message Format, Remote Function Call, Open Network Computing RPC, JSON-RPC, and so forth.In some examples, the SDN controller 350 may provide packet processing rules for execution by the ACC 320. For example, the ACC 320 may program table rules (e.g., header field alignment and corresponding action) applied by the packet processing pipeline circuitry 340 based on a policy change and changes to VMs, containers, microservices, applications, or other processes. The ACC 320 may be configured to provide a network policy as flow cache rules into a table to configure the operation of the packet processing pipeline 340. For example, the ACC2 control plane application 322 may configure rule tables applied by the packet processing pipeline circuitry 340 with rules to define a traffic destination based on packet type and content. The ACC 320 may program table rules (e.g., alignment action) in memory that the packet processing pipeline circuitry 340 may access based on a policy change and changes in VMs.A flow may be a sequence of packets transferred between two endpoints, which generally represents a single session using a protocol. Accordingly, a flow may be identified using a match by a set of defined tuple, and for routing purposes, a flow is identified by the two tuple identifying the endpoints, e.g., the source and destination addresses. For content-based services (e.g., load balancer (load balancer), firewall, intrusion detection system, etc.), flows can be identified at a finer granularity by using N-tuple (e.g., source address, destination address, IP protocol, transport layer source port, and destination port). A packet in a flow is expected to have the same set of tuple in the packet header. A packet flow to be controlled may be identified by a combination of tuple (e.g., Ethernet type field, source and / or destination IP address, source and / or destination user datagram protocol (UDP) ports, source / destination TCP ports, or any other header field) and source and destination queue pair (QP) unique number or identifier.For example, the ACC 320 may execute a virtual switch, such as vSwitch or Open vSwitch (OVS), stratum or vector packet processing (VPP), that provides communications between virtual machines executed by the host 300 or with other devices connected to a network. For example, the ACC 320 may configure the packet processing pipeline circuitry 340 as to which VM is to receive traffic and which type of traffic a VM may transmit. For example, packet processing pipeline circuitry 340 may execute a virtual switch, such as vSwitch or Open vSwitch, that provides communications between virtual machines executed by host 300 and packet processing device 310.The MCC 330 may execute a host management control plane, a global resource manager, and perform a hardware register configuration. The control plane 332 executed by the MCC 330 may perform the provisioning and configuration of the packet processing circuitry 340. For example, a VM executing on the host 300 may use the packet processing device 310 to receive or transmit packet traffic. The MCC 330 may execute boot, power, management, and manageability software (SW) or firmware (FW) code to boot and initialize the packet processing device 310, manage device power consumption, provide connectivity to the management controller 334 (e.g., baseboard management controller (BMC)), and other operations.One or both control planes of the ACC 320 and the MCC 330 may define traffic routing table content and network topology that are applied by the packet processing circuitry 340 to select a path of a packet in a network to a next hop or to a device connected to the target network. For example, a VM executing on the host 300 may use the packet processing device 310 to receive or transmit packet traffic.The ACC 320 may execute control plane drivers to communicate with the MCC 330. At least to provide a configuration and provisioning interface between control planes 322 and 332, communication interface 325 may provide control plane-to-control plane communications. The control plane 332 may perform a gatekeeper operation for configuring shared resources. For example, the ACC control plane 322 may communicate with the control plane 332 via the communication interface 325 to perform one or more of: determining hardware capabilities, accessing the data plane configuration, reserving hardware resources and configuration, communications between ACC and MCC through interrupts or queries, subscription to receive hardware events, performing indirect hardware register read-write operations for debugability, configuring flash and physical layer interface (PHY), or performing system provisioning for different deployments of a network interface device, such as: storage nodes, tenant hosting nodes, microservice backend, compute nodes, or others.Communication interface 325 may be utilized by a negotiation protocol and configuration protocol that executes between ACC control plane 322 and MCC control plane 332. Communication interface 325 may include a universal mailbox for various operations performed by packet processing circuitry 340. Examples of operations of packet processing circuitry 340 include outputting non-volatile memory express (NVMe) reads or writes, outputting non-volatile memory express over fabrics (LCE) reads or writes, address translation engine (ATE) (e.g., input-output memory management unit (IOMMU) to provide a virtual-to-physical address translation), encryption or decryption, configuration as a storage node, configuration as a tenant hosting node, Configuration as a compute node, provision of multiple different types of services between different peripheral component interconnect express (PCIe) endpoints, or others.The communication interface 325 may include one or more mailboxes that may be accessed as registers or memory addresses. For communications from control plane 322 to control plane 332, communications may be written to the one or more mailboxes by control plane drivers 324. For communications from control plane 332 to control plane 322, communications may be written to the one or more mailboxes. Communications written in mailboxes may include descriptors including message opcode, message errors, message parameters, and other information. Communications written in mailboxes may include messages in a defined format that communicate data.Communication interface 325 may provide communications based on writes or reads to particular memory addresses (e.g., dynamic random access memory (DRAM)), registers, other mailboxes that are written and read to pass commands and data. To provide secure communications between control planes 322 and 332, registers and memory addresses (and memory address translations) may be available for communications only to be written to or read from control planes 322 and 332 or cloud service provider (CSP) software executing on ACC 320 and device provider software, embedded software, or firmware executing on MCC 330. The communication interface 325 may support communications between multiple different computing complexes, such as from host 300 to MCC 330, host 300 to ACC 320, MCC 330 to ACC 320, basic board management control (BMC) to MCC 330, BMC to ACC 320, or BMC to host 300.The packet processing circuitry 340 may be implemented using one or more of application specific integrated circuit (ASIC), field programmable gate array (FPGA), processors executing software, or other circuitry. The control plane 322 and / or 332 may configure the packet processing pipeline circuitry 340 or other processors to perform operations related to NVMe, NVMe oF reads or writes, LCE (Lookaside Crypto Engine), ATE (Address Translation Engine), local area network (LAN), compression / decompression, encryption / decryption, or other accelerated operations.Various message formats may be used to configure the ACC 320 or the MCC 330. In some examples, a P4 program may be compiled and provided to the MCC 330 to configure the packet processing circuitry 340. The following is a JSON configuration file that can be transmitted from the ACC 320 to the MCC 330 to obtain capabilities of the packet processing circuitry 340 and / or other circuitry in the packet processing device 310. In particular, the file may be used to specify a number of transmit queues, a number of receive queues, a number of traffic classes (TC) supported, a number of available interrupt vectors, a number of available virtual ports and the types of ports, a size of allocated memory, supported parser profiles, exactly matching table profiles, packet mirroring profiles, among others.FIG. 3B illustrates an example network interface device system. The network subsystem 360 may be communicatively coupled to the computing complex 380. The device interface 362 may provide an interface for communicating with a host. Various examples of device interface 362 may utilize protocols based on Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), or others, as well as a virtual device interface, such as virtual device interfaces.The interfaces 364 may initiate and terminate at least offload remote direct memory access (RDMA) operations, non-volatile memory express (NVMe) operations, and LAN operations. The packet processing pipeline 366 may perform packet processing (e.g., packet headers and / or packet payload) based on configuration and support quality of service (QoS) and telemetry reporting. Inline processor 368 may perform offload encryption or decryption of packet communications (e.g., Internet Protocol Security (IPSec), or others). The traffic shaper 370 may plan the transmission of communications. The network interface 372 may provide an interface to at least one Ethernet network through media access control (MAC) and serializer / deserializer (Serdes) operations.The cores 382 may be configured to perform infrastructure operations, such as storage initiator, transport layer security (TLS) proxy, virtual switch (e.g., vSwitch), or other operations. The memory 384 may store applications and data to be performed or processed. Offload circuitry 386 may perform at least cryptographic operations and compression operations for the host or use by the computational complex 380. Offload circuitry 386 may include one or more graphics processing units (GPUs) that may access memory 384. The management complex 388 may perform secure booting, lifecycle management, and management of the network subsystem 360 and / or the computing complex 380.The management controller 390 may operate in a similar manner to that of the management controller 334.FIG. 4 illustrates an example network interface device or packet processing device. In some examples, the circuitry of the network interface device may be used as part of a network interface, such as for network interface devices described with reference to FIG. 3A or 3B. In some examples, the packet processing device 400 may be implemented as a network interface controller, a network interface card, a host fabric interface (HFI), or a host bus adapter (HBA), and such examples may be interchangeable. The packet processing device 400 may be coupled to one or more servers using a bus, PCIe, CXL, or dual data rate (DDR). The package processing device 400 may be implemented as part of a system-on-a-chip (SoC) that includes one or more processors, or may be included on a multi-chip package that also includes one or more processors.Some examples of the packet processing device 400 are part of an infrastructure processing unit (IPU) or a data processing unit (DPU) or are used by an IPU or DPU. An xPU may refer to at least one IPU, DPU, GPU, GPGPU, or other processing units (e.g., accelerator devices). An IPU or DPU may include a network interface with one or more programmable or fixed function processors for performing offloading operations that may have been performed by a CPU. The IPU or DPU may include one or more memory devices. In some examples, the IPU or DPU may perform virtual switching operations, manage storage transactions (e.g., compression, cryptography, virtualization), and manage operations performed on other IPUs, DPUs, servers, or devices.Network interface 400 may include transceiver 402, processors 404, transmit queue 406, receive queue 408, memory 410, and bus interface 412, and DMA engine 452. Transceiver 402 may be capable of receiving and transmitting packets in accordance with applicable protocols, such as Ethernet as described in IEEE 802.3, although other protocols may be used. The transceiver 402 may receive and transmit packets from and to a network over a network medium (not shown). The transceiver 402 may include PHY circuitry 414 and media access control (MAC) circuitry 416. PHY circuitry 414 may include encoding and decoding circuitry (not shown) for encoding and decoding data packets according to valid physical layer specifications or standards. The MAC circuitry 416 may be configured to assemble data to be transmitted into packets that include destination and source addresses along with network control information and error detection hash values.The processors 404 may be any combination of the following: processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that enables programming of the network interface 400. For example, a "smart network interface" may provide packet processing capabilities in the network interface using processors 404.The processors 404 may include one or more packet processing pipelines that may be configured to perform a matching action on received packets to identify packet processing rules and next hops using information stored in ternary content addressable memory (TCAM) tables or, in some embodiments, exact matching tables. For example, matching action tables or circuitry may be used whereby a hash of a portion of a packet is used as an index to find an entry. The packet processing pipelines may perform one or more of: packet parsing (parser), exact matching action (e.g., small exact exact exact match (SEM) engine or large exact match (LEM)), wildcard matching action (WCM), longest prefix matching block (LPM), hash block (e.g., receive side scaling (RSS)), packet modifier (modifier), or traffic manager (e.g., transmitter rate measurement or shaping). Packet processing pipelines may implement, for example, an Access Control List (ACL) or packet corruption due to queue overflow.The configuration of the operation of the processors 404, including their data plane, may be programmed based on one or more of the following: protocol-independent packet processors (P 4), software for open networking in the cloud (SONiC), Broadcom® network programming language (NPL), NVIDIA® CUDA® NVIDIA® DOCA™ infrastructure programmer development kit (IPDK), among others.A packet allocator 424 may provide a distribution of received packets for processing by multiple CPUs or cores using time slot allocation or RSS described herein. When the packet allocator 424 uses RSS, the packet allocator 424 may hash or otherwise make a determination based on contents of a received packet to determine which CPU or core is to process a packet.Interrupt coalescence 422 may perform interrupt mitigation, where network interface interrupt coalescence 422 waits for multiple packets to arrive or for a timeout to elapse before generating an interrupt to the host system to process one or more received packets. Receive segment coalescing (RSC) may be performed by network interface 400, thereby combining portions of incoming packets into segments of a packet. Network interface 400 provides this coalesced packet to an application.The direct memory access (DMA) engine 452 may copy a packet header, packet payload, and / or descriptor directly from the host memory to the network interface, or vice versa, rather than copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the target buffer.The memory 410 may be any type of volatile or non-volatile memory device and may store any queue or instructions used to program the network interface 400. The transmit queue 406 may include data or references to data for transmission through the network interface. The receive queue 408 may include data or references to data received from a network by the network interface. Descriptor queues 420 may include descriptors referencing data or packets in transmit queue 406 or receive queue 408. Bus interface 412 may provide an interface with the host device (not shown). For example, the bus interface 412 may be compatible with the PCI, PCI Express, PCI-x, serial ATA, and / or USB compatible interface (although other connection standards may be used).FIG. 5 illustrates a system. For example, host 110 may utilize circuitry and / or software of system 500. The system 500 includes a processor 510 that provides processing, operation management, and execution of instructions to the system 500. Processor 510 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), XPU, processing core, or other processing hardware for providing processing to system 500, or a combination of processors. An XPU may include one or more of the following: a CPU, a graphics processing unit (GPU), a general purpose GPU (GPGPU), and / or other processing units (e.g., accelerators or programmable or fixed function FPGAs). Processor 510 controls the overall operation of system 500 and may be or include one or more general purpose or special purpose programmable microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.In one example, system 500 includes an interface 512 coupled to processor 510, which may represent a higher speed interface or a high throughput interface for system components that require higher bandwidth connections, such as storage subsystem 520 or graphics interface components 540 or accelerators 542. The interface 512 represents an interface circuit, which may be a stand-alone component or may be integrated on a processor die. Where present, the graphics interface 540 is associated with graphics components to provide a visual display to a user of the system 500. In one example, the graphics interface 540 may drive a display that provides output to a user. In an example, the display may include a touch screen display. In an example, the graphics interface 540 generates a display based on data stored in the memory 530, or based on operations performed by the processor 510, or both. In an example, the graphics interface 540 generates a display based on data stored in the memory 530, or based on operations performed by the processor 510, or both.Accelerators 542 may be a programmable or fixed function offload engine that may be accessed or used by a processor 510. An accelerator among the accelerators 542 may provide, for example, data compression (DC) capability, cryptography services such as public key encryption (PKE), encryption, hash / authentication capabilities, decryption, or other capabilities or services. In some cases, accelerators 542 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). Accelerators 542 may include, for example, a single or multi-core processor, a graphics processing unit, a single or multi-level cache of a logical execution unit, functional units that may be used to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs). The accelerators 542 may provide multiple neural networks, CPUs, processor cores, general purpose graphics processing units, or graphics processing units, which may be provided for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI model may use or include one or a combination of: an intensifying learning scheme, Q learning scheme, deep Q learning or asynchronous advanced actor-critic (A3C), combinatorial neural network, recurrent combinatorial neural network, or another AI or ML model. Multiple neural networks, processor cores, or graphics processing units may be provided for use by AI or ML models to perform learning and / or inferencing operations.Storage subsystem 520 represents main memory of system 500 and provides storage for code to be executed by processor 510 or for data values to be used in executing a routine. The storage subsystem 520 may include one or more storage devices 530, such as read only memory (ROM), flash memory, one or more pluralities of random access memory (RAM), such as DRAM, or other storage devices, or a combination of such devices. The memory 530 stores and hosts, among other things, the operating system (OS) 532 to provide a software platform for executing instructions in the system 500. Additionally, applications 534 may be executed on the software platform of OS 532 from memory 530. Applications 534 represent programs that have their own operational logic for performing execution of one or more functions. Processes 536 represent agents or routines that provide auxiliary functions to OS 532 or one or more applications 534 or a combination. OS 532, applications 534, and processes 536 provide software logic to provide functions to system 500. In one example, storage subsystem 520 includes a storage controller 522, which is a storage controller for generating and issuing commands to memory 530. It should be appreciated that the memory controller 522 could be a physical portion of the processor 510 or a physical portion of the interface 512. For example, the memory controller 522 may be an integrated memory controller integrated into a circuit with the processor 510.Applications 534 and / or processes 536 may instead or additionally reference a virtual machine (VM), container, microservice, processor, or other software. Various examples described herein may execute an application composed of microservices, wherein a microservice is executed in its own process, and communicated by using protocols (e.g., application program interface (API), hypertext transfer protocol (HTTP) resource API, message service, remote procedure calls (RPC), or google RPC (gRP)). Microservices may communicate with each other using a service mesh and may be executed in one or more data centers or edge networks. By central management of these services, microservices can be used independently. The management system may be written in different programming languages and use different data storage technologies. A microservice may be characterized by one or more of: polyglot programming (e.g., code written in multiple languages to detect additional functionality and efficiency not available in a single language), or lightweight container or virtual machine deployment and decentralized continuous microservice delivery.In some examples, the OS 532 may be Linux® Windows® server or personal computer, FreeBSD® Android® MacOS® iOS® VMware vSphere, openSUS, RHEL, CentOS, Debian, Ubuntu, or any other operating system. The OS and driver may be executed on a processor sold or designed by, among others, Intel® ARM® AMD® Qualcomm® IBM® Nvidia® Broadcom® Texas Instruments®.Although not specifically illustrated, it should be appreciated that system 500 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines may communicatively or electrically couple components together or both communicatively and electrically couple the components. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers or other circuitry, or a combination. Buses may include, for example, a system bus and / or a Peripheral Component Interconnect (PCI) bus and / or a Hyper Transport or Industry Standard Architecture (ISA) bus and / or a Small Computer System Interface (SCSI) bus and / or a Universal Serial Bus (USB) and / or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).In one example, system 500 includes an interface 514 that can be coupled to interface 512. In one example, interface 514 represents an interface circuit that may include stand-alone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 514. Network interface 550 provides system 500 with the ability to communicate with remote devices (e.g., servers or other computing devices) via one or more networks. The network interface 550 may include an Ethernet adapter, wireless connection components, cellular network connection components, Universal Serial Bus (USB), or other wired or wireless standard-based or proprietary interfaces. The network interface 550 may transmit data to a device located in the same data center or rack or a remote device, which may include sending data stored in memory. The network interface 550 may receive data from a remote device, which may include storing received data in memory. In some examples, the packet processing device or network interface device 550 may refer to one or more of: a network interface controller (NIC), a remote direct memory access (RDMA) enabled NIC, smartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU). An example IPU or DPU is described with reference to FIGS. 3A, 3B, or 4.In some examples, operations of the management controller 544 may be configured by the arbitration circuitry 552, as described herein. For example, the management controller 544 may store an encrypted device identifier and provide the device identifier to arbitration circuitry (not shown) to authenticate the management controller 544. The management controller 544 may receive a signal from the arbitration circuitry 552 indicating that the management controller 544 is a primary or secondary management controller. The management controller 544 may receive a configuration of operations to be performed from the arbitration circuitry 552, and the management controller 544 may perform operations according to the received configuration.In an example, the system 500 includes one or more input / output (I / O) interfaces 560. I / O interface 560 may include one or more interface components through which a user interacts with system 500. The peripheral interface 570 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that establish a dependent connection to system 500.In one example, the system 500 includes a storage subsystem 580 for storing data in a non-volatile manner. In one example, in certain system implementations, at least certain components of storage 580 may overlap with components of storage subsystem 520. Storage subsystem 580 includes one or more storage devices 584, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical disks, or a combination thereof. The storage 584 maintains code or instructions and data 586 in a persistent state (e.g., the value is maintained despite suspension of power to the system 500). Storage 584 may be generally considered a "memory," although memory 530 is typically the execution or operational memory to provide instructions to processor 510. Whereas the storage 584 is non-volatile, the memory 530 may include volatile memory (e.g., the value or state of the data is indeterminate if power to the system 500 is interrupted). In one example, storage subsystem 580 includes a controller 582 to interface with storage 584. In one example, the controller 582 is a physical part of the interface 514 or the processor 510, or may include circuitry or logic in both the processor 510 and the interface 514.Volatile memory is a memory whose state (and hence the data stored therein) is indeterminate if power to the device is interrupted. A nonvolatile memory (NVM) device is a memory whose state is determined even when power supply to the device is cut off.In an example, system 500 may be implemented using interconnected computing sleds of processors, memories, memories, network interfaces, and other components. High speed interconnects may be used, such as: Ethernet (IEEE 802.3), RDMA (Remote Direct Memory Access), InfiniBand, iWAR (Internet Wide Area RDMA Protocol), TCP (Transmission Control Protocol), UDP (User Datagram Protocol), QUIC (Quick UDP Internet Connections), RoCE (RDMA over Converged Ethernet), PCIe (Peripheral Component Interconnect Express), Intel QPI (QuickPath Interconnect), Intel UPI (UltraPath Interconnect), IOSF (Intel On-Chip System Fabric), Omnipath, CXL (Compute Express Link), HyperTransport, High Speed Fabric, NVLink, AMBA (Advanced Microcontroller Bus Architecture) Interconnect, OpenCAPI, Gen-Z, Integrity Fabric (IF), CCIX (Cache Coherent Interconnect for Accelerators), 3GPP LTE (Long Term Evolution) (4G), 3GPP-5G, and variations thereof. Data may be copied or stored in virtualized storage nodes or accessible using a protocol such as NVMe over Fabrics (NVMe-oF) or NVMe (e.g., a non-volatile memory express (NVMe) device may operate in a manner consistent with the non-volatile memory express (NVMe) specification, revision 1.3c, published May 24, 2018 ("NVMe-Special i cation"), as well as earlier versions, later versions, and variations thereof).Communications between devices may occur using a network that provides die-to-die communications; chip-to-chip communications; circuit board-to-circuit board communications; and / or package-to-package communications.In an example, system 500 may be implemented using interconnected computing sleds of processors, memories, memories, network interfaces, and other components. High speed interconnects may be used, such as PCIe, Ethernet, or optical interconnects (or a combination thereof).Examples herein may be implemented in various types of computing and networking devices, such as switches, routers, racks, and blade servers, such as those deployed in a data center and / or server farm environment. The servers used in data centers and server farm include queued server configurations, such as rack-based servers or blade servers. These servers are in communication with each other via various network provisions, such as partition sets of servers in local area networks (LANs) with appropriate switching and routing facilities between the LANs to form a private intranet. For example, cloud hosting devices may typically employ large data centers with a plurality of servers. A blade includes a separate computing platform configured to perform server-type functions, i.e., a "server-on-a-card", Accordingly, a blade includes components common to conventional servers, including a main circuit board (motherboard) that provides internal wirings (e.g., buses) for coupling suitable integrated circuits (ICs) and other components mounted on the board.Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and / or software elements may vary according to any number of factors, such as a desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation. A processor may be one or more combinations of a hardware state machine, digital control logic, central processing unit, or any hardware, firmware, and / or software elements.Some examples may be implemented using or as an article of manufacture or at least one computer readable medium. A computer readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer readable storage media that can store electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.According to some examples, a computer readable medium may include a non-transitory storage medium for storing or holding instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predetermined computer language, type, or syntax to direct a machine, computing device, or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium representing various logic within the processor, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the manufacturing machines that actually manufacture the logic or processor.The occurrence at multiple places of the phrase "an example" does not necessarily all refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with reference to the same figure or element. Division, omission, or inclusion of block functions shown in the accompanying figures does not mean that the hardware components, circuits, software, and / or elements for implementing these functions necessarily need to be divided, omitted, or included in embodiments.Some examples may be described using the term "coupled" and "connected" along with their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.The terms "first", "second", and the like herein do not denote order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" and "an" herein do not denote a limitation of quantity, but rather the presence of at least one of the stated elements. The term "asserted" as used herein with respect to a signal refers to a state of the signal in which the signal is active and which can be achieved by applying any logic level of either logic 0 or logic 1 to the signal. The terms "follow" or "after" may mean immediately following or following one or more other event(s). Other sequences of operations may also be performed according to alternative embodiments. Moreover, additional operations may be added or removed depending on the respective applications. Any combination of changes may be used, and one of ordinary skill in the art having the benefit of this disclosure would understand the many variations, modifications, and alternative embodiments thereof.Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood in the context, unless specifically stated otherwise, as generally used to represent that an element, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Therefore, such disjunction language is generally not intended to imply that certain embodiments require that at least one of X, at least one of Y, or at least one of Z be present. In addition, unless expressly stated otherwise, conjunctival language such as the phrase "at least one of X, Y, and Z" should also be understood to mean X, Y, Z, or any combination thereof, including "X, Y, and / or Z".Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An embodiment of the devices, systems, and methods may include any one or more and any combination of the examples described below.Example 1 includes one or more examples, and includes an apparatus comprising: an interface; and circuitry coupled to the interface, the circuitry, in operation, to: based on detection of a plurality of management controllers, select a primary management controller and a secondary management controller from the plurality of management controllers, wherein: the primary management controller is to perform at least one operation different than that of the secondary management controller, the primary management controller comprises a base board management controller (BMC), the secondary management controller comprises a BMC, and the plurality of management controllers are positioned in at least one programmable network interface device and a host system.Example 2 includes one or more examples, wherein the host system comprises a management controller among the plurality of management controllers, and wherein the circuitry is to provide a signal to the host system that the management controller of the host system is the primary management controller.Example 3 includes one or more examples, wherein the programmable network interface device comprises a management controller among the plurality of management controllers, and wherein the circuitry is to provide a signal to the programmable network interface device that the management controller of the programmable network interface device is the primary management controller.Example 4 includes one or more examples, wherein the primary management controller is to perform at least one operation other than the secondary management controller comprises prohibiting the secondary management controller from issuing a command that is also issued by the primary management controller.Example 5 includes one or more examples, wherein the primary management controller is to perform at least one operation other than the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.Example 6 includes one or more examples, wherein the primary management controller is to perform at least one operation other than the secondary management controller comprises allowing the primary management controller and the secondary management controller to issue certain commands and forward the issued certain commands from the primary management controller to a target device, but not forward certain commands from the second management controller to the target device.Example 7 includes one or more examples, wherein the circuitry is to authenticate the plurality of management controllers, and based on the authentication of the plurality of management controllers, the circuitry is to select the primary management controller and the secondary management controller.Example 8 includes one or more examples, wherein the primary management controller is to perform one or more of: configure the operating frequency of cores of a host system and at least one network interface device, power management of the host system and the at least one network interface device, memory management of the host system and the at least one network interface device, control of platform updates of the host system and the at least one network interface device, or control of firmware updates of the host system and the at least one network interface device.Example 9 includes one or more examples, and includes the host system comprising at least one core and a management controller of the plurality of management controllers and the at least one programmable network interface device communicatively coupled to the host system via at least one host interface, wherein the at least one programmable network interface device comprises a management controller of the plurality of management controllers, a direct memory access (DMA) circuitry, and a network interface.Example 10 includes one or more examples, wherein the circuitry is positioned in a host system or in a server in a data center.Example 11 includes one or more examples, and includes a non-transitory computer-readable medium comprising instructions stored thereon that, when executed by one or more processors, cause the one or more processors to: determine whether one or more management controllers are operating in a platform; based on a determination that one management controller is operating in the platform, permit outputs from the one management controller; and based on a determination that multiple management controllers are operating in the platform, select a primary management controller and a secondary management controller from the multiple management controllers, and permit at least one output from the primary management controller but prohibit at least one output from the secondary management controller.Example 12 includes one or more examples, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises resolving conflicts between commands from the primary management controller and the secondary management controller.Example 13 includes one or more examples, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.Example 14 includes one or more examples, wherein the primary management controller and the secondary management controller are to provide at least one different command.Example 15 includes one or more examples and includes instructions stored thereon that, when executed by one or more processors, cause the one or more processors to: authenticate the plurality of management controllers and, based on the authentication of the plurality of management controllers, select the primary management controller and the secondary management controller.Example 16 includes one or more examples, and includes a method including: determining whether one or more management controllers are operating in a platform; based on a determination that one management controller is operating in the platform, permitting outputs from the one management controller; and based on a determination that multiple management controllers are operating in the platform, selecting a primary management controller and a secondary management controller from the multiple management controllers, and permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller.Example 17 includes one or more examples, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises resolving conflicts between commands from the primary management controller and the secondary management controller.Example 18 includes one or more examples, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.Example 19 includes one or more examples, wherein the primary management controller and the secondary management controller are to provide at least one different command.Example 20 includes one or more examples, and includes alerting the plurality of management controllers and, based on the alerting of the plurality of management controllers, selecting the primary management controller and the secondary management controller.

Claims

An apparatus comprising: an interface; and circuitry coupled to the interface, wherein the circuitry is operative to: based on detection of a plurality of management controllers, select a primary management controller and a secondary management controller from the plurality of management controllers, wherein: the primary management controller is to perform at least one operation different from that of the secondary management controller, the primary management controller comprises a base board management controller (BMC), the secondary management controller comprises a second BMC, and the plurality of management controllers are positioned in at least one programmable network interface device and a host system.The apparatus of claim 1, wherein the host system comprises a management controller among the plurality of management controllers, and wherein the circuitry is to provide a signal to the host system that the management controller of the host system is the primary management controller.The apparatus of claim 1, wherein the at least one programmable network interface device comprises a management controller among the plurality of management controllers, and wherein the circuitry is to provide a signal to the at least one programmable network interface device that the management controller of the at least one programmable network interface device is the primary management controller.The apparatus of claim 1, wherein the at least one operation other than that of the secondary management controller comprises prohibiting the secondary management controller from issuing a command that is also issued by the primary management controller.The apparatus of claim 1, wherein the at least one operation other than that of the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.The apparatus of claim 1, wherein the at least one operation other than that of the secondary management controller comprises allowing the primary management controller and the secondary management controller to issue certain commands and forward the issued certain commands from the primary management controller to a target device, but not to forward certain commands from the second management controller to the target device.The apparatus of claim 1, wherein the circuitry is to authenticate the plurality of management controllers, and based on the authentication of the plurality of management controllers, the circuitry is to select the primary management controller and the secondary management controller.The apparatus of claim 1, comprising: the host system comprising at least one core and a management controller of the plurality of management controllers, and the at least one programmable network interface device communicatively coupled to the host system via at least one host interface, wherein the at least one programmable network interface device comprises a management controller of the plurality of management controllers, a direct memory access (DMA) circuitry, and a network interface.The apparatus of claim 1, wherein the circuitry is positioned in a host system or in a server in a data center.The apparatus of any of claims 1-9, wherein the primary management controller is to perform one or more of: configuring the operating frequency of cores of a host system and at least one network interface device, power management of the host system and the at least one network interface device, memory management of the host system and the at least one network interface device, control of platform updates of the host system and the at least one network interface device, or control of firmware updates of the host system and the at least one network interface device.A non-transitory computer readable medium or media comprising instructions stored thereon that, when executed by one or more processors, cause the one or more processors to: determine whether one or more management controllers are operating in a platform; based on a determination that one management controller is operating in the platform, permit outputs from the one management controller; and based on a determination that multiple management controllers are operating in the platform, select a primary management controller and a secondary management controller from the multiple management controllers, and permit at least one output from the primary management controller but prohibit at least one output from the secondary management controller.The non-transitory computer readable medium of claim 11, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises resolving conflicts between instructions from the primary management controller and the secondary management controller.The non-transitory computer readable medium of claim 11, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.The non-transitory computer readable medium of claim 11, comprising instructions stored thereon that, when executed by one or more processors, cause the one or more processors to: authenticate the plurality of management controllers and, based on the authentication of the plurality of management controllers, select the primary management controller and the secondary management controller.The non-transitory computer readable medium of any of claims 11-14, wherein the primary management controller and the secondary management controller are to provide at least one different command.A method comprising: determining whether one or more management controllers are operating in a platform; based on a determination that one management controller is operating in the platform, permitting outputs from the one management controller; and based on a determination that a plurality of management controllers are operating in the platform, selecting a primary management controller and a secondary management controller from the plurality of management controllers and permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller.The method of claim 16, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises resolving conflicts between commands from the primary management controller and the secondary management controller.The method of claim 16, wherein permitting at least one output from the primary management controller but prohibiting at least one output from the secondary management controller comprises prohibiting the secondary management controller from issuing at least one particular command.The method of claim 16, wherein the primary management controller and the secondary management controller are to provide at least one different command.The method of any of claims 16, comprising: alerting the plurality of management controllers and, based on the alerting of the plurality of management controllers, selecting the primary management controller and the secondary management controller.The method of any of claims 16-20, wherein the primary management controller is to perform one or more of: configuring the operating frequency of cores of a host system and at least one network interface device, power management of the host system and the at least one network interface device, memory management of the host system and the at least one network interface device, control of platform updates of the host system and the at least one network interface device, or control of firmware updates of the host system and the at least one network interface device.

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