ADAPTIVE ZERO-VOLTAGE SWITCHING FOR NEAR-FIELD COMMUNICATION

Abstract

Systems and methods for operating a wireless power transmission device are described. A circuit can generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter has dropped below ground. The circuit can delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit can combine the first and second signals to generate a third signal. A controller can use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specified time. Turning on the first LS transistor at the specified time reduces the diode conduction time of a body diode of the first LS transistor.

Description

BACKGROUND

[0001] The present disclosure generally relates to devices and methods for wireless power transmission devices. In particular, operating efficiency of a wireless power receiver can be improved by reducing diode conduction time.

[0002] Wireless power transfer using a near-field communication (NFC) protocol (e.g., NFC wireless power systems) may occur between two devices incorporating near-field communication (NFC) interfaces. Such NFC wireless power systems may include a bollard having a transmit coil and a receiver ("listener") having a receiver coil. In one aspect, the bollard may be connected to a structure incorporating a wireless charging area. In response to a device incorporating the receiver being placed near a device incorporating the bollard, the transmit coil and the receiver coil may be inductively coupled to establish an NFC communication link between the bollard and the receiver, and an inductive transfer of alternating current (AC) power may occur using the established NFC communication link.The transfer of AC power from the bollard to the receiver can facilitate charging of a battery of the device containing the receiver. SUMMARY

[0003] In one embodiment, a semiconductor device in a wireless power transmission device is generally described. The semiconductor device may include a controller, a switching converter, and a circuit. The switching converter may include a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor, and a second LS transistor. The circuit may be configured to generate a first signal indicating that a voltage at a node between the first HS transistor and the first LS transistor drops below ground. The circuit may be further configured to delay a gate-source voltage of the second LS transistor to generate a second signal. The circuit may be further configured to combine the first signal and the second signal to generate a third signal.The controller may be configured to use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at the specific time may reduce a diode conduction time of a body diode of the first LS transistor.

[0004] In one embodiment, a semiconductor device for a semiconductor device in a wireless power transmission device is generally described. The semiconductor device may include a comparator configured to generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falls below ground. The semiconductor device may further include a delay circuit configured to delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The semiconductor device may further include an OR gate configured to combine the first signal and the second signal to generate a third signal.The OR gate may be further configured to send the third signal to a controller to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at the specific time may reduce a diode conduction time of a body diode of the first LS transistor.

[0005] In one embodiment, a method for operating a wireless power transfer device is generally described. The method may include generating a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falls below ground. The method may further include delaying a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The method may further include combining the first signal and the second signal to generate a third signal. The method may further include using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specified time.Turning on the first LS transistor at the specific time can reduce a diode conduction time of a body diode of the first LS transistor.

[0006] Further features, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram illustrating an exemplary system that may implement adaptive zero-voltage switching for near-field communication in one embodiment. Fig. 2 is a diagram showing an exemplary circuit that can implement adaptive zero-voltage switching for near-field communication in one embodiment. Fig. 3 is a diagram showing waveforms of signals in an exemplary implementation of adaptive zero-voltage switching for near-field communication in one embodiment. Fig. 4 is a flowchart illustrating a process for implementing adaptive zero-voltage switching for near-field communication in one embodiment. DETAILED DESCRIPTION

[0007] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, one of ordinary skill in the art will recognize that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0008] NFC wireless power systems can provide charging in a static mode or a negotiated mode. Static mode can use a standard radio frequency (RF) field strength and provide a consistent power level, and negotiated mode can use a relatively higher RF field that supports various power transfer classes, such as 250, 500, 750, and 1000 milliwatts (mW). In NFC wireless power systems, the poller and receiver can communicate using NFC communication protocols. In one aspect, NFC wireless power systems can use a specific base frequency (e.g., 13.56 megahertz (MHz)) and utilize the NFC communication link between the two devices to control power transfer.To perform NFC communication, one device may apply or transmit a modulation signal, for example, an amplitude shift keying (ASK) signal, to the other device, and the other device may demodulate the modulation signal.

[0009] Fig. 1 is a diagram illustrating an exemplary system that may implement adaptive zero-voltage switching for near-field communication in one embodiment. System 100 may include power devices, such as a transmitter 110 and a receiver 120, configured to wirelessly transmit power and data therebetween via inductive coupling. Although described herein as transmitter 110 and receiver 120, both transmitter 110 and receiver 120 may be configured to both transmit and receive power or data therebetween via inductive coupling. Transmitter 110 may be referred to as a wireless power transmitter, and receiver 120 may be referred to as a wireless power receiver. In an embodiment where system 100 is configured as an NFC wireless power system, transmitter 110 may be configured as a poller, and receiver 120 may be configured as a listener.The transmitter 110 and the receiver 120 may include various types of circuit components, such as integrated circuits (ICs), which may be semiconductor devices made of semiconductor materials.

[0010] The transmitter 110 is configured to receive power from one or more power supplies and wirelessly transmit AC power to the receiver 120. For example, the transmitter 110 may be configured to connect to a power supply 116, such as an adapter or a DC power supply. The transmitter 110 may be a semiconductor device including a controller 112, a resonant circuit 113, and a switching converter 114. The switching converter 114 may be an integrated circuit (IC) that may be part of a power driver configured to convert one type of electrical current to another type of electrical current. For example, the switching converter 114 may be configured as an inverter to convert a DC signal to an AC signal.

[0011] The controller 112 may be configured to control and operate the switching converter 114 and other components of the transmitter 110. The controller 112 may include, for example, a processor, a central processing unit (CPU), a field-programmable gate array (FPGA), or any other circuit configured to control and operate the switching converter 114. Although described as a CPU in illustrative embodiments, the controller 112 in these embodiments is not limited to a CPU and may include any other circuit configured to control and operate the switching converter 114. In one exemplary embodiment, the controller 112 may be configured to control the switching converter 114 to drive the resonant circuit 113 to generate a magnetic field.The switching converter 114 can drive the coil TX in a range of frequencies and configurations defined by wireless performance standards, such as the NFC Forum's wireless charging (WLC) specifications. The resonant circuit 113 can include a coil TX and one or more capacitors, inductors, and resistors, which can form a circuit for outputting various signals and transmitting AC power 130 to the receiver 120.

[0012] The receiver 120 may be configured to receive AC power 130 transmitted from the transmitter 110 and to supply the power to one or more loads, such as a load 126 or other components of a target device that includes the receiver 120. The load 126 may include, for example, a battery charger configured to charge a battery, a DC-DC converter configured to supply DC power 132 to a processor, a display or other electronic components of the target device 140, or any other load of the target device 140. A target device may include the receiver 120 and may be, for example, a computing device, a smart device, a wearable device, or any other electronic device configured to receive power wirelessly.In other embodiments, the receiver 120 may be separate from a target device and connected to the target device via a wire or other component configured to provide power to the target device 140.

[0013] The receiver 120 may be a semiconductor device including a controller 122, a resonant circuit 123, a switching converter 124, and a circuit 150. In one embodiment, the circuit 150 may be an IC, such as a semiconductor device made of semiconductor materials. The controller 122 may be an integrated circuit, including, for example, a digital controller such as a microcontroller, a processor, a CPU, an FPGA, or any other circuit configured to control and operate the switching converter 124. The resonant circuit 123 may include a coil RX and one or more capacitors, inductors, and resistors that may form a circuit for receiving AC power 130 and outputting communication packets 136. The switching converter 124 may be an IC configured to convert one type of electrical power to another type of electrical power.For example, switching converter 124 may be configured as a power rectifier to convert an AC signal into a DC signal. When configured as a power rectifier, switching power converter 124 may include a rectifier circuit, such as a half-bridge rectifier, full-bridge rectifier, or other types of rectifier circuits, which may be configured to rectify power received via resonant coil RX of resonant circuit 123 into a power type required by load 126.

[0014] For example, when the receiver 120 is placed near the transmitter 110, the magnetic field generated by the coil TX of the resonant circuit 113 and the switching converter 114 induces a current in the coil RX of the resonant circuit 123. The induced current causes AC power 130 to be inductively transmitted to the switching converter 124 via the resonant circuit 123. The switching converter 124 receives AC power 130 and converts AC power 130 to DC power 132 for the load 126.

[0015] The transmitter 110 and the receiver 120 are also configured to exchange information or data, e.g., messages, via the inductive coupling of the power driver 106 and the resonant circuits 113 and 123. For example, before the transmitter 110 begins transmitting power to the receiver 120, a power contract may be agreed upon and created between the receiver 120 and the transmitter 110. For example, the receiver 120 may send communication packets 136 to the transmitter 110 using ASK signals indicating power transfer information, such as, for example, an amount of power to be transferred to the receiver 120, commands to increase, decrease, or maintain a power level of the AC power 130, commands to stop a power transfer, or other power transfer information.In another example, in response to the receiver 120 being brought into proximity with the transmitter 110, e.g., close enough so that a transformer can be formed by the coil TX and the coil RX to enable power transfer, the receiver 120 may be configured to initiate communication by sending a signal to the transmitter 110 requesting a power transfer. In such a case, the transmitter 110 may respond to the request by the receiver 120 by establishing the power contract or initiating a power transfer to the receiver 120, e.g., if the power contract already exists. The transmitter 110 and the receiver 120 may send and receive ASK signals, data, or other information via the inductive coupling of the coil TX and the coil RX.

[0016] As in Fig. As shown in Figure 1, the switching converter 124 may be formed by two half-bridge circuits comprising two high-side metal-oxide-semiconductor field-effect transistors (MOSFETs) HS1, HS2 and two low-side MOSFETs LS1, LS2. The MOSFETs HS1 and LS2 may turn on and off simultaneously, and the MOSFETs HS2 and LS1 may turn on and off simultaneously. The pair HS1, LS2 and the pair HS2, LS1 may be alternately switched to rectify AC power 130 into DC power 132. The alternate switching may cause current to flow alternately from node AC1 to AC2 and vice versa. When HS2 and LS1 are turned on, current may flow from AC1 to AC2; during this phase, the AC1 voltage will become low, while the AC2 voltage will be high. When HS1 and LS2 are switched on, current can flow from AC2 to AC1, during this phase the AC2 voltage will become low while the AC1 voltage will be high.

[0017] Maximizing operating efficiency is an important aspect of wireless charging. Beyond environmental impacts, operating efficiency affects the power density and charging time of the portable device. In one aspect, some receivers may use Schottky diodes to rectify the received AC power, but Schottky diodes can have a large forward voltage drop and may limit the receiver to less than 80% efficiency. Some receivers may implement active rectifiers using low RDS(on) transistors, but active rectifiers may require precise control of the MOSFETs while accommodating the high frequency of the AC signals (e.g., in the range of 13.56 MHz).

[0018] In one aspect, when the switching converter 124 detects current flowing through a diagonal (e.g., either LS1-HS2 or LS2-HS1), the corresponding MOSFETs are driven ON, providing a low-loss current path. However, there is a delay in turning on the corresponding MOSFETs in the diagonal. During this delay, the current path may pass through the body diode of MOSFETs, causing a diode forward voltage drop. The diode forward voltage drop may cause an increase in losses, thereby increasing heat and reducing operating efficiency. In one aspect, if the delay causes a diode conduction time of more than 3 nanoseconds (ns), then the receiver experiences an efficiency loss of more than 0.7%.

[0019] To improve efficiency of receiver 120, receiver 120 may include at least one circuit 150 that may be configured to perform zero voltage switching (ZVS) control. ZVS control may include monitoring the case where voltages at nodes AC1 and / or AC2 cross zero voltage (e.g., go below zero or below ground) and performing one or more tasks to control other aspects of receiver 120 in response to the voltages crossing zero voltage. In one aspect, ZVS control may include one or more circuits configured to perform one or more of the following tasks: In one embodiment, circuit 150 may monitor low-side MOSFETs LS1, LS2 and reduce the diode conduction time when MOSFETs LS1 and LS2 are turned on.One copy of circuit 150 may be connected across LS1, and another copy of circuit 150 may be connected across LS2. In one embodiment, circuit 150 may measure a voltage across a MOSFET, such as LS1 or LS2, and, based on the measured voltage, reduce the diode conduction time of the MOSFET by anticipating the rising edge of the MOSFET's gate-source voltages (Vgs). The reduced diode conduction time may also result in a reduction in electromagnetic interference (EMI).

[0020] Fig. Figure 2 is a diagram showing an exemplary circuit that can implement adaptive zero-voltage switching for near-field communication in one embodiment. Descriptions of Fig. 2 may refer to components that are Fig. 1. The Fig. The embodiment shown in Figure 2 may be an implementation of the circuit 150 for monitoring LS1 and reducing the diode conduction time of a body diode 200 of LS1. The implementation of the circuit shown in Fig. 2 shown circuit 150 can also be applied to LS2 of the switching converter 124 in Fig. 1. In one embodiment, the circuit 150 may be implemented using the Fig. 2 shown components must be implemented. In the Fig. 2, the circuit 150 may include a comparator 202, a delay circuit 206, a delay circuit 208, an OR gate 210, an arbiter 212, a filter 214, and a counter 216.

[0021] Inputs of the comparator 202 may be connected via a low-side MOSFET in the switching converter 124, such as LS1 or LS2 (LS1 in Fig. 2). Comparator 202 may monitor the voltage at node AC1. A gate-source voltage VGS_LS1 may be applied to the gate of LS1. When VGS_LS1 is greater than a threshold voltage of LS1, LS1 may be turned on. When LS1 is turned on, current may flow through LS1 and the voltage at node AC1 may become low. A voltage output by comparator 202, referred to as comparator output 204 or on1_comp signal, may indicate whether the voltage at node AC1 is above ground or below ground (e.g., above zero or below zero).

[0022] Circuit 150 may receive gate-source voltages from LS1 (VGS_LS1) and gate-source voltages from LS2 (VGS_LS2). A delay circuit 206 may apply a delay (e.g., a fine-tuned delay) to VGS_LS1. Delay circuit 206 may output a delayed VGS_LS1, denoted as signal 207. In one embodiment, the delay applied by delay circuit 206 may be predefined and fixed and may be equivalent to the propagation delay of comparator 202. A delay circuit 208 may apply a programmable delay to the falling edge of VGS_LS2, where the programmable delay may be dependent on a delay signal 217. Delay circuit 208 may output a delayed version of the falling edge of VGS_LS2, denoted as signal 209.

[0023] Arbiter 212 may be configured to check the order of arrival of the VGS_LS1 signals and the comparator output 204 (or on1_comp) cycle by cycle. If on1_comp arrives at the r1 input of arbiter 212 before VGS_LS1 arrives at the r2 input of arbiter 212, then arbiter 212 may output a g1 signal. If VGS_LS1 arrives at the r2 input of arbiter 212 before on1_comp arrives at the r1 input of arbiter 212, then arbiter 212 may output a g2 signal.

[0024] The filter 214 may be a digital filter configured to filter noise from the output of the arbiter 212 and may also check whether either g1 or g2 is output by the arbiter 212 for more than one consecutive cycle. If g1 is output by the arbiter 212 for more than one cycle, then the counter 216 may count down by decrementing the delay signal 217. If g2 is output by the arbiter 212 for more than one cycle, then the counter 216 may count up by incrementing the delay signal 217. The delay signal 217 may be applied to the delay circuit 208 to adjust the delay applied to the falling edge of VGS_LS2. In one embodiment, the system (e.g.,Receiver 120) may eventually reach a stable state and the counter 216 may stop counting or alternately increment and decrement the delay signal 217 to maintain the delay signal 217.

[0025] OR gate 210 may receive comparator output 204 and signal 209. OR gate 210 may combine or combine comparator output 204 and signal 209. Controller 122 may receive the ON1 output from OR gate 210. ON1, which is a high voltage (e.g., binary one), may trigger a rising edge of a command signal 219 output by controller 122. Driver 220 may receive command signal 219 and turn on LS1 by applying VGS_LS1 to the gate of LS1 (e.g., VGS_LS1 goes high). When LS1 is turned on, body diode 200 may be rectified, ending the diode conduction time.

[0026] In one aspect, when circuit 150 is deactivated or the applied delay is too long (e.g., after power-up, when the system has not yet reached steady state), comparator 202 may provide comparator output 204 directly to controller 122 to trigger controller 122 to control driver 220 to turn on LS1. Propagation delays in comparator 202, controller 122, and driver 220 may contribute to the diode conduction time of body diode 200 of LS1. Activation of circuit 150 may anticipate a turn-on time of LS1 and turn on LS1 earlier than when circuit 150 is deactivated. The earlier turn-on time may reduce the diode conduction time of body diode 200 in LS1.

[0027] In one embodiment, the ON1 signal generated based on the delay-applied delay circuit 208 and output from the OR gate 210 may replace the comparator output 204 (on1_comp) to trigger the rising edge of the command signal 219 at an earlier time compared to using on1_comp to trigger the rising edge of the command signal 219 (or when the circuit 150 is disabled). Triggering the rising edge of the command signal 219 earlier to turn on LS1 may align the timing of the rising edge of the on1_comp signal with the VGS_LS1 signal.

[0028] Furthermore, the use of arbiter 212 and counter 216, and optionally filter 214, can provide adaptive compensation for transmission delays and precise control of the alignment of the on1_comp signal and the VGS_LS1 signal. For example, if the on1_comp signal lags the VGS_LS1 signal, then signal 207 may arrive at arbiter 212 earlier than comparator output 204. Arbiter 212 may output g2 to trigger counter 216 to increment delay signal 217 to increase the programmable delay applied by delay circuit 208. The increased delay applied by delay circuit 208 may delay the VGS_LS1 signal to align VGS_LS1 with the lagging on1_comp signal. If the VGS_LS1 signal lags the on1_comp signal, then the comparator output 204 may arrive at the arbiter 212 earlier than the signal 207.Arbiter 212 may output g1 to trigger counter 216 to decrement delay signal 217 to reduce the programmable delay applied by delay circuit 208. The reduced delay applied by delay circuit 208 may trigger the rising edge of the VGS_LS1 signal earlier to align the lagging VGS_LS1 with the on1_comp signal. The adaptive alignment may maintain the reduced diode conduction time of body diode 200 and result in an improvement in the efficiency of receiver 120.

[0029] Fig. Figure 3 is a diagram showing waveforms of signals in an exemplary implementation of adaptive zero-voltage switching for near-field communication in one embodiment. Descriptions of Fig. 3 may refer to components that are in Fig. 1 and Fig. 2. A variety of waveforms of different signals in an implementation of the circuit 150 are shown in Fig. 3. In the Fig. 3, the voltage at node AC1 may begin to drop below ground at approximately time t1. A propagation delay of comparator 202 may cause comparator 202 to raise the on1_comp signal to a high voltage at approximately time t3. The descriptions of Fig. 3, which relate to the exemplary implementation of the circuit 150 for LS1, may also be applicable to the implementation of the circuit 150 for LS2.

[0030] A waveform of the signal 209 output from the delay circuit 208 is also shown in Fig. 3. The rising edge of signal 209 is a delayed version of the falling edge of VGS_LS2. Signal 209 remains high for a fixed period of time sufficient to be latched by controller 122. When delay signal 217 increases the delay applied by delay circuit 208, the rising edge of signal 209 is delayed for a longer time. When delay signal 217 decreases the delay applied by delay circuit 208, signal 209 is delayed for a shorter time.

[0031] With reference to Fig. 2, since signal 209 and on1_comp are input to OR gate 210, the output of OR gate 210 or the ON1 signal may be high in response to either one or both of signal 209 and on1_comp being high. Signal 209 and on1_comp may be combined by OR gate 210, and the rising edge of the ON1 signal may be triggered relatively earlier to compensate for the transmission delay in controller 122 and driver 220. As shown in Fig. As shown in Figure 3, when signal 209 is high and on1_comp remains low, command signal 219 output by controller 122 also goes high because OR gate 210 outputs ON1 as a high voltage. Therefore, signal 209 can trigger the rising edge of command signal 219 to begin turning on LS1 before the rising edge of the on1_comp signal. After the propagation delay of driver 220, VGS_LS1 can begin rising to turn on LS1 at approximately time t2.

[0032] At time t3, the on1_comp signal may rise and VGS_LS1 may exceed the threshold voltage Vth of LS1, causing LS1 to fully turn on and the diode conduction time of the body diode 200 in LS1 to end. The diode conduction time may begin at t1 and end at t3, which is the difference between the transfer time of comparator 202 (e.g., from the voltage at AC1 going below ground to the rising edge of on1_comp) and the delay applied by circuit 206. Thus, the example in Fig. 3 shows an implementation of circuit 150 in which the transmission delay in controller 122 and driver 220 is eliminated, greatly reducing the transmission delay of 202.

[0033] In one embodiment, if the on1_comp signal rises later than t3, then the on1_comp signal lags the VGS_LS1 signal, and circuit 150 may increase the delay applied by delay circuit 208 to increase the delay of the rising edge of signal 209. In one embodiment, if the on1_comp signal rises earlier than t3, then the VGS_LS1 signal lags the on1_comp signal, and circuit 150 may decrease the delay applied by delay circuit 208 to decrease the delay of the rising edge of signal 209. In one embodiment, a reduction of approximately 300 picoseconds (ps) may result in an operating efficiency improvement of more than 0.7%.

[0034] Fig.Figure 4 is a flowchart illustrating a process for implementing adaptive zero-voltage switching for near-field communication in one embodiment. The process may include one or more operations, actions, or functions, as illustrated by one or more of blocks 402, 404, 406, and / or 408. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0035] The process 400 may be implemented by a wireless power transmission device (e.g., a receiver or a transceiver, such as the receiver 120 described herein). The process 400 may begin at block 402, where a circuit may generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falls below ground. In one embodiment, the switching converter may be located in a receiver ("listener") of a near-field communication (NFC) power transmission system. In one embodiment, a rising edge of a gate-source voltage of the first LS transistor is aligned with a rising edge of the first signal at the particular time.

[0036] Process 400 may proceed from block 402 to block 404. At block 404, the circuit may delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. In one embodiment, the delay applied to the gate-source voltage of the second LS transistor may be a fixed delay.

[0037] The process 400 may proceed from block 404 to block 406. At block 406, the circuit may combine the first signal and the second signal to generate a third signal. The process 400 may proceed from block 406 to block 408. At block 408, a controller may use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at the specific time may reduce a diode conduction time of a body diode of the first LS transistor.

[0038] In one embodiment, the circuit may delay a gate-source voltage of the first LS transistor to generate a fourth signal. The circuit may generate a delay signal based on an arbitration between the first signal and the fourth signal. The circuit may use the delay signal to adjust the delay applied to the gate-source voltage of the second LS transistor. Adjusting the delay may adjust the specific time. In one embodiment, the delay applied to the gate-source voltage of the first LS transistor may be a programmable delay.

[0039] In one embodiment, in response to the decision indicating that the first signal arrives at an arbiter before the fourth signal, the circuit may generate the delay signal to decrease the delay. In response to the decision indicating that the fourth signal arrives at the arbiter before the first signal, the circuit may generate the delay signal to increase the delay.

[0040] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions specified in the blocks may occur out of the order specified in the figures. For example, two blocks shown in succession may actually execute substantially concurrently, or the blocks may sometimes execute in the reverse order, depending on the functionality involved.It is also noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, may be implemented by special purpose hardware-based systems that perform the specified functions or acts or execute combinations of special purpose hardware and computer instructions.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements, if any, in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention.The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

[1] A semiconductor device comprising: a controller; a switching converter comprising a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor, and a second LS transistor; and a circuit configured to: generating a first signal indicating that a voltage at a node between the first HS transistor and the first LS transistor falls below ground; Delaying a gate-source voltage of the second LS transistor to generate a second signal; and Combining the first signal and the second signal to produce a third signal, wherein the controller is configured to use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein turning on the first LS transistor at the specific time reduces a diode conduction time of a body diode of the first LS transistor. [2] The semiconductor device according to claim 1, wherein the switching converter is located in a receiver of a near field communication (NFC) power transmission system. [3] The semiconductor device according to claim 1, wherein the circuit is configured to: Delaying a gate-source voltage of the first LS transistor to generate a fourth signal; Generating a delay signal based on a decision between the first signal and the fourth signal; and Using the delay signal to set the delay applied to the gate-source voltage of the second LS transistor, wherein the delay setting sets the specific time. [4] A semiconductor device according to claim 3, wherein the delay applied to the gate-source voltage of the first LS transistor is a fixed delay. [5] A semiconductor device according to claim 3, wherein: in response to the decision indicating that the first signal arrives at an arbiter before the fourth signal, generating the delay signal to reduce the delay; and in response to the decision indicating that the fourth signal arrives at the arbiter before the first signal, generating the delay signal to increase the delay. [6] The semiconductor device according to claim 1, wherein the delay applied to the gate-source voltage of the second LS transistor is a programmable delay. [7] The semiconductor device according to claim 1, wherein a rising edge of a gate-source voltage of the first LS transistor is aligned with a rising edge of the first signal at the specific time. [8] A semiconductor device comprising: a comparator configured to generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falls below ground; a delay circuit configured to delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal; and an OR gate configured to: Combining the first signal and the second signal to produce a third signal; and Sending the third signal to a controller to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein turning on the first LS transistor at the specific time reduces a diode conduction time of a body diode of the first LS transistor. [9] The semiconductor device of claim 8, wherein the switching converter is located in a receiver of a near field communication (NFC) power transmission system. [10] The semiconductor device according to claim 8, wherein the delay circuit is a first delay circuit, and the semiconductor device further comprises: a second delay circuit configured to delay a gate-source voltage of the first LS transistor to generate a fourth signal; an arbiter configured to decide between the first signal and the fourth signal; and a counter configured to: Generating a delay signal based on the decision between the first signal and the fourth signal; and Sending the delay signal to the controller to set the delay applied to the gate-source voltage of the second LS transistor, wherein the delay setting sets the specific time. [11] The semiconductor device according to claim 10, wherein the delay applied to the gate-source voltage of the first LS transistor is a fixed delay. [12] The semiconductor device according to claim 11, wherein the fixed delay is equivalent to a transmission delay of the comparator. [13] The semiconductor device according to claim 10, wherein the counter is configured to: in response to the decision indicating that the first signal arrives at an arbiter before the fourth signal, generating the delay signal to reduce the delay; and in response to the decision indicating that the fourth signal arrives at the arbiter before the first signal, generating the delay signal to increase the delay. [14] The semiconductor device of claim 8, wherein the delay applied to the gate-source voltage of the second LS transistor is a programmable delay. [15] The semiconductor device according to claim 8, wherein a rising edge of a gate-source voltage of the first LS transistor is aligned with a rising edge of the first signal at the specific time. [16] A method of operating a wireless power transmission device, the method comprising: Generating a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falls below ground; Delaying a gate-source voltage of a second LS transistor in the switching converter to generate a second signal; Combining the first signal and the second signal to produce a third signal; and Using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, wherein turning on the first LS transistor at the specific time reduces a diode conduction time of a body diode of the first LS transistor. [17] The method of claim 16, wherein the switching converter is located in a receiver of a near field communication (NFC) power transmission system. [18] The method of claim 16, further comprising: Delaying a gate-source voltage of the first LS transistor to generate a fourth signal; Generating a delay signal based on a decision between the first signal and the fourth signal; and Using the delay signal to set the delay applied to the gate-source voltage of the second LS transistor, wherein the delay setting sets the specific time. [19] The method of claim 18, wherein: in response to the decision indicating that the first signal arrives at an arbiter before the fourth signal, generating the delay signal to reduce the delay; and in response to the decision indicating that the fourth signal arrives at the arbiter before the first signal, generating the delay signal to increase the delay. [20] The method of claim 18, wherein a rising edge of a gate-source voltage of the first LS transistor is aligned with a rising edge of the first signal at the particular time.

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