Method for fabricating a photonic integrated circuit and photonic integrated circuit

Abstract

The present invention relates to a method for fabricating a photonic integrated circuit (1000) comprising a substrate (10); at least one optical waveguide core (20) having at least one core material (25); a first cladding region (30) having at least one first cladding material (35) adjoining the optical waveguide core (20); a second cladding region (40) having at least one second cladding material (45) adjoining the optical waveguide core (20); at least one electrode structure (50); and a dielectric filling structure (60) which at least partially surrounds the electrode structure (50), wherein the method comprises the following steps: a) Providing the optical waveguide core (20), the first cladding region (30), the electrode structure (50) and the dielectric filling structure (60) and producing at least one temporary cladding structure (70) adjacent to the optical waveguide core (20); b) Removal of a first temporary sub-area (90) of the at least one temporary sheath structure (70), wherein the first temporary sub-area (90) comprises at least one first temporary sheath material (80a), in a first etching process (105) using a first etching process (100); c) Removing a second temporary sub-area (110) of the at least one temporary cladding structure (70), wherein the second temporary sub-area (110) comprises at least a second temporary cladding material (80b), in a second etching process (125) using a second etching method (120) such that the waveguide core (20) is exposed at least in one region (28); and d) Applying the second sheathing material (45) to the exposed area (28).

Description

Field of invention

[0001] The present invention lies in the field of integrated optics and relates to integrated optical circuits. It relates in particular to a method for fabricating a photonic integrated circuit (PIC) and preferably to a photonic integrated circuit fabricated by this method. State of the art

[0002] Integrated optical circuits are compact and robust and can be efficiently manufactured in large quantities on semiconductor wafers. This typically involves complex manufacturing processes that comprise a multitude of precisely coordinated and jointly optimized manufacturing and process control steps, and which, in the case of the widely used silicon photonics, are based on corresponding processes from microelectronics. Within these manufacturing processes, optical waveguides or their waveguide cores are often produced at the beginning of the process (front end of line, FEOL) and subsequently covered with a variety of special layers (back end of line, BEOL), particularly metallic conductor structures embedded in dielectrics for electrical contacting and interconnection of the previously produced FEOL components and / or further optical waveguide structures.A deviation from known manufacturing processes and the materials used is generally not possible without impairing the reliability and yield of the entire process sequence.

[0003] However, for various reasons, it may be necessary to expose the optical structures created in the FEOL, and in particular the waveguide cores, at the end of the fabrication process and make them accessible for contact with other materials. This is the case, for example, in the fabrication of hybrid organic devices that rely on the interaction of an evanescent component of an optical mode guided by the optical waveguide with special optically functional materials, particularly for light emission, absorption, or modulation. Further examples are found in the field of waveguide-based chemical or biochemical sensors, where the waveguide core must be in direct contact with the analyte surrounding or deposited on the surface of the waveguide core in order to enable the corresponding optical sensor function via an interaction of the analyte with the evanescent field.To utilize highly optimized and standardized processes for the fabrication of photonic integrated circuits for such applications, it is often necessary to first fabricate the entire chip, including a global covering of the BEOL layer stack (which serves, for example, for electrical connections, as an optical cladding material, or as a protective layer), and then, in a subsequent process, to remove the BEOL layers at least locally, for example, in designated windows. This local opening of the BEOL layer stack in the designated windows should be as precise as possible and as close as possible to adjacent functional elements, which absolutely require an intact BEOL structure, or to functional structures such as electrical conductors, without impairing them or their function.For this purpose, highly directional (anisotropic) etching processes can be used, which allow the BEOL cover layers to be removed lithographically precisely defined in an area (“window”) by a mask on the surface of the cover layers, without significant undercutting of the mask and associated impairment of adjacent structures (see S. Wolf, H. Zwickel, W. Hartmann, M. Lauermann, Y. Kutuvantavida, C. Kieninger, L. Altenhain, R. Schmid, J. Luo, AK-Y. Jen, S. Randel, W. Freude and C. Koos, Silicon-Organic Hybrid (SOH) Mach-Zehnder Modulators for 100 Gbit / s on-off Keying, Scientific Reports 2018, 8:2598).

[0004] However, highly anisotropic etching processes often exhibit strong physical components for material removal, which are generally based, at least in part, on bombarding the surface to be removed with high-energy ions. For example, in ion beam etching (IBE), the surface to be removed is ablated by bombardment with high-energy accelerated ions, such as argon, and the resulting sputtering processes. This leads to highly anisotropic material removal, oriented along the direction from which the ions strike the surface. In pure sputtering effects, i.e., purely physical material removal, the rate of material removal is generally not very dependent on the material being removed, so purely physical IBE processes do not exhibit high material selectivity. Reactive ion etching (IBE)Reactive ion beam etching (RIBE) is based on a similar approach to inert ion beam etching (IBE), but it uses reactive ions that further enhance the etching process through chemical reactions with the material being removed, thus enabling etching with improved material selectivity. Similarly, in reactive ion etching (RIE), the surface to be etched is bombarded with an ionized reaction gas generated in a plasma. This gas weakens or breaks the chemical bonds of the atoms being removed, thereby intensifying the etching on the surface. Here, too, high material selectivity can be achieved by appropriately balancing the physical and chemical (reactive) material removal processes.

[0005] When using such methods to open the BEOL layer stack, it is practically unavoidable that at least some of the optical structures to be exposed, which were created in the FEOL, are subjected to the etching process used to remove the BEOL layer stack for at least a certain period of time. This can lead to undesirable material removal on the surface of the exposed optical structure, since, due to the strong anisotropy of the etching processes used, a strong physical component of the material removal, which is either non-selective or only weakly material-selective, is unavoidable.In addition to material removal, damage and / or structural changes to the microscopic material structure can also occur through at least temporary bombardment of the surface of the optical structures to be exposed. These changes can occur, for example, in near-surface regions of the structures to be exposed and can negatively affect the function of the associated component. In particular, these changes can involve alteration or destruction of a monocrystalline, polycrystalline, or amorphous material structure, chemical reactions leading to undesirable surface modifications, and / or the diffusion of unwanted substances into the material. This diffusion can, for example, alter the electronic and / or optical properties of the optical structures by changing local doping.Such effects occur particularly towards the end of the respective etching process, when the surface of the structures to be exposed is already exposed or is only protected from direct bombardment with high-energy ions by a thin remaining layer of the BEOL layer stack to be removed.

[0006] The problems described above are exacerbated by the fact that in many cases a relatively thick BEOL stack is present, consisting of many individual layers whose layer thicknesses and composition are typically subject to manufacturing-related variations. This is particularly true for silicon photonic devices that are manufactured in sophisticated CMOS-based processes together with electronic circuits, such as memory chips, and where the BEOL layer stack can contain, for example, nine metallization layers and have a layer thickness of more than 5 µm (see JS Orcutt, RJ Ram and V. Stojanović, Integration of silicon photonics into electronic processes, Proc. of SPIE 8629, 86290F, 2013).At the same time, the etching rates, i.e., the speed of material removal, of the etching processes used are subject to process- and material-related fluctuations, both with regard to the materials being removed and the composition of the reactive media used for material removal. Therefore, an accurate prediction of the process time required to remove the BEOL layer stack is not always possible. To ensure reliable and complete removal of the layer stack, the process time is usually set slightly longer than the average expected etching time, so that the structures to be exposed are typically left completely unprotected by the etching process for a certain period of time at the end of the opening process.

[0007] A similar problem arises in the case of optical structures with strong topography that need to be exposed, where different layer thicknesses of cover material must be removed depending on the position, or in the case of optical structures with elements to be exposed that have spaces or cavities with high aspect ratios from which the material associated with the BEOL layer stack cannot be removed, or can only be removed with difficulty. This is particularly the case with so-called slotted waveguides, which have two parallel silicon strips separated by a slot (see C. Koos, L. Jacome, C. Poulton, J. Leuthold and W. Freude, Nonlinear silicon-on-insulator waveguides for all-optical signal processing, Optics Express 15(10), pp. 5976-90, 2007), or also with so-called photonic crystals (see photonic crystals).Photonic crystal (PhC) or sub-wavelength grating (SWG) waveguides consist of individual structural elements with dimensions and spacings far below the material's wavelength. Both types of waveguides can be used for hybrid integrated components as well as waveguide-based sensors. When removing the material associated with the BEOL layer stack from the cavities in these structures, significantly reduced etch rates often occur due to poorer accessibility for reactive substances and / or high-energy ions. This leads to longer etching times, meaning that even in these cases, exposed structural elements remain unprotected for a certain period during the etching process.In some cases, it is even desirable to provide the exposed structures with slight undercuts after a complete removal of the respective spaces or cavities, which are created by a partial removal of material from under the remaining structural elements and thus away from a line of sight defined by the anisotropic etching process used.

[0008] FR 2840415 A1 discloses a two-stage etching process for the fabrication of optical waveguides with very low optical losses for wavelengths greater than 1.2 µm. First, a waveguide structure is fabricated on a substrate using an anisotropic dry etching process. Subsequently, the outer surfaces of the fabricated waveguide structure are smoothed using a wet chemical etching process, thus minimizing the optical losses in the structure.

[0009] TW 201131226 A discloses a method for manufacturing a silicon waveguide using a two-stage etching process. First, anisotropic etching is performed using reactive ion etching to define an optical waveguide core. Then, a further isotropic dry etching process using electron cyclotron resonance is used to undercut the waveguide structure in order to decouple the optical waveguide core from the silicon substrate.

[0010] US 6767756 B2 discloses a method for manufacturing tapered optical waveguide cores. This method employs various lithography steps and an anisotropic etching process to taper the waveguide core. To set the etch depth, the optical waveguide core is first coated with a wedge-shaped layer of photoresist and then etched to achieve a taper in the profile of the optical waveguide core.

[0011] Z. Zhou, M. Chao, X. Su, S. Fu, R. Liu, Z. Li, S. Bo, Z. Chen, Z. Wu and X. Han, Silicon-Organic Hybrid Electro-Optic Modulator and Microwave Photonics Signal Processing Applications, Micromachines 2023, 14, 1977, describe a method for fabricating a slotted waveguide using a two-stage etching process. First, anisotropic etching using reactive ion etching is performed to define an optical waveguide core and the electronic contact structure. Then, in a first step, another anisotropic etching process is used to etch to a depth of 1.2 µm down to the surface of the slotted waveguide. In a second step, the area within the slot is wet-etched for 3 minutes. Object of the invention

[0012] Based on this, the object of the present invention is to provide a method for manufacturing a photonic integrated circuit and preferably a photonic integrated circuit manufactured using this method, which at least partially overcome the disadvantages and limitations of the prior art mentioned above.

[0013] The object of the present invention is, in particular, to ensure that the photonic integrated circuits, preferably produced using the present manufacturing process, have at least partially exposed waveguide structures. The present manufacturing process is intended, in particular, to allow the local removal of BEOL cover layers with high precision and at the smallest possible distance to adjacent functional elements, without affecting them and without exposing the surface of the structures to be exposed to the influence of high-energy ions.

[0014] The present manufacturing process is intended to be particularly applicable for exposed structures with complex topography, where varying thicknesses of cover material must be removed depending on the position. Furthermore, it should enable the exposure of structures with interstitial and / or cavities with a high aspect ratio, especially slotted waveguides or PhC or SWG structures, and / or the removal of the material associated with the BEOL layer stack from the cavities. The present manufacturing process should also be suitable for underetching exposed structures. Disclosure of the invention

[0015] This problem is solved by a method for fabricating a photonic integrated circuit and a photonic integrated circuit preferably fabricated by this method. Advantageous embodiments, which are implemented individually or in any combination, are described below and in the dependent claims.

[0016] In a first aspect, the present invention relates to a method for manufacturing a photonic integrated circuit, which - a substrate; - at least one optical waveguide core comprising at least one core material; - a first cladding region comprising at least one first cladding material adjacent to the optical waveguide core; - a second cladding area comprising at least a second cladding material adjacent to the optical waveguide core; - at least one electrode structure; and - a dielectric filling structure that surrounds the electrode structure at least in certain areas, The process for manufacturing the photonic integrated circuit comprises the following steps: a) Providing the optical waveguide core, the first cladding region, the electrode structure and the dielectric filling structure and producing at least one temporary cladding structure adjacent to the optical waveguide core; b) Removal of a first temporary sub-area of ​​the at least one temporary sheath structure, wherein the first temporary sub-area comprises at least one first temporary sheath material, in a first etching process using a first etching method; c) Removing a second temporary sub-area of ​​the at least one temporary cladding structure, wherein the second temporary sub-area comprises at least a second temporary cladding material, in a second etching process using a second etching method such that the optical waveguide core is exposed at least in one region; and d) Applying the second coating material to the exposed area.

[0017] The present method serves to manufacture a photonic integrated circuit, which - a substrate; - at least one optical waveguide core comprising at least one core material; - a first cladding region comprising at least one first cladding material adjacent to the optical waveguide core; - a second cladding area comprising at least a second cladding material adjacent to the optical waveguide core; - at least one electrode structure; and - a dielectric filling structure that surrounds the electrode structure at least in certain areas, includes.

[0018] The term "optical waveguide" refers to a spatial structure comprising at least one optical waveguide core and at least one waveguide cladding. Herein, the term "optical waveguide core" refers to a region of the optical waveguide that interacts with light guided within the waveguide and whose refractive index is greater than the refractive index of the mode of light guided within the waveguide. Furthermore, the term "waveguide cladding" refers to another region of the optical waveguide that also interacts with light guided within the waveguide, but whose effective refractive index is less than the refractive index of the mode of light guided within the waveguide.Within the scope of the present invention, the terms "cladding area" or "cladding structure" will continue to be used for sections of the waveguide cladding.

[0019] The at least one optical waveguide core comprises at least one core material. The core material is particularly suitable if it exhibits low optical losses and a sufficiently high refractive index. Preferably, the core material can be selected from the group comprising electrical semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP), but also compounds such as silicon nitride (especially Si3N4 or SiN4). x ), silicon dioxide nitride (SiN x O y) or titanium dioxide (especially TiO2 or TiO). However, the use of other materials is possible; in particular, a ceramic compound, an organic compound, or a polymer may be used. In the case of a semiconductor, the core material can be doped or undoped. Doping agents such as germanium or phosphorus can be used to adjust the optical and electrical properties of the waveguide core. The optical refractive index of the core material is preferably at least 2.1, particularly preferably at least 2.8, and particularly at least 3.3.

[0020] The at least one waveguide cladding comprises at least one cladding material. Efficient light guidance within the optical waveguide core can be achieved by embedding the optical waveguide core in a suitably chosen cladding material. For this purpose, several cladding sections made of typically, but not necessarily, different materials can be used. Preferably, the at least one cladding material can be selected from the group comprising silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxide nitride (SiN4). x O y,) Aluminum dioxide (Al₂O₃), an organic material, and / or a polymer, in particular polyvinyl chloride (PVC), polyurethane (PUR), or a fluorinated hydrocarbon. The refractive index of the first cladding material must be selected such that the first cladding region has a lower refractive index than the optical waveguide core. The refractive index of the second cladding region can also be selected to be lower than that of the optical waveguide core, but this is not required. In the latter case, the core material in the optical waveguide core must have the lowest possible refractive index to maximize the electric field strength within the optical waveguide core.This goal often conflicts with the requirement that the optical waveguide core has a higher refractive index than the waveguide cladding. Therefore, the thickness of the first cladding layer must be chosen to be large enough to reliably prevent optical power from being radiated into the second cladding layer. Examples of such waveguide structures include electro-optical phase shifters based on slotted waveguides, which can be used to create highly efficient electro-optical modulators.

[0021] The term "light" refers to at least one region of electromagnetic radiation from the electromagnetic spectrum, in particular electromagnetic waves with vacuum wavelengths from 10 nm to 1 mm and, preferably, from 30 nm to 300 µm, corresponding to frequencies from 1 THz to 10 PHz. The term "light" encompasses at least the following regions of the electromagnetic spectrum. - the ultraviolet range, encompassing vacuum wavelengths from 10 nm to 380 nm or frequencies from 790 THz to 10 PHz; - the visible range, encompassing vacuum wavelengths from 380 nm to 780 nm or frequencies from 380 THz to 790 THz); and - the infrared range, encompassing vacuum wavelengths from 790 nm to 1 mm or frequencies from 1 THz to 380 THz.

[0022] Furthermore, the term "light" used here refers exclusively to electromagnetic radiation that can be guided within the optical waveguide.

[0023] According to step a), the optical waveguide core and the first cladding region are provided. Preferably, the optical waveguide core has previously been fabricated on a semiconductor substrate. Microstructuring processes, particularly those suitable for structuring optical waveguides, can preferably be used for this purpose. Additive and / or subtractive process steps can be employed and / or combined, especially for structuring the optical waveguide core. An additive process step can, in particular, comprise a process selected from PECVD or LPCVD. A subtractive process step can, in particular, comprise a lithography step or an etching step. If an SOI wafer is selected, at least one material for the optical waveguide core can already be integrated into the substrate. However, the use of at least one other material or structure is also conceivable.

[0024] According to step a), the electrode structure and the dielectric filling structure are also provided, which surrounds the electrode structure at least partially, preferably completely, with the exception of the electrical contacts provided for external contact. The term "electrode structure" refers to an electrically conductive material structure configured for electronic control of the optical waveguide core. The term "dielectric filling structure" refers to an electrically non-conductive material structure configured for electrical insulation of the optical waveguide core and the electrode structure. The electrode structure preferably comprises at least two metal layers, while the dielectric filling structure preferably comprises a plurality of thin layers of dielectrics (interlayer dielectric, ILD). However, the use of at least one other material or structure is conceivable.

[0025] According to step a), a temporary cladding structure adjacent to the optical waveguide core is fabricated. For this purpose, the optical waveguide core is embedded in at least one temporary cladding material. In a particular embodiment, at least two temporary cladding materials can be used, which can be applied stepwise in at least two layers. The term "temporary cladding structure" refers to a section of the waveguide cladding that is fabricated during step a) but removed before completion of the photonic integrated circuit after step a) during steps b) and c), which are described in detail below. In this context, the term "temporary cladding material" refers to a cladding material that is encompassed by the temporary cladding structure.

[0026] To expose the optical structures, a two-stage etching process according to steps b) and c) is used. The term "etching process" here refers to a subtractive manufacturing process in which a partial area of ​​a material is removed, preferably selectively, during an etching process. The etching process can be a wet chemical etching process in which at least one chemical etchant is used during the etching process. Alternatively or additionally, the etching process can be a dry chemical etching process in which a physical process is applied during the etching process, preferably involving the use of reactive ions.The etching process can be an isotropic etching process, in which etching occurs equally in all spatial directions, or an isotropic etching process, in which etching occurs preferentially in one or two spatial directions. The term "etching process" refers to the application of a selected etching process to at least one material. The term "etch rate" refers to the rate of material removal achieved by an etching process.

[0027] According to step b), a first temporary sub-region of the at least one temporary cladding structure is removed in a first etching process using a first etching method. For this purpose, the first temporary sub-region comprises at least one first temporary cladding material. In this process, a first sub-region comprising at least one first temporary cladding material is exposed from the temporary cladding structure by means of an etching process using a first etching method. The first cladding material can preferably be selected from the group comprising silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiN3N4), and silicon dioxide nitride (SiN3N4). x O y,) aluminum dioxide (Al₂O₃), an organic material and / or a polymer, in particular polyvinyl chloride (PVC), polyurethane (PUR), or a fluorinated hydrocarbon. The first etching process is preferably a dry chemical etching process, particularly preferably an anisotropic etching process, which is particularly preferably carried out using high-energy ions whose energy in particular exceeds 150 eV and is less than 1 keV. The dry chemical etching process preferably used for this purpose may in particular be selected from the group comprising ion-beam etching (IBE), reactive ion etching (RIE), inductively coupled plasma (ICP), and deep reactive ion etching (ORIE).Particularly preferably, a reactive component is used during the first etching process, wherein the reactive component is selected from fluorine, chlorine, sulfur, or a compound containing at least one of these elements and released during the first etching process. By means of the first etching process, the first temporary cladding material forming the first temporary cladding region is at least partially removed, thus exposing a partial region between the dielectric filling structure and the remaining second partial region, which comprises a second temporary cladding material.

[0028] Particularly due to gases generated during the first etching process, a passivation layer can form at the edges of the dielectric filling structure. For this purpose, an etching pit can be formed, especially during step b), which has side walls onto which the passivation layer is applied. The term "passivation layer" refers to a layer designed to reduce the amount of material entering a further layer located below it. The passivation layer can comprise at least one passivation material, wherein the passivation material comprises polymer compounds, in particular polymer compounds that form during the first etching process, during the preferably employed dry-chemical etching process. Preferably, the passivation layer can comprise silanes (SiH4) or fluorocarbons, in particular thermoplastics and / or elastomers.

[0029] In a preferred embodiment, particularly to prevent damage to optical structures, an etch stop layer comprising at least one stop layer material can be applied between the first and second sub-regions of the at least one temporary cladding structure. The term "etch stop layer" refers to a layer designed to reduce the effective etch rate to a further layer located beneath the etch stop layer. For this purpose, the etch stop layer can comprise a stop layer material exhibiting a lower etch rate compared to the first etching process. The etch rate of an etching material used in the first etching process to etch the first cladding material can exceed the etch rate of the stop layer material, in particular by a factor of at least 5, preferably at least 10, most preferably at least 15, and most preferably at least 20.The etch stop layer material preferably exhibits high resistance to common etching solutions. For this purpose, the stop layer material can preferably be selected from the group comprising silicon nitride (Si3N4), aluminum nitride (AlN), gallium arsenide (GaAs), silicon germanium (SiGe), silicon dioxide (SiO2), aluminum oxide (Al2O3), gold (Au), aluminum (Al), titanium (Ti), tungsten (W), and polymer compounds. However, the use of a different stop layer material is conceivable. The layer thickness of the second sub-region between the optical waveguide core and the etch stop layer can preferably be at least three times, more preferably at least twice, and particularly at least 1.5 times, the penetration depth of the ions used in the first etching process.

[0030] According to step c), a second temporary sub-region of the at least one temporary cladding structure, wherein the second temporary sub-region comprises at least a second temporary cladding material, is removed in a second etching process using a second etching method such that the optical waveguide core is exposed at least in one region. The second etching method is preferably a wet chemical etching method, and particularly preferably an isotropic etching method, which especially features a high material-selective etch rate with respect to the second temporary cladding material encompassed by the second sub-region of the at least one temporary cladding structure.In this process, the etching rate of an etching material used in the second etching process for etching the second jacket material can exceed the etching rate of the material used for etching the core material, in particular by a factor of at least 5, preferably at least 10, more preferably at least 15, and more preferably at least 20. Furthermore, the etching rate of an etching material used in the second etching process for etching the second jacket material can exceed the etching rate of the material used for etching the passivation material, in particular by a factor of at least 5, preferably at least 10, more preferably at least 15, and more preferably at least 20. In a particular embodiment, partial areas of the first jacket area can also be removed during the second etching process.

[0031] In a preferred embodiment, the second etching process can be configured to reduce or preferably prevent a functionally impairing structural change in the core material forming the optical waveguide core. The term "functionally impairing structural change" refers to a structural change that can adversely affect a function of the optical waveguide core or the core material forming the optical waveguide core, in particular by - a reduction in the electrical conductivity of the core material of the optical waveguide core; - a reduction in the bandwidth of the core material of the optical waveguide core; - a change in at least one physical dimension of the core material of the optical waveguide core, which may lead to an increase in optical losses in the core material.

[0032] By means of the multi-stage etching process presented here, in which, in addition to the dry chemical etching process preferably used for step b), at least one further wet chemical etching process preferably used for step c) is employed, the risk of a functionally impairing structural change of the core material during the exposure of the optical structures of a waveguide component can be reduced or preferably completely avoided.

[0033] According to step d), the second coating material is applied to the exposed area. The term "application" refers to the addition of a material to a layer by means of an additive process step. For application, the second coating material can preferably be selected from the group comprising electro-optical materials, electro-optical dyes, electro-optical polymers, liquid crystals, and ferroelectrics. In particular, the second coating material can be selected from a material exhibiting a Pockels effect, especially barium titanate (BaTiO2), lithium niobate (LiNbO3), or a perovskite structure.

[0034] Furthermore, in a preferred embodiment, the waveguide core can be exposed for electrical interconnection of the component. Following the fabrication of the photonic integrated circuit and the BEOL layer stack, an opening can preferably be defined using at least one lithographic process, so that only desired areas on the surface of the optical waveguide core are exposed.

[0035] The present method can preferably be carried out sequentially, beginning with step a), followed by step b), then by step c), and finally by step d). In a particular embodiment, the removal of the first part of the temporary cladding structure according to step b) and, preferably also the removal of the second part of the cladding structure according to step c) can be performed either before or after the provision of the optical waveguide core, the first cladding section, the electrode structure, and the dielectric filling structure according to step a).

[0036] The present method can be used, in particular, to fabricate various photonic integrated circuits, preferably optoelectronic waveguide devices, especially resistively or capacitively coupled slotted waveguides or finned waveguides. A slotted waveguide has a slot-shaped waveguide core comprising a core material. For this purpose, the optical waveguide core can be divided into at least two separate parts, wherein the at least two separate parts have parallel strips, each separated from the other by a slot. The two parts of the waveguide core can be made of the same material or different materials. This contrasts with the prior art, in which slotted waveguides often comprise only silicon as the core material. The aforementioned materials can be used as the cladding material for the second cladding region.To circumvent bandwidth limitations, slot waveguides can also be coupled capacitively instead of resistively. In this method, an additional material with a high refractive index (high imaginary part), also known as a "high-k material," is inserted between the contact structure and the optical waveguide core. This material allows an electric field to be guided to the optical waveguide core without ohmic losses, thus enabling high bandwidths (see S. Ummethala, J.N. Kemal, AS. Alam, M. Lauermann, A. Kuzmin, Y. Kutuvantavida, SH. Nandam, L. Hahn, D.L. Elder, L.R. Dalton, T. Zwick, S. Randel, W. Freude, and C. Koos, Hybrid electro-optic modulator combining silicon photonic slot waveguides with high-k radio-frequency slotlines, Optica 8 (4), pp. 511–519, 2021).

[0037] In a further aspect, the present invention relates to a photonic integrated circuit, preferably a photonic integrated circuit produced by the method described herein, which - a substrate; - at least one optical waveguide core comprising at least one core material; - a first cladding region comprising at least one first cladding material adjacent to the optical waveguide core; - a second cladding area comprising at least a second cladding material adjacent to the optical waveguide core; - at least one electrode structure; and - a dielectric filling structure that surrounds the electrode structure at least in certain areas, includes.

[0038] For further details of the present method and the photonic integrated circuit preferably produced by it, reference is made to the figures and their description below. Advantages of the invention

[0039] The present invention offers several advantages over prior art methods for fabricating photonic integrated circuits and, preferably, photonic integrated circuits fabricated using this method. The photonic integrated circuits preferably fabricated using the present method exhibit at least partially exposed waveguide structures. In particular, the present fabrication method allows for the local removal of BEOL cover layers with high precision and at the smallest possible distance to adjacent functional elements, without affecting them and without exposing the surface of the exposed structures to the influence of high-energy ions. The present fabrication method is particularly applicable for exposed structures with complex topography, where different layer thicknesses of cover material must be removed depending on the position.Furthermore, this method allows for the exposure of structures with interstitial and / or cavities with a high aspect ratio, in particular slotted waveguides or PhC or SWG structures, and / or the removal of the material associated with the BEOL layer stack from the cavities. The present manufacturing process is also suitable for enabling underetching of exposed structures.

[0040] In contrast to the method presented here, in TW 201131226 A the waveguide core is not produced using lithographic methods and subsequently exposed by an etching process, but is etched directly into the substrate. The subsequent etching process used there is another dry chemical etching process. Furthermore, the method disclosed in TW 201131226 A is not designed for the mass production of optical integrated circuits.

[0041] US patent 6767756 B2 describes the use of an anisotropic etching process for the exposure of optical structures. However, in this patent, the etching process serves not only to etch the optical structures themselves, but also to etch the optical structures themselves. This is expressly prevented by the two-stage etching process described in steps b) and c) of the method presented here.

[0042] In contrast to the method presented here according to claim 1, Z. Zhou et al. do not describe a solution to the problem addressed here, since the waveguide structure is not protected during dry etching. Furthermore, the waveguide structure is partially exposed by the dry etching step.

[0043] Here, the terms "have," "exhibit," "comprise," or "include," or any grammatical forms thereof, are used in a non-exclusive manner. Accordingly, these terms can refer both to situations in which, apart from the features introduced by these terms, no other features are present, and to situations in which one or more additional features are present. For example, the expression "A has B," "A exhibits B," "A comprises B," or "A includes B" can refer both to the situation in which, apart from B, no other element is present in A (i.e., a situation in which A consists solely of B), and to the situation in which, in addition to B, one or more other elements are present in A, such as element C, elements C and D, or other elements.

[0044] Furthermore, it should be noted that the terms "at least one" and "one or more," as well as grammatical forms of these terms, when used in connection with one or more elements or features and intended to express that the element or feature may be provided for once or multiple times, are generally used only once, for example, when the feature or element is first introduced. Upon subsequent mention of the feature or element, the corresponding term "at least one" or "one or more" is generally no longer used, without restricting the possibility that the feature or element may be provided for once or multiple times.

[0045] Furthermore, the terms "preferred," "preferably," "in particular," "for example," or similar terms are used herein in conjunction with optional features without limiting alternative embodiments. Features introduced by these terms are therefore optional, and it is not intended that these features limit the scope of protection of the claims, and in particular the independent claims. Thus, as the person skilled in the art will recognize, the invention can also be implemented using other embodiments. Similarly, features introduced by "in an embodiment of the invention" or by "in an exemplary embodiment of the invention" are understood as optional features without limiting alternative embodiments or the scope of protection of the independent claims.Furthermore, these introductory expressions are intended to leave all possibilities of combining the features introduced herein with other features, whether optional or non-optional features, unaffected.

[0046] In summary, the following embodiments are particularly preferred within the scope of the present invention: Embodiment 1: Method for manufacturing a photonic integrated circuit, comprising - a substrate; - at least one optical waveguide core comprising at least one core material; - a first cladding region comprising at least one first cladding material adjacent to the optical waveguide core; - a second cladding area comprising at least a second cladding material adjacent to the optical waveguide core; - at least one electrode structure; and - a dielectric filling structure that surrounds the electrode structure at least in certain areas, the procedure comprises the following steps: a) Providing the optical waveguide core, the first cladding region, the electrode structure and the dielectric filling structure and producing at least one temporary cladding structure adjacent to the optical waveguide core; b) Removal of a first temporary sub-area of ​​the at least one temporary sheath structure, wherein the first temporary sub-area comprises at least one first temporary sheath material, in a first etching process using a first etching method; c) Removing a second temporary sub-area of ​​the at least one temporary cladding structure, wherein the second temporary sub-area comprises at least a second temporary cladding material, in a second etching process using a second etching method such that the waveguide core is exposed at least in one area; and d) Applying the second coating material to the exposed area. Embodiment 2: Method according to the preceding embodiment, wherein during step b) an etching pit is formed having side walls, and wherein a passivation layer is applied to the side walls of the etching pit. Embodiment 3: Method according to the preceding embodiment, wherein the passivation layer comprises at least one passivation material, wherein the passivation material comprises polymer compounds, in particular polymer compounds that form during the first etching process. Embodiment 4: Method according to one of the preceding embodiments, wherein the etch rate of an etching material used in the second etching process to form the second temporary sheath material exceeds the etch rate for etching the passivation material by a factor of at least 5. Embodiment 5: Method according to one of the preceding embodiments, wherein an etch stop layer is additionally produced between the first sub-area and the second sub-area of ​​the at least one temporary jacket structure, wherein the etch stop layer comprises a stop layer material which has a low etch rate compared to the first etching method. Embodiment 6: Method according to the preceding embodiment, wherein the etch rate of an etching material used in the first etching process for etching the first sheath material exceeds the etch rate of the stop layer material by a factor of at least 5. Embodiment 7: Method according to one of the two preceding embodiments, wherein the stop layer material is selected from silicon nitride, aluminum nitride, gallium arsenide, silicon germanium, silicon oxide, aluminum oxide, gold, aluminum, titanium, tungsten or a polymer compound. Embodiment 8: Method according to one of the preceding embodiments, wherein the first etching method is selected from an anisotropic etching method, and wherein the second etching method is selected from an isotropic etching method. Embodiment 9: Method according to one of the preceding embodiments, wherein the first etching method is or comprises a dry chemical etching method, preferably selected from ion beam etching, reactive ion etching, inductively coupled plasma, or deep reactive ion etching. Embodiment 10: Method according to one of the preceding embodiments, wherein a reactive component is used during the first etching process, wherein the reactive component is selected from fluorine, chlorine, sulfur, or a compound which has at least one of these elements and releases it during the first etching process. Embodiment 11: Method according to one of the preceding embodiments, wherein high-energy ions with an energy of at most 1 keV are used for the first etching process. Embodiment 12: Method according to one of the preceding embodiments, wherein the second etching method is or comprises a material-selective etching method having a high etch rate for the formation of the second temporary sheath material. Embodiment 13: Method according to one of the preceding embodiments, wherein the etch rate of an etching material used in the second etching process to form the second temporary sheath material exceeds the etch rate for etching the core material by a factor of at least 5. Embodiment 14: Method according to one of the preceding embodiments, wherein during the second etching process partial areas of the first jacket area are also removed. Embodiment 15: Method according to one of the preceding embodiments, wherein the height of the first temporary sub-area is at least 2 µm, the width of the first temporary sub-area is at most 15 µm, and wherein the ratio of the height to the width of the first temporary sub-area is at least 0.7. Embodiment 16: Method according to one of the preceding embodiments, wherein the first temporary sheath material and the second temporary sheath material are identical. Embodiment 17: Method according to one of the preceding embodiments, wherein the first etching method and the second etching method are identical. Embodiment 18: Method according to one of the preceding embodiments, wherein the position and extent of the temporary sheath structure is selected such that, after removal of the first temporary sub-area and the second temporary sub-area of ​​the temporary sheath structure, the electrode structure is at least 2 µm away from one of the surfaces formed by the removal. Embodiment 19: Method according to one of the preceding embodiments, wherein the top coverage thickness measured perpendicular to the substrate plane in the exposed area with the second temporary sheath material after carrying out step c) is at least 300 nm, but at least twice the penetration depth of the ions generated during the first etching process. Embodiment 20: Photonic integrated circuit, manufactured by a method according to one of the preceding embodiments, comprising - a substrate; - at least one optical waveguide core comprising at least one core material; - a first cladding region comprising at least one first cladding material adjacent to the optical waveguide core; - a second cladding area comprising at least a second cladding material adjacent to the optical waveguide core; - at least one electrode structure; and - a dielectric filling structure that surrounds the electrode structure, at least in some areas. Embodiment 21: Photonic integrated circuit according to the preceding embodiment, further comprising - a passivation layer which at least partially separates the first cladding region from the dielectric filling structure. Embodiment 22: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the optical waveguide core is divided into at least two separate parts, wherein the optical waveguide core is in particular designed as a slotted waveguide. Embodiment 23: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the optical waveguide core is a plasmonic waveguide or comprises a plasmonic waveguide. Embodiment 24: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the optical waveguide core has at least one electrically conductive contact structure, wherein the electrically conductive contact structure preferably comprises at least a doped or undoped semiconductor, wherein the contact structure is configured to electrically connect at least a part of the optical waveguide core to the at least one electrode structure. Embodiment 25: Photonic integrated circuit according to the preceding embodiment, wherein the contact structure is a planar layer which electrically connects at least a part of the optical waveguide core in a direction perpendicular to a longitudinal axis of the optical waveguide core. Embodiment 26: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the electrode structure has at least two metal layers, while the dielectric filling structure comprises a plurality of thin layers of dielectrics. Embodiment 27: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein a common layer thickness of the electrode structure and the dielectric filling structure is at least 5 µm. Embodiment 28: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the optical waveguide core is at least partially electrically conductive, wherein the optical waveguide core preferably comprises at least partially a doped or undoped semiconductor. Embodiment 29: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the optical waveguide core has an optical refractive index of at least 2.5 at an operating wavelength of the photonic integrated circuit. Embodiment 30: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the core material is selected from silicon, germanium, gallium arsenide, indium phosphide, silicon nitride, silicon oxide nitride or titanium dioxide. Embodiment 31: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the first cladding material and the second cladding material are each selected from silicon dioxide, silicon nitride, silicon oxide nitride, aluminum dioxide, an organic material and / or a polymer. Embodiment 32: Photonic integrated circuit according to one of the preceding embodiments relating to the photonic integrated circuit, wherein the second cladding material is selected from an electro-optic material, an electro-optic dye, an electro-optic polymer, a liquid crystal or a ferroelectric. Embodiment 33: Photonic integrated circuit according to the preceding embodiment, wherein the ferroelectric is selected to be barium titanate (BaTiO2), lithium niobate (LiNbO3) or a perovskite structure. Brief description of the characters

[0047] Further details and features of the present invention will become apparent from the following description of a preferred embodiment, particularly in conjunction with the dependent claims. The respective features may be implemented individually or in combination with one another. The invention is not limited to the embodiments described.

[0048] The exemplary embodiments are shown schematically in the following figures. Here, identical reference numerals in the figures denote identical or functionally equivalent elements, or elements corresponding to each other with respect to their functions. Specifically, the figures show: Fig. 1 A schematic representation of a preferred method for fabricating a photonic integrated circuit with a representation of step a) in Fig. 1a), of step b) in Fig. 1b), of step c) in Fig. 1c) and step d) in Fig. 1d); Fig. 2 a schematic representation of a first etching process during a first etching procedure according to step b); Fig. 3 each a schematic representation of preferred embodiments for photonic integrated circuits after carrying out steps a) and b); Fig. 4 a schematic representation of a preferred embodiment of a resistively coupled phase shifter based on a slotted waveguide; and Fig. 5 a schematic representation of a preferred embodiment of a plasmonic electro-optical phase shifter. Description of the exemplary implementations

[0049] Fig. Figure 1 shows a schematic representation of a preferred method for manufacturing a photonic integrated circuit 1000 according to steps a) to d).

[0050] Fig. Figure 1a) shows a cross-section of a substrate 10, an optical waveguide core 20 comprising at least one core material 25, and a first cladding region 30 comprising at least one first cladding material 35 adjacent to the optical waveguide core 20. Electrode structures 50 and dielectric filling structures 60, which partially surround the electrode structures 50, are also shown. For a selection of the respective materials for the core material 25, the first cladding material 35, the electrode structures 50, and the dielectric filling structures 60, which are provided according to step a), reference is made to the description above.

[0051] According to step a), at least one temporary cladding structure 70 adjacent to the optical waveguide core 20 is produced, the cladding structure comprising at least one temporary cladding material 80. In the embodiment according to Fig. 1a) The temporary sheath structure 70 comprises a first temporary sub-section 90 which includes at least one first temporary sheath material 80a, and a second temporary sub-section 110 which has at least one second temporary sheath material 80b. The temporary sheath materials 80a, 80b are generally different; however, in a special embodiment they may also be the same. How Fig. Figure 1 a) shows that the first temporary sub-region 90 is located further away from a surface of the optical waveguide core 20 compared to the second temporary sub-region 110. While the second temporary sub-region 110 is located in Fig. 1a) directly adjacent to the optical waveguide core 20, the first temporary sub-region 90 forms a common interface with the second temporary sub-region 110.

[0052] Fig. Figure 1b) schematically shows in cross-section how, according to step b), the first temporary sub-region 90 of the temporary shell structure is largely removed from the surface of the second temporary sub-region 110 during a first etching process 105 using a first etching method 100. For this purpose, as described above, preferably a dry chemical etching process, and particularly preferably an anisotropic etching process, can be used, which is particularly preferably carried out using high-energy ions whose energy is in particular above 150 eV and below 1 keV.

[0053] By removing the first temporary section 90, an etching pit 130 is formed, which, as in Fig. 1 b) shown, can be laterally bounded by a passivation layer 150 opposite the dielectric filling structures 60. The passivation layer 150 can form at the edges of the dielectric filling structure 60, in particular due to gases generated during the first etching process 105. The passivation layer 150 can comprise at least one passivation material 155, in particular polymer compounds that can be formed during the first etching process 105. Preferably, the passivation layer can comprise silanes (SiH4) or fluorocarbons, in particular thermoplastics and / or elastomers.

[0054] Fig. Figure 1c) also shows in cross-section how, according to step c), the second temporary sub-section 110 of the temporary cladding structure 70 is subsequently removed during a second etching process 125 using a second etching method 120. The removal of the second temporary sub-section 110 of the temporary cladding structure 70 is carried out in such a way that the waveguide core 20 is exposed at least in a region 28. The passivation layer 150 formed during the preceding step b) remains unchanged.

[0055] Fig. Figure 1d) also shows in cross-section how, according to step d), a second cladding material 45 is subsequently applied to the exposed area 28, thereby obtaining the desired photonic integrated circuit 1000. A second cladding area 40, thus formed and comprising the second cladding material 45, borders the optical waveguide core 20. For a selection of materials for the second cladding material 45, reference is made to the description above.

[0056] Furthermore, the following distances are shown in part of the figures: - h4 between the surface of the first cladding region 30 and the surface of the dielectric filling structures 60; - h 110 between the surface of the second temporary sub-region 110 and the surface of the optical waveguide core 20; - h 90as the original height of the removed second temporary sub-area 110, after removal corresponding to the depth of the etching pit 130; and - b 90 between the dielectric filling structures 60, which define the etching pit 130, whereby the respective layer thickness of the passivation layer 150 is disregarded here.

[0057] Fig. Figure 2 schematically shows a cross-sectional view of the first etching process 105 during the first etching method 100 according to step b). As described above, a dry chemical etching process, and particularly preferably an anisotropic etching process, is used, which is particularly preferably carried out using high-energy ions whose energy exceeds 150 eV and is less than 1 keV. The dry chemical etching process preferably used for this purpose can be selected from the group comprising ion-beam etching (IBE), reactive ion etching (RIE), inductively coupled plasma (ICP), and deep reactive ion etching (ORIE).

[0058] Fig. Figure 3 shows a schematic cross-sectional representation of preferred embodiments of photonic integrated circuits 1000 after carrying out steps a) and b) according to the Fig. 1 and Fig. 2.

[0059] Fig. Figure 3a) shows an embodiment of a slotted waveguide, particularly suitable for sensor applications, after steps a) and b) have been carried out. As shown therein, the optical waveguide core 20 is divided into two separate parts, each having parallel strips separated by a slot. In particular, the slotted waveguide is not in electrical contact with the electrode structure. The two parts of the waveguide core can be made of the same material or of different materials.

[0060] Fig. Figure 3b) shows an embodiment of a resistively coupled phase shifter based on a slotted waveguide after carrying out steps a) and b). Here, the slotted waveguide is connected to the electrode structure via a contact structure.

[0061] Fig. Figure 3c) shows an embodiment of a capacitively coupled phase shifter based on a slotted waveguide after carrying out steps a) and b). Here, a material 205 with a high refractive index (high-k material) is introduced into a capacitive coupling region 200 between the electrode structure 50 and the optical waveguide core 20. The electric field can be guided to the optical waveguide core 20 via the material 205 without ohmic losses, thus enabling high bandwidths.

[0062] Fig. Figure 3d) shows an embodiment of a capacitively coupled phase shifter based on a finned waveguide after carrying out steps a) and b). Here, too, the material 205, which has a high refractive index (high-k material), is introduced into the capacitive coupling region 200 between the electrode structure 50 and the optical waveguide core 20. The electric field can be conducted to the optical waveguide core 20 via the material 205 without ohmic losses, thus enabling high bandwidths to be achieved.

[0063] Fig. Figure 4a) shows a schematic cross-sectional view of a preferred embodiment of a resistively coupled phase shifter based on a slotted waveguide after carrying out all steps a) to d). The resistively coupled phase shifter can be used in particular for the realization of SOH Mach-Zehnder modulators; however, other uses are conceivable.

[0064] Fig. 4b) shows an excerpt from the Fig. 4a) with a schematic representation of the slotted waveguide. Both sides 2020, 2021 of the optical waveguide core 20 can comprise different materials. These materials are often based on silicon, which also serves as the core material. Organic materials, barium titanate, lithium niobate, liquid crystals, or ferroelectrics, especially perovskites, can be used as cladding materials.

[0065] Fig.Figure 5 shows a schematic cross-sectional view of a preferred embodiment of a plasmonic electro-optic phase shifter. A plasmonic waveguide core 250 comprises a slotted waveguide, which can be made of either the same material as the electrode structure 50 or, alternatively, a different metal. Reference symbol list 10 substrate 20 optical waveguide core 25 core material 28 (exposed) area 30 first mantle area 35 first coat material 40 second mantle area 45 second coat material 50 Electrode structure 60 dielectric filling structure 70 temporary mantle structure 80 Coating material 80a first temporary sheathing material 80b second temporary sheath material 90 first temporary sub-area 100 first etching process 105 first etching process 110 second temporary sub-area 120 second etching process 125 second etching process 130 Etching pit 140 side panels 150 passivation layer 155 Passivation material 160 etch stop layer 165 Stop layer material 200 capacitive coupling range 205 Material whose refractive index has a high imaginary part (English: high-k material) 250 plasmonic waveguide core 1000 photonic integrated circuits 2010, 2011 Contact Structure 2020, 2021 side of the optical waveguide core QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] FR 2840415 A1

[0008] TW 201131226 A [0009, 0040] US 6767756 B2 [0010, 0041] Cited non-patent literature

[0000] C. Koos, L. Jacome, C. Poulton, J. Leuthold and W. Freude, Nonlinear silicon-on-insulator waveguides for all-optical signal processing, Optics Express 15(10), pp. 5976-90, 2007

[0007] Z. Zhou, M. Chao, X. Su, S. Fu, R. Liu, Z. Li, S. Bo, Z. Chen, Z. Wu and L.R. Dalton, T. Zwick, S. Randel, W. Freude und C. Koos, Hybrid electro-optic modulator combining silicon photonic slot waveguides with high-k radio-frequency slotlines, Optica 8 (4), S. 511-519, 2021

[0036]

Claims

A method for fabricating a photonic integrated circuit (1000) comprising: - a substrate (10); - at least one optical waveguide core (20) having at least one core material (25); - a first cladding region (30) having at least one first cladding material (35) adjoining the optical waveguide core (20); - a second cladding region (40) having at least one second cladding material (45) adjoining the optical waveguide core (20); - at least one electrode structure (50); and - a dielectric filling structure (60) which at least partially surrounds the electrode structure (50), the method comprising the following steps: a) providing the optical waveguide core (20), the first cladding region (30), the electrode structure (50) and the dielectric filling structure (60) and fabricating at least one temporary cladding structure (70) adjoining the optical waveguide core (20);b) Removing a first temporary sub-area (90) of the at least one temporary cladding structure (70), wherein the first temporary sub-area (90) comprises at least one first temporary cladding material (80a), in a first etching process (105) using a first etching method (100); c) Removing a second temporary sub-area (110) of the at least one temporary cladding structure (70), wherein the second temporary sub-area (110) comprises at least one second temporary cladding material (80b), in a second etching process (125) using a second etching method (120) such that the waveguide core (20) is exposed at least in one region (28); and d) Applying the second cladding material (45) to the exposed region (28). Method according to the preceding claim, wherein during step b) an etching pit (130) is formed having side walls (140), and wherein a passivation layer (150) is applied to the side walls (140) of the etching pit (130). Method according to one of the preceding claims, wherein the etch rate of an etching material used in the second etching process (120) to form the second temporary sheath material (80b) exceeds the etch rate for etching the passivation material (155) by a factor of at least 5. Method according to one of the preceding claims, wherein an etch stop layer (160) is additionally produced between the first sub-area (90) and the second sub-area (110) of the at least one temporary sheath structure (70), wherein the etch stop layer (160) comprises a stop layer material (165) which has a low etch rate compared to the first etching method (100). Method according to the preceding claim, wherein the etch rate of an etching material used in the first etching process (100) for etching the first jacket material (35) exceeds the etch rate of the stop layer material (165) by a factor of at least 5. Method according to one of the two preceding claims, wherein the stop layer material (165) is selected from silicon nitride, aluminum nitride, gallium arsenide, silicon germanium, silicon oxide, aluminum oxide, gold, aluminum, titanium, tungsten or a polymer compound. Method according to one of the preceding claims, wherein the first etching method (100) is selected from an anisotropic etching method, and wherein the second etching method (120) is selected from an isotropic etching method. Method according to one of the preceding claims, wherein the first etching method (100) is or comprises a dry chemical etching method, preferably selected from ion beam etching, reactive ion etching, inductively coupled plasma, or deep reactive ion etching. A method according to one of the preceding claims, wherein a reactive component is used during the first etching process (100), the reactive component being selected from fluorine, chlorine, sulfur, or a compound comprising at least one of these elements and releasing it during the first etching process (100). Method according to one of the preceding claims, wherein for the first etching process (100) high-energy ions with an energy of at most 1 keV are used. Method according to any of the preceding claims, wherein the second etching method (120) is or comprises a material-selective etching method having a high etch rate for forming the second temporary sheath material (80b). Method according to one of the preceding claims, wherein the etch rate of an etching material used in the second etching process (120) to form the second temporary sheath material (80b) exceeds the etch rate for etching the core material (25) by a factor of at least 5. Method according to one of the preceding claims, wherein the first temporary sheath material (80a) and the second temporary sheath material (80b) are identical. Photonic integrated circuit (1000) manufactured by a method according to any of the preceding claims, comprising: - a substrate (10); - at least one optical waveguide core (20) comprising at least one core material (25); - a first cladding region (30) comprising at least one first cladding material (35) adjoining the optical waveguide core (20); - a second cladding region (40) comprising at least one second cladding material (45) adjoining the optical waveguide core (20); - at least one electrode structure (50); and - a dielectric filling structure (60) surrounding the electrode structure (50) at least partially. Photonic integrated circuit (1000) according to the preceding claim, further comprising a passivation layer (150) which at least partially delimits the first cladding region (40) from the dielectric filling structure (60). Photonic integrated circuit (1000) according to one of the preceding claims relating to the photonic integrated circuit (1000), wherein the optical waveguide core (20) is divided into at least two separate parts (2020, 2021), wherein the optical waveguide core (20) is in particular designed as a slotted waveguide. Photonic integrated circuit (1000) according to one of the preceding claims relating to the photonic integrated circuit (1000), wherein the optical waveguide core (20) has at least one electrically conductive contact structure (2010) at least partially, wherein the electrically conductive contact structure (2010) preferably comprises at least partially a doped or undoped semiconductor, wherein the contact structure (2010) is configured to electrically connect at least a part of the optical waveguide core (20) to the at least one electrode structure (50). Photonic integrated circuit (1000) according to the preceding claim, wherein the contact structure (2010) is a planar layer which electrically connects at least a part of the optical waveguide core (20) in a direction perpendicular to a longitudinal axis of the optical waveguide core (20). Photonic integrated circuit (1000) according to one of the preceding claims relating to the photonic integrated circuit (1000), wherein the electrode structure (50) has at least two metal layers, while the dielectric filling structure (60) comprises a plurality of thin layers of dielectrics.

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