Display device and method for its manufacture

Abstract

The disclosure relates to a display device and a method for manufacturing it. A display device comprises a substrate having a display area and a non-display area outside the display area; a light-emitting element in a pixel in the display area; a trim hole in a border of the non-display area; a crack detection line arranged between the trim hole and the display area and surrounding the display area; and a bridge pattern at least in the trim hole.

Description

The present disclosure claims priority from Korean patent application No. 10-2024-0196879, which was filed in the Republic of Korea on December 26, 2024. TECHNICAL AREA The present disclosure relates to a display device (e.g. a display assembly) and a method for its manufacture, and more specifically to a display device that can be easily assembled into a set, and a method for its manufacture. BACKGROUND With the advancement of information technology, various types of small and thin display devices are being introduced, such as liquid crystal displays, organic light-emitting displays, plasma displays, and micro-LED displays. These display devices are applied to various electronic devices, such as smartphones and tablet PCs. The display device comprises various electrodes, different organic or inorganic layers, and various elements that display actual images. Cracks can develop in such a display device due to external influences. If moisture penetrates the display device through these cracks, the problem arises that electrodes corrode or the organic light-emitting layer deteriorates. SUMMARY The present disclosure relates to a display device and a method for its manufacture which substantially eliminate one or more of the problems associated with the limitations and disadvantages of the related prior art. One of the objectives of the present disclosure is to provide a display device and a method for its manufacture which can reduce or prevent defects caused by static electricity in the process of forming a crack detection line. One or more of these problems are solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims. To achieve the above-mentioned objectives of the present disclosure, a display device in one aspect comprises a substrate having a display area and a non-display area outside the display area; a light-emitting element in a pixel in the display area; a trim hole in a border of the non-display area; a crack detection line arranged between the trim hole and the display area and surrounding the display area; and a bridge pattern in the trim hole. The display device can include a buffer layer on the substrate. The display device can include a thin-film transistor in the pixel and on the buffer layer. The thin-film transistor can include a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an intermediate insulating layer on the gate electrode, a source electrode, and a drain electrode on the intermediate insulating layer. The crack detection line can be made of the same material and / or located on the same layer as the gate electrode. The bridge pattern can be made of the same material and / or arranged on the same layer as the gate electrode. The bridge pattern can include multiple patterns arranged along the trim hole and / or spaced apart from each other. The bridge pattern, as an integrated body, can be arranged along the trim hole. The bridging pattern can extend from the trim hole to an upper surface of the gate insulating layer outside the trim hole. The bridge pattern can be associated with the crack detection line on the gate insulation layer. The buffer layer can comprise a first buffer layer on the substrate, a second buffer layer on top of the first buffer layer, and a third buffer layer on top of the second buffer layer. The trim hole can be provided in the first to third buffer layers and the gate insulating layer, and / or from a side face of the trim hole, the second buffer layer can protrude more than the first and third buffer layers. A side surface of the second buffer layer, a section of a lower surface of the second buffer layer and / or a section of an upper surface of the second buffer layer can be covered by the bridge pattern. The display device may have a cover layer in the trim hole that covers the bridge pattern. The bridge pattern can include a first bridge pattern section located inside the trim hole and / or a second bridge pattern section located outside the trim hole. The first bridge pattern section can continuously cover an inner wall of the trim hole and / or be connected to the second bridge pattern section. In another aspect, a method for manufacturing a display device comprises: forming a buffer layer on the substrate having a display area and a non-display area; forming a semiconductor layer on the buffer layer and in the display area; forming a gate insulating layer on the buffer layer such that it covers the semiconductor layer; forming a trim hole along a circumference of the display area by etching the buffer layer and the gate insulating layer; forming a metal layer on the gate insulating layer and in the trim hole; forming a first photoresist pattern on the metal layer corresponding to the display area, a second photoresist pattern on the metal layer corresponding to the non-display area, and a third photoresist pattern on the metal layer corresponding to the trim hole;Structuring the metal layer using the first to third photoresist patterns to form a gate electrode in the display area, a crack detection line in the non-display area, and a bridge pattern in the trim hole; forming an interlayer insulating layer on the gate electrode and the crack detection line; forming a source electrode and a drain electrode on the interlayer insulating layer and in the display area; forming a light-emitting element above the drain electrode; cutting and trimming the substrate along the trim hole. The step of structuring the metal layer can include etching the metal layer using an etching gas. The etching gas for the trim hole can be blocked by the third photoresist pattern. The process can further include the formation of a planarization layer on the drain electrode and / or under the light-emitting element. The process may also include the formation of a top layer that covers the trim hole. The steps of forming the leveling layer and the step of forming the top layer can be carried out simultaneously. The buffer layer can comprise a first buffer layer on the substrate, a second buffer layer on top of the first, and a third buffer layer on top of the second. The trim hole can be provided in the first through third buffer layers and the gate insulating layer, and / or the second buffer layer can protrude more than the first and third buffer layers from one side face of the trim hole. It should be understood that both the preceding general description and the following detailed description are exemplary and explanatory and are intended to further explain the present disclosure according to the claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included for a better understanding of the present disclosure and form part of this description, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Fig. 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure. Fig. 2 is a schematic block diagram showing a subpixel of a display device according to an embodiment of the present disclosure. Fig. 3 is a circuit diagram of a subpixel of a display device according to an embodiment of the present disclosure. Fig. 4 is a schematic top view of a display device according to an embodiment of the present disclosure. Fig. 5 is an enlarged view of area “A” in Fig. 4. Fig. 6 is a cross-sectional view along line II’ in Fig. 4.Figure 7 is an enlarged cross-sectional view of area “B” in Figure 6. Figures 8A to 8F are schematic cross-sectional views showing a process for manufacturing a display device according to one embodiment of the present disclosure. Figures 9A and 9B are views showing the loss of photoresist pattern for forming a crack detection line when no photoresist pattern is formed in a trim hole. Figure 10 is a schematic top view of a section of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION The following section refers in detail to aspects of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, a precise description of known functions or configurations related to this document is omitted if it is determined that such a description would unnecessarily obscure the core of the invention concept. The sequence of processes and / or operations described is a non-limiting example. The sequence of steps and / or operations is not limited to that presented here and may be modified to occur in a different order than that described herein, with the exception of steps and / or operations that must necessarily occur in a specific sequence.In one or more examples, depending on the function or process involved, two successive operations may be performed essentially simultaneously, or the two operations may be performed in reverse order or in a different sequence. Identical reference symbols consistently denote identical elements. The names of the respective elements used in the following explanations are chosen for the sake of simplicity and may therefore differ from those used in actual products. The advantages and features of this disclosure and the methods for its realization will become apparent from the aspects described in detail below and the accompanying drawings. However, this disclosure is not limited to the aspects disclosed below, but can be realized in a variety of different forms, and only these aspects complete the disclosure of this present revelation. This disclosure is provided to give experts in the field of this disclosure comprehensive information about the scope of the disclosure. The shapes, sizes, proportions, angles, numbers, and the like shown in the drawings to illustrate aspects of this disclosure are for illustrative purposes only, and this disclosure is not limited to the matters shown. The same reference numerals refer to the same elements throughout the description. If, in describing this disclosure, it is found that a detailed description of the associated known technology would unnecessarily obscure the subject matter of this disclosure, the detailed description may be omitted. If the terms "comprise," "include," "have," "consist of," and the like are used in this description, other parts may be added, provided that no terms such as "only," "merely," or the like are used.When a component is expressed in the singular, cases with the plural are included unless a specific indication is given. The phrase “at least one of a, b and c” used throughout the description can include “a alone”, “b alone”, “c alone”, “a and b”, “a and c”, “b and c”, or “all of a, b and c”. The advantages and features of the present invention, as well as the methods for its implementation, will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. When designing an element, the element is designed to include a fault or tolerance range, even if such a fault or tolerance range is not explicitly described. For example, when describing a positional relationship, if a positional relationship between two parts is described as "on", "above", "below" and "next to", one or more other parts may be located between the two parts, unless a more restrictive term such as "immediately" or "directly" is used. For example, when describing a temporal relationship, if the temporal sequence is described as "after", "subsequently", "next", and "before", a non-continuous case may be included unless a more restrictive term such as "just", "immediately", or "directly" is used. The area, length or thickness of each component described in the description is shown for the sake of clarity and the present invention is not necessarily limited to the area and thickness of the component shown. It is understood that the terms "first," "second," etc., used here to describe various elements, are not intended to limit these elements. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and likewise a second element could be called a first element, without altering the scope of the present revelation. Features of various aspects of this disclosure can be partially or completely coupled or combined and, as those skilled in the art can readily understand, interact and be technically controlled in various ways. The aspects of this disclosure can be implemented independently or in a mutually dependent manner. In the present disclosure, the “display device” can comprise a narrowly defined display device such as a display module with a display panel and a control unit for controlling the display panel. Furthermore, the “display device” can also comprise an electronic group device or group unit such as a notebook computer, a television, a computer monitor, a vehicle display, an equipment display, a smartphone, wearable devices such as smartwatches, portable multimedia players (PMPs), personal digital assistants (PDAs), an electronic tablet, or the like, which constitute a complete product (or an end product) with a display module. Accordingly, the display device of the present invention can comprise a display device in the narrower sense, such as a display module, and a group device that is an application product or an end-user device comprising the display module. The following section refers in detail to some of the examples and preferred embodiments shown in the accompanying drawings. Fig. 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure, and Fig. 2 is a schematic block diagram showing a subpixel of a display device according to an embodiment of the present disclosure. As shown in Fig. 1, a display device 100 of the present disclosure comprises an image processing unit 102, a time control unit 104, a gate control unit 106, a data control unit 107, a power supply unit 108 and a display panel 109. The image processing unit 102 outputs image data supplied externally, as well as a control signal for controlling various elements. The control signal output by the image processing unit 102 can include, for example, a data release signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing control unit 104 receives the image data and the control signal from the image processing unit 102. The timing control unit 104 generates a gate timing control signal (GDC) to control the operating time of the gate control unit 106 and a data timing control signal (DDC) to control the operating time of the data control unit 107 based on the control signal input from the image processing unit 102. The gate driver unit 106 responds to the gate timing control signal GDC supplied by the timing control signal 104 and outputs a sampling signal to the display panel 109. The gate driver unit 106 outputs the sampling signal via several gate lines GL1 to GLm. In this case, the gate driver unit 106 can be implemented as an IC (integrated circuit), but is not limited to this. The gate driver unit 106 comprises various gate drive circuits, and these gate drive circuits can be implemented directly on the substrate of the display panel 109. In this case, the gate driver unit 106 can be a GIP (gate-in-panel). The data control unit 107 responds to the data time control signal DDC input from the time control signal 104 and outputs the data voltage to the display panel 109. The data control unit 107 samples the digital data signal DATA supplied from the time control signal 104 and temporarily stores it. The data control unit 107 converts the digital data signal DATA into an analog data voltage based on the gamma voltage. The data control unit 107 outputs the data voltage via several data lines DL1 to DLn. In this case, the data control unit 107 can be implemented as an integrated circuit (IC), but is not limited to this. The power supply unit 108 outputs a high potential voltage VDD and a low potential voltage VSS and supplies the display panel 109 with these voltages. The high potential voltage VDD is supplied to the display panel 109 via a first power line EVDD, and the low potential voltage VSS is supplied to the display panel 109 via a second power line EVSS. In this case, the voltage output by the power supply unit 108 can be output to the gate control unit 106 or the data control unit 107. The display panel 109 shows an image in response to the sampling signal from the gate control unit 106, the data voltage from the data control unit 107 and the voltage from the power supply unit 108. The display panel 109 comprises several subpixels SP and displays an actual image. The subpixels SP can include a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP can also include a white subpixel. The white, red, green, and blue (W, R, G, B) subpixels SP can have the same area. Alternatively, the white, red, green, and blue (W, R, G, B) subpixels SP can have different areas. As shown in Fig. 2, a subpixel SP can be connected to a gate line GL1, a data line DL1, a first power line EVDD, and a second power line EVSS. Depending on the pixel circuit configuration, the subpixel SP can include multiple thin-film transistors and a storage capacitor. For example, the subpixel SP can include two transistors and a capacitor (e.g., a 2T1C structure). Alternatively, the subpixel SP can have a structure of 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, and 8T2C. Fig. 3 is a circuit diagram of a subpixel of a display device according to an embodiment of the present disclosure. As shown in Fig. 3, the display device comprises a gate line GL, a data line DL, and a power line PL. The gate line GL crosses the data line DL and the power line PL to define the subpixel SP. A switching transistor Ts, a drive transistor Td, a storage capacitor Cst, and a light-emitting element D are arranged within the subpixel SP. The switching transistor Ts is connected to the gate line GL and the data line DL, and the driver transistor Td and the storage capacitor Cst are connected to the switching transistor Ts and the power line PL. The light-emitting element D is connected to the driver transistor Td. In the organic light-emitting display device, when the switching transistor Ts is switched on by a gate signal applied via the gate line GL, a data signal is applied from the data line DL to the gate electrode of the control transistor Td and an electrode of the storage capacitor Cst. When the driver transistor Td is switched on by the data signal, electrical current is supplied to the light-emitting element D from the power line PL. As a result, the light-emitting element D emits light. In this case, when the driver transistor Td is switched on, the level of the electrical current applied to the light-emitting element D from the power line PL is set such that the light-emitting element D can produce a gray level. The storage capacitor Cst serves to maintain the voltage of the gate electrode of the drive transistor Td when the switching transistor Ts is switched off. Accordingly, even when the switching transistor (e.g. thin-film transistor (TFT)) Ts is switched off, a level of a current applied from the power line PL to the light-emitting element D is maintained until the next frame. In Fig. 3, the subpixel SP comprises two transistors Td and Ts and one storage capacitor Cst. Alternatively, the subpixel SP can comprise three or more transistors and two or more storage capacitors. Fig. 4 is a schematic top view of a display device according to an embodiment of the present disclosure. As shown in Fig. 4, the display device 100 of the present disclosure comprises a display panel PNL, a flexible printed circuit board (e.g., a flexible printed circuit) FPC, and a printed circuit board PCB. The display panel PNL comprises a display area AA for displaying an image and a non-display area NA outside the display area AA. A subpixel SP, comprising several subpixels SP1, SP2, and SP3, is located in the display area AA. Subpixels SP1, SP2, and SP3 can include a red subpixel R, a green subpixel G, and a blue subpixel B. Additionally, subpixel SP can also include a white subpixel W. Several gate lines and several data lines are arranged in the display area AA, and the subpixel SP is located at a junction of the gate and data lines. Each of the subpixels SP1, SP2, and SP3 contains a transistor as a switching and / or control element and a display element. The display element can comprise various display elements. For example, the display element can be an organic light-emitting element (or an organic electroluminescent display element), a liquid crystal display element, a quantum dot display element, a micro-LED display element, or a mini-LED display element. A gate driver (e.g., gate driver 106 in Fig. 1) and a data driver (e.g., data driver 107 in Fig. 1) for applying a signal to the subpixels SP1, SP2, and SP3 can be arranged in the non-display area NA. The gate driver supplies a sampling signal (e.g., a gate signal) to the subpixel via the gate line, and the data driver supplies a picture signal (e.g., a data signal) to the subpixel via the data line. The gate driver can be a gate-in-board (GIP) circuit implemented in a non-display area NA of a substrate. One end of the flexible printed circuit board (FPC) is attached to the underside of the display area (AA) at one end of the non-display area (NA), and the printed circuit board (PCB) is attached to the other end of the FPC. The data control unit and several signal lines can be located within the FPC, while a timing control unit and a power supply unit can be located within the PCB. In this case, the gate control unit can be located directly on the display panel (PNL). The control signal and voltage from the timing control unit and the power supply unit in the printed circuit board (PCB) can be supplied to the gate control unit and the data control unit via the signal lines. A crack detection line PCD is arranged around one perimeter of the display area AA of the scoreboard PNL. The crack detection line PCD can surround three sides of the display area AA. For example, the crack detection line PCD can have a "U" shape or a picture frame shape with one open side. The crack detection line (PCD) is electrically connected to the signal line of the flexible printed circuit board (FPC). A resistor The flexible printed circuit board (FPC) or printed circuit board (PCB) is equipped with a resistance measurement unit to measure the resistance value of the crack detection line (PCD). If the measured resistance value is detected as infinite, it is determined that a crack has occurred in the crack detection line (PCD) and that the crack has propagated to or approached the display area (AA). If the output resistance value is a predetermined value less than infinity, it is determined that no crack has occurred in the crack detection line (PCD). Fig. 5 is an enlarged view of area “A” in Fig. 4. As shown in Fig. 5, a trim hole TRIM is formed on an outer edge of the non-display area NA of the PNL display panel. The trim hole TRIM is used to separate a carrier substrate on which several PNL display panels are formed. The parent substrate is cut into at least one PNL display panel. In the manufacture of an irregularly shaped display device, such as a clock display or a vehicle display device, the display panels are formed on a rectangular substrate. A cutting and trimming process is then performed to produce a display device with the desired shape. The trimming hole (TRIM) can be formed for this process. The TRIM can be created by removing several insulating layers formed in the display panel (PNL). The TRIM trim hole is formed with a width of a defined length from the outer edge of the non-display area NA towards the display area AA. The TRIM trim hole will be explained in detail later. The crack detection line PCD is located between the trim hole TRIM and the display area AA. The crack detection line PCD is positioned at a predetermined distance from the trim hole TRIM. Since the trim hole TRIM extends along the entire circumference of the display panel PNL, and the crack detection line PCD is located along at least three sides of the display panel PNL, the trim hole TRIM and the crack detection line PCD can be positioned adjacent to each other along at least three sides of the display panel PNL. A bridge pattern BPAT is formed within the trim hole TRIM. The bridge pattern BPAT may be formed only within the trim hole TRIM, but is not limited to it. At least one segment of the bridge pattern BPAT can be formed within the trim hole TRIM. For example, one segment of the bridge pattern BPAT (which can be referred to as the first bridge pattern segment) can be formed within the trim hole TRIM, while another segment of the bridge pattern BPAT (which can be referred to as the second bridge pattern segment) can extend to the outside of the trim hole TRIM. The first bridge pattern segment can continuously cover the inner wall of the trim hole TRIM and be connected to the second bridge pattern segment.The second bridge pattern section can increase the contact area between the BPAT bridge pattern and the attached layer on the substrate, thereby increasing the stability of the formed structure and making it more suitable for subsequent cutting and trimming processes. The bridge pattern BPAT can extend a predetermined distance in the direction of the display area AA. The bridge pattern BPAT is positioned such that it is spaced a predetermined distance from the crack detection line PCD. The bridge pattern BPAT can have a band-like pattern with a predetermined width. Multiple bridge patterns BPAT can be arranged along the perimeter of the scoreboard PNL at predetermined intervals. For example, the bridge pattern BPAT can have multiple patterns arranged and spaced apart along the trim hole TRIM. Furthermore, the bridge pattern BPAT can be arranged as a continuous, integrated body along the perimeter of the scoreboard PNL. For example, the bridge pattern BPAT can be arranged as an integrated body along the trim hole TRIM. Fig. 6 is a view showing a structure of a display board of the present disclosure, and is a cross-sectional view along line II' in Fig. 4 . To facilitate explanation, Fig. 6 shows a subpixel of the display area AA and the non-display area NA. A substrate 140 comprises a display area AA and a non-display area NA. The substrate 140 can be made of a hard material, e.g., glass, or a flexible plastic material. For example, substrate 140 can be composed of at least one material from polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone and polycarbonate, but is not limited to these. In one embodiment of the present disclosure, the substrate 140 may, but is not limited to, comprise several polyimide layers and an inorganic layer between the polyimide layers. A buffer layer 142 is arranged on the substrate 140. The buffer layer 142 can be arranged over the entire surface of the substrate 140 to improve the adhesion between the substrate 140 and the layers formed on the substrate 140 and to keep contaminants, e.g., alkaline components, away from the substrate 140. In addition, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated the substrate 140. The buffer layer 142 can comprise a first buffer layer 142a, a second buffer layer 142b on top of the first buffer layer 142a, and a third buffer layer 142c on top of the second buffer layer 142b. For example, each of the first and third buffer layers 142a and 142c can be made of silicon dioxide (SiOx), and the second buffer layer 142b can be made of silicon nitride (SiNx), without being limited to this. A thin-film transistor (TFT) T is located on the buffer layer 142 in the display area AA. To simplify the explanation, Fig. 6 shows a driver transistor (e.g., the driver transistor Td in Fig. 3). Additional TFTs, such as a switching TFT (e.g., the switching transistor Ts in Fig. 3), can also be arranged on the buffer layer 142 and in the display area AA. The TFT T in Fig. 6 has a top-gate structure. Alternatively, the TFT T can have a bottom-gate structure. The TFT T comprises a semiconductor layer 112 on the buffer layer 142, a gate insulating layer 144 on the semiconductor layer 112, a gate electrode 114 on the gate insulating layer 144, an intermediate insulating layer 146 on the gate electrode 114 and a source and drain electrode 115 and 116 on the intermediate insulating layer 146. Semiconductor layer 112 can be made of a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material can be low-temperature polysilicon (LTPS), but is not limited to this. In one embodiment of the present disclosure, the semiconductor layer 112 can be formed from an oxide semiconductor material. For example, the semiconductor layer 112 can be formed from indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited to these materials. The semiconductor layer 112 can comprise a channel region 112a, a source region 112b on one side of the channel region 112a, and a drain region 112c on the other side of the channel region 112a. The gate insulating layer 144 can cover the display area AA and the non-display area NA. The gate insulating layer 144 may cover only the display area AA. The gate insulating layer 144 can be formed from an inorganic insulating material, such as silicon dioxide or silicon nitride, and can have a single-layer or multi-layer structure. However, it is not limited to this. The interlayer insulating layer 146 can cover the display area AA and the non-display area NA. The interlayer insulating layer 146 may cover only the display area AA. The interlayer insulating layer 146 can be made of an organic insulating material, such as photoacrylic, or an inorganic insulating material, such as silicon dioxide or silicon nitride, and can have a single-layer or multilayer structure. For example, the interlayer insulating layer 146 can have a multilayer structure comprising an organic insulating layer and an inorganic insulating layer, but it is not limited to this. The gate electrode 114, the source electrode 115, and the drain electrode 116 can each be made of a conductive material, e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), and can have a single-layer or multi-layer structure. However, they are not limited to this. The source and drain electrodes 115 and 116 can each be connected (e.g., by contacting) the source and drain regions 112b and 112c of the semiconductor layer 112 via a contact hole in the gate insulating layer 144 and the interlayer insulating layer 146, respectively. A lower shielding metal layer can be arranged between the semiconductor layer 112 and the substrate 140. The backchannel phenomenon caused by charges trapped in the substrate 140 can be reduced or minimized by the lower shielding metal layer, thus reducing or preventing afterimages or performance degradation of the TFT T. The lower shielding metal layer can be made of a conductive material, e.g., titanium (Ti), molybdenum (Mo), or their alloys, and can have a single-layer or multi-layer structure. However, it is not limited to this. A planarization layer 148 is formed over the substrate 140, including the TFT T. The planarization layer 148 can be made of an organic insulating material, e.g., photoacrylic, but is not limited to this. The planarization layer 148 can have a multilayer structure comprising an inorganic insulating layer and an organic insulating layer, or a multilayer structure comprising two or more organic insulating layers. A first electrode 132 is arranged on the planarization layer 148 and connected to the drain electrode 116 of the TFT T via a contact hole in the planarization layer 148. The first electrode 132 can be made of at least one material from aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and their alloys. Alternatively, the first electrode 132 can comprise a transparent conductive oxide material layer made of indium tin oxide (ITO) or indium zinc oxide (IZO). In an upward-emitting display device 100, the first electrode 132 can comprise an opaque (or reflective) conductive material layer with a transparent conductive oxide material layer. In a downward-emitting display device 100, the first electrode 132 can comprise a transparent conductive oxide material layer without an opaque conductive material layer. A bank of BNK is located at the boundary of each subpixel and on planarization layer 148. The bank of BNK can act as a partition to define a subpixel. The bank of BNK surrounds the subpixel, thus reducing or preventing color mixing in neighboring subpixels. The BNK bank can be made of an inorganic insulating material, e.g., silicon nitride (SiNx) or silicon dioxide (SiOx), an organic insulating material, e.g., benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, or a photosensitive material with a black pigment. However, it is not limited to these materials. A light-emitting layer 134 can be formed on an upper surface of the first electrode 132, an inclined surface of bank BNK, and a section of an upper surface of bank BNK in the display area AA. The light-emitting layer 134 can extend into at least one section of the non-display area NA. The light-emitting layer 134 can comprise a red-emitting layer, a green-emitting layer, and a blue-emitting layer. The red-emitting layer is located in the red subpixel and provides red emission, the green-emitting layer is located in the green subpixel and provides green emission, and the blue-emitting layer is located in the blue subpixel and provides blue emission. For example, the light-emitting layer 134 can comprise an organic light-emitting layer or an inorganic light-emitting layer, such as a nanoscale material layer, a quantum dot layer, a light-emitting micro-LED layer, or a light-emitting mini-LED layer. However, it is not limited to these. The light-emitting layer 134 can include an emissive material layer. Furthermore, the light-emitting layer 134 can comprise at least one hole injection layer for injecting holes, one electron injection layer for injecting electrons, one hole transport layer for transporting holes, one electron transport layer for transporting electrons, one hole blocking layer, and one electron blocking layer. However, it is not limited to these. A second electrode 136 is arranged on the light-emitting layer 134. The second electrode 136 can be made of a metal or an alloy and can have a single-layer or a multi-layer structure. In one embodiment of the present disclosure, the second electrode 136 can be made of a transparent conductive oxide material. However, it is not limited to this. In an upward-emitting display device 100, the second electrode 136 can have a thin profile, so that it exhibits a transparent or semi-transparent property. For example, the second electrode 136 can be formed from at least one of the alloys LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag or LiF / Ca:Ag. In a downward-emitting display device 100, the second electrode 136 can be made of an opaque conductive material such that it is a reflective electrode. For example, the second electrode 136 can be made of at least one material of Ag, Al, Au, Mo, W, Cr or alloys thereof. The first electrode 132, the light-emitting layer 134, and the second electrode 136 form a light-emitting element D. The light-emitting element D can be an organic light-emitting element, in which case the light-emitting layer 134 is an organic light-emitting layer, or an inorganic light-emitting element, in which case the light-emitting layer 134 is an inorganic light-emitting layer. The light-emitting element D can be a light-emitting diode. The light-emitting element D can have a tandem structure. In the light-emitting tandem structure element D, the light-emitting layer comprises several emission material layers and one or more charge-generating layers between adjacent emission material layers. The charge-generating layer controls charge balancing in the multiple emission material layers and can have a multilayered structure comprising an n-type charge-generating layer and a p-type charge-generating layer. The charge-generating layer can be doped with an alkali metal, e.g., Li, Na, K, Cs, or the like, and an alkaline earth metal, e.g., Mg, Sr, Ba, Ra, or the like. However, it is not limited to these. An encapsulation layer 180 is arranged on the display area AA and the non-display area NA such that it covers or seals the light-emitting element D. If the light-emitting element D is exposed to oxygen and / or moisture, pixel shrinkage can occur, in which the emission area decreases, or a defect such as dark spots can appear within the emission area. Furthermore, moisture or oxygen can oxidize the metal electrodes. The encapsulation layer 180 blocks the ingress of moisture and / or oxygen from the outside, thus reducing or preventing defects in the light-emitting element D and various electrodes. The encapsulation layer 180 can comprise a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186. In one embodiment of the present disclosure, the encapsulation layer 180 can have a two-layer structure or a multi-layer structure with four or more layers. The first and third encapsulation layers 182 and 186 can each be made of an inorganic insulating material, e.g., silicon dioxide (SiOx), silicon oxynitride (SiON), or silicon nitride (SiNx), and can have a single-layer or multi-layer structure. The first and third encapsulation layers 182 and 186 can also contain an organic insulating material. The second encapsulation layer 184 can be made of an organic material such as epoxy resin. A touch element can be positioned. The touch element can be positioned in the display area AA to detect touch input. The touch element can detect external touch information using a user's finger or a stylus. A dam DAM is arranged in the non-indication area NA. The organic material forming the second encapsulation layer 184 is fluid. As the second encapsulation layer 184 forms, the fluidity of the organic material allows it to flow from the outside of the non-indication area NA to the outside of the substrate 140. The dam DAM is designed to surround the indication area AA in order to contain the organic material flowing outward from the substrate 140 during the formation of the second encapsulation layer 184. This reduces or prevents the outflow of organic material from the substrate 140. Figure 6 shows a single dam DAM. Alternatively, multiple dams DAM can be arranged. The DAM dam can have a multi-layered structure. For example, the DAM dam can comprise a first layer made of the same material as the planarization layer 148 and a second layer made of the same material as the BNK bank. Alternatively, the DAM dam can have a single-layered structure or a multi-layered structure with three or more layers. The crack detection line PCD is located in the non-display area NA and outside the dam DAM. The crack detection line PCD can be located on the gate insulating layer 144, but is not limited to this. If the crack detection line PCD is located on the gate insulating layer 144 (i.e., on the same layer as the gate electrode 114), the crack detection line PCD can be made of the same metal as the gate electrode 114 of the TFT T. However, it is not limited to this. For example, the crack detection line PCD can be located on the intermediate insulating layer 146. In this case, the encapsulation layer 180 can extend to cover and protect the crack detection line PCD. Since the crack detection line PCD is located on the same layer as the source electrode 115 and the drain electrode 116 of the TFT T, the crack detection line PCD can be formed from the same metal as the source electrode 115 and the drain electrode 116. Furthermore, the second bridge pattern section of the bridge pattern BPAT can be located on the same layer as the crack detection line PCD. Therefore, the second bridge pattern section can be formed on the same layer as the crack detection line PCD and at least one of the gate electrode 114, source electrode 115, and drain electrode 116 of the TFT T.The first and second bridge pattern sections can be formed from the same material as the crack detection line PCD and at least one of the gate electrode 114, the source electrode 115, and the drain electrode 116 of the TFT T. Thus, the crack detection line PCD and the bridge pattern BPAT can be formed together with the TFT T, thereby reducing or preventing a decrease in process efficiency. The trim hole TRIM is formed at one edge end of the display device 100. The trim hole TRIM can be formed by removing at least some layers from the intermediate insulating layer 146, the gate insulating layer 144, and the buffer layer 142. Since the trim hole TRIM is an area where the display panel PNL is cut and trimmed, a display panel with the finished (or final) shape may only have half of the original trim hole TRIM, and the remainder of the trim hole TRIM may be removed by the trimming process. At least one section of the bridge pattern BPAT can be formed in the trim hole TRIM. The bridge pattern BPAT can extend from the trim hole TRIM to a section on the gate insulating layer 144, thus placing the second bridge pattern section on the gate insulating layer 144 (i.e., on the same layer as the gate electrode 114). The bridge pattern BPAT is positioned spaced away from the crack detection line PCD. The bridge pattern BPAT can be formed from the same metal as the crack detection line PCD or the gate electrode 114, but is not limited to this. A cover layer 149 is formed in the trim hole TRIM such that it covers the bridge pattern BPAT. The cover layer 149 can cover a side face of the intermediate layer insulating layer 146 and a section of an upper surface of the intermediate layer insulating layer 146. The penetration of moisture and / or oxygen into the display panel PNL through the trim hole TRIM can be reduced or prevented by the cover layer 149. The cover layer 149 can be formed from an organic or an inorganic material, but is not limited to this. Fig. 7 is an enlarged cross-sectional view of area “B” in Fig. 6. The trim hole TRIM is explained in more detail with reference to Fig. 7. As shown in Fig. 7, the buffer layer 142 on the substrate 140 comprises the first to third buffer layers 142a, 142b and 142c. The first and third buffer layers 142a and 142c can each be made of silicon dioxide (SiOx), and the second buffer layer 142b can be made of silicon nitride (SiNx). The gate insulating layer 144 is arranged on the buffer layer 142, and the intermediate insulating layer 146 is arranged on the gate insulating layer 144. The trim hole TRIM can be formed by removing the gate insulating layer 144, the intermediate insulating layer 146, and a section of the buffer layer 142, or by removing the gate insulating layer 144 and a section of the buffer layer 142. In this case, the first buffer layer 142a arranged on the substrate 140 is partially removed, leaving a thin first buffer layer 142a on the substrate 140 within the trim hole TRIM. That is, the first buffer layer 142a has a first thickness within the trim hole TRIM and a second thickness, greater than the first thickness, outside the trim hole TRIM. As described later, the buffer layer 142, the gate insulating layer 144, or the intermediate insulating layer 146 can be removed by a dry etching process. The first buffer layer 142a and the third buffer layer 142c are made of silicon dioxide, and the second buffer layer 142b is made of silicon nitride. When the buffer layer 142 is etched by the dry etching process, there is a difference in the etch rate between the silicon dioxide layer and the silicon nitride layer, such that the second buffer layer 142b can protrude from the sidewall of the trim hole TRIM, i.e., more than the first buffer layer 142a and the third buffer layer 142c. Of course, this revelation is not limited to the configuration in which the first buffer layer 142a and the third buffer layer 142c are made of silicon dioxide and the second buffer layer 142b is made of silicon nitride.Under predetermined process conditions, the etch rate of the materials of the first buffer layer 142a and the third buffer layer 142c is greater than the etch rate of the material of the second buffer layer 142b, so that the second buffer layer 142b can protrude from the side wall of the trim hole TRIM. The bridge pattern BPAT is formed in the trim hole TRIM and on the upper surface of the gate insulating layer 144. The bridge pattern BPAT extends from the outer edge of the display panel PNL to the trim hole TRIM and the upper surface of the gate insulating layer 144. Because the second buffer layer 142b projects from the side face of the first and third buffer layers 142a and 142c toward the trim hole TRIM, the bridge pattern BPAT has a step difference on one side face of the trim hole TRIM. Since the second buffer layer 142b projects from the side wall of the trim hole TRIM, a side face of the second buffer layer 142b (e.g., a side face of the projecting section), a section of a lower surface of the second buffer layer 142b (e.g., a section of the projecting section), and a section of an upper surface of the second buffer layer 142b (e.g.,A portion of the protruding section may be covered by or in contact with the BPAT bridge pattern. The buffer layer 142 with such a protruding section can increase the contact area with the BPAT bridge pattern, thereby increasing the stability of the formed structure and making it more suitable for subsequent cutting and trimming processes. As described above, the occurrence of a crack in the non-indication area NA can be detected quickly because the indicator device 100, according to the present disclosure, has the crack detection line PCD arranged along the outer circumference of the non-indication area NA. As a result, measures can be taken quickly when a crack occurs, and a defect in the indicator device 100 can be reduced or prevented. A manufacturing process for the display device 100 of the present disclosure is described. Figures 8A to 8F are schematic cross-sectional views showing a process for manufacturing a display device according to an embodiment of the present disclosure. As shown in Fig. 8A, the buffer layer 142 is formed over the entire surface of the first substrate 140, including the display area AA and the non-display area NA. The substrate 140 can be made of a rigid material, e.g., glass, or a flexible plastic material, e.g., polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate. The buffer layer 142 can be formed by sequentially applying the first buffer layer 142a made of silicon oxide, the second buffer layer 142b made of silicon nitride and the third buffer layer 142c made of silicon oxide. Next, the semiconductor layer 112 is formed on the buffer layer 142 by forming and etching a polysilicon layer or an oxide semiconductor layer, e.g., IGZO, IZO, IGTO, or IGO. Additionally, impurities can be doped into both ends of the semiconductor layer 112 to form the source region 112b and the drain region 112c on either side of the channel region 112a. Next, the gate insulating layer 144 is formed by applying an inorganic insulating material, e.g., silicon oxide or silicon nitride. The gate insulating layer 144 is located in the display region AA and in the non-display region NA and covers the semiconductor layer 112. Next, as shown in Fig. 8B, the first to third buffer layers 142a, 142b, and 142c and the gate insulating layer 144 are etched using an etching gas to form the trim hole TRIM in the non-display area NA. In this case, the etch rate of the first and third buffer layers 142a and 142c differs from the etch rate of the second buffer layer 142b, so that one end of the second buffer layer 142b may protrude from a side face of the trim hole TRIM into the interior (e.g., the center) of the trim hole TRIM. Next, as shown in Fig. 8C, a metal layer 114a is formed over the entire surface of the substrate 140 by depositing a metal, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, or Cu, using a sputtering process. Photoresist (PR) is applied and developed to form a first PR pattern 160a on the metal layer 114a in the display area AA, and a second PR pattern 160b and a third PR pattern 160c on the metal layer 114a and the non-display area NA. The first PR pattern 160a corresponds to the channel area 112a, the second PR pattern 160b corresponds to the crack detection line PCD (from Fig. 6), and the third PR pattern 160c corresponds to the trim hole TRIM (from Fig. 8B). The third PR pattern 160c corresponds to the metal layer 114a on the bottom of the trim hole TRIM and one side of the trim hole TRIM and / or covers it.In other words, the third PR pattern 160c corresponds to and / or covers the metal layer 114a on a top surface of the first buffer layer 142a and a side surface of the first to third buffer layers 142a to 142c and the gate insulating layer 144. Next, as shown in Fig. 8D, the metal layer 114a is etched using the first to third PR patterns 160a, 160b, and 160c as an etch mask to form the gate electrode 114, the crack detection line PCD, and the bridge pattern BPAT. The gate electrode 114 is positioned above the semiconductor layer 112, and the crack detection line PCD and the bridge pattern BPAT are located in the non-indication area NA. The bridge pattern BPAT can be located in the trim hole TRIM and a portion of the upper surface of the gate insulating layer 144. Since the first buffer layer 142a is partially removed, the bridge pattern BPAT in the trim hole TRIM contacts an upper surface of the first buffer layer 142a. In the present disclosure, the bridge pattern BPAT is formed in the process of forming the gate electrode 114 and the crack detection line PCD for the following reasons. When the metal layer 114a is deposited, the thickness of the metal layer 114a on a side face (e.g., an inclined surface) in the trim hole TRIM is less than the thickness of the metal layer 114a on a top surface of the gate insulating layer 144. Accordingly, as shown in Fig. 9A, when the etching process, e.g., a dry etching process, is carried out on the metal layer 114a without the third PR pattern 160c (from Fig. 8C), which corresponds to the trim hole TRIM, the metal layer 114a on the side face in the trim hole TRIM is removed first. Accordingly, as shown in Fig. 9B, during the etching process the metal layer 114a1 on the gate insulating layer 144 and the metal layer 114a2 on a bottom of the trim hole TRIM are electrically insulated with the inclined surface of the trim hole TRIM in between. Since a plasma gas or a reactive gas is used in the dry etching process, static electricity can be generated during etching. This static electricity creates a potential difference between the metal layer 114a1 on the upper surface of the gate insulating layer 144 and the metal layer 114a2 at the bottom of the trim hole TRIM. This potential difference causes an arc discharge between the metal layer 114a1 on the upper surface of the gate insulating layer 144 and the metal layer 114a2 at the bottom of the trim hole TRIM. The second PR pattern 160b on the metal layer 114a1 can be damaged by this arc discharge. As a result, the second PR pattern 160b can be damaged or lost. Furthermore, due to static electricity during the etching process, an impulse voltage may be generated in the preceding section of the second buffer layer 142b, and the second PR pattern 160b may be damaged or lost due to the impulse voltage. The problem may arise that the crack detection line PCD was damaged or interrupted during its formation due to damage to or loss of the second PR sample 160b. In other words, problems such as the crack detection line PCD not forming at all or having a poor line width may occur. On the other hand, according to the present disclosure, the formation of the third PR pattern 160c in the trim hole TRIM prevents the metal layer 114a formed on the inclined surface of the trim hole TRIM from being etched during the etching process of the metal layer 114a. Accordingly, the metal layer 114a on the upper surface of the gate insulating layer 144 and the metal layer 114a inside the trim hole TRIM are in an electrically connected state during the etching process, so that an arc discharge due to static electricity generated during the etching process can be reduced or prevented. Furthermore, by blocking the interior of the trim hole TRIM from the outside with the third PR pattern 160c, it is possible to reduce or prevent the generation of an impulse voltage caused by static electricity generated during the etching process in the protruding section of the second buffer layer 142b. As described above, in the present disclosure, by forming the third PR pattern 160c, which corresponds to the trim hole TRIM, a defect in the crack detection line PCD due to static electricity during the process can be reduced or prevented. Referring to Fig. 8E, an intermediate insulating layer 146 is formed by depositing an organic insulating material, e.g., photoacrylic, or an inorganic insulating material, e.g., silicon nitride (SiNx) or silicon dioxide (SiOx). A metal, e.g., Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy, is applied to the intermediate insulating layer 146 by a sputtering process and etched to form a source electrode 115 and a drain electrode 116. The source and drain electrodes 115 and 116 are each in ohmic contact with the source and drain regions 112b and 112c of the semiconductor layer 112 via a contact hole in the intermediate insulating layer 146. The TFT T is produced by the above processes. Next, a planarization layer 148 is formed in the display area AA and a cover layer 149 is formed in the non-display area NA by applying an organic insulating material, e.g., photoacrylic, or an inorganic insulating material, e.g., silicon nitride (SiNx) or silicon dioxide (SiOx). The planarization layer 148 and the cover layer 149 can be formed by the same process. That is, the step to form the planarization layer 148 and the step to form the cover layer 149 are performed simultaneously. Alternatively, the planarization layer 148 and the cover layer 149 can be formed by different processes. The planarization layer 148 is positioned in the display area AA. The cover layer 149 is positioned in the trim hole TRIM.For example, the cover layer 149 comprises a first cover layer at a first section of the trim hole TRIM and a second cover layer at a second section of the trim hole TRIM. The first and second cover layers are spaced apart from each other with respect to the center of the trim hole TRIM. Next, a first electrode 132 is formed on the planarization layer 148. For example, a transparent conductive oxide material, e.g., ITO or IZO, a metal, e.g., Ag, Au, Mo, W, or Cr, and another transparent conductive oxide material, e.g., ITO or IZO, are stacked and etched sequentially to form the first electrode 132, which has a three-layer structure consisting of a transparent conductive layer, a metal layer, and another transparent conductive layer. The first electrode 132 is connected to the drain electrode 116 of the TFT T via a contact hole in the planarization layer 148. Next, at least one material is applied to the planarization layer 148, consisting of an inorganic insulating material, e.g., SiNx or SiOx, an organic insulating material, e.g., benzocyclobutene (BCB), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, or a photosensitive agent containing a black pigment, and etched using a dry etching process to form a bank of BNK. Additionally, a dam of DAM is formed in the non-display area NA, comprising a first layer of the same material as the planarization layer 148 and a second layer of the same material as the bank of BNK. Next, an emissive material is applied to the display area AA and a translucent (e.g., semi-transparent) alloy, e.g., LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag or LiF / Ca:Ag, is applied to form a light-emitting layer 134 and a second electrode 136. Next, an encapsulation layer 180 is formed, comprising a first inorganic layer (e.g., first encapsulation layer 182) made of an inorganic insulating material, an organic layer (e.g., second encapsulation layer 184) made of an organic insulating material, and an inorganic layer (e.g., third encapsulation layer 186) made of an inorganic insulating material. The display device 100 (or the light-emitting element (e.g., OLED) D) is encapsulated by the encapsulation layer 180. Next, the substrate 140 is cut and trimmed along the trim hole TRIM to create the display device 100 in Fig. 8F. The substrate 140 can be cut using various methods. For example, it can be cut using a mechanical cutting device such as a cutting wheel or with a laser. When using a laser cutting device, a carbon dioxide laser can be used, but this is not the only option. The substrate 140 can also be trimmed using various methods. For example, the substrate 140 can be trimmed with a laser. The laser can be an Nd:YAG laser, but is not limited to this. By cutting and trimming, the outer area of ​​the display area AA around the center of the trim hole TRIM is removed. This allows the display device 100 to be created with the desired shape. As described above, in the display device of the present disclosure, the trim hole TRIM is provided in a trimming area where the substrate is cut and trimmed, and a PR pattern is formed in the trim hole during the process of forming the crack detection line PCD. This keeps the crack detection line PCD and the bridge pattern BPAT at the same potential, so that damage to or loss of the PR pattern used to form the crack detection line PCD can be reduced or prevented. Accordingly, defects in the crack detection line PCD due to damage to and / or loss of the PR pattern can be reduced or prevented. Fig. 10 is a schematic top view of a section of a display device according to a further embodiment of the present disclosure. As shown in Fig. 10, the display device 200 comprises a display panel PNL (from Fig. 4) with a display area AA for displaying an image and a non-display area NA outside the display area AA. A trim hole TRIM is formed on an outer edge of the non-display area NA of the display panel PNL. The trim hole TRIM serves to separate a mother substrate on which several display panels PNL are formed into individual display panels PNL or to produce a display device with a different shape. The trim hole TRIM has a predetermined width extending from the outer edge of the non-display area NA to the display area AA. A crack detection line PCD is located between the trim hole TRIM and the display area AA. The crack detection line PCD is positioned at a predetermined distance from the trim hole TRIM. The trim hole TRIM extends along the entire circumference of the display panel PNL, and the crack detection line PCD is located along at least three sides of the display panel PNL. Accordingly, the trim hole TRIM and the crack detection line PCD can be adjacent along at least three sides of the display panel PNL. A bridge pattern BPAT is formed in the trim hole TRIM. The bridge pattern BPAT extends from the trim hole TRIM to the crack detection line PCD and can be electrically connected to the crack detection line PCD. In this case, the crack detection line PCD and the bridge pattern BPAT can be formed as a single unit. Those skilled in the art will recognize that various modifications and variations of the embodiments of the present disclosure are possible. Therefore, the modifications and variations are intended to cover this disclosure, provided they fall within the scope of the appended claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0196879

[0001]

Claims

Display device (100) comprising: a substrate (140) having a display area (AA) and a non-display area (NA) outside the display area (AA); a light-emitting element (D) in a pixel in the display area (AA); a trim hole (TRIM) in a border of the non-display area (NA); a crack detection line (PCD) arranged between the trim hole (TRIM) and the display area (AA) and surrounding the display area (AA); and a bridge pattern (BPAT) at least in the trim hole (TRIM). Display device (100) according to claim 1, further comprising: a buffer layer (142) on the substrate (140); and a thin-film transistor (T) in the pixel and on the buffer layer (142), wherein the thin-film transistor (T) comprises a semiconductor layer (112) on the buffer layer (142), a gate insulating layer (144) on the semiconductor layer (112), a gate electrode (114) on the gate insulating layer (144), an intermediate insulating layer (146) on the gate electrode (114), a source electrode (115) and a drain electrode (116) on the intermediate insulating layer (146). Display device (100) according to claim 2, wherein the crack detection line (PCD) is formed from the same material and is arranged on the same layer as the gate electrode (114). Display device (100) according to claim 2 or 3, wherein the bridge pattern (BPAT) is formed from the same material and arranged on the same layer as the gate electrode (114). Display device (100) according to one of the preceding claims, wherein the bridge pattern (BPAT) comprises several patterns arranged along the trim hole (TRIM) and spaced apart from each other. Display device (100) according to one of the preceding claims, wherein the bridge pattern (BPAT) is arranged as an integrated body along the trim hole (TRIM). Display device (100) according to one of claims 2 to 6, wherein the bridge pattern (BPAT) extends from the trim hole (TRIM) to an upper surface of the gate insulating layer (144) outside the trim hole (TRIM). Display device (100) according to one of claims 2 to 7, wherein the bridge pattern (BPAT) is connected to the crack detection line (PCD) on the gate insulating layer (144). Display device (100) according to any one of claims 2 to 8, wherein the buffer layer (142) comprises a first buffer layer (142a) on the substrate (140), a second buffer layer (142b) on the first buffer layer (142a) and a third buffer layer (142c) on the second buffer layer (142b). Display device (100) according to claim 9, wherein the trim hole (TRIM) is provided in the first to third buffer layer (142a, 142b, 142c) and the gate insulating layer (144), and wherein, from a side face of the trim hole (TRIM), the second buffer layer (142b) protrudes more than the first and third buffer layers (142a, 142c). Display device (100) according to claim 9 or 10, wherein a side surface of the second buffer layer (142b), a section of a lower surface of the second buffer layer (142b) and a section of an upper surface of the second buffer layer (142b) are covered by the bridge pattern (BPAT). Display device (100) according to one of the preceding claims, further comprising: a cover layer (149) in the trim hole (TRIM) designed to cover the bridge pattern (BPAT). Display device (100) according to one of the preceding claims, wherein the bridge pattern (BPAT) comprises a first bridge pattern section located in the trim hole (TRIM) and a second bridge pattern section located outside the trim hole (TRIM). Display device (100) according to claim 13, wherein the first bridge pattern section is designed to continuously cover an inner wall of the trim hole (TRIM) and is connected to the second bridge pattern section. A method for manufacturing a display device (100) comprising: forming a buffer layer (142) on a substrate (140) having a display area (AA) and a non-display area (NA); forming a semiconductor layer (112) on the buffer layer (142) and in the display area (AA); forming a gate insulating layer (144) on the buffer layer (142) such that it covers the semiconductor layer (112); forming a trim hole (TRIM) along a circumference of the display area (AA) by etching the buffer layer (142) and the gate insulating layer (144); forming a metal layer (114a) on the gate insulating layer (144) and in the trim hole (TRIM); forming a first photoresist pattern on the metal layer (114a) corresponding to the display area (AA), and a second photoresist pattern on the metal layer (114a) corresponding to the display area (AA). corresponding to the non-display area (NA), and a third photoresist pattern on the metal layer (114a) corresponding to the trim hole (TRIM);Structuring the metal layer (114a) using the first to third photoresist pattern to form a gate electrode (114) in the display area (AA), a crack detection line (PCD) in the non-display area (NA), and a bridge pattern (BPAT) in the trim hole (TRIM); forming an interlayer insulating layer (146) on the gate electrode (114) and the crack detection line (PCD); forming a source electrode (115) and a drain electrode (116) on the interlayer insulating layer (146) and in the display area (AA); forming a light-emitting element (D) over the drain electrode (116); cutting and trimming the substrate (140) along the trim hole (TRIM). Method according to claim 15, wherein the step of structuring the metal layer (114a) comprises etching the metal layer (114a) using an etching gas, and wherein the etching gas is blocked towards the trim hole (TRIM) by the third photoresist pattern. Method according to claim 15 or 16, further comprising: forming a planarization layer (148) on the drain electrode (116) and under the light-emitting element (D). Method according to any one of claims 15 to 17, further comprising: forming a cover layer (149) that covers the trim hole (TRIM). Method according to claims 17 and 18, wherein the step of forming the planarization layer (148) and the step of forming the cover layer (149) are carried out simultaneously. Method according to any one of claims 15 to 19, wherein the buffer layer (142) comprises a first buffer layer (142a) on the substrate (140), a second buffer layer (142b) on the first buffer layer (142a) and a third buffer layer (142c) on the second buffer layer (142b), wherein the trim hole (TRIM) is provided in the first to third buffer layers (142a, 142b, 142c) and the gate insulating layer (144), and wherein, from a side face of the trim hole (TRIM), the second buffer layer (142b) protrudes more than the first and third buffer layers (142a, 142c).

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