Light-emitting indicator device

Abstract

A light-emitting display device includes a sampler circuit comprising a sampler stage with a first buffer section that outputs a first sample signal, and a first and second buffer section that output two second sample signals. The first buffer section includes first and second buffer transistors connected to a common BG node. The second-first buffer section includes a third buffer transistor connected to a SQ node and a fourth buffer transistor connected to the BG node. The second-second buffer section includes a fifth buffer transistor connected to the SQ node and a sixth buffer transistor connected to the BG node.The first buffer transistor receives a gate high voltage, the second, fourth and sixth buffer transistors receive a gate low voltage, and the third and fifth buffer transistors each receive a second first sampling clock and a second-second sampling clock.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS This application claims the benefits and priority of Korean patent application No. 10-2024-0195685, which was filed in the Republic of Korea on December 24, 2024. BACKGROUND Technical field The present disclosure relates to a light-emitting display device. Discussion of the state of the art With the development of the information society, the demand for display devices for showing images in various forms has increased, and in recent years various flat display devices such as organic light-emitting display devices and liquid crystal display devices have been used. A gate driver circuit of a light-emitting display device includes a sampler driver circuit that generates a sample signal. A buffer transistor in one stage of the sampler driver circuit, which outputs the sample signal, has a width greater than the vertical length of the stage. Accordingly, the buffer transistor is arranged in a horizontal direction, so that the width of a non-display area of ​​a display field in which the sampler driver circuit is located increases. Therefore, the bezel around the light-emitting display device increases, making it difficult to achieve a narrow bezel. The description of the prior art should not be considered prior art simply because it is mentioned in or associated with this section. The description of the prior art includes information that describes one or more aspects of the technology at issue, and the description in this section does not limit the scope of the present disclosure. PRESENTATION OF THE INVENTION The problems mentioned above are solved by the features of the independent claims. Advantageous embodiments can be derived from the respective dependent claims. In one or more aspects, an advantage of the present disclosure is to provide a light-emitting display device that can implement a narrow bezel by modifying the design of a sampler driver circuit such that a buffer transistor is arranged in a vertical direction. Additional features and advantages of the disclosure are set forth in the following description and are partly evident from the description itself or can be learned through practical application of the disclosure. These and other advantages of the disclosure are realized and achieved through the structure, which is set forth in particular in the written description and the claims thereto, as well as in the accompanying drawings. In one aspect, a light-emitting display device includes a display array comprising a display area and a non-display area, wherein the display area contains pixels, a light-emitting diode, and a plurality of transistors electrically connected to the light-emitting diode within the pixel (meaning there are a plurality of pixels, and each pixel comprises a light-emitting diode and a plurality of pixels), and a sampler circuit located in the non-display area comprising a sampler stage comprising a first buffer section that outputs a first sample signal applied jointly to the pixels of two adjacent horizontal lines, and a second-first buffer section and a second-second buffer section that output two second sample signals, each applied to the pixels of the two adjacent horizontal lines.wherein the second-first buffer section includes a first buffer transistor and a second buffer transistor whose gate electrodes are connected to a BG node, wherein the second-second buffer section includes a fourth buffer transistor whose gate electrode is connected to the BG node, and a third buffer transistor whose gate electrode is connected to an SQ node which receives a voltage from an output terminal of the first buffer section, wherein the buffer section of the second type includes a sixth buffer transistor whose gate electrode is connected to the BG node, and a fifth buffer transistor whose gate electrode is connected to the SQ node, wherein the first buffer transistor receives a gate high voltage, and wherein the second,The fourth and sixth buffer transistors receive a gate low voltage, and the third and fifth buffer transistors receive a second-first sampling clock and a second-second sampling clock, respectively. The sampling stage can include a first control transistor and a second control transistor connected in parallel to each other, configured to receive a transmission signal, and connected to a CNT node. The sampling stage may further include a third control transistor and a fourth control transistor connected in series with the BG node in between, and having gate electrodes connected to the CNT node. The sampling stage may also include a transfer transistor that is connected between the output terminal of the first buffer section and the SQ node. The transmission signal can be a first sampling signal from a previous sampling stage. The first control transistor can be configured as an N-type transistor and can have a gate electrode for receiving a first B-type sampling clock signal. The second control transistor can be configured as a P-type transistor and can have a gate electrode for receiving a first sampling clock signal. The first sampling clock and the first B sampling clock can have opposite phases. The third control transistor can be configured as an N-type transistor and can have a source electrode for receiving the gate low voltage. The fourth control transistor can be configured as a P-type transistor and can have a source electrode for receiving the gate high voltage. The transfer transistor can have a gate electrode for receiving the gate high voltage. The sampler driver circuit can include nth and n+1th sample stages, corresponding to 2n-1th to 2n+2th horizontal lines of the display area, and are arranged on one side and the other side of the display area, respectively. The nth sampling stage can be set up to output an nth first sampling signal and 2n-1th and 2n-th second sampling signals to drive the 2n-1th and 2n-th horizontal lines. The n+1th sampling stage can be set up to output an n+1th first sampling signal and 2n+1th and 2n+2th second sampling signals to drive the 2n+1th and 2n+2th horizontal lines, where n is an integer. The width direction of the first, second, third, fourth, fifth and sixth buffer transistors of the sampling stage can be vertical. The light-emitting display device may further comprise an nth emission stage located on the other side of the display area and an n+1th emission stage located on one side of the display area. The nth emission stage can be set up to output an nth emission control signal to control the 2n-1th and 2n-th horizontal lines. The n+1 emission stage can be set up to output an n+1 emission control signal to control the 2n+1 and 2n+2 horizontal lines. The pixel can include a drive transistor; a first transistor that is connected between a gate electrode and a drain electrode of the drive transistor and can be configured to receive the first sampling signal; and a second transistor that is connected between a source electrode of the drive transistor and a data line and can be configured to receive one of the two second sampling signals. In one aspect, a light-emitting display device includes a display field comprising a display area and a non-display area, wherein the display area includes pixels, a light-emitting diode, and a plurality of transistors electrically connected to the light-emitting diode within the pixel, and a plurality of sampling stages in the non-display area, wherein each of the plurality of sampling stages includes a first buffer section that outputs a first sampling signal applied jointly to the pixels of two adjacent horizontal lines, and a second-first buffer section and a second-second buffer section that output two second sampling signals, each applied to the pixels of the two adjacent horizontal lines, wherein the plurality of sampling stages includes nth and n+1th sampling stages.the 2n-1th to 2n+2th horizontal lines of the display area and are arranged on one side and the other side of the display area, wherein the nth sampling stage outputs an nth first sampling signal and 2n-1th and 2n-th second sampling signals to control the 2n-1th and 2n-th horizontal lines, and wherein the n+1th sampling stage outputs an n+1th first sampling signal and 2n+1th and 2n+2th second sampling signals to control the 2n+1th and 2n+2th horizontal lines. The first buffer section can include a first buffer transistor and a second buffer transistor. A gate electrode of the first buffer transistor and a gate electrode of the second buffer transistor can be connected together via a BG node. The second-first buffer stage can include a third buffer transistor and a fourth buffer transistor. A gate electrode of the third buffer transistor can be connected to an SQ node to receive a voltage from an output terminal of the first buffer stage. A gate electrode of the fourth buffer transistor can be connected to the BG node. The second-to-second buffer section can include a fifth buffer transistor and a sixth buffer transistor. One gate electrode of the fifth buffer transistor can be connected to the SQ node. One gate electrode of the sixth buffer transistor can be connected to the BG node. The first buffer transistor can be configured to receive a gate high voltage. Each of the second, fourth, and sixth buffer transistors can be configured to receive a gate low voltage. The third and fifth buffer transistors can be configured to receive a second first sampling clock and a second-second sampling clock, respectively. Each of the multiple sampling stages can include a first control transistor and a second control transistor connected in parallel. These transistors can be configured to receive a transmission signal and can be connected to a CNT node. A third control transistor and a fourth control transistor can be connected in series with the BG node in between, and can have gate electrodes connected to the CNT node. Each of the multiple sampling stages can include a transfer transistor that is connected between the output terminal of the first buffer section and the SQ node. The nth sampling stage can be configured to receive a first sampling signal from an n-2th sampling stage, which is located on one side of the display area, as the transmission signal. The n+1th sampling stage can be configured to receive a first sampling signal from an n-1th sampling stage located on the opposite side of the display area as the transmission signal. The width direction of the first, second, third, fourth, fifth and sixth buffer transistors of each of the multitude of sampling stages can be vertical. The light-emitting display device may further comprise an nth emission stage located on the other side of the display area and an n+1th emission stage located on one side of the display area. The nth emission stage can be set up to output an nth emission control signal to control the 2n-1th and 2n-th horizontal lines. The n+1 emission stage can be set up to output an n+1 emission control signal to control the 2n+1 and 2n+2 horizontal lines. The pixel can include a drive transistor; a first transistor that is connected between a gate electrode and a drain electrode of the drive transistor and can be configured to receive the first sampling signal; and a second transistor that is connected between a source electrode of the drive transistor and a data line and can be configured to receive one of the two second sampling signals. In one or more aspects of the present disclosure, a light-emitting display device comprises: a display area and a non-display area; and a sampler driver circuit located in the non-display area, comprising a sampler stage comprising a first buffer section configured to output a first sample signal, and a first buffer section and a second buffer section configured to output second sample signals, wherein the first buffer section, the first buffer section, and the second buffer section share control nodes to jointly drive corresponding horizontal lines using the first sample signal and to each drive the corresponding horizontal lines individually using the second sample signals. One of the second sampling signals can control one of the corresponding horizontal lines, and another of the second sampling signals can control another of the corresponding horizontal lines. The control nodes can include an input node and an output node of the first buffer section. The input node can be connected to the gate electrodes of transistors in the first buffer section. The input node can be connected to a gate electrode of a transistor of the first buffer and to a gate electrode of a transistor of the second buffer section. The output node can be connected to a gate electrode of another transistor of the first buffer and to a gate electrode of another transistor of the second buffer section. The output node is set up to output the first sample signal. The transistors of the first buffer section, the transistor and the other transistor of the first buffer, and the transistor and the other transistor of the second buffer can be arranged in a vertical direction that is perpendicular to a direction of the corresponding horizontal lines. As described above, in the embodiment of the present disclosure, the sampling stages can be provided on both sides of the display area in a unit of four horizontal lines, and in each sampling stage, the first buffer section that outputs the first sampling signal, and the first buffer section and the second buffer section that output the two second sampling signals, can share the control nodes, so that each sampling stage can output the first sampling signal and the two second sampling signals that drive the two horizontal lines. Accordingly, the vertical length of the sampling stage can be greater than the widths of the buffer transistors, so that the buffer transistors forming the sampling stage can be arranged vertically, thereby reducing the width of the sampling stage. Therefore, the width of the non-display area of ​​the light-emitting display device can be reduced, so that the light-emitting display device can effectively implement a narrow bezel. Additional features, advantages, and aspects of the present disclosure are partly set forth in the following description and partly become apparent from the present disclosure or can be learned through the practical implementation of the inventive concepts provided herein. Other features, advantages, and aspects of the present disclosure can be realized and achieved through, or derived from, the descriptions provided in the present disclosure and the claims thereto, as well as the drawings. It is intended that all such features, advantages, and aspects are contained in this description, are within the scope of the present disclosure, and are protected by the following claims. Nothing in this section should be considered a limitation of these claims. Further features, advantages, and aspects are discussed below in connection with embodiments of the present disclosure. It is understood that both the preceding general description and the following detailed description are examples and explanations and are intended to provide a further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the present disclosure, are integrated into and form part of the present disclosure, illustrate aspects and embodiments of the present disclosure, and, together with the description, serve to explain principles and examples of the disclosure. In the drawings, Fig. 1 shows a view schematically illustrating a light-emitting display device according to an embodiment of the present disclosure; Fig. 2 shows a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present disclosure; Fig. 3 shows a view illustrating a configuration of a gate driver section of a light-emitting display device according to an embodiment of the present disclosure; Fig.Figure 4 is a view schematically illustrating the structure of a sampling stage of a sampler driver circuit according to an embodiment of the present disclosure; Figure 5 is a waveform view schematically illustrating the timing of signals driving a sampling stage according to an embodiment of the present disclosure; Figure 6 is a view comparing non-display areas of display fields according to a comparative example and an embodiment of the present disclosure; and Figure 7 is a cross-sectional view schematically illustrating an example of a cross-sectional structure of a display field according to an embodiment of the present disclosure. Unless otherwise specified, the same drawing reference symbols in the drawings and detailed descriptions are to be understood as referring to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, areas, and elements, and their representation, may be exaggerated for the sake of clarity, illustration, and / or practicality. DETAILED DESCRIPTION Extensive reference will now be made to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. Where a detailed description of well-known processes, functions, structures, or configurations might unnecessarily obscure aspects of the present disclosure, such a detailed description may have been omitted for the sake of brevity. Furthermore, repetitive descriptions may be omitted for the sake of brevity. The sequence of processing steps and / or operations described is a non-limiting example. The sequence of steps and / or operations is not limited to that set forth herein and may be modified to occur in an order different from that described herein, except that steps and / or operations necessarily occur in a particular order. In one or more examples, two successive operations may be performed substantially simultaneously, or the two operations may be performed in reverse order or in a different order depending on a function or operation involved. Unless otherwise specified, the same reference numerals may refer to the same elements throughout, even if they are shown in different drawings. Unless otherwise specified, the same reference numerals may be used to refer to the same or substantially the same elements throughout the description and drawings. In one or more aspects, identical elements (or elements with identical names) in different drawings may have the same or substantially the same functions and properties, unless otherwise specified. The names of the respective elements used in the following explanations are chosen for convenience only and may therefore differ from those used in actual products. The advantages and features of the present disclosure and its implementation methods are clarified by the embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are examples and are provided so that this disclosure may be thorough and complete to help those skilled in the art understand the inventive concepts without limiting the protected scope of the present disclosure. Shapes, dimensions (e.g., sizes, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), proportions, ratios, angles, numbers, the number of elements disclosed herein, and the like, including those illustrated in the drawings, are merely examples, and thus the present disclosure is not limited to the illustrated details. It is noted, however, that the relative dimensions of the components illustrated in the drawings are part of the present disclosure. When the term “comprises”, “has”, “includes”, “contains”, “forms”, “made of”, “formed of”, “composed of”, or the like is used in reference to one or more elements (e.g., layers, films, components, electrodes, structures, nodes, transistors, sections, elements, parts, areas, surfaces, segments, stages, operations, and / or the like), one or more other elements may be added unless a term such as “only” or the like is used. The terms used in this disclosure are used merely to describe certain exemplary embodiments and are not intended to limit the scope of this disclosure. Any references to the singular may include the plural and vice versa, unless expressly stated otherwise.In one or more examples, an element may be one or more elements unless expressly stated otherwise; and an element may contain a plurality of elements. The word "exemplary" is used to mean that it serves as an example or illustration. Embodiments are exemplary embodiments. Aspects are exemplary aspects. In one or more implementations, "embodiments," "examples," "aspects," and the like should not be construed as preferable or advantageous over other implementations. An embodiment, an example, an exemplary embodiment, an aspect, or the like may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, or the like, unless stated otherwise.Furthermore, the term "can" encompasses all meanings of the term "can". In one or more aspects, unless explicitly stated otherwise, an element, feature, or related information (e.g., a level, range, dimension, size, or the like) is interpreted as containing an error or tolerance range, even if no explicit description of such an error or tolerance range is provided. An error or tolerance range may be caused by various factors (e.g., process factors, internal or external influences, noise, or the like). When interpreting a numerical value, the value is interpreted as containing an error range unless explicitly stated otherwise. When a positional relationship between two elements (e.g., layers, films, components, electrodes, structures, nodes, transistors, sections, elements, parts, areas, surfaces, segments, and / or the like) is described using any of the following terms such as "on," "on a top of," "on," "on a top of," "above," "below," "over," "upper," "at an upper section," "at an upper side," "below," "lower," "at a lower section," "at a lower side," "below," "near," "adjacent to," "next to," "next to," "on or on a side of," and / or the like, indicating a position or location, one or more other elements may be located between the two elements unless a restrictive term such as "immediately," "directly," or "nearly" is used.For example, when one element and another element are described using any of the preceding terms, this description should be interpreted as including a case where the elements are directly touching each other, as well as a case where one or more additional elements are positioned or arranged between them. Furthermore, spatially relative terms such as those above, as well as other terms like "front," "back," "left," "right," "top," "bottom," "upper," "lower," "downward," "upward," "upward," "column," "row," "vertical," "horizontal," "diagonal," and the like, refer to any frame of reference. For example, these terms can be used to illustrate a relative relationship between elements, including any correlation, as shown in the drawings.However, embodiments of the disclosure are not limited by or to this. The spatially relative terms are to be understood as terms that, in addition to the orientation shown in the drawings or described herein, include different orientations of the elements in use or operation. For example, if a lower element or an element positioned below another element is inverted, then the element may be described as an upper element or an element positioned above another element. An exemplary term such as "below" or the like may include all directions, including directions of "below," "above," and diagonal directions. Likewise, an exemplary term such as "above," "on," or the like may include all directions, including directions of "above," "on," "below," and diagonal directions. When describing a temporal relationship, for example, when the temporal sequence is described as "after", "following", "subsequent", "next", "preceding", "preceding", or the like, a case that is not consecutive or non-sequential may be included, and thus one or more other events may occur in between, unless a restrictive term such as "only", "immediately" or "directly" is used. It is understood that, although the terms "first", "second", "first-second", "second-first", "second-second", "first B", "A", "B", "(a)", "(b)", node-identifying terms (e.g., BG, SQ, QB, CNT, NO1, NO2_1, and NO2_2), transistor-identifying terms (e.g., TA, T1b, T2b, Tb3, Tb4, Tb5, Tb6, Ts1, Ts2, Ts3, and Ts4), and the like may be used herein to describe various elements (e.g., layers, films, components, electrodes, structures, nodes, transistors, sections, elements, parts, areas, surfaces, segments, stages, operations, and / or the like), these elements should not be restricted by these terms, for example, to a particular sequence, ranking, or number of elements. Furthermore, these terms are not used to define the nature or basis of the elements. These terms are used simply to refer to one element separately from another.For example, a first element may denote a second element, and likewise a second element may denote a first element, without deviating from the scope of the present disclosure. Furthermore, the first element, the second element, and the like may be named arbitrarily, according to the expediency of the person skilled in the art, without deviating from the scope of the present disclosure. For the sake of clarity, the functions or structures of these elements (e.g., the first element, the second element, and the like) are not limited by ordinal numbers or the names preceding the elements. Furthermore, a first element may comprise one or more first elements. Likewise, a second element or the like may comprise one or more second elements or the like. The expression that an element (e.g., layer, film, component, electrode, structure, transistor, section, element, part, area, surface, or the like) is "interacting" with another element can be understood, for example, as meaning that the element is either directly or indirectly involved with the other element. The term "interacting" or similar expressions may refer to a concept such as "covers," "surrounds," "is in contact," "overlaps," "crosses," "cuts," "is connected," "is coupled," "is attached," "is bonded," "is combined," "is linked," "is provided," "is arranged," "interacts," or the like. The interaction may involve one or more interposed elements that are positioned or arranged between the element and the other element, unless otherwise specified.Furthermore, the element may engage at least partially or completely (or entirely) with the other element, unless otherwise specified. Furthermore, the element may be contained within at least one of two or more elements that engage with each other. Likewise, the other element may be contained within at least one of two or more elements that engage with each other. If the element engages with the other element, at least one section of the element may engage with at least one section of the other element. The phrase "with another element" or similar expressions may be understood as "another element" or "with, on, in, or upon another element," whichever is appropriate to the context. Likewise, the phrase "with each other" may be understood as "together" or "with, on, or upon each other," whichever is appropriate to the context. The term "through" can be understood, for example, to mean that it is at least partially continuous or completely continuous. Terms such as “line” or “direction” should not be interpreted solely on the basis of a geometric relationship in which the respective lines or directions are parallel, perpendicular, diagonal, or inclined in relation to each other, and may be meant as lines or directions with broader directional effects within the area within which the components of the present disclosure can operate functionally.For example, the terms “first direction”, “second direction”, “horizontal direction”, “vertical direction”, “latitude direction”, “latitude direction”, “longitudinal direction”, “longitudinal direction”, and the like should not be interpreted solely on the basis of a geometric relationship in which the respective directions are parallel, perpendicular, diagonal, or inclined relative to each other, and may be meant as directions with broader directional effects within the range within which the components of the present disclosure can operate functionally. The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, each of the expressions "at least one of a first element, a second element, or a third element" and "at least one of a first element, a second element, and a third element" can represent (i) a combination of elements provided by two or more of the first element, the second element, and the third element, or (ii) only one of the first element, the second element, or the third element. Furthermore, "at least one of a plurality of elements" can represent (i) one element of the plurality of elements, (ii) some elements of the plurality of elements, or (iii) all elements of the plurality of elements.Furthermore, “at least some”, “a few”, “at least some sections”, “at least some parts”, “at least one section”, “at least one or more sections”, “at least one part”, “at least one or more parts”, “at least some elements”, “one or more”, or the like of a multitude of elements can represent (i) one element of the multitude of elements, (ii) a section (or part) of the multitude of elements, (iii) one or more sections (or parts) of the multitude of elements, (iv) one or more elements of the multitude of elements, (v) several elements of the multitude of elements, or (vi) all of the multitude of elements.Furthermore, “at least some”, “some”, “at least some sections”, “at least some parts”, “at least one section”, “at least one or more sections”, “at least one part”, “at least one or more parts” or the like of an element can represent (i) a section (or part) of the element, (ii) one or more sections (or parts) of the element, (iii) the element or (iv) all sections of the element. The expression "and / or" of a first element, a second element, or a third element is to be understood as any one of the first, second, and third elements, or as any or all combinations of the first, second, and third elements. Similar interpretations apply to the use of "and / or" with two elements or with more than three elements. For example, A, B, and / or C may refer to only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); a combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. Furthermore, the expression "A / B" may be understood as A and / or B. For example, the expression "A / B" may refer to only A; only B; A or B; or A and B. In one or more aspects, the terms "between" and "under" can simply be used interchangeably for convenience, unless otherwise specified. For example, an expression "between a multitude of elements" can be understood as "under a multitude of elements." In another example, an expression "under a multitude of elements" can be understood as "between a multitude of elements." In one or more examples, the number of elements can be two. In one or more examples, the number of elements can be more than two. Furthermore, when an element is described as being "between" at least two elements, the element can be the only element between the at least two elements, or there can be one or more elements in between. In one or more aspects, the expressions "each other" and "each other" can simply be used interchangeably for convenience, unless otherwise indicated. For example, an expression "different from each other" can be understood as different from each other. In another example, an expression "different from each other" can be understood as different from each other. In one or more examples, the number of elements involved in the preceding expression can be two. In one or more examples, the number of elements involved in the preceding expression can be more than two. In one or more aspects, the expressions "one or more among" and "one or more of" may simply be used interchangeably for convenience, unless otherwise specified. In one or more aspects, unless otherwise specified, the term "nth" may refer to "nnd" (e.g., 2nd, where n is 2) or "nrd" (e.g., 3rd, where n is 3), and n may be a natural number or an integer, preferably an integer. That is, unless otherwise stated or clear from the context, the expression "using xa or b" means any of the natural inclusive permutations. For example, "a, b or c" can mean "a, b or c" or "a, b and c". The expression “essentially the same” or “nearly the same” can indicate a degree to which they are considered equivalent to each other, taking into account minute differences due to errors in the manufacturing process. Features of different embodiments of the present disclosure may be partially or completely coupled or combined, may be technically linked, and may be operated, linked, or driven together in different ways. Embodiments of the present disclosure may be implemented or executed independently of one another or may be implemented or executed together in a codependent or related relationship. In one or more aspects, the components of each device and apparatus according to different embodiments of the present disclosure are operationally coupled and configured. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meanings as they would normally be understood by an average person skilled in the field to which the examples of implementation belong. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense, unless expressly defined otherwise.For example, the term "part" or "unit" may refer to a circuit, a component, an integrated circuit, a computing block of a circuit device, or a structure configured to perform a described function, as it should be understood by an average professional in the field. The terms used here were chosen as generally applicable within the related technical field; however, other terms may exist depending on the development and / or change of technology, convention, the preferences of engineers, and so on. Therefore, the terms used here should not be understood as restrictive technical concepts, but rather as examples of terms used to describe embodiments. Furthermore, in a specific case, an applicant may arbitrarily choose a term, and in that case, its full meaning will be described here. Therefore, the terms used here should be understood not only on the basis of their names, but also on the basis of their meaning and content. In the following description, various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. With regard to reference numerals for elements in each of the drawings, identical or similar elements may be illustrated in other drawings, and identical reference numerals may refer to identical or similar elements unless otherwise specified. Identical or similar elements may be designated by the same reference numerals even if they are shown in different drawings. Repetitive descriptions of identical or similar elements may be omitted for brevity, and the descriptions provided for elements in one or more figures may also apply to elements in other figures that use the same or similar reference numerals unless otherwise specified.Additionally, for the convenience of description, the scale, dimension, size, and thickness of each of the elements illustrated in the accompanying drawings may differ from an actual scale, dimension, size, and thickness, and thus embodiments of the present disclosure are not limited to a scale, dimension, size, and thickness illustrated in the drawings. When describing the flow of a signal, for example when a signal is provided (e.g., transmitted or sent) from node A to node B, this may include a case where the signal is provided from node A to node B via one or more nodes, unless an expression such as "provided immediately", "provided directly", or the like is used. Fig. 1 is a view schematically illustrating a light-emitting display device according to an embodiment of the present disclosure. Fig. 2 is a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present disclosure. Fig. 3 is a view illustrating a configuration of a gate driver section of a light-emitting display device according to an embodiment of the present disclosure. Before a specific description, an organic light-emitting display device is described as an example of the light-emitting display device 10. Referring to Fig. 1, Fig. 2 to Fig. 3, the light-emitting display device 10 of this embodiment can include a display field 100 and a driver circuit section that controls the display field 100. Here, the driver circuit section can, for example, include a gate driver section (or gate driver circuit) 210, a data driver section (or data driver circuit) 220, and a timing section (or timing circuit) 240. Additionally, the driver circuit section can include a power supply section (or power supply circuit) 280, which provides the current required to drive the display panel 100, the gate driver section 210, the data driver section 220, and the timing section 240. The display field 100 can include a display area AA, which displays an image, and a non-display area NA, which is located outside of (or surrounding) the display area AA. In the display area AA, a multitude of pixels P can be arranged in a matrix form along a multitude of horizontal lines (or row lines) and a multitude of vertical lines (or column lines). Here, the multitude of pixels P can include pixels that display different colors, for example red, green and blue pixels that display red, green and blue respectively, but is not limited to that. In the display field 100, various signal lines that transmit control signals for controlling the pixels P can be formed on a substrate. In this respect, for example, a multitude of data lines DL, which transmit data signals (or data voltages), which are image signals, can extend in the vertical direction and be connected to the pixels P of the respective vertical lines. Additionally, a gate line GL, which carries a gate signal (or a gate voltage), can extend in the horizontal direction and be connected to the pixel P of the corresponding horizontal line. In this embodiment, a plurality of gate signals can be used to control each pixel P; for example, a first sampling signal SC1, a second sampling signal SC2, and an emission control signal EM can be used. Correspondingly, a plurality of gate lines GL, each carrying the plurality of gate signals, can be used; for example, a first sampling line SCL1, a second sampling line SCL2, and an emission control line EML can be used. As such, the multitude of pixels P can be defined by the multitude of data lines DL and gate lines GL that intersect each other. Each pixel P can contain a light-emitting diode OD as a light-emitting element and a plurality of transistors and at least one capacitor for driving the light-emitting diode OD. Meanwhile, for the sake of clarity in this embodiment, a 6T1C structure in which the pixel P is equipped with six transistors T1 to T5 and DT and a capacitor Cst, as illustrated in Fig. 2, is taken as an example. Referring to Fig. 2, the pixel P can include a light-emitting diode OD and a plurality of transistors electrically connected to the light-emitting diode OD. The pixel P can preferably include a plurality of switching transistors, for example, the first transistor T1 to the fifth transistor T5, a drive transistor DT, a storage capacitor Cst, and the light-emitting diode OD. Each of the first to fifth switching transistors T1 to T5 and the drive transistor DT can include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes can be a source electrode, and the other of the first and second electrodes can be a drain electrode. Each of the first to fifth transistors T1 to T5 and the drive transistor DT can be a P-type or N-type transistor. Figure 2 shows an example where the first, second, and fifth transistors T1, T2, and T5, and the drive transistor DT, are configured as N-type transistors, and the third and fourth transistors T3 and T4 are configured as P-type transistors, but are not limited to this configuration. The first transistor T1 through fifth transistor T5 and the driver transistor DT can contain semiconductors made of the same material or they can contain semiconductors made of different materials. For example, some of the first transistor T1 through fifth transistor T5 and the driver transistor DT may have a semiconductor layer consisting of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, while others may have a different semiconductor layer consisting of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer. An oxide semiconductor exhibits excellent reverse current properties, and polycrystalline silicon exhibits excellent mobility. In this embodiment, an example is given in which the first, second, and fifth transistors T1, T2, and T5, and the driver transistor DT, may have an oxide semiconductor layer, and the third and fourth transistors T3 and T4 may, but are not limited to, having a polycrystalline silicon layer. Meanwhile, for the sake of simplicity, pixel P of Fig. 2 can be one of the pixels P of adjacent odd and even horizontal lines driven by gate signals output from an nth stage of the gate drive section 210, e.g., one of the pixels P(2n-1) and P(2n) of a 2n-1 horizontal line and a 2n-th horizontal line. In one or more aspects, n can be a natural number. In one or more aspects, n can be an integer. In this respect, the gate signals provided to the 2n-1th or 2n-th horizontal line can, for example, be two sampling signals, e.g., a first sampling signal (SC1: SC1(n)) and a second sampling signal (SC2: SC2(2n-1) or SC2(2n)), and two emission control signals (EM: EM(n) and EM(n+2)). These gate signals can be described in more detail. The pixel P(2n-1) of the 2n-1th horizontal line can be provided by an nth first sampling signal SC1(n) and a 2n-1th second sampling signal SC2(2n-1) output by a corresponding nth sampling stage, an nth emission control signal EM(n) output by a corresponding nth emission stage, and an n+2th emission control signal EM(n+2) output by an n+2th emission stage, which is a subsequent emission stage. Additionally, the pixel P(2n) of the 2nth horizontal line can be provided with the nth first sampling signal SC1(n) and a 2nth second sampling signal SC2(2n) output by the corresponding nth sampling stage, the nth emission control signal EM(n) output by the corresponding nth emission stage, and the n+2th emission control signal EM(n+2) output by the n+2th emission stage, which is a subsequent emission stage. Thus, the first and second sampling signals SC1 and SC2, generated by a sampling stage in the gate driver section 210, and the emission control signal EM, also generated by an emission stage in the gate driver section 210, can be applied to two adjacent horizontal lines (e.g., odd and even horizontal lines). The sampling stage and the emission stage of the gate driver section 210 can be described in more detail below. In this case, a first and second scanning line SCL1 and SCL2 and an emission control line EML, which transmit the first and second scanning signal SC1 and SC2 and the emission control signal EM to the pixel P, can be arranged in the display area AA. The first transistor T1 can function as a sampling transistor, the second transistor T2 can function as a data supply transistor, the third and fourth transistors T3 and T4 can function as emission control transistors, and the fifth transistor T5 can function as an initialization transistor. The light-emitting diode OD can include an anode electrode and a cathode electrode. The anode electrode of the light-emitting diode OD can be connected to a fourth node N4, and the cathode electrode of the light-emitting diode OD can be subjected to a low-potential driver voltage EVSS. The driver transistor DT can, for example, include a first electrode connected to a third node N2, a second electrode connected to a second node N2, and a gate electrode connected to a first node N1. The driver transistor DT can supply a drive current to the light-emitting diode OD based on a voltage at the first node N1 (e.g., a voltage stored in the storage capacitor Cst). The first transistor T1 can include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode that receives the first sampling signal SC1(n). The first transistor T1 can be switched on in response to the first sampling signal SC1(n), so that the driver transistor DT can be in a diode-connected state in which the gate and drain electrodes of the driver transistor DT are electrically short-circuited, and a threshold voltage of the driver transistor DT can be sampled. The sampled threshold voltage of the driver transistor DT can be reflected at the first node N1. The storage capacitor Cst can be connected between the first node N1 and a fourth node N4. For the sake of clarity, an electrode of the storage capacitor Cst connected to the first node N1 can be called the first electrode, and an electrode of the storage capacitor Cst connected to the fourth node N4 can be called the second electrode. The second transistor T2 can include a second electrode connected to the data line DL (or receiving the data voltage Vdata), a first electrode connected to the third node N3, and a gate electrode that receives the second sampling signal SC2(2n-1) or SC2(n). The second transistor T2 can be switched on in response to the second sampling signal SC2(2n-1) or SC2(2n) and can transmit the data voltage Vdata to the third node N3. In this case, the data voltage Vdata applied to the third node N3 can be reflected to the first node N1 when the first transistor T1 is switched on, and as a result, the data voltage Vdata can be reflected to the gate electrode of the driver transistor DT. The third and fourth transistors T3 and T4 can be connected between a line carrying a high-potential drive voltage EVDD and the light-emitting diode OD, and can form a current path along which the drive current generated by the drive transistor DT flows. The third transistor T3 can include a first electrode connected to the drive transistor DT at the third node N3, a second electrode connected to the light-emitting diode OD at the fourth node N4, and a gate electrode that receives the corresponding nth emission control signal EM(n). The fourth transistor T4 can include a first electrode that receives the high-potential driver voltage EVDD, a second electrode that is connected to the second node N2, and a gate electrode that receives the n+2th emission control signal EM(n+2). The third and fourth transistors, T3 and T4, can be switched on in response to the corresponding emission control signals EM(n) and EM(n+2). When both the third and fourth transistors, T3 and T4, are switched on, the drive current can be supplied to the light-emitting diode OD, and the light-emitting diode OD can emit light with a luminance equal to the drive current. The fifth transistor T5 can include a second electrode connected to an initialization voltage line ViniL, which transmits an initialization voltage Vini, a first electrode connected to the fourth node N4, and a gate electrode that receives the corresponding emission control signal EM(n). The fifth transistor T5 can be switched on in response to the corresponding emission control signal EM(n), and the initialization voltage Vini can be applied to the anode electrode of the light-emitting diode OD (e.g., the fourth node N4). Accordingly, the anode electrode of the light-emitting diode OD can be initialized (or reset) with the initialization voltage Vini. The 6T1C structure of pixel P described above is an example, and pixel P of this embodiment may be configured with a different structure. Referring to Fig. 1, the timing section 240 can process image data Do, input from a host system, to be suitable for the size, resolution, etc., of the display field 100, and supply the processed image data Do to the data driver section 220. The timing section 240 can generate a gate control signal GCS and a data control signal DCS using synchronization signals input from the host system, for example, a dot clock signal CLK, a data release signal DE, a horizontal synchronization signal HSY, and a vertical synchronization signal VSY. By supplying the gate control signal GCS and the data control signal DCS generated in this way to the gate driver section 210 and the data driver section 220, respectively, the gate driver section 210 and the data driver section 220 can be controlled. The timing control section 240 can be configured to be combined with various processors, for example a microprocessor, a mobile processor, an application processor, etc., depending on the device to be mounted. Meanwhile, the host system can be, for example, a driver system that drives an electronic device to which the light-emitting display device 10 is applied. The electronic device can be, for example, a television (TV), a navigation system, a monitor, a mobile device, or a portable device. The gate driver section 210 can receive the gate control signal GCS from the timing control section 240, generate the gate signals, and apply the gate signals sequentially to the gate lines GL. For example, the gate signals can be output sequentially from top to bottom in the vertical direction. The gate driver section 210 can, for example, be arranged on at least one side of the display area AA. In this embodiment, a case is taken as an example in which the gate driver section 210 is configured to include a first and second gate driver section 211 and 212, which are arranged on both sides of the display area AA, for example, on the left and right sides of the display area AA. The gate driver section 210 can be formed directly in the non-display area NA on the substrate of the display field 100, for example in a GIP (gate-in-panel) structure. In this case, the gate driver section 210 can be formed during processes for forming elements of the display field 100. The gate driver section 210 can be configured with a GIP structure. The gate driver section 210 can include a sampler driver circuit. The sampler driver circuit can be located in the non-display area NA. The sampler driver circuit generates the first and second sample signals SC1 and SC2 together and outputs each of the first and second sample signals SC1 and SC2 sequentially, and an emission driver circuit outputs the emission control signal EM sequentially. Each of the sampler and emission driver circuits can contain a multitude of sample stages that output the corresponding signal(s). Each of the sampler and emission driver circuits can be configured with a shift register containing the multitude of stages that output the corresponding signals. The gate driver section 210 can be described with further reference to Fig. 3. Fig. 3 illustrates a part of the gate driver section 210, and for the convenience of the explanation, a configuration of a section of the gate driver section 210 that drives four consecutive horizontal lines in the display area AA, for example the 2n-1th, 2n-th, 2n+1th and 2n+2th horizontal lines, is illustrated. In the first gate driver section 211 of the gate driver section 210, sampling stages (SSC), which form the sampling driver circuit, and emission stages (SEM), which form the emission driver circuit, can be arranged. For example, odd (or even) sampling stages (e.g., SSC(n)) can be arranged in the first gate driver section 211 below all sampling stages (SSC) that form the sampling driver circuit. Additionally, even (or odd) emission stages (e.g., SEM(n+1)) can be arranged in the first gate driver section 211 below all emission stages that form the emission driver circuit. Additionally, in the second gate driver section 212 of the gate driver section 210, sampling stages SSC, which form the sampling driver circuit, and emission stages SEM, which form the emission driver circuit, can be arranged. For example, even (or odd) sampling stages (e.g., SSC(n+1)) can be arranged below all sampling stages that form the sampling driver circuit in the second gate driver section 212. Additionally, odd (or even) emission stages (e.g., SEM(n)) can be arranged below all emission stages that form the emission driver circuit in the second gate driver section 212. As described above, a plurality of sampling stages (SSC) forming the sampling driver circuit can be divided and arranged in the first and second gate driver sections 211 and 212, located on the left and right sides, respectively. Additionally, a plurality of emission stages (SEM) forming the emission driver circuit can be divided and arranged in the first and second gate driver sections 211 and 212, located on the left and right sides, respectively. In this embodiment, for the sake of clarity, an example is given in which the odd-numbered (e.g., n-th, n+2-th, n+4-th, etc.) sampling stages SSC are arranged in the first gate driver section 211, and the even-numbered (e.g., n+1-th, n+3-th, n+5-th, etc.) sampling stages SSC are arranged in the second gate driver section 212. Additionally, an example is given in which the even-numbered (n+1-th, n+3-th, n+5-th, etc.) emission stages SEM are arranged in the first gate driver section 211, and the odd-numbered (n-th, n+2-th, n+4-th, etc.) emission stages SEM are arranged in the second gate driver section 212. The arrangement of the sampling stages SSC and the emission stages SEM shown in Fig. 3 is an example, and they can be arranged in other ways. For example, the odd-numbered sampling stages SSC and the odd-numbered emission stages SEM can be arranged in the first gate driver section 211, and the even-numbered sampling stages SSC and the even-numbered emission stages SEM can be arranged in the second gate driver section 212. The sampling stage SSC can generate the first sampling signal SC1 and output it to the corresponding first sampling line SCL1 to provide it to the pixels P of the corresponding odd and even horizontal lines. For example, the nth sampling stage SSC(n) can generate the nth first sampling signal SC1(n), and the nth first sampling signal SC1(n) can be applied to the pixels P(2n-1) and P(2n) of the corresponding 2n-1 and 2n-th horizontal lines. Additionally, the n+1th sampling stage SSC(n+1) can generate the n+1th first sampling signal SC1(n+1), and the n+1th first sampling signal SC1(n+1) can be applied to the pixels P(2n+1) and P(2n+2) of the corresponding 2n+1 and 2n+2-th horizontal lines. Furthermore, the sampling stage SSC can sequentially generate two successive second sampling signals SC2 and output them to the corresponding second sampling lines SCL2 to provide them to the pixels P of the corresponding odd and even horizontal lines. For example, the nth sampling stage SSC(n) can sequentially generate the 2n-1th second sampling signal SC2(2n-1) and the 2nth second sampling signal SC2(2n), and the 2n-1th and 2nth second sampling signals SC2(2n-1) and SC2(2n) can be applied to the pixels P(2n-1) and P(2n) of the corresponding 2n-1th and 2nth horizontal lines, respectively. Additionally, the n+1th sampling stage SSC(n+1) can sequentially generate the 2n+1th second sampling signal SC2(2n+1) and the 2n+2th second sampling signal SC2(2n+2), and the 2n+1th and 2n+2th second sampling signals SC2(2n+1) and SC2(2n+2) can be applied to the pixels P(2n+1) and P(2n+2) of the corresponding 2n+1th and 2n+2th horizontal lines, respectively. The emission control stage SEM can generate the emission control signal EM and output it to the corresponding emission control line EML. For example, the nth emission stage SEM(n) can generate the nth emission control signal EM(n), and the nth emission control signal EM(n) can be applied to pixels P(2n-1) and P(2n) of the corresponding 2n-1th and 2nth horizontal lines. Additionally, the n+1th emission stage SEM(n+1) can generate the n+1th emission control signal EM(n+1), and the n+1th emission control signal EM(n+1) can be applied to pixels P(2n+1) and P(2n+2) of the corresponding 2n+1th and 2n+2th horizontal lines. Furthermore, as mentioned previously with reference to Fig. 2, the odd and even pixels P can receive the emission control signal EM, which is output by the emission stage SEM, which is arranged in a subsequent sequence to the corresponding emission stage SEM. For example, the n+2 emission control signal (EM(n+2) in Fig. 2), output by the n+2 emission stage SEM, which is arranged in a subsequent sequence to (or immediately after) the nth emission stage SEM(n) in the second gate drive section 212, can be applied to pixels P(2n-1) and P(2n) of the 2n-1 and 2n-th horizontal lines. Additionally, the n+3 emission control signal EM, output by the n+3 emission stage SEM, which is arranged in a subsequent sequence to (or immediately after) the n+1 emission stage SEM(n+1) in the first gate driver section 211, can be applied to pixels P(2n+1) and P(2n+2) of the 2n+1 and 2n+2 horizontal lines. As described above, in this embodiment each scanning stage SSC can generate the first and second scanning signals SC1 and SC2, which drive two horizontal lines of the display area AA, and each emission stage SEM can generate the emission control signal EM, which drives two horizontal lines of the display area AA. Additionally, the scanning stages SSC and the emission stages SEM, which sequentially perform scanning control, can be distributed and arranged on the left and right sides of the display area AA. Accordingly, the four horizontal lines of the display area AA can be used to arrange a scanning stage SSC and an emission stage SEM on each side of the display area AA as a single unit. According to this arrangement, buffer transistors provided in the sampling stage SSC, which output the sampling signals SC1 and SC2, can be arranged vertically, thereby reducing the widths of the non-display areas NA on both sides of the display field 100. Therefore, the bezel width of the light-emitting display device 10 can be reduced, effectively implementing a narrow bezel. In this respect, the buffer transistors (or their semiconductor layers) that output the sampling signals SC1 and SC2 in the sampling stage SSC have a large width (e.g., a width in a longitudinal direction), for example, approximately 120 µm. Furthermore, the vertical length of the non-display area NA, corresponding to each horizontal line of the display area AA, is, for example, approximately 80 µm. Accordingly, in a case where the sampling stages SSC are provided on both sides of the display area AA in a unit of a horizontal line, the vertical length of the sampling stage SSC is smaller than the width of the buffer transistor, so the buffer transistor must be arranged in the horizontal direction, which causes the width of the non-display area NA to widen. In this embodiment, however, the sampling stages SSC can be provided on both sides of the display area AA in a unit of four horizontal lines. Accordingly, the vertical length of the sampling stage SSC becomes greater than the width of the buffer transistor, so that a width orientation of the buffer transistor can be set in the vertical direction and thus the width of the non-display area NA can be narrowed. Therefore, the bezel width of the light-emitting display device 10 can be reduced, making it possible to implement a narrow bezel. Referring to Fig. 3, the initialization voltage line ViniL can be arranged between the gate driver section 210 and the display area AA. The initialization voltage line ViniL can supply the initialization voltage Vini from the power supply section 230 to the pixels P within the display area AA. In Fig. 3, the initialization voltage line ViniL is illustrated as being located on both the left and right sides of the display area AA, but not restricted to it, and the initialization voltage line ViniL can be located on either the left or right side. Furthermore, with reference to Fig. 3, one or more optical areas OA1 and OA2 can be arranged in the display area AA.The one or more optical areas OA1 and OA2 can be arranged to overlap one or more optical electronic devices, for example, a photographic device such as a camera (or an image sensor) and / or a detection sensor such as a proximity sensor and an illuminance sensor. For the operation of the optical electronic device, the one or more optical areas OA1 and OA2 can have a light-transmitting structure formed therein and can have a transmittance of a certain level or higher. In other words, the number of pixels P per unit area in the one or more optical areas OA1 and OA2 can be less than the number of pixels P per unit area in a regular area, with the exception of optical areas OA1 and OA2 in the display area AA.This means that the resolution of one or more optical areas OA1 and OA2 can be lower than the resolution of the regular area within the display area AA. Referring again to Fig. 1, the data driver section 220 can receive the image data Do and the data control signal DCS from the timing control section 240 and, in response to the data control signal DCS, the data driver section 220 can convert the image data Do into analog image data, e.g. data voltages Vdata, and output these to the respective data lines DL. The power supply section 280 can generate the direct current required to drive the pixel array and the driver circuit section of the display panel 100, for example, using a DC-DC converter. The DC-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply section 280 can, for example, receive a voltage Vcc, which is a driver voltage for controlling the light-emitting display device 10, from the host system and generate the DC voltages such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, a high-potential driver voltage EVDD, a low-potential driver voltage EVSS, and an initialization voltage Vini. The gate low voltages VGL and VEL and the gate high voltages VGH and VEH can be supplied to the gate driver section 210. The high-potential driver voltage EVDD, the low-potential driver voltage EVSS, and the initialization voltage Vini can be supplied together to the pixels P in the display field 100. The sampling stage forming the sampler driver circuit of this embodiment can now be described with further reference to Fig. 4. Fig. 4 is a view schematically illustrating the structure of a sampling stage of a sampler driver circuit according to an embodiment of the present disclosure. Fig. 5 is a waveform view schematically illustrating the timing of signals driving a sampling stage according to an embodiment of the present disclosure. For the sake of simplicity, Fig. 4 illustrates, as an example, the nth sampling stage SSC(n), which generates the first and second sampling signals SC1 and SC2 that drive the 2n-1th and 2n-th horizontal lines of the display area AA, among the sampling stages SSC that form the sampler driver circuit. Meanwhile, the n+1th sampling stage SSC(n+1), located on the other side of the display area AA, can be configured with essentially the same structure as the nth sampling stage SSC(n), located on one side of the display area AA. Referring to Fig. 4 and Fig. 5 together with Fig. 1, Fig. 2 to Fig. 3, the sampler driver circuit can include a plurality of sampler stages SSC that output the first and second sampler signals SC1 and SC2 corresponding to a plurality of first and second sampler lines SCL1 and SCL2 arranged in the display area AA. As mentioned above, the multiple SSC sampling stages can be arranged to be distributed on both sides of the display area AA. For example, the odd-numbered SSC sampling stages can be arranged and driven sequentially along the vertical scanning direction on one side of the display area AA, e.g., the left side, and the even-numbered SSC sampling stages can be arranged and driven sequentially along the vertical scanning direction on the other side of the display area AA, e.g., the right side. Each sampling stage SSC can, for example, include a buffer section that generates and outputs the sampling signals SC1 and SC2, and a control section that controls an output operation of the buffer section. The buffer section of the sampling stage SSC can, for example, include a first buffer section BF1, which outputs the nth first sampling signal SC1(n), which is applied jointly to the 2n-1th and 2n-th horizontal lines, which are odd and even horizontal lines, and a second-first buffer section BF2_1 and a second-second buffer section BF2_2, which output the 2n-1th and 2n-th second sampling signals SC2(2n-1) and SC2(2n), which are applied respectively to the 2n-1th and 2n-th horizontal lines. The first buffer section BF1, which outputs the nth first sampling signal SC1(n), can, for example, include a first buffer transistor Tb1, which is a pull-up transistor, and a second buffer transistor Tb2, which is a pull-down transistor. Furthermore, the first buffer section BF1 can include a first Q capacitor CQ1. The second-first buffer section BF2_1, which outputs the 2n-1 second sampling signal SC2(2n-1), can, for example, include a third buffer transistor Tb3, which is a pull-up transistor, and a fourth buffer transistor Tb4, which is a pull-down transistor. Furthermore, the second-first buffer section BF2_1 can include a second Q capacitor CQ2. The second-second buffer section BF2_2, which outputs the 2nth second sample signal SC2(2n), can, for example, include a fifth buffer transistor Tb5, which is a pull-up transistor, and a sixth buffer transistor Tb6, which is a pull-down transistor. Additionally, the second-second buffer section BF2_2 can include a third Q capacitor CQ3. The control section of the sampling stage (SSC) can, for example, include a transfer transistor (TA) and a variety of control transistors (Ts1, Ts2, Ts3, and Ts4). The variety of control transistors (Ts1, Ts2, Ts3, and Ts4) can, for example, include the first, second, third, and fourth control transistors (Ts1, Ts2, Ts3, and Ts4). Meanwhile, each of the transistors Tb1 to Tb6, Ts1 to Ts4, and TA that form the sampling stage SSC(n) can be a P-type transistor or an N-type transistor. Furthermore, each of the transistors Tb1 to Tb6, Ts1 to Ts4, and TA that form the sampling stage SSC(n) can be a transistor using an oxide semiconductor or a transistor using polycrystalline silicon. In this embodiment, among the transistors Tb1 to Tb6, Ts1 to Ts4 and TA forming the sampling stage SSC(n), the second to sixth buffer transistors Tb2 to Tb6, the first and third control transistors Ts1 and Ts3 and the transfer transistor TA can be configured as N-type transistors incorporating an oxide semiconductor layer, and the first buffer transistor Tb1 and the second and fourth control transistors Ts2 and Ts4 can be configured as P-type transistors incorporating a polycrystalline silicon layer. Here, the N-type transistors Tb2 to Tb6, Ts1, Ts3, and TA of the oxide semiconductor can, for example, be formed with the same structure as the N-type transistors DT, T1, T2, and T5 of the oxide semiconductor in pixel P. The P-type transistors Tb1, Ts2, and Ts4 made of polycrystalline silicon can, for example, be formed with the same structure as the P-type transistors T3 and T4 made of polycrystalline silicon in pixel P. The first buffer transistor Tb1 of the first buffer section BF1 can, for example, have a gate electrode that responds to a signal from a BG node to pull up the first output terminal NO1 of the first buffer section BF1. Additionally, the second buffer transistor Tb2 can have a gate electrode that responds to a signal from the BG node to pull down the first output terminal NO1. In this respect, the first and second buffer transistors Tb1 and Tb2 of the first buffer section BF1 can be configured with opposite P-type and N-type transistors, respectively, and their gate electrodes can be connected to the BG node, allowing their on / off states to be opposite. In this way, the first and second buffer transistors Tb1 and Tb2 can be configured as an inverter circuit, so that when one of them is on, the other can be turned off. The first P-type buffer transistor Tb1, for example, may have a first electrode (or source electrode) that receives a gate high voltage VGH output by the power supply section 280, and a second electrode (or drain electrode) that is connected to the first output terminal NO1. The second N-type buffer transistor Tb2 can, for example, have a second electrode (or drain electrode) connected to the first output terminal NO1, and a first electrode (or source electrode) supplied with a gate low voltage VGL provided by the power supply section 280. In one example, a gate high voltage VGH is higher than a gate low voltage VGL. The first control transistor Ts1 of the control section can, for example, respond to the corresponding sampling clock S1CLK1B to supply the n-2th first sampling signal SC1(n-2), which is an output signal of the n-2th sampling stage SSC, located before the corresponding sampling stage SSC(n), to a CNT node. The first N-type control transistor Ts1 can, for example, have a gate electrode to which the sampling clock S1CLK1B is applied, a first electrode (or source electrode) connected to the CNT node, and a second electrode (or drain electrode) to which the first sampling signal SC1(n-2) of the preceding sampling stage SSC is applied. Here, the sampling clock S1CLK1B input to the first control transistor Ts1 can be referred to as a first B sampling clock S1CLK1B. The second control transistor Ts2 can be connected in parallel with the first control transistor Ts1 to form a transfer-gate circuit. In this configuration, the second control transistor Ts2 can, for example, supply the n-2th first sample signal SC1(n-2), which is the output signal of the previous sample stage SSC, to the CNT node in response to the corresponding sample clock S1CLK1. The second P-type control transistor Ts2 can, for example, have a gate electrode to which the sample clock S1CLK1 is applied, a second electrode (or drain electrode) connected to the CNT node, and a first electrode (or source electrode) to which the previous first sample signal SC1(n-2) is applied. Here, the sample clock S1CLK1 input to the second control transistor Ts2 can be referred to as the first sample clock S1CLK1. Here, the previous first sampling signal SC1(n-2), applied to the first and second control transistors Ts1 and Ts2, can be used as a start signal (or transfer signal). Meanwhile, if the sampling stage SSC(n) is the sampling stage of the first horizontal line, a start signal supplied by the timing section 240 can be input to the first and second control transistors Ts1 and Ts2 to initiate the output process of the sampling stage. Additionally, the first sampling clock S1CLK1 and the first B sampling clock S1CLK1B can be clock signals that have waveforms that are out of phase with each other. The third control transistor Ts3 can transmit the gate low voltage VGL to the BG node in response to the voltage of the CNT node. The third N-type control transistor Ts3 can, for example, have a gate electrode connected to the CNT node, a second electrode (or drain electrode) connected to the BG node, and a first electrode (or source electrode) that receives the gate low voltage VGL. The fourth control transistor, Ts4, can be connected in series with the third control transistor, Ts3, with the BG node positioned between them, and can transmit the gate high voltage, VGH, to the BG node in response to the voltage of the CNT node. The fourth P-type control transistor, Ts4, can, for example, have a gate electrode connected to the CNT node, a second electrode (or drain electrode) connected to the BG node, and a first electrode (or source electrode) that receives the gate high voltage, VGH. As described above, the on / off states of the third and fourth control transistors Ts3 and Ts4 can be reversed. The first Q capacitor CQ1 can be connected between the BG node and a voltage line that carries the gate high voltage VGH. Here, the capacitance of the first Q capacitor CQ1 can be set so that it is greater than the capacitance of the storage capacitor Cst in pixel P. According to the configuration of the control section and the first buffer section BF1 as above, the first buffer section BF1 can be controlled by the BG node, and the sampling stage SSC(n) can shift the previous first sampling signal SC1(n-2) according to the two sampling clocks S1CLK1 and S1CLK1B input therein and output the first sampling signal SC1(n) to the corresponding first sampling line SCL1. Thus, the nth sampling stage SSC(n) can receive the first sampling clock S1CLK1 and the first B sampling clock S1CLK1B and generate and output the first sampling signal SC1(n) from the first output terminal NO1 of the first buffer section BF1. Meanwhile, the control section's transfer transistor TA can, for example, be connected to the first output terminal NO1 and can transfer charges from the first output terminal NO1 to an SQ node in response to the gate high voltage VGH. The N-type transfer transistor TA can, for example, have a gate electrode to which the gate high voltage VGH is applied, a first electrode (or source electrode) connected to the SQ node, and a second electrode (or drain electrode) connected to the first output terminal NO1. The second-first buffer section BF2_1 and the second-second buffer section BF2_2 can, for example, output two second sampling signals SC2(2n-1) and SC2(2n) according to the control of the SQ node and the BG node. Here, a signal from the BG node can have a phase that is essentially opposite to that of a signal from the SQ node, and a node of the second-first buffer section BF2_1 and the second-second buffer section BF2_2, which is connected to the BG node, can be called a QB node. Regarding the second-first buffer section BF2_1, the third buffer transistor Tb3 can, for example, have a gate electrode that responds to the signal from the SQ node to pull up a second-first output terminal NO2_1 of the second-first buffer section BF2_1. Additionally, the fourth buffer transistor Tb4 can have a gate electrode that responds to a signal from the BG node, e.g., the QB node, to pull down the second-first output terminal NO2_1. In this respect, the third N-type buffer transistor Tb3 can, for example, have a first electrode (or source electrode) that receives a corresponding sampling clock S2CLK1, and a second electrode (or drain electrode) that is connected to the second-first output terminal NO2_1 of the sampling stage SSC(n). Here, the sampling clock S2CLK1 input to the third buffer transistor Tb3 can be referred to as a second-first sampling clock S2CLK1. The fourth N-type buffer transistor Tb4, for example, can have a second electrode (or drain electrode) connected to the second-first output terminal NO2_1, and a first electrode (or source electrode) provided with the gate low voltage VGL. The second Q capacitor CQ2 can be connected between the SQ node and the second-first output terminal NO2_1. Here, the capacitance of the second Q capacitor CQ2 can be set so that it is greater than the capacitance of the storage capacitor Cst in pixel P. The second-first buffer section BF2_1, which is set up as above, can have its output controlled by the BG node and the first output terminal NO1 of the first buffer section BF1, and through this output control the second-first sampling clock S2CLK1 can be output as the second sampling signal SC2(2n-1) to the second sampling line SCL2 during the corresponding horizontal period (e.g. the horizontal period of the 2n-1th horizontal line). Thus, in the nth sampling stage SSC(n), the second-first buffer section BF2_1 can receive the second-first sampling clock S2CLK1, and the BG node and the first output terminal NO1 of the first buffer section BF1 can be used as the output control node of the second-first buffer section BF2_1, so that the 2n-1th second sampling signal SC2(2n-1) can be generated and output by the second-first output terminal NO2_1 of the second-first buffer section BF2_1. Regarding the second-second buffer section BF2_2, the fifth buffer transistor Tb5 can, for example, have a gate electrode that responds to the signal from the SQ node to pull up a second-second output terminal NO2_2 of the second-second buffer section BF2_2. Additionally, the sixth buffer transistor Tb6 can have a gate electrode that responds to a signal from the BG node, e.g., the QB node, to pull down the second-second output terminal NO2_2. In this respect, the fifth N-type buffer transistor Tb5, for example, can have a second electrode (or drain electrode) that receives a corresponding sampling clock S2CLK2, and a first electrode (or source electrode) that is connected to the second-second output terminal NO2_2 of the sampling stage SSC(n). Here, the sampling clock S2CLK2 input to the fifth buffer transistor Tb5 can be referred to as a second-second sampling clock S2CLK2. The second-second sampling clock S2CLK2 can have a different phase than the second-first sampling clock S2CLK1, and a clock pulse of the second-second sampling clock S2CLK2 can subsequently be generated on top of a clock pulse of the second-first sampling clock S2CLK1. The sixth N-type buffer transistor Tb6, for example, can have a second electrode (or drain electrode) connected to the second-second output terminal NO2_2, and a first electrode (or source electrode) provided with the gate low voltage VGL. The third Q capacitor CQ3 can be connected between the SQ node and the second-to-second output terminal NO2_2. Here, the capacitance of the third Q capacitor CQ3 can be set so that it is greater than the capacitance of the storage capacitor Cst in pixel P. The second-second buffer section BF2_2, which is set up as above, can have its output controlled by the BG node and the first output terminal NO1 of the first buffer section BF1 in the same way as the second-first buffer section BF2_1, and through this output control the second-second sampling clock S2CLK2 can be output as the second sampling signal SC2(2n) to the second sampling line SCL2 during the corresponding horizontal period (e.g. the horizontal period of the 2nth horizontal line). Thus, in the nth sampling stage SSC(n), the second-second buffer section BF2_2 can receive the second-second sampling clock S2CLK2, and the BG node and the first output terminal NO1 of the first buffer section BF1 can be used as output control nodes of the second-second buffer section BF2_2, so that the 2nth second sampling signal SC2(2n) can be generated and output by the second-second output terminal NO2_2 of the second-second buffer section BF2_2. The output processes of the first sampling signal SC1(n) and the second sampling signals SC2(2n-1) and SC2(2n) in the nth sampling stage SSC(n), which is set up as above, can be described with further reference to Fig. 5. As mentioned above, the nth sampling stage SSC(n) can receive the corresponding four sampling clocks, e.g. the first sampling clock S1CLK1, the first B sampling clock S1CLK1B, the second-first sampling clock S2CLK1 and the second-second sampling clock S2CLK2, and output a first sampling signal SC1(n) and two second sampling signals SC2(2n-1) and SC2(2n), which perform a sampling operation of the corresponding two horizontal lines. For example, during a first period t1, the previous first sampling signal SC1(n-2) may be in a low state. Within the first period t1, the first sampling clock S1CLK1 may transition from a low state to a high state, and conversely, the first B sampling clock S1CLK1B may transition from a high state to a low state. Here, during a section where the first sampling clock S1CLK1 is in a low state and the first B sampling clock S1CLK1B is in a high state, the first and second control transistors Ts1 and Ts2 can be switched on, so that a low voltage (e.g., the gate low voltage VGL) of the previous first sampling signal SC1(n-2) can be applied to the CNT node. Accordingly, the voltage at the CNT node can be at a low level. Then, during a section in which the first sampling clock S1CLK1 is high and the first B sampling clock S1CLK1B is low, the first and second control transistors Ts1 and Ts2 can be switched off, and the voltage at the CNT node can be kept at a low level. As such, the voltage of the CNT node can be low during the first period t1. When the CNT node is in a low state, the gate high voltage VGH can be applied to the BG node. Furthermore, the QB node can be powered on, and the second buffer transistor Tb2, the fourth buffer transistor Tb4, and the sixth buffer transistor Tb6 can be turned on. Furthermore, the gate low voltage VGL can be applied to the first output terminal NO1, and the SQ node can be in a low state. In this way, in the first period t1, the BG node and the QB node can be in a high state, and the SQ node can be in a low state. Accordingly, in the first buffer section BF1 the first buffer transistor Tb1 can be switched off, and the second buffer transistor Tb2 can be switched on, so that the gate low voltage VGL can be output from the first output terminal NO1, and the nth first sampling signal SC1(n) can have a low level. Additionally, in the second-first buffer section BF2_1, the third buffer transistor Tb3 can be switched off, and the fourth buffer transistor Tb4 can be switched on, so that the gate low voltage VGL can be output from the second-first output terminal NO2_1, and the 2n-1 second sample signal SC2(2n-1) can have a low level. Additionally, in the second-second buffer section BF2_2, the fifth buffer transistor Tb5 can be switched off, and the sixth buffer transistor Tb6 can be switched on, so that the gate low voltage VGL can be output from the second-second output terminal NO2_2, and the 2n-th second sample signal SC2(2n) can have a low level. Next, in a second period t2, the previous first sampling signal SC1(n-2) can be switched to a high state. During the second period t2, the first sampling clock S1CLK1 can be held in a high state, and the first B sampling clock S1CLK1B can be held in a low state. Accordingly, the first and second control transistors Ts1 and Ts2 can be held in an off state, so that the voltage of the CNT node can be kept at a low level. Accordingly, similar to the first period t1, in the second period t2 the BG node and the QB node can be in a high state, and the SQ node can be in a low state. Thus, the nth first sample signal SC1(n) of the first buffer section BF1 can maintain a low level, the 2n-1th second sample signal SC2(2n-1) of the second-first buffer section BF2_1 can maintain a low level, and the 2nth second sample signal SC2(2n) of the second-second buffer section BF2_2 can maintain a low level. Next, in a third period t3, the previous first sampling signal SC1 (n-2) can remain in a high state. Additionally, the first sampling clock S1CLK1 can be switched to a low state, and conversely, the first B sampling clock S1CLK1B can be switched to a high state. In this case, the first and second control transistors Ts3 and Ts4 can be switched on, so that the high voltage (e.g., the gate high voltage VGH) of the previous first sampling signal SC1(n-2) can be applied to the CNT node. Accordingly, the voltage of the CNT node can become high. In this way, the CNT node can be in a high state, so that the gate low voltage VGL can be applied to the BG node. Additionally, the QB node can be in a low state, allowing the second buffer transistor Tb2, the fourth buffer transistor Tb4, and the sixth buffer transistor Tb6 to be switched off. Additionally, the gate high voltage VGH can be applied to the first output terminal NO1, and the SQ node can be in a high state. In this way, in the third period t3, the BG node and the QB node can be in a low state, and the SQ node can be in a high state. Accordingly, in the first buffer section BF1 the first buffer transistor Tb1 can be switched on, and the second buffer transistor Tb2 can be switched off, so that the gate high voltage VGH can be output from the first output terminal NO 1, and the nth first sampling signal SC1(n) can have a high level. Additionally, in the second-first buffer section BF2_1, the third buffer transistor Tb3 can be switched on, and the fourth buffer transistor Tb4 can be switched off, so that the second-first sampling clock S2CLK1 can be output at a low level from the second-first output terminal NO2_1, and the 2n-1 second sampling signal SC2(2n-1) can have a low level. Additionally, in the second-second buffer section BF2_2, the fifth buffer transistor Tb5 can be switched on, and the sixth buffer transistor Tb6 can be switched off, so that the second-second sampling clock S2CLK2 can be output at a low level from the second-second output terminal NO2_2, and the 2n-th second sampling signal SC2(2n) can have a low level. Next, in the fourth period t4, the previous first sampling signal SC1(n-2) can be held in a high state. In the fourth period t4, the first sampling clock S1CLK1 can be switched to a high state, and the first B sampling clock S1CLK1B can be switched to a low state. Accordingly, the first and second control transistors Ts1 and Ts2 can be switched off, so that the voltage of the CNT node can be held at a high level. Accordingly, similar to the third period t3, in the fourth period t4 the BG node and the QB node can be in a low state, and the SQ node can be in a high state. Thus, the nth first sample signal SC1(n) of the first buffer section BF1 can maintain a high level, the 2n-1th second sample signal SC2(2n-1) of the second-first buffer section BF2_1 can maintain a low level, and the 2nth second sample signal SC2(2n) of the second-second buffer section BF2_2 can maintain a low level. Next, in the fifth period t5, the previous first sampling signal SC1(n-2) can remain high for a certain segment and then transition to a low state. In the fifth period t5, the first sampling clock S1CLK1 can remain high, and the first B sampling clock S1CLK1B can remain low. Accordingly, the first and second control transistors Ts1 and Ts2 can be held in an off state, and the voltage at the CNT node can be maintained at a high level. Accordingly, similar to the fourth period t4, in the fifth period t5 the BG node and the QB node can be in a low state, and the SQ node can be in a high state. Thus, the nth first sampling signal SC1(n) of the first buffer section BF1 can maintain a high level. Meanwhile, in the fifth period t5, the second-first sampling clock S2CLK1, which is input into the second-first buffer section BF2_1, may contain a high-voltage pulse (e.g., gate high voltage VGH). Accordingly, the second-first buffer section BF2_1 may output the 2n-1th second sampling signal SC2(2n-1) of the high pulse during the horizontal period H of the 2n-1th horizontal line. Additionally, in the fifth period t5, the second-second sampling clock S2CLK2, which is input into the second-second buffer section BF2_2, can contain a high-voltage pulse (e.g., gate high voltage VGH). Accordingly, the second-second buffer section BF2_2 can output the 2nth second sampling signal SC2(2n) of the high pulse during the horizontal period H of the 2nth horizontal line. While the second sampling signals SC2(2n-1) and SC2(2n) of the gate high voltage VGH are output from the second-first and second-second output terminals NO2_1 and NO2_2, the SQ node can be bootstrapped by the second Q capacitor CQ2 and the third Q capacitor CQ3, so that the voltage of the SQ node can essentially be increased to a voltage higher than the gate high voltage VGH. Due to the voltage increase of the SQ node through the bootstrapping action, the second-first sampling clock S2CLK1 and the second-second sampling clock S2CLK2 can be stably output from the second-first output terminal NO2_1 and the second-second output terminal NO2_2. Meanwhile, in the fifth period t5, when the second-first sampling clock S2CLK1 transitions to a low voltage, the voltage of the second-first output terminal NO2_1 can also transition to a low voltage, allowing the second low-level sampling signal SC2(2n-1) to be output. Similarly, when the second-second sampling clock S2CLK2 transitions to a low voltage, the voltage of the second-second output terminal NO2_2 can also transition to a low voltage, allowing the second low-level sampling signal SC2(2n) to be output. Additionally, when the second-first and second-second sampling clocks S2CLK1 and S2CLK2 transition to a low state, as described above, the voltage of the SQ node can be reduced to essentially the gate high voltage VGH by the second Q capacitor CQ2 and the third Q capacitor CQ3. Next, in a sixth period t6, the first sampling signal SC1 (n-2) can be held in a low state. Additionally, the first sampling clock S1CLK1 can be held in a high state, and the first B sampling clock S1CLK1B can be held in a low state. Accordingly, the first and second control transistors Ts1 and Ts2 can be held in an off state, and the voltage of the CNT node can be held at a high level. Accordingly, similar to the fifth period t5, in the sixth period t6 the BG node and the QB node can be in a low state, and the SQ node can be in a high state. Thus, the nth first sampling signal SC1(n) of the first buffer section BF1 can be kept at a high level. Meanwhile, in the sixth period t6, the second-first sampling clock S2CLK1, which is input into the second-first buffer section BF2_1, may have a low voltage (e.g., gate low voltage VGL). Accordingly, the second-first buffer section BF2_1 may output the 2n-1th second sampling signal SC2(2n-1) of a low level. Additionally, in the sixth period t6, the second-second sampling clock S2CLK2, which is input into the second-second buffer section BF2_2, can have a low voltage (e.g., gate low voltage VGL). Accordingly, the second-second buffer section BF2_2 can output the 2nth second sampling signal SC2(2n) of a low level. Next, in a seventh period t7, the previous first sampling signal SC1(n-2) can be held in a low state. Additionally, the first sampling clock SCLK1 can be switched to a low state, and conversely, the first B sampling clock SCLKB1 can be switched to a high state. Accordingly, the first and second control transistors Ts1 and Ts2 can be turned on, and the voltage of the CNT node can be at a low level. Accordingly, in the seventh period t7, the BG node and the QB node can be in a high state, and the SQ node can be in a low state. Thus, in the first buffer section BF1, the gate low voltage VGL can be output from the first output terminal NO1, and the nth first sampling signal SC1(n) can have a low level. Furthermore, in the second-first buffer section BF2_1, the gate low voltage VGL can be output from the second-first output terminal NO2_1, and the 2n-1 second sampling signal SC2(2n-1) can have a low level. Furthermore, in the second-second buffer section BF2_2, the gate low voltage VGL can be output from the second-second output terminal NO2_2, and the 2n-th second sample signal SC2(2n) can have a low level. Next, in an eighth period t8, the previous first sampling signal SC1(n-2) can be held in a low state. Additionally, the first sampling clock S1CLK1 can be switched to a high state, and the first B sampling clock S1CLK1B can be switched to a low state. Accordingly, the first and second control transistors Ts1 and Ts2 can be switched off, and the voltage of the CNT node can be held at a low level. Accordingly, similar to the seventh period t7, in the eighth period t8 the BG node and the QB node can be in a high state, and the SQ node can be in a low state. Thus, the nth first sample signal SC1(n) of the first buffer section BF1 can be kept at a low level, the 2n-1th second sample signal SC2(2n-1) of the second-first buffer section BF2_1 can be kept at a low level, and the 2nth second sample signal SC2(2n) of the second-second buffer section BF2_2 can be kept at a low level. Through the above processes, the sampling stage SSC(n) can generate and output the first sampling signal SC1(n) and the second sampling signals SC2(2n-1) and SC2(2n). The first sampling signal SC1(n) and the second sampling signals SC2(2n-1) and SC2(2n) can be applied to the corresponding two horizontal lines, e.g., the 2n-1 and 2n-th horizontal lines, and a sampling operation can be performed on them. Meanwhile, the n+1th sampling stage SSC(n+1), positioned opposite the nth sampling stage SSC(n) with the display area AA in between, can operate similarly to the nth sampling stage (SSC(n)). For example, the n+1th sampling stage SSC(n+1) can receive the n-1th first sample signal SC1(n-1), which is the previous first sample signal, and generate and output the n+1th first sample signal SC1(n+1) and the 2n+1th and 2n+2th second sample signals SC2(2n+1) and SC2(2n+2). The first sample signal SC1(n+1) and the second sample signals SC2(2n+1) and SC2(2n+2) can be applied to the corresponding two horizontal lines, e.g., the 2n+1th and 2n+2th horizontal lines, and perform a sampling operation on them. As described above, in this embodiment the sampling stages SSC can be provided on both sides of the display area (AA) in a unit of four horizontal lines, and in each sampling stage SSC the first buffer section BF1, which outputs the first sampling signal SC1, and the first and second buffer sections BF2_1 and BF2_2, which output the two second sampling signals SC2, can share control nodes. By sharing the control nodes, each sampling stage SSC can output the first sampling signal SC1, which jointly drives the corresponding two horizontal lines, and the two second sampling signals SC2, which individually drive the corresponding two horizontal lines. Accordingly, the vertical length of the sampling stage SSC can be greater than the widths of the buffer transistors Tb1 to Tb6, so that the buffer transistors Tb1 to Tb6, which form the sampling stage SSC, can be arranged in the vertical direction, thereby narrowing the width of the non-display area NA. Therefore, the bezel width of the light-emitting display device 10 can be reduced, thus enabling a narrow bezel. This can be described with further reference to Fig. 6. Fig. 6 is a view comparing non-display areas of display fields according to a comparative example and an embodiment of the present disclosure. Referring to Fig. 6, in the display field 100c of the comparative example, first sampling stages SSC1, which output first sampling signals (SC1: SC1(2n-1) to SC1(2n+2)), are arranged in a unit of a horizontal line on the left side of the display area AA, which is one side of the display area AA, and second sampling stages SSC2, which output second sampling signals (SC2: SC2(2n-1) to SC2(2n+2)), are arranged in a unit of a horizontal line on the right side of the display area AA, which is the other side of the display area AA. Thus, in the comparison example, the first and second sampling stages SSC1 and SSC2 are located on either side of the display area AA within a unit of a horizontal line. In this case, since the vertical length of each of the first and second sampling stages SSC1 and SSC2 is smaller than the widths of the buffer transistors in the sampling stage, the buffer transistors must be arranged horizontally, which increases the width of the non-display area (NA). For example, the first and second sampling stages SSC1 and SSC2 of the comparison example each have a width wc of approximately 200 µm, so the width of the non-display area NA is wide. In this embodiment, however, the sampling stages SSC can be provided on both sides of the display area AA in a unit of four horizontal lines, and each sampling stage SSC can output the first sampling signal (SC1: SC1(n) or SC(n+1)) and the second sampling signals (SC2: SC2(2n-1) and SC(2n) or SC(2n+1) and SC2(2n+2)) that drive the corresponding two horizontal lines. Accordingly, the vertical length of the sampling stage (SSC) can be greater than the widths of the buffer transistors, allowing the buffer transistors forming the SSC to be arranged vertically and thus reducing the width w of the SSC. For example, the SSC of this embodiment can have a width w of approximately 90 µm. Therefore, the width of the non-display area NA of this embodiment can be reduced so that the light-emitting display device 10 can effectively implement a narrow bezel. An example of a cross-sectional structure of the display field 100 of this embodiment is described below with further reference to Fig. 7. Fig. 7 is a cross-sectional view that schematically illustrates an example of a cross-sectional structure of a display field according to an embodiment of the present disclosure. For the sake of simplicity, Figure 7 illustrates two thin-film transistors, TFT1 and TFT2, within pixel P in the display area AA. Here, the thin-film transistor TFT1, which is positioned relatively lower and closer to substrate 101, is referred to as the first thin-film transistor, TFT1, which may be a polycrystalline silicon thin-film transistor. The thin-film transistor TFT2, which is positioned relatively higher and further away from substrate 101, is referred to as the second thin-film transistor, TFT2, which may be an oxide thin-film transistor. Meanwhile, the first thin-film transistor TFT1 can be a third transistor (T3 of Fig. 2), but is not limited to this. Additionally, the second thin-film transistor TFT2 can be a driver transistor (DT of Fig. 2), but is not limited to this. The substrate 101 can, for example, be configured as a thin glass substrate (or a thin glass film) or a plastic substrate (or a plastic film) to implement flexible properties of the display field 100. In a case where substrate 101 is configured as a glass substrate, for example, substrate 101 can have a thickness of approximately 0.2 mm. Meanwhile, in a case where the substrate 101 is configured, for example, as a plastic substrate, the substrate 101 can include at least one polyimide layer. In this embodiment, the substrate 101, configured with two polyimide layers, a first polyimide layer 101a and a second polyimide layer 101b, is taken as an example. In this case, the substrate can include an inorganic insulating layer between the first polyimide layer 101a and a second polyimide layer 101b. The first thin-film transistor TFT1 can include a first semiconductor layer 105 arranged on the substrate 101, a first gate electrode 115 overlapping the first semiconductor layer 105 with a first insulating layer 110 between them, and a first source electrode 151 and a first drain electrode 152 located on a fourth insulating layer 145 above the first gate electrode 115. Here, the first semiconductor layer 105 can be made of polycrystalline silicon, but is not limited to this. The first semiconductor layer 105 can include a central channel region and source and drain regions on both sides thereof. The first source electrode 151 and the first drain electrode 152 can be connected to the source region and drain region of the first semiconductor layer 105 by the first and second contact holes 156 and 157, which are formed in the insulating layers 110, 120, 125, 135 and 145 located beneath the first source electrode 151 and the first drain electrode 152. A second insulating layer 120 can be formed on the first gate electrode 115 of the first thin-film transistor TFT1. A first intermediate insulating layer 125 can be formed on the second insulating layer 120. The second thin-film transistor TFT2 can be formed on the first intermediate insulating layer 125. The second thin-film transistor TFT2 can include a second semiconductor layer 130 on the first intermediate insulating layer 125, a second gate electrode 140 that overlaps the second semiconductor layer 130 with a third insulating layer 135 positioned between them, and a second source electrode 153 and a second drain electrode 154 located on the fourth insulating layer 145 above the second gate electrode 140. Here, the second semiconductor layer 130 can be formed from an oxide semiconductor, but is not limited to this. The second semiconductor layer 130 can include a central channel region and source and drain regions on both sides thereof. The second source electrode 153 and the second drain electrode 154 can be connected to the source and drain regions of the second semiconductor layer 130 by third and fourth contact holes 158 and 159, which are formed in the insulating layers 135 and 145 located beneath the second source electrode 153 and the second drain electrode 154. A second intermediate insulating layer (or first planarization layer) 160 can be formed on the second thin-film transistor TFT2. Here, the first, second, third and fourth insulating layers 110, 120, 135 and 145 can be formed from an inorganic insulating material such as silicon nitride or silicon oxide, but are not limited to this. Additionally, the first and second intermediate insulating layers 125 and 160 can be formed from an organic insulating material such as photoacrylic or benzocyclobutene, but are not limited to this. A connecting electrode 162 can be formed on the second intermediate insulating layer 160. The connecting electrode 162 can be connected to the first drain electrode 152 through a contact hole 161 formed in the second intermediate insulating layer 160. A third interlayer insulating layer (or second planarization layer) 163 can be formed on the connecting electrode 162. The third interlayer insulating layer 163 can be formed from an organic insulating material such as photoacrylic or benzocyclobutene, but is not limited to this. The light-emitting diode OD and a bank 165 can be formed on the third interlayer insulating layer 163. The light-emitting diode OD can include an anode electrode (or first electrode) 171, a light-emitting layer 172 and a cathode electrode (or second electrode) 173. The anode electrode 171 can be connected to the connecting electrode 162 through the contact hole 164, which is formed in the third intermediate insulating layer 163. The bank 165 can be arranged along a boundary of pixel P and can be formed to cover an edge of the anode electrode 171. The light-emitting layer 172 can be formed on the anode electrode 171, which is exposed through an opening in the bank 165. The cathode electrode 173 can be formed on the light-emitting layer 172 and can be applied with the low-potential driver voltage (EVSS of Fig. 2). An encapsulation layer 180 can be formed on the cathode electrode 173. The encapsulation layer 180 can include, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this disclosure, a structure of the encapsulation layer 180 in which a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are stacked sequentially is described as an example. The first encapsulation layer 181 can be formed on the substrate 101 on which the cathode electrode 173 is formed. The third encapsulation layer 183 can be formed on the substrate 101 on which the second encapsulation layer 182 is formed, and can be formed to surround a top surface, a bottom surface, and a side surface of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 can prevent external moisture or oxygen from entering the light-emitting diode OD. The first encapsulation layer 181 and the third encapsulation layer 183 can be formed from an inorganic insulating material capable of low-temperature deposition, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. The second encapsulation layer 182 can act as a buffer to relieve stress between layers due to bending of the light-emitting display device 10 and can flatten steps between layers. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed, using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited to these. If the second encapsulation layer 182 is formed by an inkjet process, a dam DAM can be placed in the non-display area NA to prevent the second encapsulation layer 182 from spreading in liquid form to an edge of the substrate 101.The dam-DAM can be located closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam-DAM can prevent the second encapsulation layer 182 from spreading to a contact surface area, where a conductive contact surface is located, at an outermost edge of the substrate 101. The dam-DAM can be designed to prevent the spread of the second encapsulation layer 182, but if the second encapsulation layer 182 forms to a height exceeding that of the dam-DAM during a process, the second encapsulation layer 182 may be exposed to the outside as an organic layer, allowing moisture, etc., to easily penetrate the light-emitting element. To prevent this, 10 or more dam-DAMs can be formed sequentially, but this is not the limit. The dam-DAM can be formed simultaneously with the first intermediate insulating layer 125, the second intermediate insulating layer 160, and the third intermediate insulating layer 163. When forming the first intermediate insulating layer 125, a bottom layer of the dam-DAM can be created, and when forming the second and third intermediate insulating layers 160 and 163, an upper layer of the dam-DAM can be created, so that the dam-DAM can be formed in a triple-laminated structure. Alternatively, the dam-DAM can be formed with one or two of the first, second, and third intermediate insulating layers 125, 160, and 163, respectively. Accordingly, the dam DAM can be formed from the same material as the first intermediate layer insulating layer 125, the second intermediate layer insulating layer 160 and the third intermediate layer insulating layer 163, but is not limited to it. The dam DAM can be configured to overlap a low-potential driver voltage line (VSSL). For example, the low-potential driver voltage line (VSSL) can be formed on a lower layer of a region containing the dam DAM, in the non-display region (NA). The low-potential driver voltage line VSSL and the gate driver section 210, configured in the GIP structure, can be formed along a perimeter of the display area 100, and the low-potential driver voltage line VSSL can be located outside the gate driver section 210. Additionally, the low-potential driver voltage line VSSL can be connected to the cathode electrode 173 to apply the low-potential driver voltage EVSS. The gate driver section 210 is shown in a simple planar cross-section in the drawings, but can be configured with the same structure as the first thin-film transistor TFT1 and / or the second thin-film transistor TFT2 of the display area AA. A touch layer (or touch element layer) 190 can be arranged on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 can be positioned between a touch sensor metal, which includes touch electrode connecting lines 192 and 194 and touch electrodes 195 and 196, and the cathode electrode 173 of the light-emitting diode OD. The contact buffer layer 191 can prevent a chemical solution (developer, etchant, etc.) used in the manufacturing process of the contact sensor metal applied to the contact buffer layer 191, or external moisture, from penetrating the light-emitting layer 172, which contains an organic material. Accordingly, the contact buffer layer 191 can prevent damage to the light-emitting layer 172, which is susceptible to the chemical solution or moisture. According to a mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 can be arranged on the touch buffer layer 191, and the touch electrodes 195 and 196 can be arranged to cross each other. The contact electrode connecting leads 192 and 194 can electrically connect the contact electrodes 195 and 196. One of the contact electrode connecting leads 192 and 194 and the contact electrodes 195 and 196 can be located on different layers, with a contact insulating layer 193 positioned between them. Additionally, one of the contact electrode connecting leads 192 and 194 and the other of the contact electrode connecting leads 192 and 194 can be located on different layers, with the contact insulating layer 193 positioned between them. The contact electrode connecting leads 192 and 194 can be arranged to overlap the bank 165, thereby preventing, but not limiting, a reduction in the opening ratio. Meanwhile, part of the touch electrodes 195 and 196 and part of the touch electrode connecting line 192 can extend along the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam DAM and be electrically connected to a touch control circuit via a touch connection surface 198 and 199. Part of the touch electrodes 195 and 196 and part of the touch electrode connecting line 192 can receive a touch control signal from the touch control circuit and transmit it to the touch electrodes 195 and 196, and can transmit a touch detection signal detected by the touch electrodes 195 and 196 to the touch control circuit. In this respect, for example, a driver IC (e.g., data IC, etc.) of the data driver section 220, which includes the touch control circuit, can be configured in a COF type and connected to the non-display area NA of the substrate 101 of the display field 100, and in this case, one end of the touch connection area 198 and 199 can be connected to a flexible circuit film on which the driver IC is mounted, so that a signal can be transmitted. A touch protection layer 197 can be arranged on the touch electrodes 195 and 196. In the drawing, the touch protection layer 197 is shown such that it is arranged only on the touch electrodes 195 and 196, but is not limited to them, and the touch protection layer 197 can extend before or after the dam DAM to be arranged on the touch electrode connecting line 192. Additionally, a color filter can be arranged on the encapsulation layer 180. The color filter can be positioned on the contact layer 190 or between the encapsulation layer 180 and the contact layer 190. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0195685

[0001]

Claims

Light-emitting display device (10) comprising: a display field (100) comprising a display area (AA) and a non-display area (NA), wherein the display area (AA) comprises a plurality of pixels (P) arranged in a matrix form along a plurality of horizontal lines and a plurality of vertical lines, each pixel (P) comprising a light-emitting diode (OD) and a plurality of transistors electrically connected to the light-emitting diode (OD); and a sampler driver circuit located in the non-display area (NA) comprising a plurality of sampler stages (SSC), wherein at least one stage of the plurality of sampler stages (SSC) comprises: a first buffer section (BFl) configured to output a first sampler signal (SC1) applied jointly to pixels (P) of two adjacent horizontal lines,and a second-first buffer section (BF2_1) and a second-second buffer section (BF_2_2) configured to output two second sampling signals (SC2) applied to the pixels (P) of the two adjacent horizontal lines, wherein the first buffer section (BF1) includes a first buffer transistor (Tb1) and a second buffer transistor (Tb2), with a gate electrode of the first buffer transistor (Tb1) and a gate electrode of the second buffer transistor (Tb2) being jointly connected to a BG node, wherein the second-first buffer section (BF2_1) includes a third buffer transistor (Tb3) and a fourth buffer transistor (Tb4), with a gate electrode of the third buffer transistor (Tb3) being connected to an SQ node to receive a voltage from an output terminal (NO1) of the first buffer section (BF1), with a gate electrode of the fourth buffer transistor (Tb4) is connected to the BG node,wherein the second-second buffer section (BF2_2) includes a fifth buffer transistor (Tb5) and a sixth buffer transistor (Tb6), wherein a gate electrode of the fifth buffer transistor (TB5) is connected to the SQ node, wherein a gate electrode of the sixth buffer transistor (Tb6) is connected to the BG node, wherein the first buffer transistor (Tb1) is configured to receive a gate high voltage (VGH), wherein each of the second, fourth and sixth buffer transistors (Tb2, Tb4, Tb6) is configured to receive a gate low voltage (VGL), and wherein the third and fifth buffer transistors (Tb3, Tb5) are configured to receive a second-first sampling clock (S2CLK1) and a second-second sampling clock (S2CLK2), respectively. Light-emitting display device (10) according to claim 1, wherein the at least one scanning stage (SSC) further comprises: a first control transistor (Ts1) and a second control transistor (Ts2) connected in parallel to each other, configured to receive a transmission signal (SC1(n-2)), and connected to a CNT node; and a third control transistor (Ts3) and a fourth control transistor (Ts4) connected in series with the BG node arranged between them, and having gate electrodes connected to the CNT node. Light-emitting display device (10) according to claim 2, wherein the at least one scanning stage further includes a transfer transistor (TA) which is connected between the output terminal (NO1) of the first buffer section (BF1) and the SQ node. Light-emitting display device (10) according to claim 2 or 3, wherein the transmission signal (SC1(n-2)) is a first sampling signal of a previous sampling stage of the plurality of sampling stages. Light-emitting display device (10) according to one of claims 2 to 4, wherein the first control transistor (Ts1) is configured as an N-type transistor and has a gate electrode for receiving a first B-sampling clock (S1CLK1B), wherein the second control transistor (Ts2) is configured as a P-type transistor and has a gate electrode for receiving a first sampling clock, and wherein the first sampling clock and the first B-sampling clock (S1CLK1B) have opposite phases. Light-emitting display device (10) according to one of claims 2 to 5, wherein the third control transistor (Ts3) is configured as an N-type transistor and has a source electrode for receiving the gate low voltage (VGL), and wherein the fourth control transistor (Ts4) is configured as a P-type transistor and has a source electrode for receiving the gate high voltage (VGH). Light-emitting display device (10) according to one of claims 3 to 6, wherein the transfer transistor (TA) has a gate electrode for receiving the gate high voltage (VGH). Light-emitting display device (10) according to one of the preceding claims, wherein the plurality of scanning stages (SSC) comprises nth and n+1th scanning stages corresponding to the 2n-1th to 2n+2th horizontal lines of the display area (AA) and are arranged on one side and the other side of the display area (AA), wherein the nth scanning stage is configured to output an nth first scanning signal and 2n-1th and 2n-th second scanning signals for controlling the 2n-1th and 2n-th horizontal lines, wherein the n+1th scanning stage is configured to output an n+1th first scanning signal and 2n+1th and 2n+2th second scanning signals for controlling the 2n+1th and 2n+2th horizontal lines, and wherein n is an integer. Light-emitting display device (10) according to one of the preceding claims, wherein a width direction of the first, second, third, fourth, fifth and sixth buffer transistor (Tb1, Tb2, Tb3, Tb4, Tb5, Tb6) of the at least one scanning stage is vertical. Light-emitting display device according to claim 8, further comprising an nth emission stage arranged on the other side of the display area (AA), and an n+1th emission stage arranged on one side of the display area (AA), wherein the nth emission stage is configured to output an nth emission control signal for controlling the 2n-1th and 2n-th horizontal lines, and wherein the n+1th emission stage is configured to output an n+1th emission control signal for controlling the 2n+1th and 2n+2th horizontal lines. Light-emitting display device according to one of the preceding claims, wherein each of the plurality of pixels (P) comprises: a drive transistor (DT); a first transistor (T1) connected between a gate electrode and a drain electrode of the drive transistor (DT) and configured to receive the first sampling signal (SC1); and a second transistor (T2) connected between a source electrode of the drive transistor (DT) and a data line (DL) and configured to receive one of the two second sampling signals (SC2). Light-emitting display device (10) comprising: a display field (100) comprising a display area (AA) and a non-display area (NA), wherein the display area (AA) comprises a plurality of pixels arranged in a matrix form along a plurality of horizontal lines and a plurality of vertical lines, each pixel (P) comprising: a light-emitting diode (OD) and a plurality of transistors electrically connected to the light-emitting diode; and a plurality of sampling stages (SSC) in the non-display area (NA), each of the plurality of sampling stages (SSC) comprising a first buffer section (BF1) configured to output a first sampling signal (SC1) applied jointly to pixels (P) of two adjacent horizontal lines, and a second-first buffer section (BF2_1) and a second-second buffer section (BF2_2) configured toto output two second sampling signals (SC2), each applied to the pixels (P) of the two adjacent horizontal lines, wherein the plurality of sampling stages (SSC) includes nth and n+1th sampling stages corresponding to the 2n-1th to 2n+2th horizontal lines of the display area (AA), each arranged on one side and the other side of the display area (AA), wherein the nth sampling stage is configured to output an nth first sampling signal and 2n-1th and 2nth second sampling signals to drive the 2n-1th and 2nth horizontal lines, and wherein the n+1th sampling stage is configured to output an n+1th first sampling signal and 2n+1th and 2n+2th second sampling signals to drive the 2n+1th and 2n+2th horizontal lines. Light-emitting display device (10) according to claim 12, wherein the first buffer section (BF1) comprises a first buffer transistor (Tb1) and a second buffer transistor (Tb2), wherein a gate electrode of the first buffer transistor (Tb1) and a gate electrode of the second buffer transistor (Tb2) are jointly connected to a BG node, wherein the second buffer section (BF2_1) comprises a third buffer transistor (Tb3) and a fourth buffer transistor (Tb4), wherein a gate electrode of the third buffer transistor (Tb3) is connected to an SQ node for receiving a voltage from an output terminal (NO1) of the first buffer section (BF1), wherein a gate electrode of the fourth buffer transistor (Tb4) is connected to the BG node, wherein the second buffer section (BF2_2) comprises a fifth buffer transistor (Tb5) and a sixth buffer transistor (Tb6) includeswherein a gate electrode of the fifth buffer transistor (TB5) is connected to the SQ node, wherein a gate electrode of the sixth buffer transistor (Tb6) is connected to the BG node, wherein the first buffer transistor (Tb1) is configured to receive a gate high voltage (VGH), wherein each of the second, fourth and sixth buffer transistors (Tb2, Tb4, Tb6) is configured to receive a gate low voltage (VGL), and wherein the third and fifth buffer transistors (Tb3, Tb5) are configured to receive a second first sampling clock (S2CLK1) and a second second sampling clock (S2CLK2), respectively. Light-emitting display device (10) according to claim 13, wherein each of the plurality of sampling stages (SSC) comprises: a first control transistor (Ts1) and a second control transistor (Ts2) connected in parallel to each other, configured to receive a transmission signal (SC1(n-2)), and connected to a CNT node; and a third control transistor (Ts3) and a fourth control transistor (Ts4) connected in series with the BG node arranged between them, and having gate electrodes connected to the CNT node. Light-emitting display device according to claim 14, wherein each of the plurality of sampling stages further includes a transfer transistor (TA) which is connected between the output terminal (NO1) of the first buffer section (BF1) and the SQ node. Light-emitting display device (10) according to claim 14 or 15, wherein the n-th scanning stage is configured to receive a first scanning signal (SC1) of an n-2-th scanning stage arranged on one side of the display area (AA) as the transmission signal (SC1(n-2)), and wherein the n+1-th scanning stage is configured to receive a first scanning signal of an n-1-th scanning stage arranged on the other side of the display area (AA) as the transmission signal (SC1(n-2)). Light-emitting display device according to one of claims 13 to 16, wherein a width direction of the first, second, third, fourth, fifth and sixth buffer transistor (Tb1, Tb2, Tb3, Tb4, Tb5, Tb6) of each of the plurality of sampling stages (SSC) is vertical. Light-emitting display device (10) according to one of claims 12 to 17, further comprising an nth emission stage arranged on the other side of the display area (AA), and an n+1th emission stage arranged on one side of the display area, wherein the nth emission stage is configured to output an nth emission control signal for controlling the 2n-1th and 2n-th horizontal lines, and wherein the n+1th emission stage is configured to output an n+1th emission control signal for controlling the 2n+1th and 2n+2th horizontal lines. Light-emitting display device (10) according to one of claims 12 to 17, wherein each of the plurality of pixels (P) comprises: a drive transistor (DT); a first transistor (T1) connected between a gate electrode and a drain electrode of the drive transistor (DT) and configured to receive the first sampling signal (SC1); and a second transistor (T2) connected between a source electrode of the drive transistor (DT) and a data line (DL) and configured to receive one of the two second sampling signals (SC2).

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