HIGH-PERFORMANCE PHYSICAL COUPLING STRUCTURAL LAYER

Abstract

Processor device comprising: physical layer logic that can be executed to initialize a link, wherein initializing the link includes signaling a variety of link training states, including a reset state, a detection state, a query state, and a configuration state, wherein the physical layer logic is to send a detection supersequence to another device in association with the detection state, wherein the detection supersequence includes a pattern, and the pattern includes an electrical inactive ordered exit set (EIEOS) and a set of six instances of a training sequence for displaying the detection state, wherein the training sequence includes a defined data sequence to be used in the detection state, and each of the six instances of a training sequence includes a respective head.

Description

TECHNICAL AREA The present disclosure relates generally to the field of computer development and in particular to software development, which involves the coordination of mutually dependent constrained systems. BACKGROUND Advances in semiconductor processing and logic design have led to an increase in the amount of logic that can be present in integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present in individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor chip layer, which can include any number of cores, hardware threads or logical processors, interfaces, memory, controller hubs, and so on. As a result of the increased ability to pack more computing power into smaller packages, smaller computing devices have gained popularity. Smartphones, tablets, ultra-thin notebooks, and other subscriber terminals have proliferated exponentially. However, these smaller devices rely on servers for both data storage and complex processing that exceeds their form factor. Consequently, demand in the high-performance computing market (i.e., server storage space) has also increased. For example, modern servers typically contain not just a single multi-core processor, but multiple physical processors (also known as multi-sockets) to boost computing power. But as computing power increases along with the number of devices in a computer system, communication between sockets and other components becomes more critical. In fact, coupling structures have evolved from more traditional multipoint interconnect buses, which primarily handle electrical communications, into fully mature coupling structure architectures that facilitate high-speed communication. Unfortunately, the corresponding requirements are being allocated to the capabilities of existing coupling structure architectures, while the demand for future processors with even higher power consumption rates is increasing. US 2005 / 0262336 A1 discloses an in-band reset of the physical layers of two agents connected by a link-based connection scheme. The first agent terminates its forward clock to initiate the in-band reset. Upon detection of the termination, a second agent terminates its forward clock and enters a reset state. The first agent then enters a reset state. Subsequently, after waiting a predetermined time, both agents proceed with the re-initialization of the physical layer. US 7,564,904 B2 discloses a method for detecting switched-on devices over a network. A unique, infinite, pseudorandom sequence of pulses is generated and transmitted over the network to the connection partner at the other end of the cable. At each unit of time, a PSE decides whether to send a pulse at that moment. Thus, the generated pulses have pseudorandom delays between them. The invention disclosed herein is based on the objective of addressing certain problems in initializing connections between devices. This objective is achieved by the attached claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a simplified block diagram of a system that includes a serial point-to-point coupling structure to connect I / O devices in a computer system according to one embodiment; Fig. 2 illustrates a simplified block diagram of a layered protocol stack according to one embodiment; Fig. 3 illustrates an embodiment of a transaction descriptor. Fig. 4 illustrates an embodiment of a serial point-to-point link. Fig. 5 illustrates embodiments of potential high-performance coupling structure (HPI) system configurations. Fig. 6 illustrates an embodiment of a layered protocol stack connected to an HPI. Fig. 7 illustrates a representation of an exemplary state machine. Fig. 8 illustrates exemplary control supersequences. Fig. 9 illustrates a flowchart of an exemplary transition to a partial-width state.Figure 10 illustrates one embodiment of a block diagram for a computer system that includes a multi-core processor. Figure 11 illustrates another embodiment of a block diagram for a computer system that includes a multi-core processor. Figure 12 illustrates one embodiment of a block diagram for a processor. Figure 13 illustrates another embodiment of a block diagram for a computer system that includes a processor. Figure 14 illustrates one embodiment of a block for a computer system that includes multi-processor sockets. Figure 15 illustrates another embodiment of a block diagram for a computer system. Identical reference numbers and designations in the different drawings refer to similar elements. DETAILED DESCRIPTION The following description presents numerous specific details, such as examples of certain types of processors and system configurations, specific hardware arrangements, specific details about architecture and microarchitecture, specific register configurations, specific instruction types, specific system components, specific processor pipeline stages, specific coupling structure layers, specific packet / transaction configurations, specific transaction names, specific protocol exchange operations, specific link widths, specific implementations and operations, etc., to ensure a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that these specific details are not necessarily required to implement the subject matter of the present disclosure. In other cases, a detailed description of known components or methods, such as...Special and alternative processor architectures, special logic circuits / special code for described algorithms, special firmware code, special low-level interconnection operations, special logic configurations, special manufacturing techniques and materials, special compiler implementations, special implementation of algorithms in code, special shutdown and gating techniques / logic, and other special operating details of computer systems have been avoided in order to prevent unnecessary obfuscation of the present invention. Although the following embodiments may be described with reference to energy saving, energy efficiency, processing efficiency, and so forth, in relation to specific integrated circuits such as computer platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic assemblies. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from these features. For example, the disclosed embodiments are not limited to server computer systems, desktop computer systems, laptops, and Ultrabooks™, but may also be used in other devices such as handheld devices, smartphones, tablets, other thin notebooks, systems-on-a-chip (SoC) devices, and embedded applications. Some examples of handheld devices include, but are not limited to, the following:Mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Similar techniques for a high-performance coupling structure can be applied here to increase performance (or even save energy) in a low-energy coupling structure. Embedded applications typically include, among other things, a microcontroller, digital signal processor (DSP), system-on-a-chip, network computer (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or other systems capable of performing the functions and operations described below. Furthermore, the devices, methods, and systems described here are not limited to physical computing equipment but can also involve software optimizations for energy saving and efficiency.As is readily apparent from the following description, the embodiments of the methods, devices and systems described herein (whether referring to hardware, firmware, software or a combination thereof) can be considered crucial for a “green technology” future, balanced with performance considerations. As computer systems evolve, their components become more complex. The coupling structure architecture used to connect and communicate between these components has also increased in complexity to ensure that bandwidth demands are met for optimal component operation. Furthermore, different market segments require different aspects of coupling structure architectures to be suitable for their respective markets. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for energy savings. Yet, the singular purpose of most fabrics is to deliver the highest possible performance with maximum energy savings. Therefore, a wide variety of different coupling structures can potentially benefit from the subject matter described here. The Peripheral Component Interconnect (PCI) Express (PCIe) interconnect fabric architecture and the QuickPath Interconnect (QPI) fabric architecture, among others, can potentially be improved according to one or more of the principles described here. For example, a primary goal of PCIe is to enable components and devices from different vendors to interoperate in an open architecture spanning multiple market segments: clients (desktops and mobile), servers (standard and enterprise), and embedded and communications devices. PCI Express is a universal, high-performance I / O interconnect fabric for a wide variety of computing and communications platforms.Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been retained across revisions, while previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. Newer versions of PCI Express leverage advancements in point-to-point coupling structures, switch-based technology, and packaged protocol to deliver new levels of performance and features. Power management, Quality of Service (QoS), hot-plug / hot-swap support, data integrity, and error handling are some of the advanced features supported by PCI Express.Although the primary discussion herein refers to a new HPI architecture, aspects of the invention described herein may be applied to other coupling structure architectures, such as a PCIe-compliant architecture, a QPI-compliant architecture, a MIPI-compliant architecture, a high-performance architecture, or any other known coupling structure architecture. With reference to Fig. 1, an embodiment of a fabric is illustrated, consisting of point-to-point links connecting a set of components. The system 100 includes a processor 105 and system memory 110 coupled to the controller hub 115. The processor 105 can include any processing elements, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. The processor 105 is coupled to the controller hub 115 via the front-side bus (FSB) 106. In one embodiment, the FSB 106 is a serial point-to-point coupling structure, as described below. In another embodiment, the link 106 includes a serial differential coupling structure architecture conforming to a different coupling structure standard. System memory 110 comprises any memory unit, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to the components of system 100. System memory 110 is coupled to the controller hub 115 via memory interface 116. Examples of memory interfaces include dual-rate DDR memory interface, dual-channel DDR memory interface, and dynamic RAM (DRAM) memory interface. In one embodiment, the controller hub 115 can include a root hub, root complex, or root controller, similar to a PCIe connection hierarchy. Examples of a controller hub 115 include a chipset, memory controller hub (MCH), northbridge, coupling structure controller hub (ICH), southbridge, and a root controller / hub. Often, the term chipset refers to two physically separate controller hubs, such as a memory controller hub (MCH) coupled to a coupling structure controller hub (ICH). Note that current systems often integrate the MCH into the processor 105, while the controller 115 communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported by the root complex 115. Here, the controller hub 115 is coupled to the switch / bridge 120 via the serial link 119. The I / O modules 117 and 121, which can also be referred to as interfaces / ports 117 and 121, can include / implement a layered protocol stack to provide communication between the controller hub 115 and the switch 120. In one embodiment, multiple devices are capable of being coupled to the switch 120. Switch / bridge 120 routes packets / messages from device 125 upstream, i.e., a hierarchy upwards towards a root complex to the controller hub 115, and downstream, i.e., a hierarchy downwards away from a root controller of processor 105 or system memory 110 to device 125. In one embodiment, switch 120 is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 125 includes any internal or external device or component connected to an electronic system, such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk drive, a storage device, a CD / DVD-ROM drive, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices.In PCIe terminology, such a device is often referred to as an endpoint. Although not specifically shown, Device 125 may include a bridge (e.g., a PCIe-to-PCI / PCI-X bridge) to support legacy or other versions of devices, or coupling fabrics supported by such devices. A graphics accelerator 130 can also be coupled to the controller hub 115 via a serial link 132. In one embodiment, the graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. The switch 120, and consequently the I / O device 125, is then coupled to the ICH. The I / O modules 131 and 118 also implement a layered protocol stack for communication between the graphics accelerator 130 and the controller hub 115. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 130 itself can be integrated into the processor 105. With reference to Fig. 2, one embodiment of a layered protocol stack is illustrated. The layered protocol stack 200 can include any form of layered communication stack, such as a QPI stack, a PCIe stack, a next-generation HPI stack, or any other layered stack. In one embodiment, the protocol stack 200 can include the transaction layer 205, the link layer 210, and the physical layer 220. An interface such as interfaces 117, 118, 121, 122, 126, and 131 in Fig. 1 can be represented as the communication protocol stack 200. The representation as a communication protocol stack can also be described as a module or interface that implements / includes a protocol stack. Packets can be used to communicate information between components. Packets can be formed in the transaction layer (205) and the data link layer (210) to transport information from the sending component to the receiving component. As the sent packets move through the other layers, they are augmented with additional information necessary for processing packets at those layers. On the receiving side, the reverse process occurs, and the packets are transformed from a representation of their physical layer (220) to a representation of the data link layer (210) and finally (for transaction layer packets) into a form that can be processed by the transaction layer (205) of the receiving device. In one embodiment, the transaction layer 205 can provide an interface between a device's processor core and the coupling structure architecture, such as the data link layer 210 and the physical layer 220. In this respect, a primary responsibility of the transaction layer 205 can include merging and splitting packets (i.e., transaction layer packets, or TLPs). The translation layer 205 can also manage credit-based flow control for TLPs. Some implementations can employ split transactions, i.e., transactions in which the request and response are separated by time, allowing one link, among other examples, to carry other traffic while the destination device gathers data for the response. Credit-based flow control can be used to implement virtual channels and networks that utilize the coupling structure fabric. For example, a device can offer an initial amount of credits to each of the receive buffers in transaction layer 205. An external device at the opposite end of the link, such as controller hub 115 in Fig. 1, can count the number of credits consumed by each TLP. A transaction can be sent as long as it does not exceed the credit limit. Upon receiving a response, a credit amount is restored. One advantage, among others, of such a credit scheme is that the latency of credit return does not impact performance, provided the credit limit is not reached. In one embodiment, four transaction address spaces can include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read and write requests to transfer data to / from a memory-allocated location. In one embodiment, memory space transactions are capable of using two different instruction types, such as a short address format like a 32-bit address or a long address format like a 64-bit address. Configuration space transactions can be used to access the configuration space of various devices connected to the coupling structure. Configuration space transactions can include read and write requests.Message space transactions (or simply messages) can also be defined to support in-band communication between coupling structure agents. Therefore, in an exemplary embodiment, the transaction layer 205 can concatenate packet headers / payloads 206. With brief reference to Fig. 3, an exemplary embodiment of a transaction layer packet descriptor is illustrated. In one embodiment, the transaction descriptor 300 can be a mechanism for transporting transaction information. In this respect, the transaction descriptor 300 supports the identification of transactions in a system. Other possible uses include tracking modifications of standard transaction order and linking transactions to channels. For example, the transaction descriptor 300 can include the global identifier field 302, attribute field 304, and channel identifier field 306. In the illustrated example, the global identifier field 302 is comprehensively represented as the local transaction identifier field 308 and the source identifier field 310. In one embodiment, the global transaction identifier 302 is unique for all pending requests. According to one implementation, the local transaction identifier field 308 is generated by a requesting agent and can be unique for all pending requests requiring completion for that requesting agent. Furthermore, in this example, the source identifier 310 uniquely identifies the requesting agent within a coupling structure hierarchy. Accordingly, the local transaction identifier field 308, together with the source ID 310, provides the global identification of a transaction within a hierarchy domain. Attribute field 304 specifies properties and relationships of the transaction. In this respect, attribute field 304 is potentially used to provide additional information that allows modification of the default transaction handling. In one implementation, attribute field 304 includes the priority field 312, reserved field 314, order field 316, and the no-snoop field 318. Here, the priority subfield 312 can be modified by an initiator to assign a priority to the transaction. The reserved attribute field 314 remains reserved for future or vendor-defined use. Possible usage models that utilize priority or security attributes can be implemented using the reserved attribute field. In this example, the order attribute field 316 is used to provide optional information that conveys the type of order that can modify the default ordering rule. According to one example implementation, an order attribute of "0" indicates that default ordering rules should be applied, while an order attribute of "1" indicates relaxed ordering, where writes can pass other writes in the same direction and read operations can pass other writes in the same direction. The snoop attribute field 318 is used to determine whether transactions are snooped. As shown, the channel identifier field 306 determines a channel to which a transaction is associated. Returning to the discussion of Fig. 2, a link layer 210, also referred to as the data link layer 210, can act as an intermediate stage between the transaction layer 205 and the physical layer 220. In one embodiment, one responsibility of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components at a link. One side of the data link layer 210 accepts TLPs concatenated by the transaction layer 205, applies the packet sequence identifier 211, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 212, and submits the modified TLPs to the physical layer 220 for transmission over a physical layer to an external device. In one example, the physical layer 220 includes the logical sub-block 221 and the electrical sub-block 222 to physically send a packet to an external device. Here, the logical sub-block 221 is responsible for the "digital" functions of the physical layer 221. In this respect, the logical sub-block can include a send part to prepare outgoing information for transmission by the physical sub-block 222, and a receive part to determine and prepare received information before passing it on to the link layer 210. The physical block 222 includes a transmitter and a receiver. The transmitter is supplied with symbols by the logical subblock 221, which the transmitter serializes and sends to a peripheral device. The receiver is supplied with serialized symbols from a peripheral device and converts the received signals into a bitstream. The bitstream is deserialized and provided to the logical subblock 221. In one exemplary embodiment, an 8b / 10b transmission code is used, with ten-bit symbols being sent / received. Here, special symbols are used to form a packet containing the frames 223. In one example, the receiver also provides a symbol clock recovered from the incoming serial stream. Although the transaction layer 205, link layer 210, and physical layer 220 are described above with reference to a specific embodiment of a protocol stack (such as a PCIe protocol stack), a layered protocol stack is not limited in this respect. In fact, any layered protocol can be included / implemented and adopt features described herein. As an example, a port / interface represented as a layered protocol may include: (1) a first layer to concatenate packets, i.e., a transaction layer; (2) a second layer to sequentialize packets, i.e., a link layer; and (3) a third layer to send the packets, i.e., a physical layer. As a specific example, an HPI layered protocol as described below is used. With reference to Fig. 4, an exemplary embodiment of a serial point-to-point fabric is illustrated. A serial point-to-point link can include any transmission path for sending serial data. In the embodiment shown, a link can include two differentially driven low-voltage signal pairs: a transmit pair 406 / 411 and a receive pair 412 / 407. Accordingly, device 405 includes the transmit logic 406 to send data to device 410 and the receive logic 407 to receive data from device 410. In other words, two transmit paths, i.e., paths 416 and 417, and two receive paths, i.e., paths 418 and 419, are included in some implementations of a link. A transmission path refers to any route for sending data, such as a transmit line, a copper wire, an optical line, a wireless communication channel, an infrared communication link, or any other communication path. A connection between two devices, such as Device 405 and Device 410, is called a link, for example, Link 415. A link can support one lane—each lane represents a set of differential signal pairs (one pair for transmitting, one pair for receiving). To scale bandwidth, a link can aggregate multiple lanes, designated xN, where N is each supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider. A difference pair can refer to two transmission paths, such as lines 416 and 417, to transmit differential signals. For example, when line 416 switches from a low voltage level to a high voltage level (i.e., a rising edge), line 417 transitions from a high logic level to a low logic level (i.e., a falling edge). Differential signals, among other advantages, potentially exhibit better electrical characteristics, such as improved signal integrity (i.e., reduced cross-coupling, over- / under-voltage, and ringing). This allows for a narrower timing window, enabling faster transmission frequencies. In one embodiment, a new HPI is provided. The HPI can include a next-generation, cache-coherent, link-based coupling structure. As an example, the HPI can be used in high-performance computing platforms such as workstations or servers, including systems where PCIe or another coupling structure protocol is typically used to connect processors, accelerators, I / O devices, and the like. However, the HPI is not limited to this. Instead, the HPI can be used in any of the systems or platforms described here. Furthermore, the individually developed ideas can be applied to other coupling structures and platforms such as PCIe, MIPI, QPI, etc. To support multiple devices in an exemplary implementation, the HPI can be instruction set architecture (ISA) agnostic (i.e., the HPI can be implemented across several different devices). In another scenario, the HPI can also be used to connect high-performance I / O devices, not just processors or accelerators. For example, a high-performance PCIe device can be coupled to the HPI through a suitable translation bridge (i.e., HPI to PCIe). Furthermore, the HPI links can be used by many HPI-based devices, such as processors, in various configurations (e.g., star, ring, mesh, etc.). Figure 5 illustrates exemplary implementations of several potential multi-socket configurations. A two-socket 505 configuration can include two HPI links as shown; however, other implementations may use only one HPI link.For larger topologies, any configuration can be used as long as an identifier (ID) can be assigned and some form of virtual path exists, along with other additional or substitute features. As shown in one example, a four-socket configuration 510 has an HPI link from each processor to every other processor. However, in the eight-socket implementation shown in configuration 515, not every socket is directly connected to each other via an HPI link. If a virtual path or channel exists between the processors, however, the configuration is supported. A range of supported processors includes 2–32 in a native domain. Higher numbers of processors can be achieved, among other examples, by using multiple domains or other coupling structures between node controllers. The HPI architecture includes a definition of a layered protocol architecture, which in some examples includes protocol layers (coherent, incoherent, and optionally other memory-based protocols), a routing layer, a link layer, and a physical layer. Furthermore, HPI can include additional extensions related to power managers (such as power control units (PCUs)), design for testing and debugging (DFT), error handling, registers, and security, among other examples. Figure 5 illustrates an embodiment of an exemplary HPI layered protocol stack. In some implementations, at least some of the layers illustrated in Figure 5 may be optional. Each layer deals with its own level of granularity or set of information (the protocol layer 605a,b with the packets 630, the link layer 610a,b with the flits 635, and the physical layer 605a,b with the phits 640).It should be noted that in some implementations, a package may include partial flits, a single flit, or multiple flits. As a first example, the width of a Phit 640 implies a one-to-one mapping of the link width to bits (e.g., a 20-bit link width implies a Phit of 20 bits, and so on). Flits can have larger sizes, such as 184, 192, or 200 bits. It's important to note that if the Phit 640 is 20 bits wide and the size of the Flit 635 is 184 bits, then a fraction of the Phits 640 is required to send a Flit 635 (e.g., 9.2 Phits at 20 bits to send a 184-bit Flit 635, or 9.6 at 20 bits to send a 192-bit Flit, among other examples). It should be noted that the widths of the elementary link at the physical layer can vary. For example, the number of lanes per instruction can include 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, etc. In one embodiment, the link layer 610a,b is capable of embedding multiple parts of different transactions in a single flit and one or more headers (e.g.,1, 2, 3, 4) can be embedded within the flit. In one example, HPI divides the headers into corresponding slots to allow multiple messages in the flit intended for different nodes. In one embodiment, physical layer 605a,b can be responsible for the rapid transmission of information over the physical medium (electrical or optical, etc.). The physical link can be point-to-point between two link layer entities, such as layers 605a and 605b. Link layer 610a,b can abstract physical layer 605a,b from the upper layers and provides the capability to reliably transmit data (as well as requests) and manage flow control between two directly connected entities. The link layer can also be responsible for virtualizing the physical channel into multiple virtual channels and message classes. Protocol layer 620a,b relies on link layer 610a,b to assign protocol messages to the appropriate message classes and virtual channels before passing them to physical layer 605a,b for transmission over the physical links.The link layer 610a,b can support multiple messages such as a request, snoop response, write-back, and incoherent data, among other examples. The physical layer 605a,b (or PHY) of the HPI can be implemented above the electrical layer (i.e., electrical conductors connecting two components) and below the link layer 610a,b, as illustrated in Fig. 6. The physical layer and corresponding logic can reside at each agent and connect the link layers separately for two agents (A and B) (e.g., devices on either side of a link). The local and remote electrical layers are connected by physical media (e.g., wires, conductors, optical, etc.). In one embodiment, the physical layer 605a,b has two essential phases: initialization and operation. During initialization, the connection to the link layer is opaque, and signaling can involve a combination of timed states and handshake events.During operation, the connection to the link layer is transparent, and signaling occurs at a single velocity, with all lanes operating together as a single link. During the operational phase, the physical layer transports flits from agent A to agent B and from agent B to agent A. The connection, also referred to as a link, abstracts some physical aspects, including media, width, and velocity, from the link layers, while flits and control / status of the current configuration (e.g., width) are exchanged with the link layer. The initialization phase includes subordinate phases, such as querying and configuration. The operational phase includes subordinate phases (e.g., link power management states). In one embodiment, the link layer 610a,b can be implemented to provide reliable data transmission between two protocol or routing entities. The link layer can abstract the physical layer 605a,b from the protocol layer 620a,b and can be responsible for flow control between two protocol agents (A, B) and provide virtual channel services to the protocol layer (message classes) and routing layer (virtual networks). The interface between the protocol layer 620a,b and the link layer 610a,b can typically be at the packet layer. In one embodiment, the smallest transfer unit at the link layer is called a flit with a specific number of bits, such as 192 bits, or with another designation.Link layer 610a,b relies on physical layer 605a,b to transform the physical layer 605a,b transmission unit (phit) into the link layer 610a,b transmission unit (flit). Furthermore, link layer 610a,b can be logically divided into two parts: a sender and a receiver. A sender / receiver pair at one entity can be connected to a receiver / sender pair at another entity. Flow control is often performed on both a flit and a packet basis. Error detection and correction are also potentially performed on a flit level. In one embodiment, routing layer 615a,b can provide a flexible and distributed method for routing HPI transactions from a source to a destination. The scheme is flexible because routing algorithms for multiple topologies can be specified by programmable routing tables at each router (the programming is performed by firmware, software, or a combination thereof in one embodiment). The routing functionality can be distributed; routing can be performed through a series of routing steps, each defined by a lookup of a table at either the source, intermediate, or destination routers. The lookup at a source can be used to introduce an HPI packet into the HPI fabric. The lookup at an intermediate router can be used to route an HPI packet from an input port to an output port.Looking up a destination port can be used to address the destination HPI protocol agent. It's important to note that the routing layer can be thin in some implementations because the routing tables, and therefore the routing algorithms, are not specifically defined by specification. This allows for flexibility and a variety of usage models, including flexible architectural platform topologies, which are defined by the system implementation. Routing layer 615a,b relies on link layer 610a,b to provide the use of up to three (or more) virtual networks (VNs)—in one example, two VNs without deadlocks, VN0 and VN1, with multiple message classes defined in each virtual network.A shared adaptive virtual network (VNA) may be defined in the link layer, but this adaptive network may not be directly exposed in routing concepts, as each message class and virtual network may have fixed resources allocated and guaranteed progress, among other features and examples. In some implementations, the HPI can use an embedded clock. A clock signal can be embedded in data transmitted using the coupling structure. With the clock signal embedded in the data, distinct and associated clock paths can be omitted. This can be useful, for example, because it allows more pins of a device to be allocated for data transmission, especially in systems where pin space is at a premium. A link can be established between two agents on either side of a coupling structure. An agent that sends data can be a local agent, and the agent that receives the data can be a remote agent. State machines can be used by both agents to manage various aspects of the link. In one embodiment, the physical layer data path can send Flits from the link layer to the electrical front end. The control path, in one implementation, includes a state machine (also called a link-training state machine or similar). The actions and state exits of the state machine can depend on internal signals, timers, external signals, or other information. In fact, some states, such as certain initialization states, can have timers to provide a timeout value for exiting a state.It should be noted that in some embodiments, "detect" refers to the detection of an event on both segments of a path, but not necessarily simultaneously. In other embodiments, "detect" refers to the detection of an event by a reference agent. "Debouncing," for example, refers to a sustained assertion of a signal. In one embodiment, the HPI supports operation in the case of malfunctioning paths. Here, paths can be dropped under specific conditions. States defined in the state machine can include reset states, initialization states, and operating states, among other categories and subcategories. For example, some initialization states may have a secondary timer used to exit the state on a timeout (essentially an abort due to failure to progress within the state). An abort may involve updating registers such as status registers. Some states may also have primary timers used to time the primary functions within the state. Other states may be defined such that internal or external signals (such as handshake protocols), among other examples, cause the transition from one state to another. A state machine can also support debugging through single-step operation, freezing on initialization failure, and the use of checkers. State exits can be deferred / held until the debugging software is ready. In one instance, the exit can be deferred / held until the secondary timeout. Actions and exits can, in one embodiment, be based on the exchange of training sequences. In another embodiment, the link state machine runs in the clock domain of the local agent, and the transition from one state to the next coincides with a training sequence limit of the sender. State registers can be used to reflect the current state. Figure 7 illustrates a representation of at least part of a state machine used by agents in an exemplary HPI implementation. It should be understood that the states included in the state table of Figure 7 represent a non-exhaustive list of possible states. For example, some transitions are omitted to simplify the diagram. Furthermore, some states may be combined, split, or omitted, while others may be added. Such states may include: Event Reset State: entered upon a warm or cold start event. Restores default values. Initializes counters (e.g., synchronization counters). May exit to another state, such as another reset state. Timed Reset State: timed state for in-band reset.Can control a predefined electrical ordered set (EOS) so that remote receivers are able to detect the EOS and also enter the timed reset. The receiver has traces that hold electrical settings. Can exit to an agent to calibrate the reset state. Calibration reset state: Calibrate without signaling on the trace (e.g., receiver calibration state) or turning off drivers. Can be a predetermined duration in the state based on a timer. Can set an operating speed. Can act as a wait state when a port is not enabled. Can include a minimum residence time. Receiver conditioning or staggered off can occur based on the design. Can exit to a receiver detection state after a timeout and / or completion of a calibration. Receiver detection state: detects the presence of a receiver on a track or tracks. Can see after a receiver completion (e.g., receiver pulldown insertion). Can exit to the calibration reset state after a specified value is set, or if another specified value is not set. Can exit to the transmitter calibration state when a receiver is detected or a timeout is reached. Transmitter calibration state: for transmitter calibrations. Can be a timed state assigned for transmitter calibrations. Can include signaling on a path. Can continuously drive an EOS such as an electrically inactive Exit-Ordered-Set (EIEOS). Can exit to the compliance state upon completion of calibration or after a timer expires. Can exit to the transmitter detection state when a counter expires or a secondary timeout occurs. Sender detection state: qualifies valid signaling. Can be a handshake state where an agent completes actions and exits to the next state based on remote agent signaling. The receiver can qualify valid signaling from the sender. In one embodiment, the receiver looks for a wake-up detection, and if debouncing occurs on one or more lanes, it looks for it on the other lanes. The sender drives a detection signal. Can exit to a query state in response to debouncing that is complete for all lanes and / or a timeout, or if debouncing is not complete on all lanes and there is a timeout. Here, one or more monitoring lanes can be kept awake to debounce a wake-up signal. And if debouncing occurs, then the other lanes are potentially debounced. This can enable power savings in low-power states. Query state: The receiver adapts, initializes drift buffers, and locks at bits / bytes (e.g., determining symbol boundaries). Trajectories can be straightened. A remote agent can initiate an exit to the next state (e.g., a link width state) in response to an acknowledgment message. Queries can additionally include a training sequence lock by locking to an EOS and a training sequence header. Trajectory-to-trajectory bit shift at the remote sender can be capped at a first length for high speed and a second length for low speed. Deskew can be performed in a slow mode as well as an operating mode. The receiver can have a special maximum for straightening trajectory-to-trajectory bit shifts, such as 8, 16, or 32 intervals of bit shift. Receiver actions can include latency fixing.In one embodiment, receiver actions can be completed upon successful deskew of a valid path assignment. A successful handshake can be achieved, for example, by receiving a number of consecutive training sequence headers containing acknowledgments and sending a number of training sequences with an acknowledgment after the receiver has completed its actions. Link Width State: The agent communicates with the final path mapping to the remote sender. The receiver receives and decodes the information. The receiver can record a configured path mapping in one structure after the checkpoint of a previous path mapping value in a second structure. The receiver can also respond with an acknowledgment ("ACK"). It can initiate an in-band reset. As an example, the first state is used to initiate an in-band reset. In one embodiment, exiting to a subsequent state, such as a flit configuration state, is performed in response to the ACK. A reset signal can also be generated before entering the low-energy state if the frequency of an alarm detection signal falls below a setpoint (e.g., 1 for every number of unit intervals (UIs), such as 4K UI). The receiver can retain current and previous path mappings.The transmitter can use different groups of paths based on training sequences that have different values. Path assignment may not modify some status registers in some implementations. Flitlock configuration state: Entry by a sender, but the state is considered exited (i.e., secondary timeout disputed) when both sender and receiver have exited to a Blocking Link state or another link state. Sender exit to a link state, in one embodiment, involves starting from a Data Sequence (SDS) and Training Sequence (TS) boundary after receiving a planetary synchronization signal. Here, receiver exit can be based on receiving an SDS from a remote sender. This state can be a bridge from the agent to the link state. Receiver determines the SDS. Receiver can exit to the Blocking Link (BLS) state (or a control window) when the SDS is received after a descrambler is initialized. If a timeout occurs, exit can be to the reset state. Sender controls orbits with a configuration signal.Transmitter exit can occur due to reset, BLS, or other states based on conditions or timeouts. Send Link State: A link state. Flits are sent to a remote agent. Entry can occur from a Blocking Link State, and return to a Blocking Link State can occur upon an event such as a timeout. Sender sends Flits. Receiver receives Flits. Can also exit to a Low Energy Link State. In some implementations, the Send Link State (TLS) may be referred to as the L0 state. Block Link State: A link state in which the sender and receiver operate in a unified manner. It can be a timed state during which link layer flits are paused while physical layer information is communicated to the remote agent. It can exit to a low-energy link state (or another link state based on the design). In one embodiment, a Block Link State (BLS) occurs periodically. The period is called a BLS interval and can be timed and may vary between slow speed and operating speed. Note that the link layer can be periodically blocked with respect to sending flits, allowing a physical layer control sequence of a length similar to that transmitted during a Send Link State or a Part-Width Send Link State.In some implementations, the Block Link State (BLS) may be referred to as an L0 control or an L0c state. Partial-width transmit link state: Link state. Can save energy by entering a partial-width state. In one embodiment, asymmetric partial-width refers to each direction of a two-way link that has different widths, which can be supported in some designs. An example of an initiator, such as a transmitter, that sends a partial-width hint to enter the partial-width transmit link state is shown in the example in Fig. 9. Here, a partial-width hint is sent while transmitting on a link with a first width to cause the link to transition to transmitting at a second, new width. A mismatch can result in a reset. Note that speeds cannot be changed, but widths can. Therefore, flits are potentially transmitted at different widths.It can be logically similar to a transmit link state; however, because of the smaller bandwidth, it may take longer to transmit flits. It can exit to other link states, such as a low-energy link state based on certain received and transmitted messages, or exit the partial-width transmit link state or a link-blocking state based on other events. In one embodiment, a transmit port can turn off inactive orbits in a staggered manner to provide better signal integrity (i.e., noise reduction). Here, non-retrying flits, such as null flits, can be used during periods when the link width is changing. A corresponding receiver can drop these null flits and turn off inactive orbits in a staggered manner, as well as record the current and previous orbit mappings in one or more structures.It should be noted that status and associated status registers can remain unchanged. In some implementations, the partial-width transmit link state may be referred to as a partial L0 or L0p state. Partial-width transmit link state exit: Exit the partial-width state. May or may not use a blocking link state in some implementations. In one embodiment, the sender initiates the exit by sending partial-width exit patterns on inactive lanes to train and straighten them. As an example, an exit pattern starts with an EIEOS that is detected and debounced to signal that the lane is ready to enter a full transmit link state, and it may end with an SDS or a fast training sequence (FTS) on inactive lanes. Any failure during the exit sequence (receiver actions such as not completing a deskew before the timeout) stops flit transmissions to the link layer and asserts a reset, which is handled by resetting the link the next time a blocking link state occurs.The SDS can also initialize the scrambler / descrambler on the lanes to suitable values. Low-energy link state: This is a low-energy state. In one embodiment, it is lower energy than the partial-width link state because signaling is stopped on all paths and in both directions. Transmitters can use a block link state to request a low-energy link state. Here, the receiver can decode the request and respond with an ACK or NAK; otherwise, a reset can be triggered. In some implementations, the low-energy link state may be referred to as an L1 state. In some implementations, state transitions can be simplified to allow states to be bypassed, for example, when state actions, such as certain calibrations and configurations, have already been completed. Previous state results and configurations of a link can be stored and reused in subsequent initializations and configurations of that link. Instead of repeating such configurations and state actions, the corresponding states can be bypassed. However, traditional systems that implement state bypassing often employ complex designs and costly validation escapes. Instead of using a traditional workaround, in one example, the HPI can use short time elements in certain states where, for instance, state actions do not need to be repeated. This can potentially enable more consistent and synchronized state machine transitions, among other potential advantages. In one example, a software-based controller (e.g., via an external control point for the physical layer) can activate a short-time timer for one or more specific states. For a state where actions have already been executed and stored, the state can be short-timed, for instance, to facilitate a quick exit to the next state. However, if the preceding state action fails or cannot be applied within the short-time timer's duration, a state exit can occur. Furthermore, the controller can deactivate the short-time timer, for example, if the state actions are due to be executed again. A long-time or default timer can be set for each corresponding state. If configuration actions for the state cannot be completed within the long-time timer's duration, a state exit can occur.The long-term timer can be set to an appropriate duration to allow the completion of state actions. In contrast, the short-term timer can be considerably shorter, which in some cases makes it impossible to execute state actions without referencing previously executed state actions, among other examples. In some cases, during the initialization (or re-initialization) of a link, while agents progress through a state machine toward an operational link state, one or more errors or state exits may occur, causing the state to be reset (e.g., to a reset or another state). In fact, the link initialization may complete one or more states without finishing the initialization and entering a link state. For example, a counter can be maintained to track the number of unproductive loops in state transitions within a link initialization. For instance, each time an initialization returns to a reset state without reaching a link state, a counter can be incremented. The counter can be reset for that link once the link successfully enters a link state.Such counters can be managed by agents on either side of the link. Furthermore, a threshold can be determined, for example, by a software-based controller using one or more external control points. If the count of unproductive loops reaches (or exceeds) the defined threshold, the link's initialization can be suspended (e.g., set and held at or before the reset state). In some implementations, a software-based controller can trigger a restart or re-initialization of the link to resume initialization and release it from the suspended state. In some cases, the software-based tools can analyze the nature of the suspended initialization and perform diagnostics, set register values, and execute other operations to prevent further initialization looping.In fact, in some implementations, a controller can, among other examples, set a higher counter threshold or even override the counter when restarting a suspended link initialization. In some HPI implementations, supersequences can be defined, with each supersequence corresponding to a specific state or entry / exit into / out of that state. A supersequence can include a repetition sequence of data records and symbols. In some cases, the sequences can repeat until the completion of a state or state transition, or the communication of a corresponding event, among other examples. In some cases, the repetition sequence of a supersequence can repeat at a defined frequency, such as a defined number of unit intervals (UIs). A unit interval (UI) can correspond to the time interval for transmitting a single bit on a lane of a link or system. In some implementations, the repetition sequence can begin with an EOS (End of System).Accordingly, an instance of the EOS can be expected to repeat itself according to a predefined frequency. Such ordered sets can be implemented as defined 16-byte codes, which can be represented in hexadecimal format, among other examples. In one example, the EOS of a supersequence can be an electrically inactive ordered set (or EIEIOS). In another example, an EIEOS can resemble a low-frequency clock signal (e.g., a predefined number of repeating hexadecimal symbols FF00 or FFF000, etc.). A predefined data set can follow the EOS, such as a predefined number of training sequences or other data. Such supersequences can be used in state transitions, which include, among other examples, link state transitions and initialization. In some implementations of a coupling structure, such as QPI, serial data link terminations can be enabled and disabled, for example, when a link is reset or initialized. This approach can introduce complexity and time into link initialization. Some HPI implementations can maintain link terminations, even during a link reset or reinitialization. Furthermore, HPI can allow hot-install devices. When another device is introduced, either through hot-install or otherwise, the voltage behavior of the track to which the new remote agent is added changes. The local agent can detect these changes in track voltage to recognize the presence of the remote agent and initiate link initialization.State machine states and timers can be defined in the state machine to coordinate the detection, configuration, and initialization of a link without closures. In one implementation, HPI can support reinitialization on an in-band reset without modifying the termination values ​​by having the receiving agent screen a path for incoming signaling. This signaling can be used to determine good paths. For example, the path can be checked against any of a predefined set of signals to be sent by a transmitting device to facilitate link discovery and configuration. In another example, a supersequence can be defined according to one or more initialization or reinitialization tasks. The predefined sequence can include an EIEOS followed by additional sequence data. In some cases, devices can begin sending a supersequence according to a specific initialization state, and so on, while each device on both sides of a path becomes active.In one embodiment, two types of pin resets can be supported: power-on (or cold start) and warm start. A reset initiated by software or originating from (the physical or another layer) at one agent can be communicated in-band to the other agent. However, due to the use of an embedded clock, an in-band reset can also be performed by communicating with another agent using an ordered set, such as a special electrical ordered set or EIOS. The ordered set can be sent during initialization, and a PHY control sequence (or "block link state") can be sent after initialization. The block link state can prevent the link layer from sending flits. As another example, link layer traffic can be blocked to send some null flits, which can be discarded at the receiver. As introduced above, initialization in one embodiment can initially occur at a slow speed, followed by a high-speed initialization. The slow-speed initialization uses the default values ​​for the registers and timers. Software then uses the slow-speed link to set up the registers, timers, and electrical parameters, and clears the calibration semaphores to prepare for a high-speed initialization. As an example, the initialization could consist of states or tasks such as reset, detect, query, and configure, among other potentially different states. In one example, a link-layer blocking control sequence (i.e., a blocking link state (BLS) or L0c state) can include a timed state during which link-layer flits are paused while PHY information is communicated to the remote agent. Here, the sender and receiver can initiate a blocking control sequence timer. Upon expiration of the timer, the sender and receiver can exit the blocking state and perform other actions, such as exiting to reset, exiting to a different link state (or any other state), including states that allow sending flits over the link. In one embodiment, link training can be provided and include the transmission of one or more encrypted training sequences, ordered sets, and control sequences, as well as those associated with a defined supersequence. A training sequence symbol can include one or more headers, reserved portions, a target latency, a pair number, physical path mapping code reference paths, or a group of paths and an initialization state. In one embodiment, the header can be sent with an ACK or NAK, among other examples. As an example, training sequences can be sent as part of supersequences and can be encrypted. In one embodiment, ordered sets and control sequences are neither encrypted nor staggered and are transmitted simultaneously and completely on all lanes in an identical manner. Valid reception of an ordered set may include verification of at least a portion of the ordered set (or the entire ordered set for partial ordered sets). Ordered sets may include an EOS such as an electrically inactive ordered set (EIOS) or an EIEOS. A supersequence may include a data sequence start (SDS) or a fast training sequence (FTS). These sets and control supersequences may be predefined and may have any pattern or hexadecimal representation and any length. For example, ordered sets and supersequences may be 8 bytes, 16 bytes, or 32 bytes long, etc.For example, FTS can also be used for fast bit locking during exit from a partial-width transmit link state. It should be noted that the FTS definition can be per lane and can use a rotated version of the FTS. In one implementation, supersequences can include the introduction of an EOS, such as an EIEOS, into a training sequence stream. When signaling starts, pathways can be switched on in a staggered manner. However, this can result in initial supersequences being truncated on some pathways at the receiver. Supersequences can, however, be repeated over short intervals (e.g., approximately one thousand unit intervals (or ~1 KUI)). The training supersequences can additionally be used for one or more functions, including deskew, configuration, and communicating an initialization target, pathway assignment, etc. The EIEOS can be used for one or more functions, including switching a pathway from the inactive to the active state, screening for good pathways, and determining symbol and TS boundaries. With reference to Fig. 8, illustrations of exemplary supersequences are shown. For example, an exemplary recognition supersequence 805 may be defined. The recognition supersequence 805 may include a repetition sequence of a single EIEOS (or another EOS) followed by a predefined number of instances of a special training sequence (TS). In one example, the EIEOS may be sent, immediately followed by seven repeated instances of TS. When the last of the seven TS is sent, the EIEOS may be sent again, followed by seven additional instances of TS, and so on. This sequence may be repeated according to a special predefined frequency. In the example of Fig. 8, the EIEOS may reappear on the pathways approximately once every thousand UIs (~1KUI), followed by the remainder of the recognition supersequence 805.A receiver can monitor lanes for the presence of a repeating detection supersequence 805 and, after validation of the supersequence 705, conclude that a remote agent is present, has been added to the lanes (e.g., connected in operation), has woken up, or has been reinitialized, etc. In another example, a different supersequence 810 can be defined to indicate a query, configuration, or loopback condition or state. As with the exemplary detection supersequence 805, pathways of a link through a receiver can be monitored for such a query / config / loop supersequence 810 to determine a query state, configuration state, or loopback state, or condition. In one example, a query / config / loop supersequence 810 can begin with an EIEOS followed by a predefined number of repeated instances of a TS. For example, in one example, the EIEOS might be followed by thirty-one (31) instances of a TS, with the EIEOS being repeated approximately every four thousand UI (e.g., ~4 KUI). Furthermore, in another example, a Partial Width Transmit State (PWTS) exit supersequence 815 can be defined. In one example, a PWTS exit supersequence can include an initial EIEOS to repeat the pre-preparation of lanes before transmitting the first full sequence in the supersequence. For example, the sequence to be repeated in supersequence 815 can begin with an EIEOS (to repeat approximately once every 1 KUI). Furthermore, Fast Training Sequences (FTS) can be used instead of other training sequences (TS), with the FTS configured to assist with faster bit locking, byte locking, and deskewing. In some implementations, an FTS can be decrypted to further assist in reactivating inactive lanes as quickly and unobtrusively as possible.As with other supersequences that precede entry into a link transmit state, supersequence 815 can be interrupted and terminated by sending an SDS. Furthermore, a partial FTS (FTSp) can be sent to assist in synchronizing the new lanes with the active lanes, for example by allowing bits to be subtracted from (or added to) the FTSp, among other examples. Supersequences such as the recognition supersequence 705 and the query / config / loop supersequence 710, etc., can potentially be sent primarily during the initialization or re-initialization of a link. In some cases, after receiving and recognizing a specific supersequence, a receiver can respond by echoing the same supersequence back to the sender via the pathways. The receiving and validation of a specific supersequence by both sender and receiver can serve as a handshake to confirm a state or condition communicated by the supersequence. For example, such a handshake (e.g., using a recognition supersequence 705) can be used to determine the re-initialization of a link.In another example, such a handshake can be used to indicate the end of an electrical reset or low-energy state, resulting in corresponding pathways being reactivated, among other examples. The end of the electrical reset can be determined, for instance, by a handshake between the sender and receiver, where each transmits a detection supersequence 705. In another example, paths can be monitored for supersequences, and these supersequences can be used, among other things, in conjunction with screening paths for detection, wake-up, state exits, and entries. The predefined and predictable nature and form of supersequences can be further used to perform initialization tasks such as bit locking, byte locking, debouncing, descrambling, deskewing, adjustment, latency fixing, negotiated delays, and other possible uses. In essence, paths can be continuously monitored for such events to enhance the system's ability to respond to and process these conditions. In the case of debouncing, transients can be introduced onto tracks due to a variety of conditions. For example, adding or turning on a device can introduce transients onto the track. Additionally, voltage irregularities on a track can occur due to poor track quality or an electrical fault. In some cases, track bouncing can produce false positive results, such as a false EIEOS. However, in some implementations, defined supersequences can include further additional sequences of data as well as a defined frequency with which the EIEOS is repeated, while supersequences can begin with an EIEOS. Even where a false EIEOS appears on a track, a logic analyzer at the receiver can determine that the EIEOS is a false positive by validating data that follows the false EIEOS.For example, if an expected Transient Signal (TS) or other data does not follow the EIEOS, or if the EIEOS does not repeat within a specific predefined frequency of one of the predefined supersequences, the receiver logic analyzer may fail to validate the received EIEOS. Since bounce can occur during initiation while a device is being added to a link, false negatives can also result. For example, after being added to a set of lanes, a device may begin transmitting a detection supersequence 705 to alert the other side of the link to its presence and begin initializing the link. However, transients introduced on the lanes can corrupt the initial EIEOS, the TS instances, and the other data in the supersequence.However, a logic analyzer at the receiving device can continue to monitor the paths and determine the next EIEOS sent by the new device in the repeating recognition supersequence 705, among other examples. In some implementations, an HPI link is capable of operating at multiple speeds, facilitated by the embedded clock. For example, a slow mode may be defined. In some cases, the slow mode can be used to assist in initializing the link. Link calibration can involve software-based controllers that provide logic to set various calibrated link properties. These properties include, among others, which pathways the link is to be used for, the pathway configuration, the link's operating speed, pathway and agent synchronization, deskew, and target latency. These software-based tools can utilize external control points to add data to physical layer registers to control various aspects of the physical layer facilities and logic. The operating speed of a link can be considerably higher than the effective operating speed of software-based controllers used during link initialization. A slow mode can be used to enable the use of such software-based controllers in other situations, such as during link initialization or reinitialization. Slow mode can also be applied to pathways connecting a receiver and transmitter, for example, when a link is powered on, initialized, reset, etc., to facilitate link calibration. In one embodiment, the clock can be embedded in the data, eliminating the need for separate clock lanes. Furthermore, the flits transmitted over the lanes can be encrypted to facilitate clock recovery. The receiver clock recovery unit can, for example, supply sampling clocks to a receiver (i.e., the receiver extracts the clock from the data and uses it to sample the incoming data). In some implementations, receivers continuously adapt to an incoming bitstream. Embedding the clock can potentially reduce pin usage. Embedding the clock in the in-band data can also change how an in-band reset is handled. In one embodiment, a block-link state (BLS) can be used after initialization. Additionally, electrical ordered-set supersequences can be used during initialization to facilitate the reset, among other considerations.The embedded clock can be shared between devices on a link, and the common operating clock can be defined during link calibration and configuration. For example, HPI links can reference a common clock using drift buffers. Such an implementation can achieve lower latency than elastic buffers used in non-shared reference clocks, among other potential advantages. Furthermore, the reference clock distribution segments can be adjusted within specified limits. As previously mentioned, an HPI link can operate at multiple speeds, including a "slow mode" for standard power-on, initialization, and so on. The operating speed (or "fast") or operating mode of each device can be statically set by the BIOS. The common clock on the link can be configured based on the respective operating speeds of each device on either side of the link. For example, the link speed can be based on the slower of the two device operating speeds, among other possibilities. Each change in operating speed can be accompanied by a warm or cold boot. In some examples, the link initializes into slow mode at a throughput rate of, for example, 100 MT / s upon power-up. Software then configures the two sides for the link's operating speed and begins initialization. In other cases, a sideband mechanism can be used to establish a link that incorporates the common clock on the link, for example, in the absence or unavailability of a slow mode. In one implementation, a slow-mode initialization phase may use the same encoding, encryption, training sequences (TS), states, etc., as the operating speed, but with potentially fewer features (e.g., no electrical parameter setup, no adjustments, etc.). Similarly, the slow-mode operating phase may potentially use the same encoding, encryption, etc. (although other implementations may not), but may have fewer states and features compared to the operating speed (e.g., no low-energy states). Furthermore, the slow mode can be implemented using the device's native phase-locked loop (PLL) clock frequency. For example, the HPI can support an emulated slow mode without changing the PLL clock frequency. While some designs may use separate PLLs for slow and fast speeds, in some HPI implementations, the emulated slow mode can be achieved by allowing the PLL clock to run at the same fast operating speed during slow mode. For example, a transmitter can emulate a slower clock signal by repeating bits multiple times to simulate a slow high clock signal and then a slow low clock signal. The receiver can then oversample the received signal to locate edges emulated by the repeating bits and determine the corresponding bit.In such implementations, ports that share a PLL can coexist at slow and fast speeds. A shared slow-mode speed can be initialized between two devices. For example, the two devices on a link might have different operating speeds. A shared slow-mode speed can be configured, for example, during a discovery phase or a discovery state on the link. In one example, an emulation multiple can be set as an integer (or non-integer) ratio of the fast speed to the slow speed, and the different fast speeds can be down-converted to operate at the same slow speed. For example, two device agents that support at least one common frequency can be hot-attached, regardless of the speed at which the host port is running.Software discovery can then use the slower mode link to determine and establish the optimal link operating speeds. Where the multiple is an integer ratio of the fast speed to the slow speed, different fast speeds can operate with the same slow speed, which can be used during the discovery phase (e.g., hot-attach). Some HPI implementations can support path matching at a link. The physical layer can support both receiver matching and transmitter matching. With receiver matching, the transmitter on a path sends sample data to the receiver, which the receiver logic can process to determine deficiencies in the path's electrical properties and signal quality. The receiver can then adjust path calibration settings to optimize the path based on the analysis of the received sample data. In the case of transmitter matching, the receiver can again receive sample data and develop a metric that describes the path quality, but in this case, the metric is linked to the transmitter (e.g.,Using a return channel (such as a software, hardware, embedded, sideband, or other channel), the receivers communicate to allow the sender to make adjustments to the path based on the feedback. Receiver adjustment can be initiated at the start of the query state using the query supersequence sent by the remote sender. Similarly, sender adjustment can be performed by repeating the following for each sender parameter. Both agents can enter the loopback pattern state as the master and send the specified pattern. Both receivers can measure the metric (e.g., BER) for that particular sender by setting a remote agent. Both agents can enter the loopback marker state and then reset, using return channels (slow mode TLS or sideband) to exchange metrics. Based on these metrics, the next sender setting can be determined.Ultimately, the optimal transmitter setting can be determined and saved for subsequent use. Since both devices on a link can operate at the same reference clock (e.g., ref clk), elasticity buffers can be omitted (any elastic buffers can be bypassed or used as drift buffers with the lowest possible latency). However, phase-matching or drift buffers can be used on each lane to transfer the appropriate receiver bitstream from the remote clock domain to the local clock domain. The latency of the drift buffers can be sufficient to handle the sum of drift from all sources in the electrical specification (e.g., voltage, temperature, residual SSC introduced by reference clock routing mismatches, and so on), but it can be kept as small as possible to reduce transport delay. If the drift buffer is too shallow, drift errors can result and manifest as a series of CRC errors.Therefore, some implementations can provide a drift alarm that can initiate a reset of the physical layer before an actual drift error occurs, among other examples. Some HPI implementations can support two sides running at the same nominal reference clock frequency but with a ppm difference. In this case, frequency matching (or elasticity) buffers may be required and may need to be re-adjusted during an extended BSL window or during specific sequences that would occur periodically, among other examples. The operation of the logical HPI-PHY layer can be independent of the underlying transmission media, provided that the latency does not result in latency fixing errors or timeouts at the link layer, among other considerations. External interfaces can be provided in the HPI to assist in managing the physical layer. For example, external signals (from pins, fuses, other layers), timers, control registers, and status registers can be provided. The input signals can change relative to the PHY state at any given time, but the physical layer must consider them at specific points in time when in a corresponding state. For example, a changing synchronization signal (as introduced below) can be received but have no effect after the link enters a transmit link state, among other examples. Similarly, instruction register values ​​can be considered by physical layer entities only at specific times. For example, the physical layer logic can take a snapshot of the value and use it in subsequent operations.Therefore, in some implementations, updates to instruction registers may be associated with a limited subset of special time periods (e.g., in a send-link state or when held in reset calibration, in send-link slow mode) to avoid abnormal behavior. Because status values ​​track hardware changes, the values ​​read can depend on when they are read. However, some status values, such as link mapping, latency, speed, etc., cannot change after initialization. For example, a re-initialization (or a low-energy link state (LPLS) or L1 state exit) is the only thing that can cause this to change (e.g., a severe orbital fault in a TLS cannot result in reconfiguration of the link until the re-initialization is triggered, among other examples). Interface signals can include signals that are external to the physical layer but affect its behavior. Examples of such interface signals include encoding and clock signals. Interface signals can be design-specific. These signals can represent an input or an output. Some interface signals, such as semaphores and those prefixed with EO, can be active once per assertion edge, meaning they can be deasserted and then reasserted to be effective again. For example, Table 1 includes an exemplary list of such functions: TABLE 1 TABLE 1 Input PIN reset (also known as warm start) Input pin reset (also known as cold start) Input in-band reset pulse; causes semaphore to be set; semaphore is cleared when in-band reset occurs. Input enables low-energy states Input loopback parameter; applied to loopback pattern Entrance to enter PWLTS Entrance to exit PWLTS Entrance to enter LPLS Entrance to exit LPLS Input from inactive exit detection (also known as squelch break) Input enables the use of CPhyInitBegin Input of local or planetary alignment for the transmitter to exit initialization. Output when remote agent NAKs LPLS request Exit when agent enters LPLS Exit to the link layer to avoid forcing further flits attempts. Output to the link layer to force zero flits Output when transmitter is in Partial Width Link Transmitting State (PWLTS) Output when receiver is in PWLTS CSR timer default values ​​can be provided in pairs—one for slow mode and one for operating speed. In some cases, a value of 0 disables the timer (i.e., a timeout never occurs). Timers can include those shown in Table 2 below. Primary timers can be used to time expected actions in a state. Secondary timers are used to abort initializations that are not progressing or to perform progress state transitions in an ATE mode at precise times. In some cases, secondary timers can be much larger than the primary timers in a state. Exponential timer sets can be designated with the suffix exp, and the timer value is 2 raised to the power of the field value. For linear timers, the timer value is the field value. Each timer could use different levels of precision.Additionally, some timers in the Power Management section may be found in a set called a Timing Profile. These may be linked to a timing diagram of the same name. TABLE 2 TABLE 2. Table Tpriexp Set Reset residence to navigate to EIEOS Minimum receiver calibration time; for staggered transmitter from Minimum transmitter calibration time; for staggered one Tsecexp Set Timed receiver calibration Timed transmitter calibration Detect / debounce squelch exit DetectAtRx overhang for handshake Adapt+bit lock / byte lock / deskew Configuring link widths Waiting for planetarily aligned clean Flit boundary Re-byte lock / Deskew Tdebugexp Set For hot-plugging; non-zero value regarding debug hangs. TBL Sentry set BLS boarding delay - fine BLS boarding delay - roughly TBLS set BLS duration for the transmitter BLS duration for the recipient BLS clean Flit interval for the transmitter TBLS clean flit interval for the receiver Command and control registers can be provided. Control registers can be late-action and, in some cases, can be read or written by software. Late-action values ​​can take effect continuously during reset (e.g., passing through from the software-facing to the hardware-facing section). Control semaphores (prefixed CP) are RW1S and can be cleared by hardware. Control registers can be used to perform any of the elements described here. They can be mutable and accessible by hardware, software, firmware, or a combination thereof. Status registers can be provided to track hardware changes (written and used by hardware) and can be read-only (but debugging software may also be able to write to them). Such registers do not impair interoperability and can usually be augmented with many private status registers. Status semaphores (prefixed with SP) can be mandated, as they can be cleared by software to repeat the actions that set the status. "Standard" means that initial (on reset) values ​​can be provided as a subset of these initialization-related status bits. On an aborted initialization, this register can be copied to a memory structure. Toolbox registers can be provided. For example, testability toolbox registers in the physical layer can provide pattern generation, pattern verification, and loopback control mechanisms. Higher-level applications can use these registers, along with electrical parameters, to determine clearances. For instance, a test integrated into the coupling structure can use this toolbox to determine clearances. For transmitter tuning, these registers can be used in conjunction with the special registers described in previous sections, among other examples. In some implementations, the HPI supports Reliability, Availability, and Maintainability (RAS) capabilities using the physical layer. In one embodiment, the HPI supports hot-plugging and hot-removal with one or more layers, which may include software. Hot-removal can include shutting down the link, and an initialization start state / signal can be cleared for the agent being removed. A remote agent (i.e., the one not being removed, such as the host agent) can be set to a slow speed, and its initialization signal can also be cleared. An in-band reset (e.g., by BLS) can cause both agents to wait in a reset state, such as a Calibration Reset State (CRS); and the agent to be removed can be removed (or held in addressed pin reset, shut down), among other examples and features.In fact, some of the aforementioned events can be omitted and additional events can be added. Hot-add can include a default initialization speed of slow, and an initialization signal can be set on the agent being added. Software can set the speed to slow and clear the initialization signal on the remote agent. The link can emerge in slow mode, and software can determine an operating speed. In some cases, no PLL relock of a remote agent is performed at this point. Operating speed can be set on both agents, and an activation can be set for customization (if not previously done). The initialization start indicator can be cleared on both agents, and an in-band BSL reset can cause both agents to wait in CRS. Software can assert a warm start (e.g., an addressed or self-reset) from an agent (to be added), which can cause a PLL to relock.Software can also set the initialization start signal using any known logic and further set it at Remote (thus progressing it to the Receiver Detect State (RDS)). Software can disable a warm start of the agent being added (thus progressing it to RDS). The link can then initialize at operating speed to a Send Link State (TLS) (or to Loopback if the matching signal is set), among other examples. Indeed, some of the events mentioned above can be omitted, and additional events can be added. Data lane recovery after a failure can be supported. In one embodiment, a link in the HPI can be resilient against a critical fault on a single lane by self-configuring to less than the full width (e.g., less than half the full width), thus eliminating the faulty lane. For example, the configuration can be performed by the link state engine, and unused lanes can be deactivated in the configuration state. As a result, the Flit can be transmitted with a narrower width, among other possibilities. In some HPI implementations, trace reversal can be supported on certain links. For example, trace reversal can refer to traces 0 / 1 / 2... of a sender that are connected to traces n / n-1 / n-2... of a receiver (e.g., n can be 19 or 7, etc.). Trace reversal can be detected at the receiver as defined in a field of a TS header. The receiver can handle the trace reversal by starting in a query state using the physical trace n...0 for the logical trace 0..n. Therefore, references to a trace can point to a logical trace number. This allows board designers to more effectively design the physical or electrical layout, and the HPI can work with virtual trace assignments as described here. Furthermore, in one embodiment, the polarity can be inverted (i.e., when a differential sender + / - is connected to a receiver - / +).Polarity can also be detected by a receiver of one or more TS header fields and, in one embodiment, handled in the query state. With reference to Fig. 10, an embodiment of a block diagram for a computer system that includes a multi-core processor is shown. The processor 1000 includes any processor or processing device such as a microprocessor, an integrated processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system-on-a-chip (SoC), or any other device for executing code. In one embodiment, the processor 1000 includes at least two cores—cores 1001 and 1002—which may be asymmetric cores or symmetric cores (the illustrated embodiment). However, the processor 1000 can include any number of processing elements, which may be symmetric or asymmetric. In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element that can hold state for a processor, such as an execution state or architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit that potentially includes any number of other processing elements, such as cores or hardware threads. A core often refers to logic within an integrated circuit capable of maintaining independent architectural states, each with its own dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic on an integrated circuit capable of maintaining independent architectural states, where these independently maintained states share access to execution resources. It is evident that the distinction between the nomenclature of a hardware thread and a core overlaps when certain resources are shared and others are tightly allocated to a specific architectural state.Nevertheless, a core and a hardware thread are often regarded by an operating system as individual logical processors, whereby the operating system can schedule operations on each logical processor individually. The physical processor 1000, as illustrated in Fig. 10, includes two cores, core 1001 and 1002. Here, cores 1001 and 1002 are considered symmetric cores, i.e., cores with the same configurations, functional units, and / or logic. In another embodiment, core 1001 includes an out-of-order processor core, while core 1002 includes an in-order processor core. Cores 1001 and 1002 can be individually selected by any type of core, such as a native core, a software-managed core, a core adapted to run a native instruction set architecture (ISA), a core adapted to run a translated instruction set architecture (ISA), a co-designed core, or any other known core. In a heterogeneous core environment (i.e.,(e.g., asymmetric cores) a form of translation, such as binary translation, can be used to schedule or execute code on one or both cores. To further the discussion, the functional units illustrated in core 1001 are described in more detail below, since the units in core 1002 operate similarly in the embodiment shown. As shown, core 1001 includes two hardware threads, 1001a and 1001b, which can also be referred to as hardware thread slots 1001a and 1001b. Therefore, software entities, such as an operating system, potentially view processor 1000 in one embodiment as four separate processors—that is, four logical processors or processing elements capable of executing four software threads concurrently. As noted above, a first thread is associated with architecture state registers 1001a, a second thread is associated with architecture state registers 1001b, a third thread is associated with architecture state registers 1002a, and a fourth thread is associated with architecture state registers 1002b. Here, each of the architecture state registers (1001a, 1001b, 1002a and 1002b) can be referred to as processing elements, thread slots or thread units as described above.As illustrated, the architecture state registers 1001a are repeated in the architecture state registers 1001b, allowing individual architecture states / contexts to be stored for logical processor 1001a and logical processor 1001b. In core 1001, other smaller resources, such as instruction pointers and rename logic in the assign and rename block 1030, can also be repeated for threads 1001a and 1001b. Some resources, such as reorder buffers in reorder / reorder unit 1035, ILTB 1020, load / store buffers, and queues, can be shared through partitioning. Other resources, such as... B. Internal universal registers, page table base registers, subordinate data cache and data TLB 1015, execution unit(s) 1040 and parts of out-of-order unit 1035 are potentially fully shared. The 1000 processor often includes additional resources that can be fully shared, shared through partitioning, or tightly allocated to processing elements. Figure 10 illustrates an embodiment of a purely exemplary processor with illustrative logical units / resources. It should be noted that a processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. As illustrated, core 1001 includes a simplified, representative out-of-order (OOO) processor core. However, different embodiments may employ an in-order processor.The OOO kernel includes a branch target buffer 1020 to predict branches to be executed / taken, and an instruction translation buffer (I-TLB) 1020 to store address translation entries for instructions. The 1001 core further includes the 1025 decoding module, which is coupled to the 1020 retrieval unit to decode retrieved elements. In one embodiment, the retrieval logic includes individual sequencers connected to the thread slots 1001a and 1001b, respectively. Typically, the 1001 core is connected to a first ISA (Instruction Set Information) that specifies / defines instructions executable by the 1000 processor. Often, machine instructions that are part of the first ISA include a portion of the instruction (referred to as an instruction code) that references / specifies an instruction or operation to be performed. The 1025 decoding logic includes circuitry that recognizes these instructions from their instruction codes and passes the decoded instructions into the pipeline for processing, as defined by the first ISA.For example, as described in more detail below, in one embodiment, the Decoder 1025 can include logic designed or adapted to recognize special instructions, such as a transaction instruction. As a result of recognition by the Decoder 1025, the Architecture or Core 1001 performs special, predefined actions to execute tasks associated with the corresponding instruction. Crucially, some of the tasks, blocks, operations, and procedures described here can be executed in response to one or more instructions, some of which may be new or existing. It should be noted that in one embodiment, the Decoder 1026 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, the Decoder 1026 recognizes a second ISA (either a subset of the first ISA or a different ISA). In one example, the assigner and renamer block 1030 includes an assigner to reserve resources such as register files and to store instruction processing results. However, threads 1001a and 1001b are potentially capable of out-of-order execution, with the assigner and renamer block 1030 also reserving additional resources, such as reorder buffers, to track instruction results. Unit 1030 can also include a register renamer to rename program / instruction reference registers to other registers within processor 1000. The reorder / reorder unit 1035 includes components such as the aforementioned reorder buffers, load buffers, and memory buffers to support out-of-order execution and subsequent in-order reordering of out-of-order instructions. In one embodiment, the scheduler and execution unit block 1040 includes a scheduler unit to schedule instructions / operations at execution units. For example, a floating-point instruction is scheduled on a port of an execution unit that has an available floating-point execution unit. Register files associated with the execution units are also included to store processing results of information instructions. Example execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a memory execution unit, and other known execution units. The subordinate data cache and data translation buffer (D-TLB) 1050 are coupled to the execution unit(s) 1040. The data cache is intended to store recently used / operated elements, such as data operands, which are potentially kept in memory coherence states. The D-TLB stores recent virtual / linear to physical address translations. As a specific example, a processor might include a page table structure to divide physical memory into a multitude of virtual pages. Here, cores 1001 and 1002 share access to higher-level or more distant caches, such as a second-level cache, connected to the on-chip interface 1010. It's important to note that "higher-level" or "more distant" refers to cache levels that increase in or are located further away from the execution unit(s). In one embodiment, the higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 1000—such as a second-level or third-level data cache. However, "higher-level cache" is not limited in this respect, as it can be connected to or include an instruction cache. A trace cache—a type of instruction cache—can instead be coupled behind decoder 1025 to store recently decoded traces. Here, an instruction potentially refers to a macro instruction (i.e., a macro instruction)., a non-privileged instruction that is recognized by the decoders), which can decode into a number of micro-instructions (micro-operations). In the configuration shown, the processor 1000 also includes the interface module on the chip 1010. Historically, a memory controller, described in more detail below, was included in a computer system located external to the processor 1000. In this scenario, the chip's internal interface 101 communicates with devices located outside of the processor 1000, such as the system memory 1075, a chipset (which often includes a memory controller hub to connect to memory 1075 and an I / O controller hub to connect peripherals), a memory controller hub, a northbridge, or another integrated circuit. And in this scenario, the bus 1005 can include any known coupling structure, such as a multipoint link bus, a point-to-point coupling structure, a serial coupling structure, a parallel bus, a coherent (e.g.,cache-coherent) bus, a layered protocol architecture, a differential bus and a GTL bus. Memory 1075 can be dedicated to Processor 1000 or shared with other devices in a system. Conventional examples of Memory 1075 types include DRAM, DRAM, permanent storage (NV memory), and other familiar storage devices. Note that Device 1080 can include a graphics accelerator, processor, or card coupled with a memory controller hub, data storage coupled with an I / O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or any other familiar device. While more logic and components can be integrated onto a single chip layer such as a SoC, each of these components can be included on the Processor 1000. For example, in one embodiment, a memory controller hub is located on the same package and / or chip layer as the Processor 1000. Here, part of the core (a part on the core) 1010 includes one or more controllers to connect to other devices such as memory 1075 or a graphics assembly 1080. The configuration that includes a coupling structure and controllers to connect to such devices is often referred to as an on-core (or non-core) configuration. As an example, the on-chip interface 1010 includes a ring coupling structure for on-chip communication and a high-speed serial point-to-point link 1005 for off-chip communication.Nevertheless, in the SOC environment, even more devices such as the network interface, coprocessors, 1075 memory, 1080 graphics processor, and any other known computer device / interface can be integrated onto a single chip layer or integrated circuit to provide a small form factor with high functionality and low power consumption. In one embodiment, the processor 1000 is capable of executing compiler, optimizer, and / or translator code 1077 to compile, translate, and / or optimize application code 1076 to support or connect with the devices and procedures described herein. A compiler often includes a program or set of programs to translate source text / code into target text / code. Typically, compiling program / application code with a compiler involves multiple stages and passes to convert high-level programming language code into low-level machine or assembly code. However, single-pass compilers can still be used for simple compilation. A compiler can employ any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code translation, and code optimization.Larger compilers often include multiple stages, but most commonly these stages are enclosed within two general phases: (1) a front end, which is generally where syntactic processing, semantic processing, and some conversion / optimization can occur, and (2) a back end, which is generally where analysis, conversions, optimizations, and code generation can occur. Some compilers refer to a middle ground, illustrating the blurring of the boundaries between a compiler's front end and back end. As a result, reference to introduction, connection, generation, or any other compiler operation can occur in any of the above-mentioned stages or passes, as well as any other known stages or passes of a compiler. As an illustrative example, a compiler potentially adds operations, calls, functions, etc.Dynamic compilation involves one or more phases of the compilation process, such as inserting calls / operations in a front-end phase and then converting those calls / operations into lower-level code during a conversion phase. It's important to note that during dynamic compilation, compiler code or dynamic optimization code can insert such operations / calls and optimize the code for runtime execution. As a specific illustrative example, binary code (already compiled code) can be dynamically optimized at runtime. Here, the program code can include the dynamic optimization code, the binary code, or a combination of both. Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and / or translate code. Therefore, references to code execution, application code, program code, or another software environment can refer to: (1) the execution of a compiler program or...(1) Compiler programs, optimization code optimizers, or translators, either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) the execution of the main program code, including operations / calls such as application code that has been optimized / compiled; (3) the execution of other program code, such as libraries associated with the main program code, to maintain software structures, to perform other software-related operations, or to optimize code; or (4) a combination thereof. Referring to Fig. 11, a block diagram of an embodiment of a multi-core processor is shown. As shown in the embodiment of Fig. 11, the processor 1100 includes several domains. Specifically, a core domain 1130 includes a plurality of cores 1130A-1130N, and a graphics domain 1160 includes one or more graphics engines, comprising a media engine 1165 and a system agent domain 1110. In various embodiments, the system agent domain 1110 handles power control events and power management, allowing individual units in domains 1130 and 1160 (e.g., cores and / or graphics engines) to be controlled independently. This enables them to dynamically operate at an appropriate power mode / level (e.g., active, turbo, sleep, hibernation, deep sleep, or another extended state similar to a configuration and power management interface state) based on the activity (or inactivity) occurring in the given unit. Each of domains 1130 and 1160 can operate at different voltages and / or power levels, and furthermore, the individual units within each domain can potentially operate at independent frequencies and voltages.It should be noted that, although only three domains are shown, the scope of the present invention is not limited in this respect and additional domains may be present in other embodiments. As shown, each 1130 core further includes low-level caches in addition to various execution units and additional processing elements. Here, the different cores are coupled with each other and with a shared cache memory formed from a multitude of units or segments of a Last Level Cache (LLC) 1140A-1140N; these LLCs often include memory and cache controller functionality and are shared among the cores and potentially also among the graphics engine. As seen, a ring coupling structure 1150 couples the cores together and provides the connection between the core domain 1130, the graphics domain 1160, and the system agent circuits 1110 via a plurality of ring stops 1152A-1152N, each at a coupling between a core and an LLC segment. As shown in Fig. 11, the coupling structure 1150 is used to carry various pieces of information, including address information, data information, acknowledgment information, and snoop / invalid information. Although a ring coupling structure is illustrated, any known coupling structure or fabric can be used on the chip layer. As an illustrative example, some of the fabrics discussed above (e.g.,a different coupling structure on the chip layer, chip-internal system fabric (OSF), an advanced microcontroller bus architecture (AMBA) coupling structure, a multidimensional mesh fabric or another known coupling structure architecture) in a similar manner. As further described, the system agent domain 1110 includes the display engine 1112, which provides control of and an interface to a connected display. The system agent domain 1110 may include other units such as an integrated memory controller 1120, which provides an interface to system memory (e.g., a DRAM implemented with multiple DIMMs); ​​and coherence logic 1122 to perform memory coherence operations. Multiple interfaces may be present to enable communication between the processor and the other circuitry. In one embodiment, at least one Direct Media Interface (DMI) 1116 interface and one or more PCIe™ interfaces 1114 are provided. The display engine and these interfaces typically couple to memory via a PCIe™ bridge 1118.To provide communication between other agents such as additional processors or other circuits, one or more other interfaces can be provided. Referring to Fig. 12, a block diagram of a representative kernel is shown; specifically, logic blocks of a back end of a kernel such as kernel 1130 from Fig. 11. In general, the structure shown in Fig. 12 includes an out-of-order processor, which has a front-end unit 1270 used to fetch incoming instructions, perform various processing operations (e.g., buffering, decoding, branch prediction, etc.), and pass instructions / operations to an out-of-order (OOO) engine 1280. The OOO engine 1280 performs further processing on decoded instructions. Specifically, in the embodiment shown in Fig. 12, the out-of-order engine 1280 includes an allocation unit 1282 to receive decoded instructions, which may be in the form of one or more micro-instructions or µOps from the front-end unit 1270, and to allocate them to the appropriate resources, such as registers. The instructions are then provided to a reservation station 1284, which reserves resources and schedules them for execution by a variety of execution units 1286A-1286N. Various types of execution units may be present, including, for example, arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), and floating-point execution units. Results from these different execution units are provided to a reorder buffer (ROB) 1288, which takes any out-of-order results and reassembles them into the correct program order. With further reference to Fig. 12, it should be noted that both the front-end unit 1270 and the out-of-order engine 1280 are coupled to different levels of a memory hierarchy. Specifically, an instruction-level cache 1272 is shown, which in turn is coupled to a middle cache 1276, which is in turn coupled to a last-level cache 1295. In one embodiment, the last-level cache 1295 is implemented in an on-chip (sometimes referred to as a non-core) unit 1290. As an example, unit 1290 is similar to the system agent 810 of Fig. 8. As described above, the non-core 1290 communicates with the system memory 1299, which in the illustrated embodiment is implemented via ED RAM. It should also be noted that the various execution units 1286 within the out-of-order engine 1280 are in communication with a level 1 cache 1274, which is also in communication with the mid-level cache 1276.It should also be noted that the additional cores 1230N-2 - 1230N can couple with LLC 1295. Although shown at this high level in the embodiment of Fig. 12, it is obvious that various modifications and additional components may be present. With reference to Fig. 13, a block diagram of an exemplary computer system is illustrated, comprising a processor that includes execution units for executing an instruction, wherein one or more of the coupling structures implement one or more features according to an embodiment of the present invention. System 1300 includes a component, such as a processor 1302, to employ execution units that include logic for executing algorithms on process data according to the present invention as described herein. System 1300 is representative of processing systems based on the PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™, and / or StrongARM™ microprocessors, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used.In one embodiment, the example system 1300 runs a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (for example, UNIX and Linux), embedded software, and / or graphical user interfaces can also be used. Thus, the embodiments of the present invention are not limited to a specific combination of hardware circuits and software. Embodiments are not limited to computer systems. Alternative embodiments of the present invention can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment. In this illustrated embodiment, the processor 1302 comprises one or more execution units 1308 for implementing an algorithm that executes at least one instruction. An embodiment may be described in the context of a desktop or server system with a single processor, but alternative embodiments in a multiprocessor system may also be included. The system 1300 is an example of a "hub" system architecture. The computer system 1300 includes a processor 1302 for processing data signals. As an illustrative example, the processor 1302 includes a complex instruction set (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor with a combination of instruction sets, or another processing unit, such as a digital signal processor.The 1302 processor is coupled to a 1310 processor bus, which transmits data signals between the 1302 processor and other components in the 1300 system. The elements of the 1300 system (e.g., 1312 graphics accelerator, 1316 memory controller hub (MCH), 1320 memory, 1324 I / O controller hub (ICH), 1326 wireless transceiver, 1328 flash BIOS, 1334 network controller, 1336 audio controller, 1338 serial expansion port, 1340 I / O controller, etc.) perform their conventional functions, which are well known to a professional. In one embodiment, the processor 1302 includes an internal Level 1 (L1) cache memory 1304. Depending on the architecture, the processor 1302 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches, depending on the specific implementation and requirements. The register file 1306 stores various data types in different registers, including integer registers, floating-point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers. The execution unit 1308, containing the logic for executing integer and floating-point operations, is also located in the processor 1302. In one embodiment, the processor 1302 includes a microcode read-only memory (ucode) for storing microcode that, when executed, runs algorithms for specific macro instructions or handles complex scenarios. Here, the microcode may be updatable to handle logical errors / clean-ups for the processor 1302. In another embodiment, the execution unit 1308 includes logic for processing a packed instruction set 1309. By including the packed instruction set 1309 within the instruction set of a general-purpose processor 1302, along with the associated circuitry for executing the instructions, the operations used by many multimedia applications can be performed using the packed data in a general-purpose processor 1302.This allows many multimedia applications to run faster and more efficiently by utilizing the full bus width of a processor to perform operations on packed data. This potentially eliminates the need to transfer smaller data units across the processor data bus to perform one or more operations, each involving a single data element at a time. Alternative embodiments of an execution unit 1308 can also be used in microcontrollers, embedded processors, graphics processing units, DSPs, and other types of logic circuits. The system 1300 includes a memory 1320. The memory 1320 includes dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or another memory element. The memory 1320 stores instructions and / or data represented by data signals to be executed by processor 1302. It should be noted that any of the above-mentioned features or aspects of the invention can be used with one or more coupling structures illustrated in Fig. 13. For example, a coupling structure not shown on the chip layer (QDI) to couple internal units of the processor 1302 implements one or more aspects of the invention described above. Or the invention is connected to a processor bus 1310 (e.g., another known high-performance computing coupling structure), a high-bandwidth memory path 1318 to memory 1320, a point-to-point link to graphics accelerator 1312 (e.g., a Peripheral Component Interconnect Express (PCIe) compliant fabric), a controller hub coupling structure 1322, an I / O, or another coupling structure (e.g., USB, PCI, PCIe) to couple the other illustrated components.Some examples of such components include the audio controller 1336, firmware hub (flash BIOS) 1328, wireless transceiver 1326, data storage 1324, legacy I / O controller 1310 with interfaces for user input and keyboard 1342, a serial expansion port 1338 such as a Universal Serial Bus (USB), and a network controller 1334. The data storage device 1324 can include a hard disk drive, a floppy disk drive, a CD-ROM drive, a flash memory device, or a mass storage device. Referring to Fig. 14, a block diagram of a second system 1400 according to an embodiment of the present invention is shown. As shown in Fig. 14, the multiprocessor system 1400 is a system with a point-to-point coupling structure and comprises a first processor 1470 and a second processor 1480, which are coupled via a point-to-point coupling structure 1450. Each of the processors 1470 and 1480 can be a version of a processor. In one embodiment, 1452 and 1454 are part of a serial, coherent point-to-point coupling structure fabric, such as a high-performance architecture. As a result, the invention can be implemented within the QPI architecture. Although only two processors, 1470 and 1480, are shown, it is understood that the scope of the present invention is not limited in this way. In other embodiments, one or more additional processors may be present in a given processor. Processors 1470 and 1480 are each shown with integrated memory controller units 1472 and 1482, respectively. Processor 1470 also includes point-to-point (PP) interfaces 1476 and 1478 as part of its bus controller units; similarly, processor 1480 includes PP interfaces 1486 and 1488. Processors 1470 and 1480 can exchange information via a PP interface 1450 using PP interface circuits 1478 and 1488. As shown in Fig. 14, the IMCs 1472 and 1482 couple the processors to their respective memories, namely a memory 1432 and a memory 1434, which may be part of a main memory locally connected to the respective processors. The 1470 and 1480 processors each exchange data with a 1490 chipset via the individual PP interfaces 1452 and 1454 using the PP interface circuits 1476, 1494, 1486, and 1498. The 1490 chipset also exchanges information with a high-performance graphics circuit 1438 via an interface circuit 1492 along a high-performance graphics coupling structure 1439. A shared cache (not shown) can be enclosed within each processor or outside of both processors, but is connected to the processors via a PP coupling structure such that one (or both) of the local cache information of the processors can be stored in the shared cache when a processor is put into a power-saving mode. The chipset 1490 can be coupled to a first bus 1416 via the interface 1496. In one embodiment, the first bus 1416 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another 3rd generation I / O coupling structure bus, although the scope of the present invention is not limited in this way. As shown in Fig. 14, various I / O devices 1414 are coupled to the first bus 1416 together with a bus bridge 1418, which couples the first bus 1416 to a second bus 1420. In one embodiment, the second bus 1420 includes a Low Pin Count (LPC) bus. Various devices are coupled to the second bus 1420, including, for example, a keyboard and / or mouse 1422, communication devices 1427, and a storage unit 1428 such as a disk drive or other mass storage device, which in one embodiment often includes commands / code and data 1430. Furthermore, an audio I / O 1424 is shown coupled to the second bus 1420. It should be noted that other architectures are possible in which the included components and coupling structure architectures vary. For example, instead of the point-to-point architecture of Fig. 14, a system can implement a multidrop bus or another such architecture. With reference to Fig. 15, an embodiment of a system-on-chip (SOC) design according to the inventions is shown. As a specific illustrative example, SOC 1500 is enclosed in the subscriber terminal equipment (STE). In one embodiment, STE refers to any device used by an end-user for communication, such as a handheld telephone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Frequently, a STE connects to a base station or node, which by its very nature may correspond to a mobile station (MS) in a GSM network. Here, SOC 1500 includes two cores – 1506 and 1507. Similar to the description above, cores 1506 and 1507 can correspond to an instruction set architecture such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, or an ARM-based processor design, or to a customer thereof, as well as their licensees or users. Cores 1506 and 1507 are coupled to the cache controller 1508, which is connected to the bus interface unit 1509 and the L2 cache 1511 to communicate with other parts of the System 1500. The coupling structure 1510 includes an on-chip coupling structure such as an IOSF, AMBA, or another coupling structure discussed above, which may implement one or more of the aspects described here. The coupling structure 1510 provides communication channels to other components such as a Subscriber Identity Module (SIM) 1530 as an interface to a SIM card, a boot ROM 1535 for storing boot code for execution by the cores 1506 and 1507 for initializing and booting the SOC 1500, an SDRAM controller 1540 as an interface to external memory (e.g., DRAM 1560), a flash controller 1545 as an interface to non-volatile memory (e.g., Flash 1565), a peripheral controller 1550 (e.g., serial peripheral interface) as an interface to peripheral devices, video codecs 1520 and a video interface 1525 for displaying and receiving input (e.g., touch-enabled input), a GPU 1515 for performing graphics-related calculations, etc. Each of these interfaces can incorporate aspects of the invention described herein. Furthermore, the system illustrates communication peripherals such as a Bluetooth module (1570), 3G modem (1575), GPS (1585), and Wi-Fi (1585). As mentioned above, a UE includes radio communication capabilities. Consequently, not all of these peripheral communication modules are required. However, some form of radio communication for external communication must be present in a UE. Although the present invention has been described with regard to a limited number of embodiments, those skilled in the art are aware that many further modifications and variants thereof are possible. The appended claims are intended to cover all such modifications and variants that correspond to the purpose and scope of the present invention. A design can go through several stages, from creation to simulation to fabrication. Data representing a design can represent it in multiple ways. As is useful in simulations, the hardware can first be represented using a hardware description language or another functional description language. Additionally, a circuit-level model with logic and / or transistor gates can be created at some stage of the design process. Furthermore, most designs eventually reach a data layer that represents the physical arrangement of various devices within the hardware model. If conventional semiconductor fabrication techniques are used, the data representing the hardware model can be the data specifying the presence or absence of various features on different mask layers used to fabricate the integrated circuit.In a design representation, the data can be stored in the form of a machine-readable medium. A storage device or a magnetic or optical storage medium, such as a disc, can be the machine-readable medium for storing information transmitted by means of an optical or electrical wave that is modulated or otherwise generated to send such information. When an electrical carrier wave, indicating or carrying the code or design, is transmitted, a new copy is created by copying, buffering, or retransmitting the electrical signal. Thus, a communications service provider or network service provider can at least temporarily store an item, such as information encoded in a carrier wave, on a specific machine-readable medium, embodying the techniques of embodiments of the present invention. A module as used herein refers to any combination of hardware, software, and / or firmware. For example, a module includes hardware, such as a microcontroller, connected to a non-volatile medium to store code adapted for execution by the microcontroller. Therefore, in one embodiment, the use of a module refers to the hardware specifically configured to recognize and / or execute the code stored on a non-volatile medium. In another embodiment, the use of a module further refers to the non-volatile medium containing the code specifically adapted for execution by the microcontroller to perform predetermined operations.And as can be deduced, in yet another embodiment the term module (in this example) can refer to the combination of microcontroller and non-volatile medium. Module boundaries, illustrated as separate, conventionally vary and can potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic assemblies. The use of the phrase "is configured" in an embodiment refers to the arranging, assembling, manufacturing, offering for sale, importing, and / or constructing of a device, hardware, logic, or element to perform an intended or specific task. In this example, a device or element thereof that is not operating is still "configured" to perform an intended task if it is designed, coupled, and / or connected to perform that intended task. As a purely illustrative example, a logic gate can provide a 0 or 1 during operation. But a logic gate that is "configured" to provide a enable signal to a clock does not include every potential logic gate that can provide a 1 or 0. Instead, the logic gate is one that is coupled in such a way that, during operation, the 1 or 0 output enables the clock.Once again, it should be noted that the use of the term "is configured" does not require operation, but instead focuses on the latent state of a device, hardware and / or element, in which state the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operating. Furthermore, the use of the terms "to," "capable of," and / or "operational to" in an embodiment refers to a device, logic, hardware, and / or element that is designed in such a way as to enable the use of the device, logic, hardware, and / or element in a specified manner. As above, it should be noted that the use of "to," "capable of," and / or "operational to" in an embodiment refers to the latent state of a device, logic, hardware, and / or element where the device, logic, hardware, and / or element is not operational but is designed in such a way as to enable the use of a device in a specified manner. A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. The use of logic levels, logic values, or logical values ​​is also referred to as 1s and 0s, which simply represent binary logical states. For example, a 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or a flash cell, may be able to hold a single logical value or multiple logical values. However, other representations of values ​​have been used in computer systems. The decimal number ten, for example, can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, a value includes any representation of information that can be contained in a computer system. Furthermore, states can be represented by values ​​or parts of values. For example, a first value, such as a logical one, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. Additionally, in one embodiment, the terms reset and set refer accordingly to a default and an updated value or state. A default value, for instance, potentially includes a logical high value, i.e., reset, while an updated value potentially includes a logical low value, i.e., set. It should be noted that any combination of values ​​can be used to represent any number of states. The embodiments of the aforementioned methods, hardware, software, firmware, or code may be implemented by instructions or code stored on a machine-accessible, machine-readable, or computer-readable medium and capable of being executed by a processing element. A non-volatile machine-accessible / machine-readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine such as a computer or electronic device. Examples of non-volatile machine-accessible media include random-accessible memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; a magnetic or optical storage medium; flash memory devices; an electrical storage device, optical storage devices, acoustic storage devices; and any other form of storage device to store information transmitted by volatile (propagated) signals (e.g.,carrier waves, infrared signals, digital signals) etc. were received, which are to be distinguished from the non-volatile media that can receive information from them. Commands used to program logic to execute embodiments of the invention can be stored in a memory within the system, such as DRAM, cache, flash memory, or other storage medium. Furthermore, the commands can be disseminated over a network or using other machine-readable media. Thus, a machine-readable medium can represent any mechanism for storing or transmitting information in a (e.g.,The term "computer-readable medium" encompasses, but is not limited to, floppy disks, optical drives, CDs, read-only memory (CD-ROMs), magneto-optical disks, read-only memory (ROM), random-access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any non-volatile, machine-readable memory used in the transmission of information over the internet using electrical, optical, acoustic, or other forms of propagating signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, "computer-readable medium" includes any type of non-volatile, machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer). The following examples relate to embodiments according to this specification. One or more embodiments can provide a device, a system, a machine-readable memory, a machine-readable medium, and a method for initializing a link, wherein the link includes a number of lanes and a sender and a receiver are coupled to each lane in the number of lanes, and the re-initialization of the link includes the transmission of a predefined sequence on each of the lanes, wherein the re-initialization is provided without completing the link. In at least one example, the predefined sequence is sent from the sender to the receiver, and the receiver repeats the predefined sequence to the sender. In at least one example, the sequence includes an electrically inactive exit-ordered set (EIEOS). In at least one example, the sequence further includes a multitude of instances of a training sequence. In at least one example, the EIEOS to be repeated is the sequence according to a minimum frequency. In at least one example, the sequence must be repeated until the link is initialized. One or more examples can further provide the confirmation of received instances of the predefined sequence to detect an agent on the link. In at least one example, the link includes a differential serial data link. In at least one example, the sequence is sent during a reset state to signal the exit from the reset state. One or more embodiments can provide a device, a system, a machine-readable memory, a machine-readable medium and a method for sending a predefined sequence to another entity connected to the data link via pathways of a differential serial data link, receiving an acknowledgment of the predefined sequence from the other entity, and using the predefined sequence to facilitate initialization of the data link. In at least one example, the Flit can be sent from a first device to a second device via the data link. The first and second devices can include microprocessors, graphics accelerators, and other devices. The following examples relate to embodiments according to this specification. One or more embodiments may provide a device, a system, a machine-readable memory, a machine-readable medium, and a method for recognizing a predefined sequence on each of the lanes of a link spanning a number of lanes and determining the state of another agent based on the recognition of the predefined sequence. One or more examples can further provide the response of the predefined sequence by means of an echo to the other agent. In at least one example, the sequence includes an EIEOS, and the recognition of the predefined sequence includes the validation of the sequence. In at least one example, validating the sequence is based at least partially on determining that the EIEOS is repeated according to a predefined frequency. In at least one example, the sequence is repeated continuously during a specific link initialization state. In at least one example, the sequence indicates an initialization state. In at least one example, the initialization state is included in a re-initialization of the link. In at least one example, the sequence is detected during a reset state and indicates an exit from the reset state. One or more embodiments can provide a device, a system, a machine-readable memory, a machine-readable medium and a method for monitoring loop formation during the initialization of a link and for causing the initialization of the link to suspend it in response to the detection of an unsuccessful loop formation during initialization. One or more examples can further provide the management of a loop count in a state machine during initialization. In at least one example, the count must be managed for each agent that is communicatively connected using the link. In at least one example, the counter is reset upon successful link initialization. In at least one example, successful link initialization involves entering a link sending state. In at least one example, a loop includes re-entering a reset state of a link-training state machine. In at least one example, the initialization of the link is suspended in a reset state of a link training state machine. In at least one example, a suspended initialization of the link is restarted in response to a command from a controller. In at least one example, the link has a link width of 20 lanes. One or more embodiments may provide a device, a system, a machine-readable memory, a machine-readable medium, and a method for determining whether one or more initialization tasks are to be executed in conjunction with a specific initialization state; and the application of a short-time timer to transition from the specific state based on determining whether the initialization tasks are to be executed. One or more examples may further provide the application of a second short timer to change from a second initialization state, and the second short timer has a duration that differs from the first short time. In at least one example, the short-time timer is applied based on a decision not to execute the initialization tasks. In at least one example, a long-term transmitter is used for the specific initialization state based on a determination to execute the initialization tasks. In at least one example, the determination is based on an indication that the short-time timer is activated. In at least one example, the short-time timer is activated by a software-based controller. In at least one example, the short-time timer is activated based on a determination that a configuration associated with the initialization task is complete. In at least one example, the link includes a differential serial data link. One or more embodiments can provide a device, a system, a machine-readable memory, a machine-readable medium and a method for sending flits at a first speed in a first mode and sending flits at a second speed in a second mode, wherein a phase-locked loop (PLL) speed is the same in the first mode and in the second mode. In at least one example, the first speed includes an operating speed and the second speed includes a slow speed. In at least one example, the slow speed is emulated by the operating speed. In at least one example, emulating the slow speed involves sending a series of bits at operating speed to simulate one bit in slow mode. In at least one example, the physical layer logic continues from the first speed to the second speed. In at least one example, the bypass is based on a request from a controller that is at least partially software-based. One or more embodiments may provide a device, a system, a machine-readable memory, a machine-readable medium and a method for determining an operating speed of a first device to be connected to a second device on a link; determining an operating speed of the second device; and determining a common slow speed to be applied by the first and second devices during the transmission of data on the link. In at least one example, the common slow speed is determined during link initialization. In at least one example, the operating speed of the first device differs from the operating speed of the second device, and the initialization of the link further includes determining a common operating speed. In at least one example, the combined operating speed is based on the slower of the operating speeds of the first and second devices. In at least one example, determining the common slow mode involves determining a first ratio to be applied to the operating speed of the first device in order to realize the common slow speed, and determining a second ratio to be applied to the operating speed of the second device in order to realize the common slow speed. In at least one example, the common slow speed is emulated by the operating speeds. In at least one example, emulating the slow speed involves sending a series of bits at a corresponding operating speed to simulate one bit in common slow mode. One or more examples may further include a physical layer (PHY) configured to be coupled to a link, wherein the link includes an initial number of orbits, and wherein the PHY includes a synchronization (sync) counter, and wherein the PHY transmits an electrically inactive exit order set (EIEOS) aligned with the synchronization counter and associated with a training sequence. In at least one example, a synchronization counter value is not exchanged by the synchronization counter during each training sequence. One or more examples may further include a physical layer (PHY) configured to be coupled to a link, wherein the link includes an initial number of orbits, and wherein the PHY includes a synchronization (sync) counter, and wherein the PHY transmits an electrically inactive exit order set (EIEOS) aligned with the synchronization counter and associated with a training sequence. In at least one example, a synchronization counter value is not exchanged by the synchronization counter during each training sequence. In at least one example, the EIEOS alignment with the synchronization counter acts as a proxy for exchanging the synchronization counter value from the synchronization counter during each training sequence. One or more examples can further provide a physical layer (PHY) configured to be coupled to a link, wherein the PHY includes a software-modifiable register including a control field, and a PHY state machine to switch between a plurality of states, wherein the PHY state machine maintains the transition between a first state and a second state based on a first value of the register's control field. In at least one example, the PHY state machine switches between the first state and the second state in response to software that updates the register's control field to a second value. One or more examples can further provide a physical layer (PHY) configured to be coupled to a link, wherein the PHY includes a PHY state machine for transitioning between a plurality of states, and wherein the PHY state machine is capable of transitioning from a first state to a second state based on a handshake event and of transitioning the PHY from a third state to a fourth state based on a primary timer event. In at least one example, the PHY state machine is capable of transitioning the PHY from a fifth state to a sixth state based on a primary time event in combination with a secondary timer event. One or more examples can further provide a physical layer (PHY) configured to be coupled to a link, the link including a first number of orbits, and the PHY transmitting flits at a first speed and flits at a second speed, and where a phase-locked loop (PLL) speed is the same in fast mode and slow mode. In at least one example, the first speed is a slow speed and the second speed is a fast speed. In at least one example, the PHY transmits flits at the slow speed, which involves the PHY continuously transmitting a bit of the flits several times at the fast speed to emulate the bit at the slow speed without changing the PLL speed. One or more examples can further provide a physical layer (PHY) configured to be coupled to a link, the link including an initial number of orbits, and the PHY transmits flits at a slow speed in a slow mode and flits at a fast speed in a fast mode, the fast speed being more than 2x the slow speed, and the PLL speed being the same in both fast and slow modes. References in this description to “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, uses of the phrase “in an embodiment” at various points in this entire description do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The foregoing description provides a detailed account with reference to specific exemplary embodiments. However, it is obvious that various modifications and changes can be made to it without deviating from the broader meaning and scope of the invention as set forth in the appended claims. The description and drawings should therefore be viewed in an illustrative rather than a limiting sense. Furthermore, the foregoing use of "embodiment" and other exemplary language does not necessarily refer to the same embodiment or example, but may refer to different and distinct embodiments, as well as potentially to the same embodiment.

Claims

Processor device comprising: physical layer logic that can be executed to initialize a link, wherein initializing the link includes signaling a variety of link training states, including a reset state, a detection state, a query state, and a configuration state, wherein the physical layer logic is to send a detection supersequence to another device in association with the detection state, wherein the detection supersequence includes a pattern, and the pattern includes an electrical inactive ordered exit set (EIEOS) and a set of six instances of a training sequence for displaying the detection state, wherein the training sequence includes a defined data sequence to be used in the detection state, and each of the six instances of a training sequence includes a respective head. Processor device according to claim 1, wherein the head of each of the six instances of the training sequence comprises a type field to indicate that the training sequence corresponds to the recognition state. Processor device according to claim 1, wherein the pattern is to be repeated according to a specific frequency. Processor device according to claim 3, wherein the pattern is to be repeated approximately once in one thousand unit intervals (UIL). Processor device according to claim 1, wherein an instance of the recognition supersequence is to be sent to each of a plurality of pathways of the connection. Processor device according to claim 5, wherein the plurality of tracks comprises eight tracks or 20 tracks. Processor device according to claim 1, further comprising a receiver, wherein the receiver is to receive an instance of the recognition supersequence from the other device in conjunction with the recognition state. Processor device according to claim 7, wherein the bit layer logic is further said to evaluate the instance of the recognition supersequence in order to recognize an agent of the other device. Processor device according to claim 1, wherein the detection state comprises a transmitter detection state. Processor device according to claim 8, wherein the bit transmission layer logic is further said to leave the recognition state and enter a query state. Processor device according to claim 8, wherein the bit transmission layer logic is to enter the transmitter detection state. Processor device according to claim 10, wherein the bit transmission layer logic is to enter the transmitter detection state from a low energy state or a transmitter calibration state. Device comprising: a controller connected to a first processor, wherein the controller serves as an interface between the first processor for recognizing a first instruction set and a processor for recognizing a second instruction set that differs from the first instruction set, wherein the controller comprises protocol layer logic, data link layer logic, and physical layer logic, wherein the physical layer supports signaling to initialize a link, wherein the signaling comprises a recognition supersequence to be sent in a recognition state, wherein the recognition state is one of several link training states defined in a state machine, and wherein the recognition supersequence comprises a pattern to be repeated according to a specified frequency.and the pattern comprises an ordered set (OS) and a series of training sequences for displaying the recognition state, each of the training sequences containing a respective defined data sequence to be used in the recognition state, and each of the training sequences in the series comprising a respective header indicating the recognition state. Device according to claim 13, further comprising the first processor. Device according to claim 13, wherein the OS comprises an electrically inactive ordered output set (EIEOS). Device according to claim 15, wherein: the EIEOS comprises an ordered 16-byte set, bytes 0, 2, 4, 6, 8, 10, 12 and 14 of the EIEOS comprise a value of 8'h00, and bytes 1, 3, 5, 7, 9, 11, 13 and 15 of the EIEOS comprise a value of 8'hFF. Method comprising: Entering a recognition state in conjunction with initializing a link between a first device and a second device, wherein the recognition state is one of a plurality of link training states, further comprising a reset state, a query state, and a configuration state; transmitting a recognition supersequence to the second device, wherein the recognition supersequence comprises a pattern to be repeated according to a specified frequency, the pattern comprises an electrically inactive ordered exit set (EIEOS) followed by six instances of a training sequence to indicate the recognition state, and the training sequence contains a defined data sequence to be used in the recognition state; receiving an instance of the recognition supersequence at the first device from the second device;and exiting the recognition state into another of the multitude of states by receiving the instance of the recognition supersequence.; System comprising: a device; a processor node comprising a controller, wherein the controller comprises protocol layer logic, data link layer logic and physical layer logic, wherein the physical layer logic is configured to: enter a detection state in conjunction with initializing a link between the device and the processor node, wherein the detection state is one of a plurality of link training states, further comprising a reset state, a query state and a configuration state;Sending a recognition supersequence to the device, wherein the recognition supersequence comprises a pattern to be repeated according to a specified frequency, the pattern comprises an electrically inactive ordered exit set (EIEOS) followed by six successive instances of a training sequence to indicate the recognition state, and the training sequence contains a defined data sequence to be used in the recognition state; receiving an instance of the recognition supersequence from the device; and exiting the recognition state into another of the plurality of states based on the instance of the recognition supersequence. System according to claim 18, wherein the detection state is assumed by a low-energy state or a calibration state. System according to claim 18, wherein the other state comprises the query state. System according to claim 18, wherein the processor node comprises a first processor node and the device comprises a second processor node. System according to claim 18, wherein the device comprises a node controller. System according to claim 18, wherein the device comprises an accelerator. System comprising: Means for entering a recognition state in conjunction with initializing a link between the device and the processor node, wherein the recognition state is one of a plurality of link training states, further comprising a reset state, a query state, and a configuration state; Means for sending a recognition supersequence to the device, wherein the recognition supersequence comprises a pattern to be repeated according to a specified frequency, the pattern comprises an electrical inactive ordered exit set (EIEOS) followed by six successive instances of a training sequence to indicate the recognition state, and the training sequence contains a defined data sequence to be used in the recognition state; Means for receiving an instance of the recognition supersequence from the device;and means of exiting the recognition state into another of the multitude of states based on the instance of the recognition supersequence.;

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