High-power factor power converter with adaptive output voltage limits for fast dynamic load response

Abstract

System which includes the following: a peak current mode controller for controlling the cycle operation of a power switch in a switching power converter for controlling an output voltage to a nominal value, wherein the peak current mode controller includes a comparator (520) to generate a turn-off command in response to a comparison of a multiplied fault signal with a signal (Isense) representing an input current into an AC / DC power converter; an upper threshold voltage (VOUT-limit) matching circuit (530) configured to increase an upper threshold voltage (VOUT-limit) in response to an increase in a voltage ripple between the output voltage and the nominal value, wherein the upper threshold voltage (VOUT-limit) matching circuit (530) is further configured to decrease the upper threshold voltage in response to a decrease in the voltage ripple; a lower threshold voltage (VOUT lower limit) matching circuit (535) configured to decrease a lower threshold voltage (VOUT lower limit) in response to an increase in voltage ripple, wherein the lower threshold voltage (VOUT lower limit) matching circuit (535) is further configured to increase the lower threshold voltage in response to a decrease in voltage ripple; and a mode control circuit (525) configured to allow the comparator (520) to control the cycling of a power switch when an output voltage for the switching power converter is both lower than the upper threshold voltage (VOUT upper limit) and higher than the lower threshold voltage (VOUT lower limit), and to prevent the comparator (520) from controlling the cycling of the power switch when the output voltage is higher than the upper threshold voltage (VOUT upper limit) or lower than the lower threshold voltage (VOUT lower limit).

Description

TECHNICAL AREA

[0001] This application relates to switching power converters and in particular to a switching power converter with adaptive output voltage limits. BACKGROUND

[0002] Single-stage AC / DC switching is a cost-effective and therefore popular power supply topology. An important parameter for a single-stage AC / DC switching power converter is its power factor, which is the ratio of the active power delivered to the single-stage AC / DC switching power converter by the AC supply line to the apparent power delivered to the single-stage AC / DC switching power converter. Apparent power, unlike active power, is insensitive to the phase difference between the input current and input voltage. The power factor is therefore reduced when the input current and input power are out of phase.The rectified input voltage to a single-stage AC / DC switching power converter cycles from approximately zero volts to the peak line voltage (e.g., 120 V * 1.414 in the USA) at twice the frequency of the AC supply line. Given this sinusoidal pulsation or cycling of the rectified input voltage, the input current should have a similar profile to achieve a high power factor, for example, by using a suitable peak current control methodology or a constant on-time.

[0003] Although single-stage AC / DC power conversion can therefore achieve a high power factor, the shaping of the input current to match the rectified input voltage cycle causes the output voltage to exhibit ripple around some nominal output value. If the control loop in a single-stage AC / DC switching power converter had a bandwidth greater than twice the AC supply line frequency, it would act to suppress this output voltage ripple. In this case, however, the power factor would decrease because the input current would no longer have the same rectified sinusoidal profile as the rectified input voltage.The bandwidth for the control loop in a single-stage AC / DC switching power converter must therefore be less than twice the line frequency to achieve a high power factor. The resulting control loop is typically implemented using a proportional-integral (PI) controller.

[0004] The relatively slow response time of the PI controller is problematic with regard to its ability to handle load transitions. For example, the load can suddenly increase from a relatively low to a relatively high power demand. Conversely, a high power demand can suddenly change to a low power demand at the load. To account for these transient changes, it is common practice to compare the output voltage to an upper and a lower output voltage limit. These output voltage limits can also be referred to as output voltage thresholds. If the output voltage feedback signal indicates that the output voltage has dropped below the lower output voltage limit or risen above the upper output voltage limit, the controller's response time is significantly increased.A maximum turn-on time can be used, for example, for each power switching cycle when the lower output voltage limit is exceeded. Similarly, a minimum turn-on time can be used for each power switching cycle when the upper output voltage limit is exceeded. After the output voltage recovers so that the output voltage feedback signal lies between the upper and lower voltage limits, the low-bandwidth PI control can continue.

[0005] Although modifying the control using the upper and lower voltage limits thus accounts for load transitions in single-stage AC / DC power converters with high PFC, the output voltage typically falls below the lower output voltage limit and exceeds the upper output voltage limit. For example, the output voltage for a conventional AC / DC power converter with high PFC is... Fig. Figure 1 shows an initial current demand at a light load, followed by a sudden current demand at a heavy load. The upper and lower limits for the output voltage must provide sufficient tolerance for normal operation during the heavy-load period. For example, it is common for the tolerance between the peak output voltage and the upper output voltage limit to be at least 5% of the nominal output voltage (the DC average for the output voltage). Likewise, it is common for the tolerance between the minimum output voltage and the lower output voltage limit to be at least 5% of the nominal output voltage. During heavy-load operation, the output voltage ripple itself may be 5% of the nominal output voltage. However, during light-load operation, the output ripple is significantly less than the 5% ripple seen during heavy-load operation.The tolerance between the lower output voltage limit and the minimum value for Vout during light-load operation is therefore significant. Consequently, when Vout changes due to the application of a heavy load, it typically falls below the lower output voltage limit. At this point, the regular PI control stops, allowing the maximum power cycles (or an increase in response gain) to be applied, as discussed above. The output voltage eventually recovers, at which point the regular PI control can resume. This undershoot is problematic because the output voltage oscillates below its desired minimum value.

[0006] Consequently, there is a need in the field for an improved transition response for single-stage AC / DC power converters.

[0007] Aleksandar Prodić, Dragan Maksimović, Robert W. Erickson: “Dead-Zone Digital Controllers for Improved Dynamic Response of Low Harmonic Rectifiers”, IEEE Transactions on Power Electronics, 2006, Vol. 21, Issue 1 describes a digital control method for regulating an output voltage.

[0008] Jerry J. Zheng, Anatoly Shteynberg, Dongshen Zhou, Jim McCreary: “A Novel Multimode Digital Control Approach for Singlestage Flyback Power Supplies with Power Factor Correction and Fast Output Voltage Regulation”, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2005, Vol. 2 describes an approach to digital control for achieving the unit power factor.

[0009] In Claudio Adragna: “Design Equations of High-Power-Factor Flyback Converters based on the L6561”, Application note AN1059, STMicroelectronics, September 2003, https: / / www.st.com / resource / en / application_note / cd00004040-design-equations-o-highpowerfactor-flyback-converters-based-on-the-16561-stmicroelectronics.pdf, equations related to a specific type of flyback converter are discussed.

[0010] In US 20150160669 A1, a circuit and a method for improving the performance of voltage regulators during load changes are presented. SUMMARY

[0011] A single-stage switching power converter is created that adaptively changes the upper and lower output voltage limits, which are used to distinguish between low-bandwidth PI regulation and high-speed output voltage regulation. The resulting adaptive output voltage limits mitigate the undervoltage and overvoltage problems that plague conventional high-power-factor single-stage AC / DC power converters.

[0012] These advantageous features can be better understood by considering the detailed description below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 represents the output voltage waveform for a state-of-the-art single-stage AC / DC power converter compared to its upper and lower output voltage limits for switching between regular PI control and increased response speed in response to a low-load current condition rapidly transitioning to a heavy-load current. Fig. Figure 2 represents the output voltage waveform in comparison to its adaptive upper and lower output voltage limits for switching between low-bandwidth PI control and a fast-response mode for a rapid change from a low-load condition to a high-load condition according to an embodiment of the disclosure. Fig. Figure 3 represents the output voltage waveform in comparison to its adaptive upper and lower output voltage limits for switching between low-bandwidth PI control and a fast-response mode for a transient change from a high-load condition to a low-load condition according to an embodiment of the disclosure. Fig. Figure 4 represents the output voltage waveform in comparison to its adaptive upper and lower output voltage limits for switching between low-bandwidth PI control and a fast-response mode for a gradual change from a low-load condition to a high-load condition according to an embodiment of the disclosure. Fig. Figure 5 is a diagram of a controller configured to adjust the upper and lower output voltage limits according to one embodiment of the disclosure. Fig. Figure 6 is a diagram of a return flow converter with the controller from Fig. 5 according to one embodiment of the disclosure.

[0013] Embodiments of the present disclosure and their advantages are best understood with reference to the following detailed description. It should be noted that identical reference numerals are used to identify identical elements depicted in one or more of the figures. DETAILED DESCRIPTION

[0014] To address the need for improved transient response in single-stage AC / DC switching power converters, the upper and lower output voltage limits that trigger a transition from low-bandwidth to fast-response control are adaptively determined with respect to the current output voltage ripple. In this way, the upper and lower output voltage limits depend on the current load conditions. During periods of low output current demand, the output voltage ripple is relatively small around its nominal value. The single-state AC / DC switching power converter controller disclosed here responds to this reduced output voltage ripple by lowering the upper output voltage limit compared to the upper output voltage limit used during periods of high output current demand.Similarly, the controller adaptively increases the lower output voltage limit during periods of light load compared to the lower output voltage limit used during a heavy or high load condition.

[0015] During periods of high load, the output voltage ripple increases relative to the nominal value (the DC mean value) of the output voltage. Consequently, the upper output voltage limit is raised in response to this increased ripple. Likewise, the lower output voltage limit is lowered in response to the increased ripple. By adjusting the output voltage limits to the current load requirements, the controller can respond more quickly to either an undervoltage or overvoltage condition. Fig. Figure 2, for example, shows the output voltage waveform when the load suddenly changes from a steady-state period with low load demand to a period with high load demand. Due to the reduced output voltage ripple relative to the nominal output voltage during the light-load condition, the distance or tolerance between the upper output voltage limit and the nominal output voltage is reduced during the light-load condition because the upper output voltage limit is adjusted compared to the tolerance used during the high-load period. Similarly, the tolerance between the lower output voltage limit and the nominal output voltage is adaptively reduced during the light-load condition compared to the tolerance used during the high-load period.At time t0, the load suddenly changes to a heavy load condition, causing the output voltage to drop below the lower output voltage limit. The control methodology can then be changed from conventional low-speed PI control to high-speed control, such as by cycle-controlling the circuit breaker using a maximum on-time. Alternatively, PI control can be maintained, but with a sufficiently increased gain to adequately respond to the undervoltage condition. If the circuit breaker cycle is saturated at its maximum on-time during high-speed control mode, the high-speed control mode can also be referred to as open-loop control mode, since the on-time is not changed.Alternatively, the switching frequency can be increased during high-speed control mode. High-speed control mode can continue until the output voltage rises sufficiently above the lower output voltage limit, after which a medium-gain PI control mode can be initiated. This medium-gain mode has a response speed greater than the low-speed PI control mode but less than the high-speed control mode. To determine when the transient change in output voltage has subsided, the controller can count the number of times the output voltage crosses the nominal output voltage value following the start of the transition period at time t0. After a sufficient number of crossings of the nominal output voltage value, the controller can determine that the transition period for the output voltage has ended at time t1.If the nominal voltage crossings occur at twice the line frequency, the transition period can be assumed to have ended at time t1, after which the low-bandwidth PI control mode can continue. During the transition period, the controller can adjust the voltage limits, but the voltage limits are not used for overvoltage or undervoltage detection during this period. Due to the increased load, the upper output voltage limit following the end of the transition period at time t1 is higher compared to the upper output voltage limit used during the light load condition. Similarly, the lower output voltage limit is lower compared to the lower output voltage limit used during the light load condition.The resulting output voltage limit adjustment is quite advantageous, as the undervoltage condition can be detected and addressed more quickly by initiating regulation at high speed compared to conventional controllers. Consequently, the output voltage is better regulated with respect to the desired nominal value due to the adjustment of the upper and lower output voltage limits.

[0016] A similar adjustment occurs for a sudden or transient transition from a steady-state condition with a heavy load to a condition with a light load, as in Fig. Figure 3 shows that during steady-state heavy-load conditions, the output voltage ripple is relatively large, so adjusting the output voltage limits increases the tolerance for the limits from the nominal output voltage. At time t0, the load demand suddenly transitions to a light-demand period. The upper output voltage limit is then violated because the output voltage rises accordingly, as the relatively slow PI control during the heavy-demand period cannot respond to the sudden decrease in load demand. A high-speed control mode then follows during the subsequent transition period, in which the controller can count the number of times the nominal output voltage is crossed by the output voltage to determine the end of the transition period at time t1. As with the light-to-heavy-load transition shown in Figure 3, the output voltage can be adjusted to the maximum output voltage. Fig. As described in section 2, the controller can switch to a medium-speed control mode once the output voltage has recovered sufficiently during the transition period. The controller can adjust the output voltage limits during the transition period to reduce the tolerance between the limits and the nominal output. The reduced-tolerance output voltage limits itself when the low-bandwidth PI control continues after the end of the transition period at time t1. In this way, the controller can respond quickly to a subsequent heavy load, as described in section 2. Fig. 2 discussed.

[0017] If there are no sudden changes in load requirements, the controller can gradually adjust the output voltage limits, as shown in Fig. Figure 4 shows a gradual transition from a period with a light load demand to a period with a heavier load demand. Since the output voltage never exceeds its limits due to this gradual change in load demand, the high-speed control mode is not invoked. An example controller implementation will now be discussed.

[0018] Fig. Figure 5 shows an example controller 500. In this embodiment, the controller 500 is a peak current mode controller; however, it can be seen that the output voltage limit adjustment discussed here can also be implemented in a constant-time on-time controller. A feedback voltage (V FBThe output voltage (Vout) is compared to a reference voltage at a comparator 505 to generate an error signal. A compensation filter 510 compensates for the error signal, as is known in the field of high-power-factor controllers. A multiplier 515 multiplies the error signal by a signal representing the rectified input voltage (Vin) to generate a multiplied error signal. The rectified voltage cycles at twice the frequency of the AC supply line (not shown). A comparator 520 compares the multiplied error signal to an isense signal representing the input current to the AC / DC switching power converter, which is controlled by the regulator 500.During low-bandwidth PI control, comparator 520 switches off the power switch (not shown) in each power switching cycle when Isense exceeds the multiplied error signal. The multiplied error signal thus determines the desired peak input current to the AC / DC switching power converter. Since this desired peak input current is modulated according to the cycle of the rectified input voltage, the resulting low-bandwidth PI control achieves a high power factor.

[0019] A mode control circuit 525 compares the output voltage (as determined by V). FB(shown) with an upper output voltage limit and a lower output voltage limit. When the output voltage is between the upper and lower output voltage limits, the comparator 520 controls the power switch cycle control as discussed above. Under an overvoltage condition, in which the output voltage exceeds the upper output voltage limit, the mode control circuit 525 controls the power switch cycle control using fast-mode control. Likewise, the mode control circuit 525 invokes fast-mode control in response to an undervoltage condition, in which the output voltage falls below the lower output voltage limit. Mode control based on a comparison of the output voltage with the upper and lower output voltage limits is conventional.To mitigate the undershooting and overshooting problems associated with such conventional control, the controller 500 includes an upper output voltage limit matching circuit 530, which adaptively changes the upper output voltage limit based on the output voltage ripple compared to the nominal output voltage.

[0020] The 530 upper output voltage limit matching circuit can be configured to either use a percentage of the output voltage ripple or simply add a voltage offset to the peak output voltage to generate the upper output voltage limit. Alternatively, the 530 upper output voltage limit matching circuit can use both techniques in parallel and utilize either the resulting minimum or maximum value. The matching can be performed using either a digital or analog circuit arrangement. To create smoothing, the 530 upper output voltage limit matching circuit can low-pass filter the upper output voltage limit. A 535 lower output voltage limit matching circuit adjusts the lower output voltage limit analogously, as discussed with respect to the 530 upper output voltage limit matching circuit.Circuits 530 and 535 can be configured to fix the adjustment (preventing further changes to the upper and lower output voltage limits) under a certain condition with maximum load requirement.

[0021] The resulting output voltage limit adjustment can be implemented in any suitable high-power-factor AC / DC switching power converter topology, including buck and boost converters. An example 600 feedback converter with a 500 regulator is shown in Fig. Figure 6 shows that the regulator 500 controls the switching of a power switch, such as an NMOS transistor Q1, by driving its gate via an output pin 5. In alternative embodiments, the power switch can be implemented using a bipolar junction transistor. When switched on, the power switching transistor Q1 allows a primary current to flow through a primary winding 610 of a transformer 615 in response to the rectified input voltage Vin. A rectifier 620 with a diode bridge and a capacitor C1 rectifies the line AC voltage carried on an AC supply line 621 to create the rectified input voltage Vin. The rectified input voltage Vin consequently still maintains a pronounced sinusoidal profile over each half of an AC supply cycle.

[0022] For each cycle of the power switching transistor Q1, the primary winding current rises from zero to a peak winding current value, which depends on the input voltage Vin, the turn-on time, and the inductance of the primary winding 610. When the power switching transistor Q1 turns off in the cycle, a secondary winding current flows through a second winding 625 in the transformer 615, starting from a peak value and continuously decreasing to zero. An output capacitor C2 stabilizes a resulting output voltage Vout, which is generated by the second winding current. A diode D1 prevents the secondary winding current from flowing while the primary winding is conducting. Alternatively, the diode D1 can be replaced by a transistor switch, as is common for a flyback converter with synchronous rectification.The secondary winding current generates a reflected voltage across the primary winding 610 and also across an auxiliary winding 630 for the transformer 615. Diode D1 has a voltage drop across this voltage, which prevents a direct relationship between the reflected voltage and the output voltage while the secondary current is still flowing. However, when the secondary current drops to zero (the transformer reset time), there is no voltage drop across diode D1, so the resulting reflected voltage at this time is directly related to the output voltage. By indirectly sampling the output voltage at this transformer reset time, the regulator 500 performs primary-only feedback control of the output voltage. The regulator 500 can, for example, measure a V. FBThe regulator 500 may include a ground pin 6 and a current-sensing pin 4, which samples the reflected voltage across the auxiliary winding 630 through a voltage divider formed by a pair of resistors R3 and R4. The reflected voltage can also be rectified by a diode D2 and a capacitor C3 to form a power supply voltage VCC, which is received by the regulator 205 at a power pin 1. The regulator 500 may include a ground pin 6 and a current-sensing (isense) pin 4, which samples the primary winding current by the voltage generated across a sampling resistor Rs coupled to a source of a power switching transistor Q1. The resulting adjustment of the upper and lower output voltage limits by the regulator 500 mitigates the conventional undershooting and overshooting of the output voltage in the flyback converter 600.

[0023] In addition to mitigating undershoot and overshoot problems, the adaptive output voltage limits disclosed here also address the aging of the output capacitor C2, which typically requires a relatively large capacitance to ensure stable steady-state operation. To provide sufficient capacitance at a low cost, it is common to implement the output capacitor C2 using an electrolytic capacitor. However, the capacitance of an electrolytic capacitor gradually decreases over its lifetime. Consequently, the output voltage ripple gradually increases over the lifetime of the electrolytic capacitor. With further reference to Fig.4. The slow increase in output voltage ripple is problematic insofar as conventional fixed upper and lower output voltage limits are eventually violated by the increased output voltage ripple, after which normal operation is no longer stable. To extend the expected lifetime, manufacturers are consequently forced to increase the capacitance of the electrolytic output capacitor, which increases costs. However, the adaptation disclosed here not only allows the use of less expensive output capacitors with reduced capacitance but also advantageously adapts to the increased output voltage ripple over the output capacitor's lifetime.

[0024] As the person skilled in the art will recognize, and depending on the specific application at hand, many modifications, substitutions, and changes can be made to the materials, devices, configurations, and methods for using the devices of this disclosure without deviating from its purpose and scope of protection. In light of this, the scope of protection of this disclosure should not be limited to that of the specific embodiments explained and described herein, since they serve only as some examples, but should instead fully correspond to that of the claims appended thereafter and their functional equivalents.

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