Methods for chaining media processing

Abstract

System comprising: a processor (101, 101a, 101b), a plurality of media units (110, 111, 112) and a media manager (130, 200, 301), each coupled via a system bus (102, 202), wherein each media unit (110, 111, 112) is configured to execute one or more instructions to process a display image; wherein the processor (101, 101a, 101b) is configured to store a plurality of media processing instructions in a queue (303); where the media manager (130, 200, 301) is configured to: retrieve a first media processing command from the plurality of media processing commands from the queue (303); send the first media processing command to a first media unit from the plurality of media units (110, 111, 112);While the first media processing instruction is being executed by the first media unit, retrieve a second media processing instruction from the queue (303); if the media manager (130, 200, 301) determines that the second media processing instruction is independent of the execution of the first media processing instruction, send the second media processing instruction to a second media unit from the plurality of media units (110, 111, 112); otherwise, in response to receiving an interrupt from the first media unit indicating that the first media unit has completed the first media processing instruction: send the second media processing instruction to the second media unit; copy data from the memory of the first media unit, generated by the first media processing instruction, into the memory of the second media unit for further processing.

Description

BACKGROUNDTechnical FieldEmbodiments described herein relate to the field of integrated circuit implementations and, more particularly, to the implementation of media processors.DESCRIPTION OF THE RELATED ARTComputing systems may include a graphics or media processor for handling various tasks associated with processing media content, such as videos, games, or animated renderings. Some computing systems may include multiple media processors to perform media tasks, each processor performing a specific task or performing tasks for a portion of an image to be displayed. In such systems, a host application processor may be used to issue commands to each of the multiple media processors and transfer data regarding images from one media processor to another.To manage multiple media processors, the main application processor may wait for a media processor to complete a first task associated with an image to be displayed. Then, the main application processor may transfer data from this media processor to another media processor along with a command to perform a next task associated with the image. The task of managing the media processor may cause the application processor to remain active at times when it could otherwise be placed in a reduced power mode, or the application processor may respond more slowly due to latencies that have occurred while switching between managing media processors and managing other applications.SUMMARY OF THE EMBODIMENTSVarious embodiments of a media processing system are disclosed. Broadly stated, a system, apparatus, and method are contemplated wherein the system includes a plurality of media units, a processor, and circuitry. Each media unit of the plurality of media units may be configured to execute one or more instructions to process a display image. The processor may be configured to store a plurality of media processing instructions in a queue. The circuitry may be configured to retrieve a first media processing command of the plurality of media processing commands from the queue and send the first media processing command to a first media unit of the plurality of media units. The circuitry may be further configured to retrieve a second media processing command of the plurality of media processing commands from the queue and, responsive to receiving an interrupt from the first media unit, send the second media processing command to a second media unit of the plurality of media units. The circuitry may also be configured to copy data from the first media unit to the second media unit in response to receiving the interrupt.In another embodiment, the processor may be further configured to enter a reduced power state in response to storing the plurality of media processing instructions in the queue. In another embodiment, the system may further comprise a direct memory access unit (DMA)). To copy the data from the first media unit to the second media unit, the DMA may be configured to read the data from the first media unit and store the data in the second media unit.In one embodiment, both the first media unit and the second media unit may include a graphics processing unit. In another embodiment, the second media unit may include a display controller.In another embodiment, the second media unit may include a media scaling processor. In a particular embodiment, the circuitry may be further configured to retrieve a third media processing command from the queue and send the third media processing command to a third media unit of the plurality of media units after the circuitry retrieves the second media processing command from the queue and prior to sending the second media processing command to the second media unit.BRIEF DESCRIPTION OF THE DRAWINGSThe following detailed description will be made with reference to the accompanying drawings, which will now be briefly described. FIG. 1 illustrates a block diagram of an embodiment of a computing system. FIG. 2 illustrates a block diagram of a media management processor. FIG. 3 is a diagram illustrating a flow of data and instructions through multiple media units. FIG. 4 illustrates a flow diagram illustrating an embodiment of a method for managing multiple media units.Although the disclosure may occur in various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. It is to be understood, however, that the drawings and detailed description thereof are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organization purposes only and are not intended to be used to limit the scope of the description. As used in this application, the word "may" is used in an permitting sense (i.e., it means there is a possibility for something) and not in the obligatory sense (i.e., it means "must"). Similarly, the words "include," "including," "including," "includes" have the meaning of "including, but not limited to.".Various units, circuits, or other components may be described as being "configured" to perform one or more tasks. In such contexts, "configured to" is a broad definition of a structure that generally means having "circuitry that" performs the task or tasks during operation. As such, the unit / circuit / component may be configured to perform the task even when the unit / circuit / component is not currently powered on. In general, the circuitry forming the structure "configured to" accordingly may include hardware circuits. Likewise, for convenience in description, various units / circuits / components may be described as performing a task or tasks. Such descriptions should be interpreted as including the term "configured to.". Expressly, the mention of a device / circuit / component configured to perform one or more tasks is not intended to refer to an interpretation under 35 U.S.C. §112 paragraph (f) for that device / circuit / component. More generally, the denomination of any element is expressly not intended to refer to an interpretation under 35 U.S.C. §112, paragraph (f) for that element, unless the language "means for" or "step for" is specifically mentioned.DETAILED DESCRIPTION OF EMBODIMENTSA computing system may include one or more circuits for performing tasks related to processing data related to displaying videos, playing games, or rendering other animated graphics to a display screen. Such computing systems may include desktop or laptop computers, tablets, smartphones, or other types of devices. The one or more circuits may include, for example, graphics processors, video encoders / decoders, media scalars, and displays. These circuits are collectively referred to herein as "media agents.".To generate animated images on a display screen, a series of still images are displayed in sequence. Each still image may be referred to as a frame ("frame") and may be generated and processed by one or more media agents. For example, a graphics processor may generate a frame based on read or received data. After the graphics processor generates the frame, the frame may then be processed by a media scaler, encoder, and display. Some of the processing may occur in parallel, while some processing may occur in series.To control the processing flow of the frame by different media agents, a host application processor may be used to issue commands to each media agent and transfer the frame from one agent to another while waiting for the first agent to be ready to transfer the frame to a second or third agent. Managing the media agents in such a manner may consume processing bandwidth from the application processor that could be used for other tasks, resulting in performance latencies that may make the system appear non-responsive to a user. Otherwise, in the absence of other tasks to be performed, the processor could be placed in a reduced power mode to conserve battery / battery power.The embodiments illustrated in the drawings and described below may allow for more efficient use of a host application processor by reducing the inclusion of the processor in media processing tasks. These embodiments may provide techniques that may allow a method for managing different media agents while using less bandwidth from the main application processor.A block diagram of an embodiment of a computing system is illustrated in FIG. 1. In the illustrated embodiment, a system 100 includes processors 101 a- bcoupled to a memory controller (MC)) 104 via a system bus 102, media units 110- 112, a display driver 118, and a media manager 130. The memory controller 104 is coupled to a memory 105, and the display driver 118 is coupled to a display 119. An interrupt controller 120 is coupled to the media units 110 to 112 and the processors 101a to b. In various embodiments, the system 100 may be implemented as multiple integrated circuits (ICs)) coupled together on one or more circuit boards, as a system-on-a-chip (SoC) system) in which all circuits are integrated on a single IC, or as a combination thereof.Processors 101 a- bmay represent a general purpose processor performing computational operations in various embodiments. For example, the processors 101 ato bmay be central processing units (CPUs)), such as microprocessors, microcontrollers, application-specific integrated circuits (ASICs)) or field-programmable gate arrays (FPGAs)). Although two processors 101 are illustrated, some embodiments of the system 100 may include a single processor 101 or more than two processors.In various embodiments, processor 101 may implement any suitable instruction set architecture (ISA)), such as ARM™ PowerPC™ or x86 ISAs, or a combination thereof. The processors 101 ato bmay implement the same ISA or each processor 101 ato bmay implement a different ISA. Processor 101 may include one or more bus transceiver units that allow processor 101 to communicate with other functional blocks over system bus 102.The system bus 102 may be configured as one or more buses to enable the transfer of instructions and data between the various functional blocks within the system 100. A subset of the various function blocks, such as processors 101 a- band media manager 130, may be "bus master," or in other words, function blocks that may initiate communications over system bus 102. Other functional blocks may be limited to sending or receiving data over the system bus 102 in response to a command from one of the bus masters.The memory controller block 104 provides an interface to the memory block 105. In addition to receiving commands to read and write data to memory 105, memory controller 104 may perform additional tasks, such as assigning virtual to physical addresses, data updating, and garbage collection. Additionally, the memory controller 105 may manage performance modes of one or more memory arrays in the memory block 105.The memory block 105 may include any suitable type of memory, such as dynamic random access memory (DRAM)), static random access memory (SRAM)), read-only memory (ROM)), electrically erasable programmable read-only memory (EEPROM)), flash memory, ferroelectric random access memory (FeRAM)), for example, a resistive random access memory (RRAM or ReRAM)) or, for example, a magneto-resistive random access memory (MRAM)). Some embodiments may include a single memory, as shown, and other embodiments may include more than one memory block (not shown). In some embodiments, memory block 105 may be configured to store program instructions that may be executed by processors 101 a- b. The memory block 105 may be configured to store data to be processed, such as graphics data, in other embodiments.The media units 110-112 may include various media agents that generate and / or process media information. In various embodiments, media units 110-112 may correspond to graphics processors, video encoders, video decoders, camera processors, color processing units, and media scaling and rotation processors. In some embodiments, the media units 110-112 may each perform different functions, for example, route a frame from the media unit 110 to the media unit 111 and then from the media unit 111 to the media unit 112. A frame output from the media unit 112 may be sent to the display driver 118. In other embodiments, two or more of the media units 110-112 may perform similar functions. For example, media units 110 and 111 may both be graphics processors, with each media unit processing a portion of a given frame. The respective portions of the given frame output by media units 110 and 111 may be received by media unit 112 and / or display driver 118. Although three media units are illustrated, any suitable number of media units may be included in system 100.The display driver 118 may include an interface for sending a frame to the display 119. In some embodiments, the display driver 118 may include a memory for storing a currently displayed frame, and may also include a memory for queuing a next frame to be displayed. The display driver 118 may include circuitry for processing the frame before the image data is sent to the display 119, such as adjusting for brightness and contrast settings. The display 119 may be any suitable type of display, such as liquid crystal diode (LCD), organic light emitting diode (OLED)), electrophoretic display (EPD)), or interferometric modulator display (IMOD)). The display 119 may be included as part of the system 100 or may be located in a separate housing coupled to the display driver 118 via a cable or wireless interface. A user interface (UI)) may be included in the display 119 in some embodiments.Interrupt controller 120 receives signals from media units 110-112 and may set one or more interrupt signals for processors 101a-b or media manager 130. In addition to receiving signals from the media units 110-112, the interrupt controller 120 may receive signals from various other functional blocks in the system 100 (not shown). Each media unit 110-112 may set a signal to indicate completion upon completion of a current task or command. Interrupt controller 120 may receive the set signal and in response set a corresponding interrupt signal for one or more processors, including processors 101 a- band media manager 130. Interrupt controller 120 may include registers and circuitry that allow a given input signal to be directed to a particular interrupt. For example, in the present embodiment, the signals from the media units 110 to 112 are routed to an interrupt signal sent to the media manager 130.The media manager 130 may handle or assist in handling the generation of frames for the display 119. As mentioned previously, a frame may pass through one or more media agents before being displayed on the display 119. The movement of the frame may require a processor to read the frame from a first media agent and copy the frame to a next media agent. The media manager 130 receives an interrupt from one of the media units 110 to 112, for example, the media unit 110 corresponding to a set completion signal. In response to the interrupt, media manager 130 may copy a frame from memory in media unit 110 and store it in a next media unit, such as media unit 112, for a next processing step. The media manager 130 may retrieve commands and information regarding the next processing step from a media queue. The media queue may consist of a portion of the memory 105, be implemented as a buffer coupled to the system bus 102, or be memory implemented within the media manager 130, in various embodiments. Commands and information regarding media processes may be stored in the media queue in response to software executed in one or more of the processors 101 a- b. For example, processor 101 bmay execute instructions for a software program including displaying images of a full screen. In response to executing the software, processor 101 bstores media-related commands in the media queue, allowing media manager 130 to handle execution of the media-related commands by one or more media agents.It should be noted that the system illustrated in FIG. 1 is merely one example. In other embodiments, depending on the specific application for which the system is intended, other functional blocks and other configurations of functional blocks may be possible. For example, in other embodiments, more than three media units and / or more than a single display driver may be included.Turning to FIG. 2, an embodiment of a block diagram of a media manager is illustrated. In some embodiments, media manager 200 may correspond to media manager 130 in FIG. 1. In the illustrated embodiment, the media manager 200 includes a media processor 205, direct memory access (DMA) 206, and a memory 207. The media processor 205 and the DMA 206 are coupled to a system bus 202. The media processor 205 receives an interrupt signal 210.The media processor 205 may correspond to a universal processing core similar to the processors 101 a- bin FIG. 1 performing computational operations. For example, the media processor 205 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In various embodiments, the media processor 205 may implement any suitable instruction set architecture (ISA), such as ARM™ PowerPC™ or x86 ISAs, or a combination thereof.In the present embodiment, the DMA 206 is capable of transferring data from a source location to a destination location. The source and destination locations may be memory locations, such as memory 207 or memory block 105 in FIG. 1, or register locations within a functional block, such as media units 110-112 or display driver 118 in FIG. 1. In some embodiments, DMA 206 may be capable of performing scatter-weather or weather-scatter memory transfers. "Scatter-weather" refers to a memory transfer in which the source addresses are varied (e.g., spread ("spread")) and the destination address is a single address (e.g., gathered ("spread")). "Weather-scatter" is accordingly the opposite. The media processor 205 may program the DMA 206 for one or more data transfers simultaneously.Memory 207 includes a media command queue from which media processor 205 fetches media commands. In some embodiments, the memory 207 may be implemented as random access memory (RAM), and may also include program instructions for the operation of the media processor 205. In other embodiments, memory 207 may be a first-in, first-out (FIFO) buffer and reserved for use as the media command queue.In the illustrated embodiment, the media processor 205 performs operations to manage a flow of data regarding media, such as frames to be displayed, when the data is sent to various media agents before being sent to a display. The media processor 205 fetches a first instruction from a media queue in the memory 207 and from the first instruction detects a target media agent to execute the instruction. Based on the first command, the media processor 205 may configure the DMA 206 to retrieve a first record for a frame from another media agent or from a memory such as the memory 207 or the memory block 105 in FIG. 1. The DMA 206 copies the first record to a target media agent. The media processor 205 sends the first command to the target media agent for execution. As the target media agent executes the first media command, the media processor 205 fetches a second command from the media command queue in memory 207. The second command may correspond to a second record for a second media agent; in this case, the media processor 205 directs the DMA 206 to copy the second record to the second media agent while the first command continues to be executed.In contrast, the second command may correspond to a next step for the first record being processed by the target media agent. In this second case, the media processor 205 may wait until the target media agent completes execution of the first instruction before initiating the DMA 206 to transfer the first record from the target media agent to another media agent. While waiting for the first media agent to complete the first command, in some embodiments, the media processor 205 may fetch a third command from the media command queue, while in other embodiments, the media processor 205 may enter a reduced power mode during the waiting. When the target media agent completes execution of the first instruction, interrupt signal 210 is asserted via an interrupt controller, such as interrupt controller 120 in FIG. 1. In response to the interrupt signal 210 being asserted, the media processor 205 may begin processing the second instruction, including setting up the DMA 206 to transfer the first record to the other media agent. In embodiments where a third command is started, the media processor 205 may pause processing the third command to process the second command, or instead may complete the transfer of data regarding the third command and send the third command to the corresponding media agent before processing the second command.It is noted that the embodiment of media manager 200 illustrated in FIG. 2 is merely an example. The illustration of FIG. 2 has been simplified to emphasize features relevant to this disclosure. Various embodiments may include other configurations of the functional blocks, including additional blocks.Turning to FIG. 3, a diagram depicting a flow of data and instructions through multiple media units is presented. A diagram 300 illustrates an example data flow of commands A, B, and C stored in a media command queue 303 for generating a frame 320. Diagram 300 includes media manager 301, media command queue 303, interrupt controller 305, media units 310-312, and display interface 322.The instructions A, B, and C are stored into the media instruction queue 303 by a processor, such as the processor 101 aor 101 bof the system 100 in FIG. 1. In the present embodiment, the commands A, B, and C correspond to a single frame (frame "2") to be displayed via the display interface 322. If at least one command has been stored in queue 303, such as command A, media manager 301 retrieves command A from queue 303 and determines from the command which media unit 310-312 the command is targeted to. The media manager 301 determines that command A is intended for the media unit 310 and, in response to the determination, sends the command to the media unit 310. In some cases, the media manager 301 may also retrieve a set of data associated with command A and send that record to the media unit 310, while in other cases the media unit 310 may already have access to the record from, for example, a previously executed command. As media unit 310 executes command A, media manager 301 fetches command B from queue 303. Command B is intended for media unit 311, but command B uses the output of command A. Therefore, media manager 301 waits for media unit 310 to complete command A before sending command B to media unit 311. In some embodiments, the media manager 301 may wait for the command B to execute before fetching the command C. However, in the present embodiment, the media manager 301 fetches the command C while the media unit 310 continues to process the command A.Command C targets media unit 312 and uses a different record than commands A and B. Command C can therefore be processed in parallel with commands A and B. The media manager 301 sends the command C to the media unit 312 and, if necessary, sends an associated record to the media unit 312. While the instruction C is being processed, the media unit 310 may complete execution of instruction A and have prepared a record 2a as output. The media unit sets an end of command A (end A) signal to the interrupt controller 305. Interrupt controller 305 allocates the end-A signal from media unit 310 to media manager 301, and therefore sets an interrupt signal coupled to media manager 301. In response to the interrupt signal, the media manager 301 fetches the record 2a from the media unit 310 and transmits it to the media unit 311 together with the command B. While instruction B is being processed by media unit 311, media unit 312 may complete execution of instruction C. In response to completion of instruction C, media unit 312 sets an end of instruction C (end C) signal to interrupt controller 305. The interrupt controller responds by asserting the interrupt signal again, alerting the media manager 301. In some embodiments, the media manager 301 may include multiple interrupt inputs for the media units in the system, which may allow the media manager 301 to determine which media unit has reached the end of a command based on which associated interrupt is set. In other embodiments, the media manager may have a single interrupt input for all media units and may need to determine which media unit has completed command processing, such as by querying each active media unit.In the present embodiment, the media manager 301 determines that the media unit 312 has completed the command C. However, the media manager 301 also determines that command B needs to be completed in order for a complete frame 320 to be generated. In some embodiments, media manager 301 may retrieve record 2c from media unit 312 before instruction B is completed, while in other embodiments media manager 301 may wait until instruction B is completed before record 2c is retrieved. When the media unit 311 completes the command B and sets the signal "end of command B" (end B) to the interrupt control unit 305, the media manager receives the corresponding interrupt signal and determines that the processing for the records 2 a, 2 b, and 2 care completed, and transfers the records to the frame 320 which is sent to the display interface 322. In various embodiments, the frame 320 may be sent to another function block (e.g., a media scaler) in addition to or in place of the display interface 322.It is noted that while execution of instructions A, B, and C occurs, main processors in the system, such as processors 101 a- bin system 100 of FIG. 1, may be available for processing instructions for other applications or an operating system. Processors 101 aand 101 bmay also enter low power modes while media manager 301 manages the data flow for generating frame 320.It is also noted that the diagram of FIG. 3 illustrates only examples of data flow that may result from an embodiment presented in this disclosure. Various other embodiments may include a different number of media units and instructions and may result in a different data flow among the media units.Turning now to FIG. 4, a flowchart illustrating one embodiment of a method for managing multiple media units is illustrated. The method may be applied to a media management processor such as media manager 130 in FIG. 1. Referring collectively to the system 100 and the flowchart in FIG. 4, the method may begin at block 401.A first processor stores instructions in a queue (block 402). Instructions are queued by a first processor, such as processor 101a or 101b. In various embodiments, the queue may correspond to circuitry dedicated to storing instructions, for example a FIFO buffer, or a data structure maintained in a larger system memory, such as memory 105. The stored commands may include multiple commands to generate a single frame, in some embodiments.A second processor fetches a first instruction from the queue (block 404). In the present embodiment, the second processor corresponds to a media management processor, such as media manager 130. Media manager 130 determines a target media agent for the first command, such as media unit 111. The media manager 130 may also determine whether to copy data associated with the first command to the media unit 111.The media manager 130 sends the first command to the media unit 111 (block 406). The media unit 111 receives the first command and may receive data associated with the first command. The first command may result in a processing portion of the data to generate a frame for display. Additional processing of the output of the media unit 111 from the execution of the first command may occur before the data for the frame is complete.The media manager 130 retrieves a second command from the queue (block 408). As the media unit 111 processes the first command, the media manager 130 fetches the second command. The media manager 130 determines the target media agent for the second command, such as the media unit 112. The media manager 130 also determines that the second command is to be executed on the output from the first command executed by the media unit 111.Further operations of the method may depend on execution of the first instruction by the media unit 111 (block 410). When media unit 111 completes the first instruction, it sets a signal to indicate that the first instruction is completed. This command completion indication initiates an interrupt to the media manager 130 via, for example, the interrupt controller 120. If the interrupt was not triggered, the method remains in block 410. The media manager 130, in some embodiments, may fetch a third command while waiting for the interrupt to be triggered. If the interrupt has been triggered, the method proceeds to block 412 to process the second instruction.After the interrupt indicating that the media unit 111 has completed the first command has been set, the media manager 130 sends the second command to the media unit 112 (block 412). In response to the interrupt from the interrupt controller 120, the media manager 130 sends the second command to the media unit 112 as previously determined as the target media agent. Additionally, the media manager 130 copies output data from the media unit 111 to the media unit 112 for use in executing the second instruction. For example, the media unit 111 may generate an initial frame or portion of a frame based on the first command. The media unit 112 may adjust color, opacity, or scale of the initial frame depending on the second command, and therefore uses the output from the media unit 111 to generate an adjusted frame. The adjusted frame may be sent by the media manager 130 to a display driver, to a file in memory, to a third media agent, or to another suitable destination as determined by commands from the queue.It is noted that the method illustrated in FIG. 4 is merely an example embodiment. Variations on this method are possible. Some operations may be performed in a different sequence, and / or additional operations may be included.Although specific embodiments have been described above, it is not intended to limit these embodiments to the scope of the present disclosure, even though only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative and not restrictive unless otherwise stated. The foregoing description is intended to include such alternatives, modifications, and equivalents as would be apparent to one skilled in the art having the benefit of this disclosure.The scope of the present disclosure includes any feature disclosed herein (both explicit and implicit), or any combination of features, or any generalization thereof, regardless of whether it attenuates any or all of the problems addressed herein. Accordingly, during the continuation of this application (or an application claiming the priority thereof), new claims may be formulated to any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined with those of the independent claims, and features of the respective independent claims may be combined in any suitable manner and not just in the specific combinations recited in the appended claims.

Claims

A system, comprising: a processor (101, 101a, 101b), a plurality of media units (110, 111, 112), and a media manager (130, 200, 301), each coupled via a system bus (102, 202), each media unit (110, 111, 112) configured to execute one or more instructions to process a display image; wherein the processor (101, 101a, 101b) is configured to store a plurality of media processing instructions in a queue (303); wherein the media manager (130, 200, 301) is configured to: retrieve a first media processing instruction of the plurality of media processing instructions from the queue (303); send the first media processing instruction to a first media unit of the plurality of media units (110, 111, 112); retrieving, while the first media processing command is executed by the first media unit, a second media processing command of the plurality of media processing commands from the queue (303); if the media manager (130, 200, 301) determines that the second media processing command is independent of execution of the first media processing command, sending the second media processing command to a second media unit of the plurality of media units (110, 111, 112); and otherwise, in response to receiving an interrupt from the first media unit indicating that the first media unit has completed the first media processing command: sending the second media processing command to the second media unit, copying data from the memory of the first media unit generated by the first media processing command to the memory of the second media unit for further processing.The system of claim 1, wherein the processor (101, 101a, 101b) is further configured to enter a reduced power state in response to storing the plurality of media processing instructions in the queue (303).The system of claim 1, further comprising a direct memory access unit, DMA (206), wherein to copy the data from the memory of the first media unit to the memory of the second media unit, the DMA (206) is configured to read the data from the memory of the first media unit and store the data in the memory of the second media unit.The system of claim 1, wherein the first media unit includes at least one of a camera circuit, a video decoder, a video encoder, a graphics processing unit, a display driver (118), a color processing unit, and a media scaling processor.The system of claim 1, wherein the second media unit includes at least one of a camera circuit, a video decoder, a video encoder, a graphics processing unit, a display driver (118), a color processing unit, and a media scaling processor.The system of claim 1, wherein the media manager (130, 200, 301) is further configured to retrieve a third media processing command from the queue (303) and send the third media processing command to a third media unit of the plurality of media units (110, 111, 112).The system of claim 6, wherein the media manager (130, 200, 301) is further configured to send the third media processing command to the third media unit after the media manager (130, 200, 301) retrieves the second media processing command from the queue (303) and prior to sending the second media processing command to the second media unit.A method comprising: executing one or more instructions to process a display image, wherein each media unit of a plurality of media units (110, 111, 112) is configured to execute; storing a plurality of media processing instructions in a queue (303) by a processor (101, 101a, 101b); retrieving, by a media manager (130, 200, 301), a first media processing instruction of the plurality of media processing instructions from the queue (303); sending, by the media manager (130, 200, 301), the first media processing instruction to a first media unit of the plurality of media units (110, 111, 112); retrieving, by the media manager (130, 200, 301), a second media processing instruction of the plurality of media processing instructions from the queue (303) while the first media processing instruction is executed by the first media unit; if the media manager (130, 200, 301) determines that the second media processing command is independent of execution of the first media processing command, sending, by the media manager (130, 200, 301), the second media processing command to a second media unit of the plurality of media units (110, 111, 112), and otherwise, in response to receiving an interrupt from the first media unit indicating that the first media unit has completed the first media processing command: sending, by the media manager (130, 200, 301), the second media processing command to the second media unit, copying, by the media manager (130, 200, 301), data from the memory of the first media unit generated by the first media processing command to the memory of the second media unit for further processing.The method of claim 8, wherein the method further comprises entering a reduced power state, by the processor (101, 101a, 101b), in response to storing the plurality of media processing instructions in the queue (303).The method of claim 8, wherein copying the data from the first media unit memory to the second media unit memory comprises copying, by direct memory access, DMA (206), the data from the first media unit memory to the second media unit memory.The method of claim 8, wherein the first media unit includes at least one of a camera circuit, a video decoder, a video encoder, a graphics processing unit, a display driver (118), a color processing unit, and a media scaling processor.The method of claim 8, wherein the method further comprises displaying, by the second media unit, at least a portion of an image on a display (119) that depends on the data received from the second media unit.The method of claim 8, wherein the method further comprises scaling, by the second media unit, at least a portion of an image represented by the data received from the second media unit.The method of claim 8, further comprising: retrieving, by the media manager (130, 200, 301), a third media processing command of the plurality of media processing commands from the queue (303); and sending, by the media manager (130, 200, 301), the third media processing command to a third media unit after retrieving the second media processing command and before sending the second media processing command to the second media unit.The method of claim 14, wherein the method further comprises sending, by the media manager (130, 200, 301), the third media processing command to the first media unit in response to receiving a second interrupt from the second media unit.

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