SiC semiconductor component

Abstract

SiC semiconductor device (1, 131, 141, 151) comprising: a SiC semiconductor layer (8) of a first conductivity type having a main surface (3); a source trench (31) formed in the main surface (3) having a side wall and a bottom wall; a source electrode (33) embedded in the source trench (31) having a side wall contact section (39) in contact with a region of the side wall of the source trench (31) at an opening side of the source trench (31); a body region (41) of a second conductivity type formed in a region of a surface layer section of the main surface (3) along the source trench (31);a source region (42) of the first conductivity type, which is electrically connected to the side wall contact section (39) of the source electrode (33) in a surface layer section of the body region (41); an insulating layer (63) covering the source region (42) on the main surface (3); a source hole (67) formed in the insulating layer (63) which exposes the source electrode (33); and a source connecting electrode (85) embedded in the source hole and connected to the source electrode (33), wherein the source hole (67) exposes only the source electrode (33) and the source connecting electrode (85) is connected only to the source electrode (33) within the source hole (67).

Description

Technical field

[0001] The present invention relates to a SiC semiconductor component having a source trench. State of the art

[0002] Patent literature 1 discloses a SiC semiconductor device comprising a SiC semiconductor substrate, a source trench, a source insulating layer, a source electrode, a body region, and a source region. The source trench is formed in a main face of the SiC semiconductor substrate. The source insulating layer is formed on an inner wall of the source trench. The source electrode is embedded in the source trench via the source insulating layer. The body region is located opposite the source electrode via the source insulating layer, specifically in a surface layer section of the main face of the SiC semiconductor substrate. The source region is located opposite the source electrode via the source insulating layer, specifically in a surface layer section of the body region. List of citations from patent literature

[0003] Patent literature 1: WO 2016 / 006696 A1 Overview of the invention Technical problem

[0004] A preferred embodiment of the present invention provides a SiC semiconductor component in which a source region in a structure having a source trench can be suitably source grounded. Solution to the problem

[0005] A preferred embodiment of the present invention provides a SiC semiconductor component, a with a SiC semiconductor layer of a first conductivity type having a main surface, with a source trench formed in the main surface having a side wall and a bottom wall, with a source electrode embedded in the source trench having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, with a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and with a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.

[0006] According to this SiC semiconductor device, the source region is electrically connected to the source electrode, which is exposed opposite the side wall of the source trench. This allows for the provision of a SiC semiconductor device in which the source region can be appropriately source-grounded.

[0007] The aforementioned tasks, features and effects of the present invention, as well as further ones, will become clearer from the following description of the preferred embodiments with reference to the accompanying drawings. List of characters Fig. Figure 1 is a perspective view of a SiC semiconductor component of a first preferred embodiment of the present invention. Fig. Figure 2 is a top view of the SiC semiconductor component, which is located in Fig. 1 is shown. Fig. Figure 3 is a top view showing structures above the first main surface electrodes compared to the one in Fig. The structure shown in section 2 has been removed. Fig. 4 is an enlarged top view of an internal structure of region IV, which is located in Fig. 3 is shown. Fig. 5 is a sectional view along a line VV, which is in Fig. 4 is shown. Fig. 6 is a sectional view along a line VI-VI, which is in Fig. 4 is shown. Fig. 7 is a sectional view along a line VII-VII, which is in Fig. 4 is shown. Fig. 8 is an enlarged view of Region VIII, which is located in Fig. 5 is shown. Fig. Figure 9 is an enlarged view of Region IX, which is located in Fig. 6 is shown. Fig. 10 is a sectional view along a line XX, which is in Fig. 2 is shown. Fig. Figure 11A is an enlarged sectional view of an example of a method for manufacturing the SiC semiconductor component described in Fig. 1 is shown. Fig. 11B is an enlarged sectional view of a step after Fig. 11A. Fig. 11C is an enlarged sectional view of a step after Fig. 11B. Fig. 11D is an enlarged sectional view of a step after Fig. 11C. Fig. 11E is an enlarged sectional view of a step after Fig. 11D. Fig. 11F is an enlarged sectional view of a step after Fig. 11E. Fig. 11G is an enlarged cross-sectional view of a step after Fig. 11F. Fig. 11H is an enlarged sectional view of a step after Fig. 11G. Fig. 11I is an enlarged sectional view of a step after Fig. 11H. Fig. 11J is an enlarged cross-sectional view of a step after Fig. 11I. Fig. 11K is an enlarged cross-sectional view of a step after Fig. 11 years. Fig. 11L is an enlarged sectional view of a step after Fig. 11K. Fig. 11M is an enlarged sectional view of a step after Fig. 11L. Fig. 11N is an enlarged sectional view of a step after Fig. 11M. Fig. 11O is an enlarged cross-sectional view of a step after Fig. 11N. Fig. 11P is an enlarged cross-sectional view of a step after Fig. 110. Fig. 11Q is an enlarged sectional view of a step after Fig. 11P. Fig. 11R is an enlarged sectional view of a step after Fig. 11Q. Fig. 11S is an enlarged cross-sectional view of a step after Fig. 11R. Fig. 12 is an enlarged view of a region accordingly Fig. Figure 8 and is a diagram that partially shows a SiC semiconductor component according to a second preferred embodiment of the present invention. Fig. Figure 13A is an enlarged sectional view of an example of a method for manufacturing the SiC semiconductor component described in Fig. 12 is shown. Fig. 13B is an enlarged sectional view of a step after Fig. 13A. Fig. 13C is an enlarged sectional view of a step after Fig. 13B. Fig. 13D is an enlarged cross-sectional view of a step after Fig. 13C. Fig. 13E is an enlarged sectional view of a step after Fig. 13D. Fig. 13F is an enlarged sectional view of a step after Fig. 13E. Fig. 14 is an enlarged view of a region accordingly Fig. Figure 8 and is a diagram that partially shows a SiC semiconductor component according to a third preferred embodiment of the present invention. Fig. Figure 15A is an enlarged sectional view of an example of a method for manufacturing the SiC semiconductor component described in Fig. 14 is shown. Fig. 15B is an enlarged sectional view of a step after Fig. 15A. Fig. 16 is an enlarged view of a region accordingly Fig. Figure 8 and is a diagram that partially shows a SiC semiconductor component according to a fourth preferred embodiment of the present invention. Description of embodiments

[0008] Fig. Figure 1 is a perspective view of a SiC semiconductor component 1 according to a first preferred embodiment of the present invention. Fig. Figure 2 is a top view of the SiC semiconductor component 1, which is located in Fig. 1 is shown. Fig. Figure 3 is a top view showing structures above a gate main surface electrode 71 and a source main surface electrode 81 (first main surface electrodes) compared to the one in Fig. The structure shown in section 2 has been removed. Fig. 4 is an enlarged top view of an internal structure of region IV, which is located in Fig. Figure 3 shows a sectional view along a line VV, which is shown in Figure 5. Fig. 4 is shown. Fig. 6 is a sectional view along a line VI-VI, which is in Fig. 4 is shown. Fig. 7 is a sectional view along a line VII-VII, which is in Fig. 4 is shown. Fig. 8 is an enlarged view of Region VIII, which is located in Fig. 5 is shown. Fig. Figure 9 is an enlarged view of Region IX, which is located in Fig. Figure 6 is shown. Figure 10 is a sectional view along a line XX, which is in Fig. 2 is shown.

[0009] With reference to the Fig. 1 to Fig. 10 The SiC semiconductor component 1 contains a SiC semiconductor layer 2 The SiC semiconductor layer 2 It features a SiC monocrystal built from a hexagonal crystal. The SiC monocrystal, built from the hexagonal crystal, exhibits a variety of polytypes, including a 2H (hexagonal) SiC monocrystal, a 4H SiC monocrystal, a 6H SiC monocrystal, etc., according to a cycle or period of the atomic arrangement. Although the SiC semiconductor layer 2 The fact that this embodiment is constructed from a 4H-SiC monocrystal does not exclude other polytypes.

[0010] The thickness of the SiC semiconductor layer 2 The thickness of the SiC semiconductor layer is not less than 40 µm and not greater than 300 µm. 2 The thickness of the SiC semiconductor layer may be no less than 40 µm and no greater than 100 µm, no less than 100 µm and no greater than 150 µm, no less than 150 µm and no greater than 200 µm, no less than 200 µm and no greater than 250 µm, or no less than 250 µm and no greater than 300 µm. 2 is preferably not smaller than 60 µm and not larger than 150 µm.

[0011] The SiC semiconductor layer 2 has a first main area 3 on one side, a second main surface 4 on another side and side surfaces 5A, 5B, 5C and 5D, which form the first main surface 3and connect the second main surface 4. The side surfaces 5A to 5D include the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The first main surface 3 and the second main surface 4 are formed into four-sided shapes (rectangular shapes in this embodiment), namely in a top view when viewed from a normal direction Z thereto (hereinafter simply referred to as "top view").

[0012] In this embodiment, the first main surface 3 and the second principal surface 4 arranged along c-planes of the SiC monocrystal. The first principal surface 3 is arranged along a silicon plane ((0001) plane) of the SiC monocrystal. The first principal surface 3 is a non-mounting surface. The second principal surface 4 is arranged along a carbon plane ((000-1) plane) of the SiC monocrystal. The first principal surface 3The second principal surface 4 can have an off-angle inclined at a predetermined angle in an off-direction with respect to the c-planes. The off-direction is preferably an a-axis direction ([11-20] direction) of the SiC monocrystal. If an off-angle exists, the c-axis (

[0001] direction) of the SiC monocrystal is inclined at an off-angle with respect to the normal direction Z.

[0013] The off-angle may exceed 0° and may not exceed 10°. The off-angle may not be less than 0° and not greater than 6°. The off-angle may not be less than 0° and not greater than 2°, not less than 2° and not greater than 4°, or not less than 4° and not greater than 6°. Preferably, the off-angle exceeds 0° and is not greater than 4.5°. The off-angle may not be less than 3° and not greater than 4.5°. In this case, the off-angle is preferably not less than 3° and not greater than 3.5°, or not less than 3.5° and not greater than 4°. The off-angle may not be less than 1.5° and not greater than 3°. In this case, the off-angle is preferably not less than 1.5° and not greater than 2° or not less than 2° and not greater than 2.5°.

[0014] The second main surface 4 can be formed from a rough surface that has either grinding marks and / or annealing marks (in particular laser irradiation marks). The annealing marks can contain amorphized SiC and / or a metal and silicidal (alloyed) SiC (in particular Si). The second main surface 4 is preferably composed of an ohmic surface that has at least annealing marks.

[0015] The first face 5A and the second face 5B extend along a first direction X and are opposite each other in a second direction Y, which intersects the first direction X (specifically, perpendicular to it). In a top view, the first face 5A and the second face 5B form short sides of the SiC semiconductor layer. 2The third face 5C and the fourth face 5D extend along the second direction Y and are opposite each other in the first direction X. In a top view, the third face 5C and the fourth face 5D form long sides of the SiC semiconductor layer. 2 .

[0016] In this embodiment, the first direction X is an m-axis direction ([1-100] direction) of the SiC monocrystal. The second direction Y is the a-axis direction ([11-20] direction) of the SiC monocrystal. That is, the first face 5A and the second face 5B are formed by a-planes of the SiC monocrystal and are opposite each other in the a-axis direction of the SiC monocrystal. The third face 5C and the fourth face 5D are formed by m-planes of the SiC monocrystal and are opposite each other in the m-axis direction of the SiC monocrystal. The lengths of the respective faces 5A to 5D are optionally not less than 0.1 mm and not greater than 10 mm. Preferably, the lengths of the respective faces 5A to 5D are not less than 0.5 mm and not greater than 2.5 mm.

[0017] The side surfaces 5A to 5D can be composed of cleavage surfaces or ground surfaces. In this embodiment, the side surfaces 5A to 5D are composed of a cleavage surface. The first side surface 5A and the second side surface 5B can form inclined surfaces which, when the normal direction Z is used as a basis, are inclined with respect to the normal direction Z towards the c-axis direction (

[0001] direction) of the SiC monocrystal.

[0018] The first face 5A and the second face 5B can be inclined at an angle according to the Off-Angle with respect to the normal direction Z when the normal direction Z is set to 0°. The angle according to the Off-Angle can be equal to the Off-Angle or it can be an angle greater than 0° and less than the Off-Angle. On the other hand, the third face 5C and the fourth face 5D extend as planes along the second direction Y (a-axis direction) and the normal direction Z. More precisely, the third face 5C and the fourth face 5D are essentially perpendicular to the first principal face. 3 and formed the second main area 4.

[0019] The SiC semiconductor layer 2 exhibits a drain region 6 of n + -type. A contamination concentration of drain region 6 of n-type may not be less than 1×10 18 cm -3 and not larger than 1×10 20cm -3 The drain region 6 is formed in a surface layer section of the second main surface 4 and forms the second main surface 4. In this embodiment, the drain region 6 is made of a SiC semiconductor substrate 7 of the n + -Type constructed.

[0020] The thickness of drain region 6 may be no less than 40 µm and no greater than 250 µm. Alternatively, the thickness of drain region 6 may be no less than 40 µm and no greater than 100 µm, no less than 100 µm and no greater than 150 µm, no less than 150 µm and no greater than 200 µm, or no less than 200 µm and no greater than 250 µm. Preferably, the thickness of drain region 6 is no less than 40 µm and no greater than 150 µm. By thinning drain region 6, its resistance value can be reduced.

[0021] The SiC semiconductor layer 2Drift region 8 exhibits an n-type contamination concentration. Drift region 8 has an n-type contamination concentration that is lower than the n-type contamination concentration of drain region 6. The n-type contamination concentration of drift region 8 may not be less than 1.0 × 10⁻⁶ 11 cm -3 and not larger than 1.0×10 11 cm -3 Drift region 8 is located in a surface layer section of the first main surface. 3 formed and forms the first main area 3 Drift region 8 is electrically connected to drain region 6. A boundary between drain region 6 and drift region 8 extends parallel to the first main surface. 3 In this embodiment, the drift region 8 is composed of an n-type SiC epitaxial layer 9 formed on the SiC semiconductor substrate 7.

[0022] The thickness of drift region 8 may be not less than 1 µm and not greater than 50 µm. The thickness of drift region 8 may be not less than 1 µm and not greater than 5 µm, not less than 5 µm and not greater than 10 µm, not less than 10 µm and not greater than 15 µm, not less than 15 µm and not greater than 20 µm, not less than 20 µm and not greater than 30 µm, not less than 30 µm and not greater than 40 µm, or not less than 40 µm and not greater than 50 µm. Preferably, the thickness of drift region 8 is not less than 5 µm and not greater than 15 µm.

[0023] In this embodiment, the drift region 8 has a plurality of regions with different n-type impurity concentrations along the normal direction Z. More precisely, the drift region 8 includes a high-concentration region 10 and a low-concentration region 11. The high-concentration region 10 has a comparatively high n-type impurity concentration and is located in a region on the side of the first main surface. 3 The low concentration region 11 has an n-type impurity concentration that is lower than the n-type impurity concentration of the high concentration region 10, and is formed in a region on the side of the second main surface 4 with respect to the high concentration region 10.

[0024] A peak value of the n-type impurity concentration in the high concentration region 10 may not be less than 1.0×10 11 cm -3and not larger than 1.0×10 11 cm -3 . A peak value of the n-type impurity concentration in the low-concentration region 11 may not be less than 1.0×10 . 11 cm -3 and not larger than 1.0×10 11 cm -3 The thickness of the low-concentration region 11 exceeds the thickness of the high-concentration region 10. That is, the thickness of the high-concentration region 10 is less than the thickness of the low-concentration region 11 and is less than half the total thickness of the drift region 8. It is understood that the drift region 8 can be formed with a uniform n-type impurity concentration.

[0025] The SiC semiconductor layer 2It features an active region 12 and an outer region 13. Active region 12 is a region in which a MISFET (metal-insulator-semiconductor field-effect transistor) is formed. In the top view, active region 12 is located in a central section of the SiC semiconductor layer. 2 The active region 12 is formed with inward intervals relative to the side surfaces 5A to 5D. In this embodiment, the active region 12 is formed in a four-sided shape (rectangular in this embodiment) with four sides that are parallel to the side surfaces 5A to 5D in plan view. The outer region 13 is located on an outer side of the active region 12. The outer region 13 is formed in a region between the side surfaces 5A to 5D and the circumferential edges of the active region 12. The outer region 13 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in plan view.

[0026] The SiC semiconductor device 1 incorporates a variety of trench-gate structures 18, which are located in the first main area 3 in active region 12. The multitude of trench-gate structures 18 are each formed as bands extending along the first direction X and spaced apart in the second direction Y. In a plan view, the multitude of trench-gate structures 18 appear as strips.

[0027] In this embodiment, the plurality of trench-gate structures 18 extend as bands from a circumferential edge section on one side (the side of the third side surface 5C) to a circumferential edge section on another side (the side of the fourth side surface 5D) of the active region 12. The plurality of trench-gate structures 18 cross an intermediate section of the active region 12 between the circumferential edge section on one side and the circumferential edge section on the other side.

[0028] The length of each trench-gate structure 18 may be not less than 1 mm and not greater than 10 mm. The length of each trench-gate structure 18 may be not less than 1 mm and not greater than 2 mm, not less than 2 mm and not greater than 4 mm, not less than 4 mm and not greater than 6 mm, not less than 6 mm and not greater than 8 mm, or not less than 8 mm and not greater than 10 mm. Preferably, the length of each trench-gate structure 18 is not less than 2 mm and not greater than 6 mm. The total extension per unit area of ​​a single trench-gate structure 18 may be not less than 0.5 µm / µm. 2 and not larger than 0.75 µm / µm 2 .

[0029] Each trench-gate structure 18 comprises an active trench section 19 and a contact trench section 20. The active trench section 19 is a section oriented along a channel of the MISFET. The contact trench section 20 is a section outside the channel of the MISFET. The contact trench section 20 is an end section of the trench-gate structure 18, and one of its main purposes is to provide an external connection.

[0030] Each trench-gate structure 18 includes a gate trench. 21 , a gate insulating layer 22 and a gate electrode 23 In Fig. 4 are the gate insulating layers. 22 and the gate electrodes 23 shown with hatching.

[0031] Each gate trench 21 It is formed in Drift Region 8. The Gate Trench 21It includes side walls and a bottom wall. The side walls form the long sides of the gate trench. 21 The structures formed are created by α-planes of the SiC monocrystal. The sidewalls, the short sides of the gate trench, 21 The m-planes of the SiC monocrystal are formed by these planes.

[0032] The side walls of the gate trench 21 can extend along the normal direction Z. In this case, the side walls of the gate trench can 21 essentially perpendicular to the first main surface 3 Angles forming the side walls of the gate trench 21 with regard to the first main area 3 within the SiC semiconductor layer 2 The angles formed must be no less than 90° and no greater than 95° (for example, no less than 91° and no greater than 93°). That is to say, the gate trench 21It can be formed in a conical or tapered shape, with an opening width extending from the first main surface. 3 narrows or becomes narrower towards the floor wall.

[0033] The bottom wall of the gate trench 21 It is located in high-concentration region 10. The bottom wall of the Gate Trench 21 is arranged along a c-plane of the SiC monocrystal. The bottom wall of the gate trench 21 exhibits an off-angle inclined in the [11-20] direction with respect to a (0001) plane of the SiC monocrystal. The bottom wall of the gate trench 21 can run parallel to the first main surface 3 be formed. The bottom wall of the gate trench 21 can be formed in a shape that curves towards the second main surface 4 or is curved in shape.

[0034] A width along the second direction Y of the gate trench 21The width of the gate trench is not less than 0.1 µm and not greater than 2 µm. 21 is possibly not smaller than 0.1 µm and not larger than 0.5 µm, not smaller than 0.5 µm and not larger than 1.0 µm, not smaller than 1.0 µm and not larger than 1.5 µm or not smaller than 1.5 µm and not larger than 2 µm.

[0035] The Gate Trench 21 has a first depth D1 The first depth D1 The first depth is possibly not smaller than 0.5 µm and not larger than 3.0 µm. D1 is possibly not less than 0.5 µm and not greater than 1.0 µm, not less than 1.0 µm and not greater than 1.5 µm, not less than 1.5 µm and not greater than 2.0 µm, not less than 2.0 µm and not greater than 2.5 µm or not less than 2.5 µm and not greater than 3.0 µm.

[0036] A section of the gate trench opening 21 includes an inclined section starting from the first main surface3 towards the inside of the gate trench 21 It slopes downwards. The opening edge section of the gate trench. 21 is a section that forms the first main area 3 and the side walls of the gate trench 21 connects. The inclined section of the gate trench 21 is shaped into a form that faces an inner side of the SiC semiconductor layer 2 It is curved. The inclined section of the gate trench 21 can be shaped into a form that faces the inner side of the gate trench 21 It is curved. The inclined section of the gate trench 21 relaxes a concentration of an electric field with respect to the opening edge section of the gate trench. 21 .

[0037] The gate insulating layer 22 It contains at least one type of material consisting of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 22It can have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The gate insulating layer 22 It can have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this embodiment, the gate insulating layer 22 a single-layer structure composed of a silicon oxide layer.

[0038] The gate insulating layer 22 is like a film along the inner walls of each gate trench 21 formed and delineates an excavation area within the gate trench 21 off. The gate insulating layer 22 It includes a first region 24, a second region 25, and a third region 26. The first region 24 is located along the side walls of the gate trench. 21 The second region, 25, is formed along the bottom wall of the gate trench. 21formed. The third region 26 is along the first main area. 3 educated.

[0039] The thickness of the first region 24 is less than the thickness of the second region 25 and the thickness of the third region 26. The thickness of the first region 24 is not less than 0.01 µm and not greater than 0.2 µm. The thickness of the second region 25 is not less than 0.05 µm and not greater than 0.5 µm. The thickness of the third region 26 is not less than 0.05 µm and not greater than 0.5 µm.

[0040] The gate insulating layer 22 includes a bulging section 27, which extends from the opening edge section towards an interior of the gate trench 21 The bulging section 27 is connected to a connecting section of the first region 24 and the third region 26 of the gate insulation layer. 22 The bulging section 27 is formed into a shape that extends towards the inner side of the gate trench. 21It is curved. The bulging section 27 narrows an opening of the gate trench. 21 at the opening edge section. A gate insulating layer. 22 A gate insulating layer can be formed that does not have the bulging section 27. 22 It can be formed with a uniform thickness.

[0041] Each gate electrode 23 is across the gate insulating layer 22 in the corresponding gate trench 21 embedded. More precisely, the gate electrode is 23 embedded in the extraction space located within the gate trench 21 through the gate insulating layer 22 The gate electrode is demarcated. 23 has an electrode surface located at the opening of the gate trench 21 exposed or exposed. The electrode surface of the gate electrode. 23 is formed into a curved shape that points towards the bottom wall of the gate trench. 21is excluded or recessed. The electrode surface of the gate electrode. 23 is through the bulging section 27 of the gate insulating layer 22 narrowed.

[0042] The gate electrode 23 It is made of a different conductive material than a metal. The gate electrode 23 is preferably made of conductive polysilicon. In this embodiment, the gate electrode includes 23 A p-type polysilicon doped with a p-type impurity. The p-type impurity concentration of the gate electrode 23 is possibly not smaller than 1×10 18 cm -3 and not larger than 1×10 22 cm -3 The p-type contamination of the gate electrode 23 It can contain at least one type of material made from boron, aluminum, indium, and gallium. A sheet resistor of the gate electrode. 23The resistance may be no less than 10 Ω / □ and no greater than 500 Ω / □ (approximately 200 Ω / □ in this embodiment). Gate electrode thickness 23 is possibly not smaller than 0.5 µm and not larger than 3 µm.

[0043] The SiC semiconductor component 1 includes a gate wiring 28 located in the active region 12 on the first main surface. 3 is educated. In Fig. Figure 4 shows the gate wiring 28 with hatching. More precisely, the gate wiring 28 is located on the third regions 26 of the gate insulating layers. 22 The gate wiring 28 is formed along the first side surface 5A, the third side surface 5C and the fourth side surface 5D in the active region 12 and delimits a region from three directions within which the multitude of trench-gate structures 18 are formed.

[0044] The gate wiring 28 is connected to the gate electrode. 23connected, which is exposed opposite the contact trench section 20 of each trench-gate structure 18. In this embodiment, the gate wiring 28 is connected by lead-out portions of the gate electrodes. 23 formed by the respective gate trenches 21 on the first main area 3 are brought out. One electrode surface of the gate wiring 28 is connected to the electrode surfaces of the gate electrodes. 23 tied together.

[0045] The SiC semiconductor component 1 has a first low-resistance layer 29, which connects the gate electrodes 23 covered. The first low-resistance layer 29 contains a conductive material that has a layer resistance lower than the layer resistance of the gate electrodes. 23The film resistance of the first low-resistance layer 29 is optionally not less than 0.01 Ω / □ and not greater than 10 Ω / □. The thickness of the first low-resistance layer 29 in the normal direction Z of the first low-resistance layer 29 is preferably less than the thickness of the gate electrodes. 23 The thickness of the first low-resistance layer 29 may be no less than 0.01 µm and no greater than 3 µm.

[0046] The first low-resistance layer 29 covers the gate electrodes. 23 within the gate trenches 21 The first low-resistance layer 29 forms a section of each trench-gate structure 18. The first low-resistance layer 29 also covers the gate wiring 28. A section of the first low-resistance layer 29 covering the gate wiring 28 is integrally formed with sections of the first low-resistance layer 29 that cover the gate electrodes. 23cover. The first low-resistance layer 29 thereby covers the entire area or entire surface areas of the gate electrodes. 23 and an entire area or area of ​​the gate wiring 28.

[0047] More precisely, the first low-resistance layer 29 contains a polycide layer. The polycide layer consists of a single layer in which planar sections of the gate electrodes 23 and a surface layer section of the gate wiring 28 is silicidicated by a metallic material. That is, the polycid layer is composed of a p-type polycid layer containing a p-type impurity that is incorporated into the gate electrodes. 23 (p-type polysilicon) and the gate wiring 28 (p-type polysilicon) is doped. Furthermore, the electrode surfaces of the gate electrodes are 23and the electrode surface of the gate wiring 28 is formed by the first low-resistance layer 29. The polycid layer preferably has a resistivity of not less than 10 µΩ·cm and not more than 110 µΩ·cm.

[0048] A layer resistor within the gate trenches 21 , in which the gate electrodes 23 and the first low-resistance layer 29 is embedded, is not greater than the layer resistance of the gate electrodes 23 alone. The layer resistance inside the gate trenches 21 is preferably not greater than the layer resistance of an n-type polysilicon doped with an n-type impurity. The layer resistance inside the gate grooves 21 is approximated by the layer resistance of the first low-resistance layer 29. The layer resistance inside the gate trenches 21The film resistance inside the gate grooves is possibly not less than 0.01 Ω / □ and not greater than 10 Ω / □. 21 is preferably less than 10 Ω / □.

[0049] The first low-resistance layer 29 can comprise at least one type of material from TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these types of materials, NiSi, CoSi2, and TiSi2 are particularly suitable as the polycid layer forming the first low-resistance layer 29 because they have a comparatively low resistivity and a comparatively low temperature dependence. The first low-resistance layer 29 is most preferably composed of CoSi2, which has the property of exhibiting low diffusion to other regions.

[0050] The first low-resistance layer 29 includes contact sections in contact with the gate insulating layers. 22More precisely, the contact sections of the first low-resistance layer 29 contact the third regions 26 (bulging sections 27) of the gate insulating layers. 22 A current path between the first low-resistance layer 29 and the drift region 8 can be suppressed thereby. In particular, a design to reduce the risk of a current path is effective in which the contact sections of the first low-resistance layer 29 are connected with comparatively thick corner or edge sections of the gate insulating layers. 22 are connected.

[0051] By embedding a p-type polysilicon that has a work function that differs from an n-type polysilicon in the gate trenches 21By differentiating between different materials, the gate threshold voltage Vth can be increased by approximately 1 V. However, p-type polysilicon has a film resistance that is several tens of times (approximately 20 times) higher than that of n-type polysilicon. Therefore, if p-type polysilicon is used as the gate electrode material... 23 When applied, energy loss increases, accompanied by an increase in parasitic resistance inside the gate trenches. 21 (hereinafter referred to simply as the "gate resistor").

[0052] In the SiC semiconductor component 1, the first low-resistance layer 29 (p-type polycide) is therefore located on the gate electrodes. 23 (p-type polysilicon) is formed. The first low-resistance layer 29 reduces the layer resistance inside the gate grooves. 21The resistance can be reduced while allowing an increase in the gate threshold voltage Vth. For example, in the structure with the first low-resistance layer 29, the layer resistance can be reduced to no more than 1 / 100th compared to a structure lacking the first low-resistance layer 29. Furthermore, in the structure with the first low-resistance layer 29, the layer resistance can be reduced to no more than 1 / 5th compared to the gate electrodes. 23 , which contain n-type polysilicon.

[0053] This reduces the gate resistance, allowing current to be efficiently spread or conducted ("diffused") along the trench-gate structures 18. That is, the first low-resistance layer 29 acts as a current diffusion layer, directing the current inside the gate trenches. 21spreads or conducts ("diffuses"). Although for the transmission of electricity via the gate trenches 21 Since the switching time required for the components, which have a length on the millimeter scale (a length of not less than 1 mm), can be suitably suppressed by the low-resistance electrode layer 29. Furthermore, in the structure with the first low-resistance layer 29, the p-type impurity concentration inside the drift region 8 does not need to be increased to raise the gate threshold voltage Vth. The gate threshold voltage Vth can thus be suitably increased while an increase in channel resistance is suppressed.

[0054] The SiC semiconductor device 1 comprises a plurality of trench-source structures 30, each formed in regions between adjacent plurality of trench-gate structures 18. The plurality of trench-source structures 30 are spaced apart in the second direction Y, in a sandwich-like arrangement around a single trench-gate structure 18. The plurality of trench-source structures 30 are each formed as a band extending along the first direction X. In a plan view, the plurality of trench-source structures 30 appear as strips.

[0055] A gap (“pitch”) PS in the second direction Y between central sections of adjacent trench-source structures 30 may be no less than 1 µm and no greater than 5 µm. The gap PS may be no less than 1 µm and no greater than 2 µm, no less than 2 µm and no greater than 3 µm, no less than 3 µm and no greater than 4 µm, or no less than 4 µm and no greater than 5 µm. The gap PS is preferably no less than 1.5 µm and no greater than 3 µm.

[0056] Each trench-source structure 30 has a source trench. 31 , a source insulating layer 32 and a source electrode 33 up. In Fig. 4 are the source insulating layers 32 and the source electrodes 33 shown by hatching. Each source trench 31 It is formed in Drift Region 8. The Source Trench 31It includes side walls and a bottom wall. The side walls form the long sides of the source trench. 31 The α-planes of the SiC monocrystal are formed by these planes. The sidewalls, the short sides of the source trench, 31 The m-planes of the SiC monocrystal are formed by these planes.

[0057] The bottom walls of the Source trenches 31 are positioned in high concentration region 10. The bottom walls of the source trenches 31 are arranged along a c-plane of the SiC monocrystal. The bottom walls of the source trench(s) 31 have an off-angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC monocrystal. The bottom walls of the source trenches 31 can parallel to the first main area 3 be formed. The bottom walls of the source trenches 31 Each can be formed into a shape that is curved towards the second main surface 4.

[0058] The bottom walls of the Source trenches 31 are in regions on the side of the second main area 4 in relation to the bottom walls of the gate trenches 21 positioned. The bottom walls of the source trenches 31 are with respect to the normal direction Z in regions between the bottom walls of the gate trenches 21 and positioned in low-concentration region 11. That is, the source trenches 31 have a second depth D2 , which is the first depth D1 the gate trenches 21 exceeds. Provided that the source trenches 31 located inside the high concentration region 10, there is a DS / DG or D2 / D1 ratio of the second depth. D2 with regard to the first depth D1 Possibly not less than 1.5. The ratio DS / DG or D2 / D1 is preferably not less than 2 .

[0059] The second depth D2The second depth is possibly not smaller than 0.5 µm and not larger than 10 µm. D2 is possibly not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, not less than 4 µm and not greater than 6 µm, not less than 6 µm and not greater than 8 µm, or not less than 8 µm and not greater than 10 µm. It is understood that the source trenches 31 so that the second depth D2 essentially the same as the first depth D1 is.

[0060] In this embodiment, each source trench includes 31 a first section of the trench 34 and a second trench section 35 The first section of the trench 34 is located on one side of the Source Trench opening 31 formed. The first section of the trench 34 has a first width W1in the second direction Y. The first trench section 34 It can be formed in a tapered or conical shape, with the first width being W1 starting from the first main area 3 The first section of the trench narrows or becomes narrower towards the side of the bottom wall. 34 can be used as a first trench section 34 be formed, which forms the bottom walls of the gate trenches 21 in the normal direction Z crosses (“traverses”). That is, a depth of the first trench section. 34 can the first depth D1 the gate trenches 21 exceed.

[0061] The first section of the trench 34 is preferably located in a region on the side of the first main area 3 with regard to the bottom walls of the gate trenches 21 formed. That is, the depth of the first trench section. 34 is preferably smaller than the first depth D1 the gate trenches 21The depth of the first trench section 34 The depth of the first trench section is possibly not less than 0.1 µm and not greater than 2 µm. 34 is possibly not smaller than 0.1 µm and not larger than 0.5 µm, not smaller than 0.5 µm and not larger than 1 µm, not smaller than 1 µm and not larger than 1.5 µm, or not smaller than 1.5 µm and not larger than 2 µm.

[0062] The first width W1 of the first trench section 34 is possibly no smaller than the width of the gate trenches 21 or may be smaller than the width of the gate trenches 21 be. The first width W1 preferably exceeds the width of the gate trenches 21 The first width W1 The first width is possibly not smaller than 0.1 µm and not larger than 2 µm. W1is possibly not smaller than 0.1 µm and not larger than 0.5 µm, not smaller than 0.5 µm and not larger than 1 µm, not smaller than 1 µm and not larger than 1.5 µm, or not smaller than 1.5 µm and not larger than 2 µm.

[0063] The second section of the trench 35 is on the side of the bottom wall of the Source Trench 31 formed. In the normal direction Z, the second trench section is 35 in a region between the first trench section 34 and formed a bottom section of Drift Region 8 and crosses the bottom walls of the Gate trenches 21 In the normal direction Z, the depth of the second trench section exceeds 35 based on the first section of the trench 34 preferably the first depth D1 the gate trenches 21 .

[0064] The second section of the trench 35 has a second width in the second direction Y W2, which is smaller than the first width W1 Provided that it is smaller than the first width W1 , is the second width W2 possibly not smaller than the width of the gate trenches 21 or possibly smaller than the width of the gate trenches 21 The second width W2 The second width is possibly not smaller than 0.1 µm and smaller than 2 µm. W2 The second width is possibly not smaller than 0.1 µm and smaller than 2 µm. W2 is possibly not less than 0.1 µm and not greater than 0.5 µm, not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 1.5 µm, or not less than 1.5 µm and less than 2 µm. It is understood that the second trench section 35 with the second width W2 can be formed which are essentially equal to the first width W1 is.

[0065] The opening width of the source trench 31, which forms the first section of the trench 34 and the second section of the trench 35 It includes, is preferably shaped so that it is approximately the same as the opening width of the gate trenches. 21 The information regarding the opening width of the source trench 31 approximately the same as the opening width of the gate trenches 21 , refers to the opening width of the source trench 31 into a range of ±20% of the opening width or into a range of the opening width of the gate trenches 21 It falls by ±20%.

[0066] Side walls of the second trench section 35 They can extend along the normal direction Z. Angles that define the side walls of the second trench section 35 with regard to the first main area 3 within the SiC semiconductor layer 2The angles formed may be no less than 90° and no greater than 95° (for example, no less than 91° and no greater than 93°). The side walls of the second trench section 35 can be essentially perpendicular to the first main surface 3 be formed. The second section of the trench 35 can be formed in a tapered shape, with the second width W2 starting from the first section of the trench 34 towards the side of the floor wall, narrowing or becoming narrower.

[0067] Each source insulating layer 32 It contains at least one type of material made of silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. The source insulating layer 32 It can have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The source insulating layer 32It can have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this embodiment, the source insulating layer has 32 a single-layer structure composed of a silicon oxide layer.

[0068] The source insulating layer 32 is as a film along the inner walls of the corresponding source trench 31 formed and delineates an excavation area within the source trench 31 off. More precisely, the source insulating layer 32 as a film along the inner walls of the second trench section 35 formed, such that the first section of the trench 34 is exposed. This has exposed the source insulating layer. 32 a side wall window section 36 , which forms the first section of the trench 34 exposes and the excavation area within the second trench section 35 distinguishes itself.

[0069] The source insulating layer 32 It includes a first region 37 and a second region 38. The first region 37 is located along the side walls of the Source Trench. 31 formed. The second region 38 is along the bottom wall of the Source Trench. 31 formed. The thickness of the first region 37 is less than the thickness of the second region 38. The thickness of the first region 37 may be no less than 0.01 µm and no greater than 0.2 µm. The thickness of the second region 38 may be no less than 0.05 µm and no greater than 0.5 µm. The thickness of the first region 37 can be essentially equal to the thickness of the first regions 37 or 24 of the gate insulating layers. 22 The thickness of the second region 38 can be essentially equal to the thickness of the second regions 38 or 25 of the gate insulating layers. 22 be. The source insulating layers 32 , which each have a uniform thickness, can be formed.

[0070] Each source electrode 33 is via the source insulating layer 32 into the corresponding source trench 31 embedded. More precisely, the source electrode is 33 into the first section of the trench 34 and the second section of the trench 35 of the Source Trench 31 embedded, specifically via the source insulating layer 32 The source electrode 33 is embedded in the excavation space, which is formed by the second trench section 35 on the side of the bottom wall of the Source Trench 31 is delimited. The source electrode 33 has a side wall contact section 39 in contact with the side walls of the first trench section 34 , which are located at the opening side of the Source Trench 31 opposite the side wall window section 36 are exposed.

[0071] The source electrode 33has an electrode surface that faces the opening of the source trench. 31 is exposed. The electrode surface of the source electrode. 33 is formed into a curved shape that points towards the bottom wall of the Source trench. 31 is excluded or recessed. The electrode surface of the source electrode. 33 can run parallel to the first main surface 3 be educated.

[0072] The thickness of the source electrode 33 In the normal direction Z, the thickness may be no less than 0.5 µm and no greater than 10 µm. The thickness of the source electrode 33 is possibly not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, not less than 4 µm and not greater than 6 µm, not less than 6 µm and not greater than 8 µm or not less than 8 µm and not greater than 10 µm.

[0073] The source electrode 33It is made of a different conductive material than a metal. The source electrode 33 is preferably made of conductive polysilicon. In this embodiment, the source electrode includes 33 A p-type polysilicon doped with a p-type impurity. The p-type impurity concentration of the source electrode 33 is possibly not smaller than 1×10 18 cm -3 and not larger than 1×10 22 cm -3 The p-type impurity concentration of the source electrode 33 is preferably equal to the p-type impurity concentration of the gate electrode 23 That is, a layer resistance of the source electrode. 33 The resistance may be no less than 10 Ω / □ and no greater than 500 Ω / □ (approximately 200 Ω / □ in this embodiment). The p-type impurity of the source electrode 33may contain at least one type of material made from boron, aluminum, indium and gallium.

[0074] The SiC semiconductor component 1 has second low-resistance layers 40, each of which has a source electrode 33 cover. Every second low-resistance layer 40 covers the source electrode. 33 within the corresponding source trench 31 The second low-resistance layer 40 forms a section of the corresponding trench-source structure 30. The second low-resistance layer 40 comprises a conductive material that has a layer resistance lower than the layer resistance of the source electrode. 33 The film resistance of the second low-resistance layer 40 is optionally not less than 0.01 Ω / □ and not greater than 10 Ω / □. The thickness of the second low-resistance layer 40 in the normal direction Z is preferably less than the thickness of the source electrode. 33The thickness of the second low-resistance layer 40 may be no less than 0.01 µm and no greater than 3 µm.

[0075] More precisely, the second low-resistance layer 40 contains a polycid layer. The polycid layer is composed of a layer in which a surface layer section of the source electrode 33 is silicified by a metal material. That is, the polycid layer is composed of a p-type polycid layer containing the p-type impurity that is introduced into the source electrode. 33 is doped. Furthermore, the electrode surface of the source electrode is 33 formed by the second low-resistance layer 40. The polycid layer preferably has a resistivity of not less than 10 µΩ·cm and not greater than 110 µΩ·cm.

[0076] A layered resistance inside the source trench 31 , in which the source electrode 33and the second low-resistance layer 40 are embedded, is not greater than the layer resistance of the source electrode 33 alone. The layer resistance inside the Source Trench 31 is preferably not greater than the layer resistance of an n-type polysilicon doped with an n-type impurity. The layer resistance inside the source trench 31 is approximated by the layer resistance of the second low-resistance layer 40. The layer resistance inside the source trench 31 The film resistance inside the source trench is possibly not less than 0.01 Ω / □ and not greater than 10 Ω / □. 31 is preferably less than 10 Ω / □.

[0077] The second low-resistance layer 40 can contain at least one type of material from TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these types of materials, NiSi, CoSi2, and TiSi2 are particularly suitable as the polycid layer forming the second low-resistance layer 40 because they have a comparatively low resistivity and low temperature dependence. The second low-resistance layer 40 is most preferably composed of CoSi2, which has the property of low diffusion into other regions. The second low-resistance layer 40 is preferably composed of the same conductive material as the first low-resistance layer 29.

[0078] The SiC semiconductor component 1 includes a body region 41 of the p-type, located in a surface layer section of the first main surface 3 is formed in active region 12. The body region41 defines the active region 12. A p-type contamination concentration of the body region 41 is smaller than the p-type impurity concentration of the gate electrodes 23 The p-type contamination concentration of the body region 41 is smaller than the p-type impurity concentration of the source electrodes 33 A peak value of the p-type contamination concentration in the body region 41 is possibly not smaller than 1.0×10 17 cm -3 and not larger than 1.0×10 19 cm -3 .

[0079] In the surface layer section of the first main surface 3 covers the body region 41 the side walls of the gate trenches 21 and the side walls of the source trenches 31 The body region 41 is in a region on the side of the first main area 3 with regard to the bottom walls of the gate trenches 21formed. The body region 41 lies with the gate electrodes 23 via the gate insulating layers 22 opposite.

[0080] The body region 41 is also found in regions on the side of the first trench section 34 with regard to the second trench sections 35 the Source trenches 31 formed. The body region 41 covers the first sections of the trench 34 the Source trenches 31 More precisely, the body region 41 is with the side wall contact sections 39 the source electrodes 33 connected, opposite or at the first trench sections 34 the Source trenches 31 are exposed. The body region 41 is source-grounded, specifically within the SiC semiconductor layer 2 The body region 41 can sections of the second trench sections 35cover. In this case, the body region 41 the source electrodes 33 over sections of the source insulating layers 32 opposite each other.

[0081] The SiC semiconductor component 1 contains source regions. 42 from n + -Type, which is found in surface layer sections of the body region 41 are formed. The source regions 42 are at intervals from the contact trench sections 20 of the gate trenches 21 and along the active trench sections 19 of the Gate trenches 21 formed. A peak value of an n-type impurity concentration of the source regions. 42 exceeds the peak n-type impurity concentration of high concentration region 10. The peak n-type impurity concentration of the source regions 42 is possibly not smaller than 1.0×10 18 cm -3 and not larger than 1.0×10 21 cm -3 .

[0082] In the surface layer sections of the body region 41 cover the source regions 42 the side walls of the gate trenches 21 and the side walls of the source trenches 31 The source regions 42 lie at the gate electrodes 23 via the gate insulating layers 22 opposite. The source regions 42 The first low-resistance layer 29 is preferably located above the gate insulating layers. 22 opposite.

[0083] The source regions 42 are also found in regions on the side of the first trench section 34 with regard to the second trench sections 35 the Source trenches 31 formed. The source regions 42 cover the first sections of the trench 34 the Source trenches 31 The source regions 42 are connected to the side wall contact sections 39 the source electrodes 33connected, which are located at the first sections of the trench 34 the Source trenches 31 are exposed. The source regions 42 This makes them source-grounded within the SiC semiconductor layer. 2 .

[0084] Sections of the source regions 42 , which run along the side walls of the gate trenches 21 are oriented, define the channels of the MISFET, together with the high concentration region 10 within the body region 41 The channels are switched ON / OFF by the gate electrodes. 23 controlled.

[0085] The SiC semiconductor component 1 includes a multitude of contact regions 43vom p + -Type, which are in surface layer sections of the first main surface 3 in active region 12. A peak value of a p-type impurity concentration from each contact region. 43 exceeds the p-type contamination concentration of the body region41 The peak p-type impurity concentration from each contact region 43 is possibly not smaller than 1.0×10 18 cm -3 and not larger than 1.0×10 21 cm -3 .

[0086] The multitude of contact regions 43 are each formed in regions that run along the multitude of source trenches 31 are oriented. More precisely, a large number of contact regions. 43 in a relationship of a some-to-one correspondence with respect to a corresponding single source trench 31 formed. The multitude of contact regions 43 are each spaced along the respective individual source trench. 31 formed. The multitude of contact regions 43 are each spaced apart from the gate trenches 21 educated.

[0087] Each contact region 43 covers the first section of the trench 34of the corresponding source trench 31 Each contact region 43 is between the side wall contact section 39 the source electrode 33 and the source regions 42 on the first section of the trench 34 of the corresponding source trench 31 arranged. Furthermore, each contact region 43 between the side wall contact section 39 the source electrode 33 and the body region 41 on the first section of the trench 34 of the corresponding source trench 31 arranged.

[0088] Each contact region 43 This is within the SiC semiconductor layer 2 Source-grounded. Furthermore, every contact region is 43 electrically with the source electrode 33 , the body region 41 and the source regions 42 within the SiC semiconductor layer 2 tied together.

[0089] Sections of each contact region 43 , which comprise the first section of the trench 34 cover, are towards the gate trenches 21 led out. The sections from each contact region 43 , which comprise the first section of the trench 34 of the Source Trench 31 cover, are in regions on the side of the first main area 3 in relation to a floor section of the body region 41 formed. The sections of each contact region 43 , which comprise the first section of the trench 34 cover, can extend to intermediate regions between the gate trenches 21 and the Source Trench 31 extend.

[0090] Each contact region 43 Furthermore, it covers the second section of the trench. 35 of the corresponding source trench 31 . On the second section of the trench 35 of the corresponding source trench 31 Each contact region is located 43 the source electrode33 via the source insulating layer 32 opposite. Each contact region 43 furthermore covers the bottom wall of the corresponding source trench. 31 Each contact region 43 The source electrode is located 33 via the bottom wall of the corresponding source trench 31 opposite. A ground section from each contact region 43 can run parallel to the bottom wall of the corresponding source trench 31 be educated.

[0091] The SiC semiconductor component 1 contains a multitude of deep well regions. 44 of the p-type, which are in surface layer sections of the first main surface 3 are formed in active region 12. A peak value of a p-type impurity concentration from each deep-well region. 44 is smaller than the peak value of the p-type contamination concentration of the contact regions 43The peak p-type impurity concentration from each deep-tub region 44 is possibly not smaller than the peak value of the p-type contamination concentration of the body region 41 or is possibly smaller than the peak value of the p-type contamination concentration of the body region 41 The peak p-type impurity concentration from each deep-tub region 44 is possibly not smaller than 1.0×10 17 cm -3 and not larger than 1.0×10 19 cm -3 .

[0092] The multitude of deep-water regions 44 are in a one-to-one correspondence relationship with regard to the multitude of source trenches 31 formed. Every deep-trough region 44 is formed as a band that, in a top view, extends along the corresponding source trench. 31 extends. Each deep-tub region 44is formed in high-concentration region 10. Each deep-trough region 44 is in a region on the side of the second main surface 4 in relation to the body region 41 formed. Every deep-trough region 44 is continuously formed or directly adjacent to the body region 41 trained.

[0093] Each deep-trough region 44 includes a section that comprises the second trench section 35 of the corresponding source trench 31 covered. Every deep-trough region 44 includes sections that comprise the second trench section 35 of the corresponding source trench 31 cover, specifically across the contact regions 43 . Each deep-trough region 44 It also includes a section that forms the bottom wall of the corresponding source trench. 31 covered. Every deep-trough region 44 includes sections that form the bottom wall of the corresponding source trench31 via the contact regions 43 covered.

[0094] Each deep-trough region 44 has a floor section that is on the side of the second main area 4 in relation to the floor walls of the gate trenches 21 is positioned. The bottom section of each deep-trough region 44 can run parallel to the bottom wall from any source trench 31 be educated. The multitude of deep-trough regions 44 They are preferably formed such that they have a constant depth. Each deep basin region forms a pn transition zone with the high concentration region 10. From the pn transition zones, depletion layers extend towards the gate trenches. 21 The depletion layers can be compared with the bottom walls of the gate ditches. 21 overlap.

[0095] The SiC semiconductor component 1 includes a multitude of circumferential edge trough regions 45 of the p-type, which are located in surface layer sections of the first main surface. 3 at the peripheral edge sections of the active region 12. A peak value of a p-type impurity concentration from each peripheral edge basin region 45 is lower than the peak value of the p-type impurity concentration of the contact regions. 43 .

[0096] The peak p-type contamination concentration of each peripheral rim basin region 45 may not be less than the peak p-type contamination concentration of the body region. 41 or is possibly smaller than the peak value of the p-type contamination concentration of the body region 41 The peak value of the p-type impurity concentration from each peripheral rim basin region 45 may not be less than 1.0 × 10 17 cm -3 and not larger than 1.0×10 19 cm-3 The p-type contamination concentration of the peripheral rim basin regions 45 is preferably essentially equal to the p-type contamination concentration of the deep basin regions. 44 .

[0097] The circumferential trough regions 45 are formed in a plurality in a one-to-one correspondence with respect to the plurality of trench-gate structures 18. The circumferential trough regions 45 cover the contact trench sections 20 and expose the active trench sections 19 of the corresponding trench-gate structures 18. The circumferential trough regions 45 cover the sidewalls and the bottom walls of the gate trenches. 21 at the corresponding contact trench sections 20. Soil sections of the circumferential edge basin regions 45 are on the side of the first main area 3 with regard to the bottom walls of the deep-tank regions 44 The respective circumferential rim basin regions 45 are electrically connected to the body region.41 and the deep-trough regions 44 tied together.

[0098] In a SiC semiconductor component containing only a pn junction diode, the lack of grooves in the structure leads to a problem of electric field concentration inside the SiC semiconductor layer. 2 not frequently. The respective deep-trough regions 44 This causes the trench-gate MISFET to approximate the structure of a pn junction diode. The electric field within the SiC semiconductor layer 2 This allows the MISFET to be relaxed ("relaxed").

[0099] In the deep-trough regions 44 , which define the ground sections on the side of the second main area 4 in relation to the ground walls of the gate trenches 21 Furthermore, a concentration of an electric field with respect to the gate trenches can occur. 21Suitable for relaxing the depletion layers. A narrowing or narrowing of the space PS between adjacent source trenches of the multitude. 31 (deep basin regions) 44 ) is effective in terms of reducing the concentration of the electric field and improving withstand voltage.

[0100] The multitude of deep-water regions 44 They are preferably formed to have a constant depth. This can suppress the withstanding voltage (e.g., electrostatic breakdown strength) of the SiC semiconductor layer. 2 through the respective deep-trough regions 44 This is restricted, and consequently an improvement in standing stress can be appropriately achieved. The circumferential edge trough regions 45 show the same effects as the deep trough regions. 44 .

[0101] By using the source trenches 31 can the deep-trough regions 44 suitable for use in relatively deep regions of the SiC semiconductor layer 2 They can be formed. The deep-trough regions can also be formed. 44 along the Source ditches 31 can be formed and consequently the occurrence of a variation in the depth of the multitude of deep-trough regions can occur. 44 be appropriately suppressed.

[0102] Furthermore, in this embodiment, sections of the high-concentration region 10 are located in regions between adjacent multiple deep-trough regions. 44 arranged. This allows a JFET (junction field-effect transistor) resistor to be placed in the regions between the adjacent multiple deep-well regions. 44 be reduced.

[0103] Furthermore, in this embodiment, the bottom sections of the respective deep-trough regions are 44positioned in the high-concentration region 10. This allows current paths in lateral directions parallel to the first main surface. 3 in regions of high concentration region 10 directly below the respective deep basin regions 44 are formed. Consequently, the current spreading resistance can be reduced. The low-concentration region 11 increases the withstand voltage of the SiC semiconductor layer. 2 in such a structure.

[0104] With reference to Fig. 10 has the active region 12 an active main area 51, which is a section of the first main area 3 The active principal surface 51 and an outer principal surface 52 are each arranged along c-planes of the SiC monocrystal. The active principal surface 51 and the outer principal surface 52 each have off-angles inclined in the [11-20] direction with respect to the (0001) plane of the SiC monocrystal.

[0105] The outer region 13 features the outer main area 52, which is a section of the first main area 3 The outer main surface 52 is connected to the side surfaces 5A to 5D. The outer region 13 is formed by digging into the drift region 8 (SiC epitaxial layer 9) in the direction of the side of the second main surface 4. The outer main surface 52 is thus formed in a region that is excluded or set back from the active main surface 51 towards the side of the second main surface 4. The main surface 52 is connected to the bottom walls of the gate trenches. 21 preferably positioned on the side of the second main surface 4.

[0106] In this embodiment, the outer main surface 52 is formed at a depth position that is essentially the same as that of the bottom walls of the respective source trenches. 31The outer main surface 52 is essentially on the same plane as the bottom walls of the respective source trenches. 31 The outer main surface 52 can be positioned within a range of not less than 0 µm and not more than 1 µm towards the side of the second main surface 4, in relation to the bottom walls of the respective source trenches. 31 The outer main surface 52 exposes the high concentration region 10.

[0107] In this embodiment, the active region 12 is formed as an active mesa 53, which is delimited into a mesa shape by the outer region 13. The active mesa 53 projects upwards from the outer main surface 52. The active mesa 53 includes active side walls 54 that connect the active main surface 51 and the outer main surface 52. The active side walls 54 define a boundary region between the active region 12 and the outer region 13. The first main surface 3is formed by the active main surface 51, the outer main surface 52 and the active side walls 54.

[0108] In this embodiment, the active sidewalls 54 extend along the normal direction Z towards the active main surface 51 (outer main surface 52). The active sidewalls 54 are formed by m-planes and a-planes of the SiC monocrystal. The active sidewalls 54 can have inclined surfaces that slope downwards from the active main surface 51 towards the outer main surface 52. The active sidewalls 54 expose the high-concentration region 10. The active sidewalls 54 can 41 uncover.

[0109] The SiC semiconductor component 1 includes a diode region 55 from p +-type, which is formed in a surface layer section of the outer main surface 52. A peak value of a p-type impurity concentration of the diode region 55 exceeds the peak value of the p-type impurity concentration of the body region. 41 The peak value of the p-type impurity concentration in diode region 55 may not be less than 1.0 × 10 18 cm -3 and not larger than 1.0×10 21 cm -3 The peak p-type impurity concentration of diode region 55 can be essentially equal to the peak p-type impurity concentration of the contact regions. 43 be.

[0110] Diode region 55 is formed in the high-concentration region 10. Diode region 55 is located in a region between the active sidewalls 54 and the side surfaces 5A to 5D. Diode region 55 is formed at intervals from the active sidewalls 54 and the side surfaces 5A to 5D. Diode region 55 extends as a band along the active region 12 in a top view. In this embodiment, diode region 55 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in a top view.

[0111] Diode region 55 is located in relation to the bottom walls of the gate trenches. 21 positioned on the side of the second main surface 4. A soil section of diode region 55 is located in relation to the soil walls of the respective source trenches. 31positioned on the side of the second main surface 4. The bottom section of the diode region 55 can be formed at a depth position that is essentially the same as that of the bottom sections of the contact regions. 43 is.

[0112] The bottom section of diode region 55 can be essentially located on the same plane as the bottom sections of the contact regions. 43 The base section of diode region 55 can be positioned relative to the base sections of the contact regions. 43 The base section of diode region 55 can be positioned on the side of the second main surface 4. The base section of diode region 55 can be positioned within a range of not less than 0 µm and not more than 1 µm towards the side of the second main surface 4, relative to the base sections of the contact regions. 43 .

[0113] Diode region 55 forms a pn junction, together with high concentration region 10. This forms a pn junction diode, which has diode region 55 as an anode and high concentration region 10 as a cathode.

[0114] The SiC semiconductor device 1 includes an outer p-type well region 56, which is formed in a surface layer section of the outer main surface 52. A peak value of a p-type impurity concentration in the outer well region 56 may be no less than 1.0 × 10⁻⁶ 17 cm -3 and not larger than 1.0×10 19 cm -3The peak p-type impurity concentration of the outer trough region 56 may be lower than the peak p-type impurity concentration of the diode region 55. The peak p-type impurity concentration of the outer trough region 56 may be substantially equal to the peak p-type impurity concentration of the deep trough regions. 44 be.

[0115] The outer basin region 56 is formed in a top view in a region between the active side walls 54 and the diode region 55. The outer basin region 56 extends as a band along the active region 12. In this embodiment, the outer basin region 56 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in a top view.

[0116] The outer basin region 56 is formed in the high concentration region 10. The outer basin region 56 is located in relation to the bottom walls of the gate trenches. 21 positioned on the side of the second main surface 4. A floor section of the outer basin region 56 is in relation to the floor walls of the respective source trenches. 31 The bottom section of the outer trough region 56 is positioned on the side of the second main surface 4 with respect to the bottom section of the diode region 55. The bottom section of the outer trough region 56 can be formed at a depth position that is essentially the same as that of the bottom sections of the deep trough regions. 44 is.

[0117] The inner circumferential edges of the outer tub region 56 cover corner or edge sections that connect the active side walls 54 and the outer main surface 52. The inner circumferential edges of the outer tub region 56 also extend along the active side walls 54 and are connected to the body region. 41 connected. The inner circumferential edges of the outer basin region 56 can be formed with distances from the active side walls 54 towards the side of the diode region 55.

[0118] The outer circumferential edges of the outer well region 56 cover the diode region 55, extending from the side of the second main surface 4. The outer well region 56 is electrically connected to the diode region 55. The outer well region 56 forms a pn junction section of the diode. The outer circumferential edges of the outer well region 56 can be formed at distances from the diode region 55 to the sides of the active side wall 54.

[0119] The SiC semiconductor component 1 includes a field-limiting structure (FL structure) 57, which is formed in a surface layer section of the outer main surface 52. In a top view, the FL structure 57 is located in a region between the diode region 55 and the side surfaces 5A to 5D. In this embodiment, the FL structure 57 is positioned at intervals from the side surfaces 5A to 5D towards the side of the diode region 55. The FL structure 57 is located in the high-concentration region 10.

[0120] The FL structure 57 includes one or a plurality (for example, not fewer than two and not more than 20) p-type FL regions 58 (field limiting regions). In this embodiment, the FL structure 57 includes a group of FL regions comprising five FL regions 58A, 58B, 58C, 58D, and 58E. The FL regions 58A to 58E are arranged along a direction away from the diode region 55 in this order, spaced apart from each other.

[0121] FL regions 58A to 58E each extend as bands along the perimeter of active region 12 in a plan view. More precisely, FL regions 58A to 58E are each formed in ring shapes (more accurately, continuous shapes) that surround active region 12 in a plan view. Each of FL regions 58A to 58E is also referred to as an FLR region (field boundary ring region).

[0122] The entirety of FL regions 58A to 58E, or FL regions 58A to 58E as a whole, are in relation to the bottom walls of the gate trenches. 21 on the side of the second main surface 4. Soil sections of FL regions 58A to 58E are positioned on the side of the second main surface 4 with respect to the soil section of diode region 55. The soil sections of FL regions 58A to 58E are positioned with respect to the soil walls of the source trenches. 31The FL region 58A is positioned on the side of the second main surface 4. The FL region 58A, located on the innermost side formed by FL regions 58A to 58E, covers the diode region 55, starting from the side of the second main surface 4. FL region 58A is therefore electrically connected to diode region 55. FL region 58A can form a pn junction section of the diode.

[0123] The FL structure 57 relaxes a concentration of an electric field in the outer region 13. The number, widths, depths, p-type impurity concentrations, etc., of the FL regions 58 can assume any number of different values, according to the electric field to be relaxed. The FL structure 57 can include one or a plurality of FL regions 58 formed in the region between the active sidewalls 54 and the diode region 55, as seen from the top view.

[0124] The SiC semiconductor component 1 includes an outer insulating layer 61 covering the outer main surface 52. The outer insulating layer 61 may contain silicon oxide. The outer insulating layer 61 may also contain a further insulating film of silicon nitride, etc. In this embodiment, the outer insulating layer 61 is made of the same type of insulating material as the gate insulating layers. 22 educated.

[0125] The outer insulating layer 61 is formed as a film along the active side walls 54 and the outer main surface 52. On the active main surface 51, the outer insulating layer 61 is continuous and borders directly on the gate insulating layers. 22 (third regions 26). In the outer region 13, the outer insulating layer 61 covers the diode region 55, the outer trough region 56 and the FL structure 57.

[0126] The circumferential edges of the outer insulating layer 61 are exposed at the side surfaces 5A to 5D. In this embodiment, the circumferential edges of the outer insulating layer 61 are continuous with the side surfaces 5A to 5D. The circumferential edges of the outer insulating layer 61 can be formed with inward spacing relative to the side surfaces 5A to 5D. In this case, the outer insulating layer 61 exposes the outer main surface 52.

[0127] The SiC semiconductor device 1 further includes a sidewall structure 62 that covers the active sidewalls 54. The sidewall structure 62 protects and reinforces the active mesa 53 against the side of the outer region 13. Furthermore, the sidewall structure 62 forms a level-difference moderating structure that moderates or compensates for a level difference that exists between the active main surface 51 and the outer main surface 52.

[0128] When an upper layer structure (cover layer) is formed, covering the boundary region between the active region 12 and the outer region 13, the upper layer structure covers the side wall structure 62. The side wall structure 62 improves the flatness of the upper layer structure. The side wall structure 62 can have a sloping surface that slopes downwards from the active main surface 51 towards the outer main surface 52. The difference in level can be appropriately compensated for or moderated by the sloping surface of the side wall structure 62.

[0129] The inclined surface of the sidewall structure 62 can be formed into a curved shape facing the side of the SiC semiconductor layer. 2 is excluded or recessed. The inclined surface of the sidewall structure 62 can be formed in a shape that faces in the opposite direction to the SiC semiconductor layer. 2is curved. The inclined surface of the side wall structure 62 can extend as an a-plane from the side of the active main surface 51 towards the side of the outer main surface 52.

[0130] The sidewall structure 62 is formed along the active sidewalls 54. In this embodiment, the sidewall structure 62 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in a top view. The sidewall structure 62 preferably comprises polysilicon (p-type polysilicon in this embodiment). In this case, the sidewall structure 62 can be formed at the same time as the gate electrodes. 23 and the source electrodes 33 .

[0131] The SiC semiconductor component 1 includes an intermediate insulating layer 63 (insulating layer) which is attached to the first main surface. 3The intermediate insulating layer 63 can contain silicon oxide or silicon nitride. The intermediate insulating layer 63 can contain at least one USG (undoped silicate glass) layer, one PSG (phosphosilicate glass) layer, and one BPSG (borophosphosilicate glass) layer, as an example of silicon oxide. In this embodiment, the intermediate insulating layer 63 has a laminated structure comprising a first insulating layer 64 and a second insulating layer 65. The first insulating layer 64 is composed of a USG layer. The second insulating layer 65 is composed of a BPSG layer.

[0132] The intermediate insulating layer 63 covers the active region 12 and the outer region 13. The intermediate insulating layer 63 is formed as a film along the active main surface 51 and the outer main surface 52. In the boundary region between the active region 12 and the outer region 13, the intermediate insulating layer 63 is formed along the side wall structure 62. The intermediate insulating layer 63 forms a section of the upper layer structure that covers the side wall structure 62.

[0133] The periphery edges of the intermediate insulating layer 63 are exposed at the side surfaces 5A to 5D. The periphery edges of the intermediate insulating layer 63 are continuous with the side surfaces 5A to 5D. The periphery edges of the intermediate insulating layer 63 can be formed with inward gaps relative to the side surfaces 5A to 5D. In this case, the intermediate insulating layer 63 exposes the outer main surface 52 (outer insulating layer 61).

[0134] In active region 12, the interlayer insulating layer 63 covers the source regions. 42 Furthermore, the intermediate insulating layer 63 covers the contact regions. 43 More precisely, the intermediate insulating layer covers 63 total areas or areas of the source regions. 42 in a sectional view along the second direction Y. The intermediate insulating layer 63 covers the entire surface area of ​​the source regions. 42In top view. The intermediate insulating layer 63 covers the entire surface area of ​​the contact regions. 43 in a cross-sectional view. The intermediate insulating layer 63 covers the entire surface area of ​​the contact regions. 43 in a top view.

[0135] More precisely, the intermediate layer-insulating layer 63 crosses the first trench sections in the active region 12. 34 the Source trenches 31 and covers the source electrodes 33 . On the first main area 3 The intermediate insulating layer 63 covers the side wall contact sections. 39 the source electrodes 33 .

[0136] The intermediate insulating layer 63 has a gate hole 66, source holes 67and a diode hole 68. The gate hole 66 exposes the gate wiring 28 in the active region 12. The gate hole 66 can be formed as a band oriented along the gate wiring 28. An opening edge section of the gate hole 66 is formed into a shape that curves towards an interior of the gate hole 66.

[0137] The source holes 67 place the source electrodes 33 Free in active region 12. The Source holes 67 can be formed as bands extending along the trench-source structures 30. An opening edge section of each source hole 67 is shaped into a form that points towards the interior of the source hole 67 is curved.

[0138] More precisely, the source holes 67 formed in the interior of regions bordered by the side walls of the source trenches 31 (first sections of the trench) 34) are surrounded, specifically in a top view. The source holes 67 place the source electrodes 33 with gaps towards the inner sides of the source trenches 31 free, specifically starting from the side walls of the source trenches 31 (first sections of the trench) 34 The source holes 67 Only the source electrodes are placed 33 free.

[0139] In the electrode surfaces of the source electrodes 33 are exceptions 69 formed, which lead towards the bottom walls of the source trenches 31 are set back. The cutouts 69 can be formed as bands extending along the trench-source structures 30. The recesses 69 are formed in the interior of the regions bordered by the side walls of the source trenches 31 (first sections of the trench) 34 ) are surrounded, specifically in the top view.

[0140] The cutouts 69are opposite the side walls of the source trenches 31 (first sections of the trench) 34 ) with distances towards the inner sides of the source trenches 31 formed. The exceptions 69 The second low-resistance layers 40 are exposed. The recesses 69 can penetrate the second low-resistance layers 40. The source holes 67 are in communication with the exclusions 69 the source electrodes 33 .

[0141] The diode hole 68 exposes the diode region 55 in the outer region 13. The diode hole 68 can be formed as a band (particularly as a continuous shape) extending along the diode region 55. The diode hole 68 can expose the outer trough region 56 and / or the FL structure 57. An opening edge portion of the diode hole 68 is shaped in a form that curves towards an interior of the diode hole 68.

[0142] The SiC semiconductor component 1 has the gate main surface electrode 71, which is located on the first main surface 3 The gate main surface electrode 71 is formed on the intermediate insulating layer 63. A gate voltage is applied to the gate main surface electrode 71. The gate voltage is not less than 10 V and not greater than 50 V (for example, approximately 30 V).

[0143] The main gate surface electrode 71 is formed in the active region 12. The main gate surface electrode 71 has a gate pad 72 and a gate finger or arm 73. The gate pad 72 is formed in a region on the side of the first face 5A, as seen from a top view. More precisely, the gate pad 72 is formed along a region along a central section of the first face 5A, as seen from a top view. The gate pad 72 can be formed in a region of a corner section connecting any two of the faces 5A to 5D, as seen from a top view. The gate pad 72 can be formed in a quadrilateral shape as seen from a top view.

[0144] The gate finger 73 extends outwards from the gate pad 72 and stretches as a band along the circumferential edges of the active region 12. In this embodiment, the gate finger 73 is formed along the first side surface 5A, the third side surface 5C and the fourth side surface 5D and delimits an inner side of the active region 12 from three directions.

[0145] The gate finger 73 has a pair of open or free ends 74 and 75. The pair of open ends 74 and 75 are formed in a region opposite the gate pad 72, extending across the inner side of the active region 12. In this embodiment, the pair of open ends 74 and 75 are formed in a region along the second side surface 5B, as seen from the top view.

[0146] The gate finger 73 enters the gate hole 66 from above the intermediate insulating layer 63. The gate finger 73 is electrically connected to the gate wiring 28 within the gate hole 66. An electrical signal from the gate pad 72 is thus transmitted via the gate finger 73 to the gate electrodes. 23 and the gate wiring 28 is transmitted.

[0147] The main gate surface electrode 71 contains a conductive material that differs from that of the gate electrodes 23 (Gate wiring 28) differs. More precisely, the gate main surface electrode 71 is made of a metal material. That is, in this embodiment, the gate main surface electrode 71, which is made of the metal material, is electrically connected to the gate electrodes. 23 (Gate wiring 28) connected, which are made of conductive polysilicon.

[0148] The gate main surface electrode 71 has a laminated structure with a first barrier layer 76 and a first main body layer 77, which are arranged in this order starting from the side of the SiC semiconductor layer. 2 The first barrier layer 76 preferably comprises at least one Ti layer and one TiN layer. The first barrier layer 76 preferably has a laminated structure comprising a Ti layer and a TiN layer arranged in that order starting from the side of the SiC semiconductor layer. 2 are laminated. The first barrier layer 76 can have a single-layer structure consisting of a Ti layer or a TiN layer.

[0149] The thickness of the first barrier layer 76 may be no less than 0.01 µm and no greater than 6 µm. The thickness of the first barrier layer 76 may be no less than 0.01 µm and no greater than 0.1 µm, no less than 0.1 µm and no greater than 2 µm, no less than 2 µm and no greater than 4 µm, or no less than 4 µm and no greater than 6 µm.

[0150] The first main body layer 77 has a resistance value that is lower than the resistance value of the first barrier layer 76. The first main body layer 77 comprises at least one layer consisting of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The thickness of the first main body layer 77 exceeds the thickness of the first barrier layer 76. The thickness of the first main body layer 77 is not less than 0.05 µm and not greater than 10 µm. The thickness of the first main body layer 77 may be not less than 0.05 µm and not greater than 0.1 µm, not less than 0.1 µm and not greater than 1 µm, not less than 1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, not less than 4 µm and not greater than 6 µm, not less than 6 µm and not greater than 8 µm, or not less than 8 µm and not greater than 10 µm.

[0151] The SiC semiconductor component 1 has the source main surface electrode 81 located on the first main surface 3 The source electrode 81 is formed at intervals from the gate main surface electrode 71. More precisely, the source main surface electrode 81 is formed on the intermediate insulating layer 63. A source voltage is applied to the source main surface electrode 81. The source voltage can be a reference voltage (for example, a ground voltage or GND voltage).

[0152] The source main surface electrode 81 is formed in the active region 12 and the outer region 13. The source main surface electrode 81 includes a source pad 82, a source wiring 83, and a source coupling section 84. The source pad 82 is formed in the active region 12, spaced apart from the gate main surface electrode 71. In a top view, the source pad 82 is formed in a C-shape such that it covers a region of the C-shape that is delimited by the gate main surface electrode 71.

[0153] The Source-Pad 82 includes source connection electrodes. 85 and a source covering electrode 86. The source connecting electrodes 85 are in the source holes 67 embedded. The source connection electrodes 85 are within the source holes 67 with the source electrodes 33 connected. The source connection electrodes 85 are within the source holes 67only with the source electrodes 33 tied together.

[0154] The source covering electrode 86 covers the interlayer insulating layer 63 in a region outside the source holes. 67 In this embodiment, the source covering electrode 86 is integrally formed with the source connecting electrodes. 85 formed. The Source-Pad 82 is thus electrically connected to the body region. 41 , the source regions 42 and the contact regions 43 connected, specifically via the source electrodes 33 .

[0155] The source wiring 83 is formed in the outer region 13. The source wiring 83 extends as a band along the active region 12. The source wiring 83 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in plan view. The source wiring 83 enters the diode hole 68 from above the interlayer insulating layer 63. The source wiring 83 is electrically connected to the diode region 55 within the diode hole 68.

[0156] Source coupling section 84 connects source pad 82 and source wiring 83. Source coupling section 84 crosses the open ends 74 and 75 of gate finger 73, extending from source pad 82, and is connected to source wiring 83. Source coupling section 84 crosses the sidewall structure 62, extending from active region 12 to the outer region 13. Source coupling section 84 forms a section of the upper layer structure covering sidewall structure 62.

[0157] The source main surface electrode 81 has a conductive material that differs from that of the source electrodes. 33 This differs. More precisely, the source main surface electrode 81 is made of a metallic material. That is, in this embodiment, the source main surface electrode 81, which is made of the metallic material, is electrically connected to the source electrodes. 33connected, which are made up of conductive polysilicon.

[0158] The source main surface electrode 81 has a laminated structure comprising a second barrier layer 87 and a second main body layer 88, arranged in this order starting from the side of the SiC semiconductor layer. 2 The second barrier layer 87 preferably comprises at least one Ti layer and one TiN layer. The second barrier layer 87 preferably has a laminated structure with a Ti layer and a TiN layer arranged in that order starting from the side of the SiC semiconductor layer. 2 are laminated. The second barrier layer 87 can have a single-layer structure consisting of a Ti layer or a TiN layer.

[0159] The thickness of the second barrier layer 87 may be not less than 0.01 µm and not greater than 6 µm. The thickness of the second barrier layer 87 may be not less than 0.01 µm and not greater than 0.1 µm, not less than 0.1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, or not less than 4 µm and not greater than 6 µm.

[0160] The second main body layer 88 has a resistance value that is lower than the resistance value of the second barrier layer 87. The second main body layer 88 comprises at least one layer consisting of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The thickness of the second main body layer 88 exceeds the thickness of the second barrier layer 87. The thickness of the second main body layer 88 is not less than 0.05 µm and not greater than 10 µm. The thickness of the second main body layer 88 may be not less than 0.05 µm and not greater than 0.1 µm, not less than 0.1 µm and not greater than 1 µm, not less than 1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, not less than 4 µm and not greater than 6 µm, not less than 6 µm and not greater than 8 µm, or not less than 8 µm and not greater than 10 µm.

[0161] Due to its structure, the MISFET formed in the active region 12 incorporates a parasitic npn-type transistor. When an avalanche current generated in the outer region 13 flows into the active region 12, the parasitic transistor is switched on. In this case, the operation of the MISFET becomes unstable due to latch-up. Therefore, in the SiC semiconductor device 1, the structure of the source main area electrode 81 is used to form an avalanche current-absorbing structure.

[0162] The avalanche current generated in the outer region 13 is absorbed by the source wiring 83 via the diode region 55. The avalanche current absorbed by the source wiring 83 reaches the source pad 82 via the source coupling section 84. If a connecting wire, such as a bond wire, is electrically connected to the source pad 82, the avalanche current reaches the outer surface via this connecting wire. This suppresses the activation of the parasitic transistor due to the avalanche current. Latchup can thus be suppressed, and the stability of the MISFET can therefore be improved.

[0163] The SiC semiconductor component 1 has an insulating layer 91 on, which is formed on the intermediate insulating layer 63. In Fig. 2 is the insulating layer 91 Shown by hatching. Circumferential edges of the insulating layer. 91are formed with inward gaps relative to the side surfaces 5A to 5D. The insulating layer 91 This creates the perimeter boundaries of the SiC semiconductor layer. 2 (more precisely, the intermediate layer insulating layer 63) is free, as seen from above.

[0164] The circumferential edges of the insulating layer 91 They define a dicing street DS, together with the side surfaces 5A to 5D. The dicing street DS eliminates the need for the insulating layer. 91 Physical cutting or separation occurs when the SiC semiconductor component 1 is cut or separated from a SiC wafer. This allows the SiC semiconductor component 1 to be cut out of the SiC wafer without damage, and at the same time prevents peeling and deterioration of the insulating layer. 91 be suppressed. Consequently, protective objects, such as the SiC semiconductor layer, can be protected. 2, the gate main surface electrode 71, the source main surface electrode 81, etc. suitable through the insulating layer 91 be protected.

[0165] The width of the separation zone DS may be no less than 1 µm and no greater than 25 µm. The width of the separation zone DS is a width in a direction perpendicular to the direction in which the separation zone DS extends. The width of the separation zone DS may be no less than 1 µm and no greater than 5 µm, no less than 5 µm and no greater than 10 µm, no less than 10 µm and no greater than 15 µm, no less than 15 µm and no greater than 20 µm, or no less than 20 µm and no greater than 25 µm.

[0166] The insulating layer 91 selectively covers the gate main surface electrode 71 and the source main surface electrode 81. The insulating layer 91It has a gate pad opening 92 and a source pad opening 93. Gate pad opening 92 exposes gate pad 72. Source pad opening 93 exposes source pad 82. The plane shape of gate pad opening 92 is arbitrary. The plane shape of source pad opening 93 is arbitrary.

[0167] In this embodiment, the insulating layer 91 a laminated structure with a passivation layer 94 and a resin layer 95, arranged in this order starting from the side of the SiC semiconductor layer 2The passivation layer 94 can contain at least one silicon oxide layer and one silicon nitride layer. The passivation layer 94 can have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any sequence. The passivation layer 94 can have a single-layer structure composed of either a silicon oxide layer or a silicon nitride layer. The passivation layer 94 preferably includes an insulating material that differs from that of the intermediate insulating layer 63. In this embodiment, the passivation layer 94 has a single-layer structure composed of a silicon nitride layer.

[0168] The passivation layer 94 is formed as a film along the intermediate insulating layer 63. The passivation layer 94 covers the active region 12 and the outer region 13, extending across the intermediate insulating layer 63. The passivation layer 94 crosses the sidewall structure 62 starting from the active region 12 and extends to the outer region 13. The passivation layer 94 forms a section of the upper layer structure that covers the sidewall structure 62.

[0169] The passivation layer 94 has a first gate opening 96 and a first source opening 97. The first gate opening 96 exposes the gate pad 72. The first source opening 97 exposes the source pad 82. The plane shape of the first gate opening 96 is arbitrary. The plane shape of the first source opening 97 is arbitrary.

[0170] The thickness of the passivation layer 94 may be no less than 0.1 µm and no greater than 20 µm. The thickness of the passivation layer 94 may be no less than 0.1 µm and no greater than 1 µm, no less than 1 µm and no greater than 5 µm, no less than 5 µm and no greater than 10 µm, no less than 10 µm and no greater than 15 µm, or no less than 15 µm and no greater than 20 µm.

[0171] The resin layer 95 can contain a photosensitive resin. The photosensitive resin can be of a negative type or a positive type. The resin layer 95 can contain at least one material consisting of a polyimide, a polyamide, and a polybenzoxazole. In this embodiment, the resin layer 95 includes polybenzoxazole.

[0172] The resin layer 95 is formed as a film along a major surface of the passivation layer 94. The resin layer 95 crosses the sidewall structure 62 starting from the active region 12 and extends towards the outer region 13. The resin layer 95 forms a section of the upper layer structure that covers the sidewall structure 62. In this embodiment, the circumferential edges of the resin layer 95 expose the circumferential edges of the passivation layer 94. 91 are formed by the circumferential edges of the resin layer 95 and the circumferential edges of the passivation layer 94. The resin layer 95 can cover the circumferential edges of the passivation layer 94.

[0173] The resin layer 95 has a second gate opening 98 and a second source opening 99. The second gate opening 98 communicates with the first gate opening 96 of the passivation layer 94 and forms the gate pad opening 92 with the first gate opening 96. The second source opening 99 communicates with the first source opening 97 of the passivation layer 94 and forms the source pad opening 93 with the first source opening 97.

[0174] The inner walls of the second gate opening 98 can be flush with the inner walls of the first gate opening 96. The inner walls of the second gate opening 98 can be positioned outside the first gate opening 96 in a top view. The inner walls of the second gate opening 98 can also be positioned inside the first gate opening 96 in a top view. That is, the resin layer 95 can cover the inner walls of the first gate opening 96.

[0175] The inner walls of the second source opening 99 can be flush with the inner walls of the first source opening 97. The inner walls of the second source opening 99 can be positioned outside the first source opening 97 in a top view. The inner walls of the second source opening 99 can also be positioned inside the first source opening 97 in a top view. That is, the resin layer 95 can cover the inner walls of the first source opening 97.

[0176] The thickness of the resin layer 95 may be no less than 1 µm and no greater than 50 µm. The thickness of the resin layer 95 may be no less than 1 µm and no greater than 10 µm, no less than 10 µm and no greater than 20 µm, no less than 20 µm and no greater than 30 µm, no less than 30 µm and no greater than 40 µm, or no less than 40 µm and no greater than 50 µm.

[0177] The SiC semiconductor device 1 has an uneven structure 101 formed in the outer main surface 52. More precisely, the uneven structure 101 has an unevenness formed using the interlayer insulating layer 63 that covers the outer main surface 52. Even more precisely, the uneven structure 101 has an anchoring hole 102 formed in the interlayer insulating layer 63.

[0178] The anchoring hole 102 is formed by a trench in a section of the interlayer insulating layer 63 that covers the outer region 13. The anchoring hole 102 can be formed in a region between the diode region 55 and the side surfaces 5A to 5D, as seen from a top view. In this embodiment, the anchoring hole 102 is formed in a region between the FL structure 57 and the side surfaces 5A to 5D, as seen from a top view.

[0179] The anchoring hole 102 can be delimited by the intermediate insulating layer 63. In this embodiment, the anchoring hole 102 exposes the outer main surface 52. The anchoring hole 102 can be excavated or embedded in the outer main surface 52 towards the second main surface 4. An opening edge section of the anchoring hole 102 is formed or shaped in a form that is curved towards the interior of the anchoring hole 102.

[0180] The anchoring hole 102 extends as a band along the active region 12 in plan view. In this embodiment, the anchoring hole 102 is formed in a ring shape (more precisely, a continuous shape) that surrounds the active region 12 in plan view. The number of anchoring holes 102 is arbitrary. A single anchoring hole 102 can be formed in the intermediate insulating layer 63, or a plurality of anchoring holes 102 can be formed in the intermediate insulating layer 63.

[0181] The resin layer 95 has an anchoring section 103 that engages the anchoring hole 102. In this embodiment, the resin layer 95 engages the anchoring hole 102 via the passivation layer 94. More precisely, the passivation layer 94 enters the anchoring hole 102 from above the intermediate insulating layer 63. The passivation layer 94 contacts the outer main surface 52 within the anchoring hole 102. A recess 104, which is cut out or set back towards the anchoring hole 102, is formed in a section of the main surface of the passivation layer 94 that covers the anchoring hole 102.

[0182] A section of the resin layer 95 forms the anchoring section 103 within the recess 104 of the passivation layer 94. A bond strength of the resin layer 95 with respect to the first main surface 3This can improve the process, and this can effectively suppress peeling of the resin layer 95.

[0183] The SiC semiconductor component 1 has a drain electrode 105 which is attached to the second main surface 4 of the SiC semiconductor layer. 2 The drain electrode 105 is electrically connected to the drain region 6. The drain electrode 105 comprises at least one layer consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, an Ag layer, and an Al layer. The drain electrode 105 preferably has a Ti layer that forms an ohmic contact with the second main surface 4.

[0184] The drain electrode 105 preferably has a laminated structure comprising at least one Ti layer, one Ni layer, and one Au layer, laminated in that order starting from the side of the second main surface 4. More precisely, the drain electrode 105 has a laminated structure comprising one Ti layer, one Ni layer, one Au layer, and one Ag layer, laminated in that order starting from the side of the second main surface 4. Preferably, a Pd layer is arranged between the Ni layer and the Au layer. An Al layer can be arranged on any layer in the laminated structure.

[0185] As described above, the source electrodes have 33 in the SiC semiconductor component 1 the side wall contact sections 39 , which are located on the side wall window sections 36 are exposed. The source regions 42are electrically connected to the side wall contact sections 39 the source electrodes 33 connected, which are on the side walls of the source trenches 31 within the SiC semiconductor layer 2 are exposed. The source regions 42 This allows suitable placement within the SiC semiconductor layer 2 Source-grounded.

[0186] In the SiC semiconductor component 1, the body region 41 furthermore, electrically with the side wall contact sections 39 the source electrodes 33 connected, which are on the side walls of the source trenches 31 within the SiC semiconductor layer 2 are exposed. The body region 41 This makes it suitable for use within the SiC semiconductor layer 2 Be source-grounded.

[0187] Furthermore, the contact regions of the SiC semiconductor component 1 are 43 between body regions 41and the side wall contact sections 39 arranged, namely in surface layer sections of the first main surface 3 The contact regions 43 are electrically connected to the side wall contact sections 39 the source electrodes 33 connected, which are on the side walls of the source trenches 31 within the SiC semiconductor layer 2 are exposed. The contact regions 43 This allows suitable placement within the SiC semiconductor layer 2 Source-grounded.

[0188] Furthermore, the source regions of the SiC semiconductor component 1 are 42 within the SiC semiconductor layer 2 Source-grounded, and therefore the intermediate layer insulating layer 63 can be formed, which is on the first main surface 3 the source regions 42covered. Furthermore, the intermediate layer-insulating layer 63 can be formed, which covers the entire surfaces or surface areas of the source regions. 42 covered in a cross-sectional view. The intermediate insulating layer 63 can also be formed, which covers the entire areas or surface areas of the source regions. 42 covered in a top view. Furthermore, the intermediate insulating layer 63 can be formed, which is on the first main surface. 3 the side wall contact sections 39 the source electrodes 33 covered.

[0189] In the SiC semiconductor component 1, the source regions are 42 furthermore within the SiC semiconductor layer 2 Source-grounded, and therefore an opening width of the source holes is possible. 67 , which are the source electrodes 33 to be exposed, narrower or tighter. An alignment margin of the source holes. 67This allows it to be widened or expanded. That is, the SiC semiconductor component 1 can be provided, which is robust against positional deviations of the source holes. 67 .

[0190] Furthermore, the source holes in the SiC semiconductor component 1 can 67 are formed that only use the source electrodes 33 expose, and at the same time the source connection electrodes can 85 are formed that only use the source electrodes 33 are connected. Therefore, the source regions can 42 Suitable source grounding is possible, and at the same time, a variation in electrical characteristics can occur due to positional deviations of the source connection electrodes. 85 (Source holes) 67 ) be appropriately suppressed.

[0191] The source electrodes 33are preferably made of a conductive material other than a metal. The source electrodes 33 are preferably made of conductive polysilicon. The source main surface electrode 81 is preferably made of a conductive material that differs from that of the source electrodes. 33 The source main surface electrode 81 is preferably made of a metal material.

[0192] With such a structure, the source electrodes 33 suitable in the source trenches 31 be embedded, and at the same time the source main surface electrode 81 can be suitablely equipped with the source electrodes 33 They can be connected. Such a structure is particularly effective in a case where the opening width of the source trenches is 31 approximately the same as the opening width of the gate trenches 21 and where the source trenches 31the second depth D2 have, which have the first depth D1 the gate trenches 21 exceeds.

[0193] A metal material can also be found in the source trenches. 31 to be embedded. In this case, however, the depth of the source trenches is affected. 31 a limitation, and at the same time the source trenches must 31 formed with an opening width that corresponds to the opening width of the gate trenches 21 significantly exceeds this limit. It must be noted that this conflicts with the requirement to design the SiC semiconductor component 1 to have a high withstand voltage and a compact form factor. This problem can be solved for the SiC semiconductor component 1.

[0194] The Fig. 11A to Fig. Figures 11S are enlarged sectional views of an example of a method for manufacturing the SiC semiconductor component 1, which is described in Fig. 1 is shown. Fig. 11A to Fig. 11S are enlarged views of the region, which Fig. 8 corresponds to.

[0195] First, with reference to Fig. 11A a SiC wafer 111 from n + A SiC-type substrate 111 is provided or prepared, which is intended to be the base of the drain region 6 (SiC semiconductor substrate 7). Next, a SiC epitaxial layer 112, which is intended to be the base of the drift region 8 (SiC epitaxial layer 9), is formed on a major face of the SiC wafer 111. The SiC epitaxial layer 112 is formed on the major face of the SiC wafer 111 by an epitaxial growth process.

[0196] In this step, the SiC epitaxial layer 112, which has the high-concentration region 10 and the low-concentration region 11, is formed by adjusting the doping amount of an n-type impurity. The SiC semiconductor layer 2The region comprising drain region 6 and drift region 8 is formed by this process. A description is given below using the SiC semiconductor layer. 2 , the first main area 3 and the second main area 4.

[0197] Next, with reference to Fig. 11B the body region 41 of the p-type in a surface layer section of the first main surface 3 formed. The body region 41 is in an entire area of ​​the surface layer section of the first main surface 3 formed. The body region 41 is formed by introducing a p-type impurity into the first main surface 3 Next, a source region will be created. 42 from n + -Type in a surface layer section of the body region 41 formed. The source region 42 is located in a region of the surface layer section of the body region 41formed, in which the channels of the MISFET are to be formed. The source region 42 is formed by introducing an n-type impurity into the surface layer section of the body region 41 .

[0198] Next, with reference to Fig. 11C a hard mask 113 with a predetermined pattern on the first main surface 3 formed. The hard mask 113 has a multitude of openings 114, the regions of the first main surface 3 uncover where the gate trenches 21 , the Source trenches 31 and the outer region 13 are to be formed. The hard mask 113 may contain silicon dioxide. The hard mask 113 can be formed by a CVD (chemical vapor deposition) process or by a heat oxidation treatment process. In this step, the hard mask 113 is formed by a heat oxidation treatment process.

[0199] Next, unnecessary sections of the SiC epiaxial layer 112 are removed by an etching process over the hard mask 113. The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably a dry etching process. The gate trenches 21 and the Source trenches 31 This process creates new regions in active region 12. The outer region 13 is also created, which is set back from active region 12 towards the side of the second main surface 4. The hard mask 113 is then removed.

[0200] Next, with reference to Fig. 11D a mask 115, which has a predetermined pattern, on the first main surface 3 formed. The mask 115 has a multitude of openings 116, which form the source trenches. 31and expose the outer region 13. In this step, the mask 115 has a laminated structure comprising a polysilicon layer 117 and an insulating layer 118. The insulating layer 118 contains silicon oxide. The polysilicon layer 117 can be formed by a CVD process. The insulating layer 118 can be formed by a CVD process or by a heat oxidation treatment process. In this step, the insulating layer 118 is formed by a heat oxidation treatment process performed on the polysilicon layer 117.

[0201] Next, unnecessary sections of the SiC epiaxial layer 112 are removed via the mask 115 by an etching process. The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably a dry etching process. The source trenches 31 and the outer region 13 will thereby be further excavated towards the second main area 4.

[0202] Next, with reference to Fig. 11E the deep-tub regions 44 , the circumferential trough regions 45 and the outer trough region 56 in surface layer sections of the first main surface 3 formed. The deep-trough regions 44 , the circumferential rim basin regions 45 and the outer basin region 56 are , by introducing a p-type contaminant into the first main surface 3 The p-type contaminant is introduced into the outer main surface 52 via an ion implantation mask. The p-type contaminant can also be introduced into the outer main surface 52 via mask 115, in addition to the ion implantation mask.

[0203] Next, the multitude of FL regions 58 (or the FL structure 57) will be divided into surface layer sections of the first main area. 3(outer main surface 52). The multitude of FL structures 57 are formed by introducing a p-type impurity into the first main surface. 3 The p-type impurity is introduced into the outer main surface 52 via an ion implantation mask.

[0204] Next, with reference to Fig. 11F the contact regions 43 and the diode region 55 in surface layer sections of the first main surface 3 formed. The contact regions 43 and the diode region 55 are formed by introducing a p-type impurity into the first main surface 3 The p-type contamination is placed in the first main area. 3 inserted via an ion implantation mask.

[0205] Next, with reference to Fig. 11G a base insulating layer 119 on the first main surface 3 formed, which is intended to be the basis for the gate insulating layers22 , the source insulating layers 32 and the outer insulating layer 61. The base insulating layer 119 may contain silicon dioxide.

[0206] The base insulating layer 119 can be formed by a CVD process or by a heat oxidation treatment process. Sections of the base insulating layer 119 are used to form the sidewalls of the gate trenches. 21 cover, and sections that form the side walls of the source trenches 31 They cover, forming thinner sections than other sections. Also, 119 sections of the base insulating layer form the opening edge sections of the gate trenches. 21 cover, and sections that form the opening edge sections of the source trenches 31 cover, formed thicker than other sections.

[0207] The base insulating layer 119, which has such a structure, is formed by setting conditions or boundary conditions of the CVD process or the heat oxidation treatment process. For example, predetermined boundary conditions, such as a gas flow rate, a gas type, a gas ratio, a gas supply time, a temperature, etc., of the CVD process or the heat oxidation treatment process should be set.

[0208] Next, with reference to Fig. 11H a first polysilicon layer 120, which is intended to be a basis for the gate electrodes 23 , the gate wiring 28 and the source electrodes 33 , on the first main area 3 formed. The first polysilicon layer 120 fills the gate trenches. 21 and the Source trenches 31 and covers the first main area 3 .

[0209] The first polysilicon layer 120 can be formed by a CVD process. This CVD process can be a low-pressure CVD (LP-CVD) process. The first polysilicon layer 120 is composed of conductive polysilicon to which conductivity is imparted by a p-type impurity. The p-type impurity can be doped into the first polysilicon layer 120 simultaneously with the CVD process or can be doped separately after the CVD process.

[0210] Next, with reference to Fig. 11I Non-essential sections of the first polysilicon layer 120 are removed. The non-essential sections of the first polysilicon layer 120 are removed until the base insulating layer 119 is exposed. The non-essential sections of the first polysilicon layer 120 can be removed by an etching process. The etching process can be a wet etching process and / or a dry etching process. The gate electrodes23 , the gate wiring 28 and the source electrodes 33 are formed as a result.

[0211] In this step, a section of the first polysilicon layer 120 remains in a state where it is attached to the active sidewalls 54. The sidewall structure 62, which includes the section of the first polysilicon layer 120, is thereby formed. The sidewall structure 62 is self-aligned with respect to the active main surface 51.

[0212] Next, with reference to Fig. 11J a resist mask 121 with a predetermined pattern on the first main surface 3 formed. The resist mask 121 has openings 122 that form the source trenches. 31 , sections of the source regions 42 and the contact regions 43 exposes, and covers regions adjacent to these.

[0213] Next, unnecessary sections of the source insulation layers will be removed. 32and unnecessary or non-essential sections of the source electrodes 33 by an etching process via the resist mask 121. In this step, sections of the SiC epiaxial layer 112 are also removed. The source trenches 31 , each of which forms the first section of the trench 34 and the second section of the trench 35 have, are formed by this. Furthermore, the side wall window sections are 36 , which comprise the first sections of the trench 34 the Source trenches 31 expose, in the source insulating layer 32 formed. The Resist Mask 121 is then removed.

[0214] Next, with reference to Fig. 11K a second polysilicon layer 123, which is intended to be a base for the source electrodes 33 , on the first main area 3 formed. The second polysilicon layer 123 fills the first trench sections. 34 the Source trenches31 and covers the first main area 3 .

[0215] The second polysilicon layer 123 can be formed by a CVD process. This CVD process can be a low-pressure CVD (LP-CVD) process. The second polysilicon layer 123 is composed of conductive polysilicon to which conductivity is imparted or mediated by a p-type impurity. The p-type impurity can be doped into the second polysilicon layer 123 simultaneously with the CVD process or can be doped separately after the CVD process.

[0216] Next, with reference to Fig. 11L Non-essential sections of the second polysilicon layer 123 are removed. The non-essential sections of the second polysilicon layer 123 are removed until the first main surface 3The non-essential sections of the second polysilicon layer 123 can be removed by an etching process. The etching process can be a wet etching process and / or a dry etching process. The source electrodes 33 are thereby regenerated.

[0217] In this step, a section of the second polysilicon layer 123 remains in a state where it is attached to the active sidewalls 54. The sidewall structure 62, which includes the section of the second polysilicon layer 123, is thereby formed. The sidewall structure 62 is self-aligned with respect to the active main surface 51.

[0218] Next, with reference to Fig. 11M a metal layer 124 which forms the gate electrodes 23 , the gate wiring 28 and the source electrodes 33 covered, on the first main area 3The metal layer 124 comprises a metal material capable of polyciding with the p-type polysilicon. The metal layer 124 can contain at least one of Mo, W, Ni, Co, and Ti. The metal layer 124 can be formed by a CVD process, a sputtering process, and / or a vapor deposition process.

[0219] Next, p-type polycid layers are deposited in area layer sections of the gate electrodes. 23 , a surface layer section of the gate wiring 28 and surface layer sections of the source electrode or source electrodes 33The polycid layers are formed by performing a heat treatment process on the metal layer 124. The heat treatment process can be a rapid thermal annealing (RTA) process. The p-type polycid layers, which contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2, are formed by this process. The first low-resistance layer 29 and the second low-resistance layers 40 are formed by the p-type polycid layers.

[0220] Next, with reference to Fig. 11N removed the unreacted portions of the metal layer 124. These unreacted portions can be removed by an etching process. The etching process can be a wet etching process and / or a dry etching process.

[0221] If the first low-resistance layer 29 and the second low-resistance layers 40 contain TiSi or CoSi, a heat treatment process can be applied again to the first low-resistance layer 29 and the second low-resistance layers 40 after removing the unreacted sections of the metal layer 124. The heat treatment process to be performed on the first low-resistance layer 29 and the second low-resistance layers 40 can be an RTA process. This can modify the TiSi to TiSi2 and the CoSi to CoSi2.

[0222] Next, with reference to Fig. 11O the intermediate layer insulating layer 63 on the first main surface 3The intermediate insulating layer 63 covers the active region 12 and the outer region 13 in its entirety. The intermediate insulating layer 63 includes the first insulating layer 64 and the second insulating layer 65. The first insulating layer 64 is composed of a USG layer. The second insulating layer 65 is composed of a BPSG layer. The first insulating layer 64 and the second insulating layer 65 can be formed by a CVD process.

[0223] Next, with reference to Fig. 11P a resist mask 125, which has a predetermined pattern, is formed on the intermediate insulating layer 63. The resist mask 125 has a plurality of openings 126 that expose regions where the gate hole 66, the source holes 67 , the diode hole 68 and the anchoring hole 102 are to be formed.

[0224] Next, unnecessary sections of the intermediate insulating layer 63 are removed by an etching process over the resist mask 125. The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably a dry etching process. The gate hole 66, the source holes 67 The diode hole 68 and the anchoring hole 102 are thereby formed.

[0225] A heat treatment process can then be carried out on the intermediate insulating layer 63. The opening edge section of the gate hole 66, the opening edge sections of the source holes. 67 , the opening edge section of the diode hole 68 and the opening edge section of the anchoring hole 102 are thereby rounded off into curved shapes or formed roundly.

[0226] Next, with reference to Fig. 11Q A base barrier layer 127, which is intended to be a base for the first barrier layer 76 and the second barrier layer 87, is formed on the intermediate insulating layer 63. The base barrier layer 127 has a laminated structure including a Ti layer and a TiN layer, which are laminated in that order starting from the side of the intermediate insulating layer 63. The Ti layer and the TiN layer can each be formed by a sputtering process.

[0227] Next, with reference to Fig. 11R A base main body layer 128, which is intended to be a base for the first main body layer 77 and the second main body layer 88, is formed on the base barrier layer 127. The base main body layer 128 has at least one layer consisting of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The base main body layer 128 can be formed by a sputtering process.

[0228] Next, unnecessary sections of the laminated structure, which includes the base barrier layer 127 and the base main body layer 128, are removed by an etching process over a resist mask (not shown). The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably a dry etching process. The gate main surface electrode 71 and the source main surface electrode 81 are thereby formed.

[0229] Next, the insulating layer will be applied. 91 formed on the intermediate insulating layer 63. The insulating layer 91 The laminated structure comprises the passivation layer 94 and the resin layer 95. The passivation layer 94 can be formed by a CVD process. The resin layer 95 can be formed by coating the passivation layer 94 with a photosensitive resin. Next, the resin layer 95 is selectively exposed or exposed and then developed. The second gate opening 98, the second source opening 99, and the separation path DS are thereby formed in the resin layer 95.

[0230] Next, sections of the passivation layer 94 exposed at the second gate opening 98, the second source opening 99, and the separation path DS are removed. The unnecessary sections of the passivation layer 94 can be removed by an etching process over the resin layer 95. The etching process can be a wet etching process and / or a dry etching process.

[0231] The first gate opening 96, the first source opening 97, and the separation path DS are thereby formed in the passivation layer 94. The first gate opening 96 delimits the gate pad opening 92, together with the gate opening 98. The first source opening 97 delimits the source pad opening 93, together with the second source opening 99.

[0232] Next, with reference to Fig. 11S the drain electrode 105 is formed on the second main surface 4. The drain electrode 105 comprises a Ti layer, a Ni layer, a Pd layer, an Au layer, an Ag layer, and an Al layer. The Ti layer, the Ni layer, the Pd layer, the Au layer, the Ag layer, and / or the Al layer can be formed by a sputtering process, a vapor deposition process, a CVD process, and / or a plating process.

[0233] The second main surface 4 can be ground before the step of forming the drain electrode 105. The SiC semiconductor layer 2 This allows it to be thinned to a desired thickness. Furthermore, an annealing treatment can be carried out on the ground second main surface 4 using a laser irradiation process.

[0234] The SiC semiconductor layer is then 2The SiC semiconductor components are separated or cut along the separation line DS. A large number of SiC semiconductor components 1 are thereby cut or separated from a single SiC wafer 111. The SiC semiconductor component 1 is formed by steps that include the steps described above.

[0235] Fig. 12 is an enlarged view of a region accordingly Fig. Figure 8 is a diagram that partially shows a SiC semiconductor component 131 according to a second preferred embodiment of the present invention. Below, structures corresponding to those described with respect to the SiC semiconductor component 1 are designated with the same reference numerals, and a description thereof is omitted.

[0236] With reference to Fig. In this embodiment, the source insulating layers are 12. 32 each a floor wall window section 132, which forms the bottom wall of the corresponding source trench 31 exposes. In this embodiment, the floor-wall-window section exposes 132 a central section of the bottom wall with distances from the side walls of the source trench 31 free. The floor-wall-window section 132 can the side walls and the bottom wall of the Source trench 31 on the bottom wall side of the Source trench 31 uncover.

[0237] In this embodiment, the bottom wall of the source trench 31 A recess 133 is cut out or set back towards the side of the second main surface 4. The recess 133 defines the central section of the bottom wall with distances from the side walls of the source trench. 31 free. The floor-wall-window section 132 is related to Exclusion 133.

[0238] The source electrodes 33 Each has a floor-wall contact section134 in contact with the bottom wall (recess 133) of the Source trench 31 , specifically exposed at the floor-wall-window section 132 A section from each contact region 43 , which forms the bottom wall of the Source Trench 31 Covered, is electrically connected to the floor-wall contact section 134 the corresponding source electrode 33 tied together.

[0239] Each deep-trough region 44 includes sections that are electrically connected to the floor-wall contact section 134 the corresponding source electrode 33 are connected, specifically via the contact regions 43 on the bottom wall of the corresponding source trench 31 . Each deep-trough region 44 includes a section that is electrically connected to the floor-wall contact section 134 the source electrode 33 is connected, namely to the bottom wall of the Source Trench. 31 .

[0240] The same effects can be observed in the SiC semiconductor component 131 described above as in the SiC semiconductor component 1. The source electrodes of the SiC semiconductor component 131 also exhibit the same effects. 33 each the side wall contact section 39 , which is located on the side wall window section 36 is exposed, and have the floor-wall contact section 134 , which is located at the floor-wall-window section 132 exposed. The contact regions 43 are electrically connected to the side wall contact sections 39 the source electrodes 33 at the opening sides of the Source trenches 31 connected and electrically linked to the floor-wall contact sections 134 the source electrodes 33 on the bottom wall sides of the source trenches 31 tied together.

[0241] If a negative drain-source voltage (VGS) is applied across the source electrodes 33When the drain electrode 105 is applied, the MISFET operates in the third quadrant ("third-quadrant operation"). In third-quadrant operation, a forward current flows through the pn-junction diode located in the body region. 41 (deep basin regions) 44 ) is formed. The forward current flows from the source electrodes. 33 towards the drain electrode 105 and is therefore a reverse current with respect to the MISFET.

[0242] The forward current of the pn junction diode flows from the sidewall contact sections. 39 the source electrodes 33 into drift region 8, specifically via the side window sections 36 , and at the same time it flows from the soil-wall contact sections 134 the source electrodes 33 into drift region 8, specifically via the floor-wall-window sections 132This increases the forward current paths of the pn junction diode, and consequently reduces the on-resistance. As a result, the forward characteristics of the pn junction diode are improved.

[0243] In this embodiment, an example was described in which the recesses 133 of the source trenches 31 through the contact regions 43 are covered. However, source trenches may exist. 31 Exemptions 133 can be formed that do not have the exceptions 133. Exceptions 133 can also be formed that include the contact regions. 43 penetrate. In other words, contact regions can 43 to be formed, covering the side walls of the recesses 133 and exposing the bottom walls of the recesses 133.

[0244] The Fig. 13A to Fig. Figures 13H are enlarged sectional views of an example of a method for manufacturing the SiC semiconductor component 131, which is described in Fig. 12 is shown.

[0245] With reference to Fig. 13A will be the SiC semiconductor layer 2 in the state where the base insulating layer 119 has been formed, via the steps of the Fig. 11A to Fig. 11G prepared.

[0246] Next, with reference to Fig. 13B a ​​base polysilicon layer 135, which is a basis or foundation of the gate electrodes 23 and the source electrodes 33 is to be traded on the first main area 3 The base polysilicon layer 135 is formed as a film along the inner walls of the gate trenches. 21 , the inner walls of the Source trenches 31 and the first main area 3 educated.

[0247] The base polysilicon layer 135 can be formed by a CVD process. This CVD process can be a low-pressure CVD (LP-CVD) process. The base polysilicon layer 135 consists of conductive polysilicon to which conductivity is imparted by a p-type impurity. The p-type impurity can be doped into the base polysilicon layer 135 simultaneously with the CVD process or separately after the CVD process.

[0248] Next, with reference to Fig. 13C removed non-essential sections of the basal polysilicon layer 135. These non-essential sections are those that run parallel to the first main surface. 3The unnecessary sections of the base polysilicon layer 135 can be removed by an etching process. The etching process is preferably an anisotropic dry etching process. The dry etching process can be a RIE (reactive ion etching) process.

[0249] Sections of the base polysilicon layer 135 therefore remain in a state where they form the sidewalls of the gate trenches. 21 cover and the bottom walls of the gate trenches 21 Expose. Sections of the basal polysilicon layer 135 also remain in a state where they form the sidewalls of the source trenches. 31 cover and the bottom walls of the source trenches 31 uncover.

[0250] Next, with reference to Fig. 13D a resist mask 136 with a predetermined pattern on the first main surface 3 formed. The resist mask 136 has openings 137 that form the source trenches. 31to expose, and covers regions next to these..

[0251] Next, sections of the base insulating layer 119, which adjoin the polysilicon layer 135 inside the source trenches, will be examined. 31 The exposed material is removed by an etching process via the resist mask 136. The etching process is preferably an anisotropic dry etching process. The dry etching process can be a RIE process.

[0252] The floor-wall-window sections 132 , which form the bottom walls of the Source trenches 31 This exposes sections of the base insulating layer 119, which form the bottom walls of the source trenches. 31 cover. In this step, sections of the SiC epiaxial layer 112, which are attached to the bottom wall window sections, are covered. 132 Exposed, also removed. The recesses 133 in conjunction with the floor-wall-window sections. 132 This results in [something] on the bottom walls of the source trenches 31formed. The Resist Mask 136 is then removed.

[0253] Next, with reference to Fig. 13E the first polysilicon layer 120, which is the base of the gate electrodes 23 , the gate wiring 28 and the source electrodes 33 is to be traded on the first main area 3 formed. The first polysilicon layer 120 fills the gate trenches. 21 and the Source trenches 31 and covers the first main area 3 The first polysilicon layer 120 is integral or integral with the base polysilicon layer 135 inside the gate trenches. 21 and the Source trenches 31 educated.

[0254] The first polysilicon layer 120 can be formed by a CVD process. This CVD process can be a low-pressure CVD (LP-CVD) process. The first polysilicon layer 120 is composed of conductive polysilicon to which conductivity is imparted by a p-type impurity. The p-type impurity can be doped into the first polysilicon layer 120 simultaneously with the CVD process or separately after the CVD process.

[0255] Next, with reference to Fig. 13F Non-essential sections of the first polysilicon layer 120 are removed. The non-essential sections of the first polysilicon layer 120 are removed until the base insulating layer 119 is exposed. The non-essential sections of the first polysilicon layer 120 can be removed by an etching process. The etching process can be a wet etching process and / or a dry etching process. The gate electrodes 23 , the gate wiring 28 and the source electrodes 33 are formed as a result.

[0256] In this step, a section of the first polysilicon layer 120 remains in a state where it is attached to the active sidewalls 54. The sidewall structure 62, which includes the section of the first polysilicon layer 120, is thereby formed. The sidewall structure 62 is self-aligned with respect to the active main surface 51.

[0257] Then the same steps are followed as in the Fig. 11 years to Fig. 11S was performed to form the SiC semiconductor device 131.

[0258] Fig. 14 is an enlarged view of a region accordingly Fig. Figure 8 is a diagram that partially shows a SiC semiconductor device 141 according to a third preferred embodiment of the present invention. Below, structures corresponding to those described with respect to the SiC semiconductor device 1 are designated with the same reference numerals, and a description thereof is omitted.

[0259] With reference to Fig. 14 In this embodiment, the trench-source structures 30 do not have the source insulating layers. 32 The source electrodes 33each has a first side wall contact section 142, a second side wall contact section 143 and a bottom wall contact section 145 inside the corresponding source trench. 31 on.

[0260] The first side wall contact section 142 contacts the side walls of the first trench section. 34 The second side wall contact section 143 contacts the side walls of the second trench section. 35 The bottom wall contact section 145 contacts the bottom wall of the source trench. 31 Each contact region 43 is electrically connected to the first side wall contact section 142, the second side wall contact section 143 and the bottom wall contact section 145 of the corresponding source electrode 33 tied together.

[0261] Each deep-trough region 44includes sections that are electrically connected to the first side wall contact section 142, the second side wall contact section 143 and the bottom wall contact section 145 of the corresponding source electrode 33 are connected, specifically via the contact regions 43 . Each deep-trough region 44 includes a section that is electrically connected to the first side wall contact section 142, the second side wall contact section 143 and the bottom wall contact section 145 of the source electrode 33 is connected.

[0262] The SiC semiconductor component 141 described above exhibits the same effects as those described for SiC semiconductor component 1. In SiC semiconductor component 141, the source electrodes include 33 in addition, the first side wall contact section 142, the second side wall contact section 143 and the bottom wall contact section 145. The contact regions 43are electrically connected to the first side wall contact section 142, the second side wall contact section 143 and the bottom wall contact section 145 of the source electrode 33 tied together.

[0263] If a negative drain-source voltage (VGS) is applied across the source electrodes 33 When the drain electrode 105 is applied, the MISFET operates in the third quadrant. In third-quadrant operation, a forward current flows through the pn-junction diode located in the body region. 41 (deep basin regions) 44 ) is formed. The forward current flows from the source electrodes. 33 towards the drain electrode 105 and consequently represents a reverse or blocking current with respect to the MISFET.

[0264] The forward current of the pn junction diode flows from the sidewall contact sections. 39 or 142 of the source electrodes 33into drift region 8, specifically via the side window sections 36 , and at the same time it flows from the soil-wall contact sections 134 or 145 of the source electrodes 33 into drift region 8, specifically via the floor-wall window sections 132 This increases the forward current paths of the pn junction diode, and consequently reduces the on-resistance. As a result, the forward characteristics of the pn junction diode can be improved.

[0265] The Fig. 15A and Fig. Figure 15B shows enlarged sectional views of an example of a method for fabricating the SiC semiconductor component 141, which is described in Fig. 14 is shown.

[0266] With reference to Fig. 15A will be the SiC semiconductor layer 2 in the state where the first polysilicon layer 120 is in the gate trenches 21 and the Source trenches 31is embedded, prepared, namely via the steps of the Fig. 11A to Fig. 11I.

[0267] Next, with reference to Fig. 15B the resist mask 121 with the predetermined pattern on the first main surface 3 formed. The resist mask 121 has openings 122 that form the source trenches. 31 , sections of the source regions 42 and the contact regions 43 to expose, and covers regions next to these.

[0268] Next, sections of the first polysilicon layer 120, which extend into the source trenches, will be examined. 31 The embedded components are completely removed by an etching process using the resist mask 121. In this step, the source insulating layers are also removed. 32 completely removed. Sections of the SiC epiaxial layer 112 are also removed in this step. The source trenches 31 , each of which forms the first section of the trench 34and the second section of the trench 35 have, are formed by this.

[0269] After this, the same steps are taken as those of the Fig. 11K to Fig. 11S was performed to form the SiC semiconductor device 141.

[0270] Fig. 16 is an enlarged view of a region accordingly Fig. Figure 8 is a diagram that partially shows a SiC semiconductor component 151 according to a fourth preferred embodiment of the present invention. Below, structures corresponding to those described with respect to the SiC semiconductor component 1 are designated with the same reference numerals, and a description thereof is omitted.

[0271] In this embodiment, the source pad 82 includes the source connection electrodes. 85and the source covering electrode 86, which are formed in one piece from the same metal material. On the other hand, with reference to Fig. 16, the source pad 82 according to the SiC semiconductor component 151 includes the source connection electrodes 85 and the source covering electrode 86, which are formed as separate bodies made of different metal materials.

[0272] More precisely, each source junction electrode 85 The plug electrode 152 is constructed from a plug electrode. In particular, the plug electrode 152 is constructed from a tungsten plug electrode, which includes a barrier layer 153 and a tungsten layer 154 extending from the side of the source hole. 67 laminated in this order.

[0273] Barrier layer 153 is defined as a film along an inner wall of the source hole. 67and an electrode surface of the corresponding source electrode 33 formed. Barrier layer 153 borders a recessed space inside the source hole. 67 The barrier layer 153 preferably has a laminated structure including a Ti layer and a TiN layer extending from the inner wall side of the source hole. 67 are laminated in this order. The barrier layer 153 can have a single-layer structure consisting of a Ti layer or a TiN layer. The tungsten layer 154 is embedded in the source hole. 67 embedded over barrier layer 153.

[0274] The source covering electrode 86 has a laminated structure including the second barrier layer 87 and the second main body layer 88. The source covering electrode 86 covers the intermediate insulating layer 63 and the source connecting electrodes. 85The source covering electrode 86 is electrically connected to the source electrodes 33 via the source connection electrodes 85 tied together.

[0275] The SiC semiconductor component 151 described above exhibits the same effects as those described for SiC semiconductor component 1. Furthermore, the source junction electrodes in SiC semiconductor component 151 are... 85 , which are made up of the plug electrodes 152, in the source holes 67 embedded. This allows the opening width of the source holes to be adjusted. 67 They can be made narrower, and at the same time the source connection electrodes can be made narrower. 85 suitable in the source holes 67 They are embedded with a narrow width. The source connection electrodes 85 This allows them to be used appropriately with the source electrodes 33The structure of the SiC semiconductor component 151 can also be applied to the SiC semiconductor component 131 according to the second preferred embodiment and to the SiC semiconductor component 141 according to the third preferred embodiment.

[0276] The preferred embodiments of the present invention can be implemented in further embodiments.

[0277] In each of the preferred embodiments described above, an example has been described in which the first low-resistance layer 29 and the second low-resistance layers 40 are formed. However, a structure can be used in which one or both of the first low-resistance layer 29 and the second low-resistance layers 40 are not formed.

[0278] For each of the preferred embodiments described above, an example has been described in which the gate electrodes 23 and the gate wiring 28 comprises p-type polysilicon doped with a p-type impurity. However, if an increase in the gate threshold voltage Vth is not the primary concern, the gate electrodes can 23 and the gate wiring 28 contains an n-type polysilicon doped with an n-type impurity instead of the p-type polysilicon.

[0279] In this case, the first low-resistance layer 29 can be silicified by means of a metallic material, of sections of the gate electrodes 23(n-type polysilicon) can be formed, forming surface layer sections. That is, the first low-resistance layer 29 can have an n-type polysilicon structure. In the case of such a structure, the gate resistance can be reduced. It is understood that the first low-resistance layer 29 does not have to be formed.

[0280] For each of the preferred embodiments described above, an example has been described in which the source electrodes 33 These are formed by polysilicon of the p-type doped with a p-type impurity. However, instead of the p-type polysilicon, n-type polysilicon doped with an n-type impurity may be used.

[0281] In this case, the second low-resistance layers 40 can be created by silicifying sections of the source electrodes using a metallic material. 33(n-type polysilicon) are formed, forming the surface layer sections. That is, the second low-resistance layers 40 can contain an n-type polysilicon. It is understood that the second low-resistance layers 40 do not have to be formed.

[0282] For each of the preferred embodiments described above, an example has been described in which the source electrodes 33 are formed that contain p-type polysilicon doped with a p-type impurity. However, source electrodes can be used. 33 , each consisting of a laminated structure of a p-type polysilicon and an n-type polysilicon, are formed by forming the first polysilicon layer 120, which is composed of a p-type, and by forming the second polysilicon layer 123, which is composed of an n-type.

[0283] In this case, the second low-resistance layers 40 can be formed by silicification of sections forming surface layer sections using a metallic material. That is, the second low-resistance layers 40 can have an n-type polycide. It is understood that the second low-resistance layers 40 do not have to be formed.

[0284] For each of the preferred embodiments described above, an example has been described in which the insulating layer 91 The laminated structure comprises the passivation layer 94 and the resin layer 95. The insulating layer 91 However, it can have a single-layer structure, which is made up of the passivation layer 94 or the resin layer 95.

[0285] In each of the preferred embodiments described above, an example has been described in which the first direction X is the m-axis direction ([1-100] direction) of the SiC monocrystal and in which the second direction Y is the a-axis direction ([11-20] direction) of the SiC monocrystal. However, an embodiment can be used in which the first direction X is the a-axis direction ([11-20] direction) of the SiC monocrystal and in which the second direction Y is the m-axis direction ([1-100] direction) of the SiC monocrystal.

[0286] In each of the preferred embodiments described above, an example was provided in which a MISFET was formed as an example of an insulated-gate transistor. Instead of the drain region 6 of the n + However, the -type can be a collector region of p +-type can be applied. In this structure, an IGBT (bipolar transistor with insulated gate) can be provided instead of a MISFET. In this case, in each of the preferred embodiments described above, the "source" of the MISFET is to be replaced by an "emitter" of the IGBT, and the "drain" of the MISFET is to be replaced by a "collector" of the IGBT.

[0287] In each of the preferred embodiments described above, a structure can be used in which the conductivity types of the respective semiconductor sections are inverted. That is, a p-type section can be made into an n-type, and an n-type section can be made into a p-type.

[0288] For each of the preferred embodiments described above, an example has been described that incorporates the SiC semiconductor layer. 2containing a SiC monocrystal. However, in each of the preferred embodiments described above, a Si semiconductor layer composed of a Si monocrystal can be used instead of the SiC semiconductor layer. 2 be applied.

[0289] The present application corresponds to the Japanese patent application No. 2019-096289, which was filed with the Japanese Patent Office on May 22, 2019, and the entire disclosure content of that application is contained herein by reference.

[0290] Although the preferred embodiments of the present invention have been described in detail, these are merely specific examples used to illustrate the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of protection of the present invention is limited only by the attached claims. Reference symbol list 1 SiC semiconductor component 2 SiC semiconductor layers 3 first main area 21 Gate Trench 22 Gate insulating layer 23 Gate electrode 31 Source Trench 32 Source insulating layer 33 Source electrode 34 first trench section 35 second trench section 36 Side wall window section 39 Side wall contact section 41 Body region 42 Source Region 43 Contact Region 44 Deep trough region 67 Source Hole 69 Exclusion 85 Source connection electrode 91 Insulating layer 131 SiC semiconductor component 132 Floor wall window section 134 Floor-to-wall contact section 151 SiC semiconductor component D1 first depth of gate trench D2 second depth of source trench W1 first width of first trench section W2 second width of second trench section QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2016 / 006696 A1

[0003] JP 2019096289

[0289]

Claims

[1] SiC semiconductor device with: a SiC semiconductor layer of a first conductivity type having a main surface; a source trench formed in the main surface and having a sidewall and a bottom wall; a source electrode embedded in the source trench and having a sidewall contact portion in contact with a region of the sidewall of the source trench at an opening side of the source trench; a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench; and a source region of the first conductivity type electrically connected to the sidewall contact portion of the source electrode in a surface layer portion of the body region. [2] The SiC semiconductor device according to claim 1, wherein the body region is electrically connected to the sidewall contact portion of the source electrode. [3] A SiC semiconductor device according to claim 1 or 2, further comprising: an insulating layer covering the source region on the main surface. [4] The SiC semiconductor device according to claim 3, wherein the insulating layer covers the sidewall contact portion of the source electrode on the main surface. [5] The SiC semiconductor device according to claim 3 or 4, wherein the insulating layer covers an entire area of the source region in a sectional view. [6] The SiC semiconductor device according to any one of claims 3 to 5, wherein the insulating layer covers an entire area of the source region in a plan view. [7] A SiC semiconductor device according to any one of claims 3 to 6, comprising: a source hole formed in the insulating layer and exposing the source electrode; and a source connection electrode embedded in the source hole and connected to the source electrode. [8] The SiC semiconductor device according to claim 7, wherein the source connection electrode comprises a conductive material different from the source electrode. [9] The SiC semiconductor device according to claim 7 or 8, wherein the source hole exposes only the source electrode and the source connection electrode is connected only to the source electrode within the source hole. [10] A SiC semiconductor device according to any one of claims 7 to 9, wherein the source electrode has an electrode surface with a recess recessed towards the bottom wall of the source trench, and wherein the source hole is in communication with the recess of the source electrode. [11] The SiC semiconductor device according to any one of claims 1 to 10, wherein the source electrode is constructed of a conductive material other than a metal material. [12] The SiC semiconductor device according to any one of claims 1 to 11, wherein the source electrode is constructed of a conductive polysilicon. [13] A SiC semiconductor device according to any one of claims 1 to 12, wherein the source electrode is constructed of a p-type conductive polysilicon. [14] A SiC semiconductor device according to any one of claims 1 to 13, wherein the source trench has a first trench portion formed on the opening side with a first width and a second trench portion formed on the bottom wall side with a second width smaller than the first width, and wherein the sidewall contact portion of the source electrode is exposed from the first trench portion. [15] A SiC semiconductor device according to any one of claims 1 to 14, further comprising: a second conductivity type contact region disposed between the source region and the sidewall contact portion of the source electrode, such that it is electrically connected to the sidewall contact portion of the source electrode in the surface sectional portion of the body region and has a second conductivity type impurity concentration exceeding a second conductivity type impurity concentration of the body region. [16] The SiC semiconductor device of claim 15, wherein a plurality of said contact regions are formed at intervals along said source trench. [17] The SiC semiconductor device according to claim 15 or 16, wherein the contact region is disposed between the body region and the sidewall contact portion of the source electrode. [18] The SiC semiconductor device according to any one of claims 15 to 17, wherein the contact region covers the sidewall and the bottom wall of the source trench. [19] A SiC semiconductor device according to any one of claims 15 to 18, further comprising: a deep well region of the second conductivity type formed along the source trench in a region below the body region in a surface layer portion of the main surface and having an impurity concentration of the second conductivity type that is smaller than the impurity concentration of the second conductivity type of the contact region. [20] The SiC semiconductor device of claim 19, wherein the deep well region covers the sidewall and the bottom wall of the source trench. [21] A SiC semiconductor device according to any one of claims 1 to 20, further comprising: a gate trench formed in the main surface; a gate insulating layer formed on an inner wall of the gate trench; and a gate electrode embedded in the gate trench via the gate insulating layer. [22] The SiC semiconductor device of claim 21, wherein the gate trench has a first depth and wherein the source trench has a second depth that exceeds the first depth. [23] A SiC semiconductor device according to any one of claims 1 to 22, further comprising: a source insulating layer having a sidewall window portion that exposes the sidewall of the source trench in a region on the opening side of the source trench and that covers the sidewall and the bottom wall of the source trench; and wherein the sidewall contact portion of the source electrode contacts the sidewall of the source trench exposed from the sidewall window portion. [24] A SiC semiconductor device according to any one of claims 1 to 22, further comprising: a source insulating layer having a sidewall window portion exposing a region on the opening side of the source trench on the sidewall of the source trench, and a bottomwall window portion exposing the bottom wall of the source trench, and covering at least the sidewall of the source trench; and wherein the source electrode is embedded in the source trench via the source insulating layer and has the sidewall contact portion in contact with the sidewall of the source trench exposed from the sidewall window portion, and has a bottom wall contact portion in contact with the bottom wall of the source trench exposed from the bottom wall window portion.