DRIVER CIRCUIT, DISPLAY PANEL, DISPLAY SUBSTRATE AND DISPLAY DEVICE

Abstract

A driver circuit, a display panel, a display substrate, and a display device are provided. The driver circuit includes a first node control circuit, a second node control circuit, and a first output circuit; the second node control circuit is configured to control the connection of the first node and the second node under the control of a low-voltage signal provided from the first low-voltage input terminal; the first node control circuit is configured to control the connection of the first node and the second low-voltage input terminal under the control of a first clock signal provided from the first clock signal line; the first output circuit is configured to control the connection of the driver signal output terminal and the third low-voltage input terminal under the control of a potential of the pull-down node;At least two of the first low-voltage input terminal, the second low-voltage input terminal, and the third low-voltage input terminal are different from each other. At least two low-voltage signals are used in the present disclosure.

Description

FIELD OF TECHNOLOGY

[0001] The present disclosure relates to the field of display technology, in particular to a driving circuit, a display panel, a display substrate and a display device. STATE OF THE ART

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) are used in many products due to their flexibility, high contrast ratio, and low power consumption.

[0003] In the prior art, an AMOLED display device generally includes an AMOLED display panel and a gate drive circuit. An AMOLED display panel includes multiple rows of pixels. The gate drive circuit includes a plurality of cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to the row of pixels to drive the row of pixels to emit light. The plurality of cascaded shift register units can realize line-by-line scanning control of multiple rows of pixels, so that the AMOLED display panel displays images.

[0004] However, the corresponding shift register units use the same voltage input terminal, and the potential of each node cannot be flexibly adjusted. SUMMARY

[0005] In a first aspect, the present disclosure provides, in some embodiments, a driver circuit comprising a first node control circuit, a second node control circuit, and a first output circuit; the second node control circuit is electrically connected to a first low-voltage input terminal, a first node, and a second node, respectively, and is configured to control the connection of the first node and the second node under the control of a low-voltage signal provided by the first low-voltage input terminal;the first node control circuit is electrically connected to a second low-voltage input terminal, a first clock signal line, and the first node, and is configured to control the electrical connection of the first node and the second low-voltage input terminal under the control of a first clock signal provided by the first clock signal line; the first output circuit is electrically connected to a pull-down node, a drive signal output terminal, and a third low-voltage input terminal, and is configured to control the connection of the drive signal output terminal and the third low-voltage input terminal under the control of a potential of the pull-down node; wherein at least two of the first low-voltage input terminal, the second low-voltage input terminal, and the third low-voltage input terminal are different from each other.

[0006] Optionally, according to at least one embodiment of the present disclosure, the driver circuit further comprises a second output circuit and a fourth node control circuit; the second output circuit is electrically connected to a pull-up node, a first high-voltage input terminal, and the driver signal output terminal, respectively, and is configured to control the connection of the first high-voltage input terminal and the driver signal output terminal under the control of a potential of the pull-up node; the fourth node control circuit is electrically connected to the first node, a fourth node, and a fourth high-voltage input terminal, respectively, and is configured to control the connection of the fourth node and the fourth high-voltage input terminal under the control of a potential of the first node;the first high-voltage input terminal is different from the fourth high-voltage input terminal.;

[0007] Optionally, according to at least one embodiment of the present disclosure, the driver circuit further comprises a third node reset circuit; the third node reset circuit is electrically connected to a reset line, a third high-voltage input terminal, and a third node, respectively, and configured to control the connection of the third high-voltage input terminal and the third node under the control of a reset signal provided by the reset line; the third high-voltage input terminal is different from the first high-voltage input terminal and / or the fourth high-voltage input terminal.

[0008] Optionally, according to at least one embodiment of the present disclosure, the driver circuit further comprises a pull-up node control circuit; the pull-up node control circuit is electrically connected to the third node, a second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of a potential of the third node; the second high-voltage input terminal is different from the first high-voltage input terminal and / or the fourth high-voltage input terminal.

[0009] Optionally, according to at least one embodiment of the present disclosure, the driver circuit further comprises a pull-up node control circuit; the pull-up node control circuit is electrically connected to the third node, the second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of the potential of the third node; the second high-voltage input terminal is different from the third high-voltage input terminal.

[0010] Optionally, according to at least one embodiment of the present disclosure, the driver circuit further comprises a pull-down node control circuit; the pull-down node control circuit is electrically connected to a fourth low-voltage input terminal, a third node, and the pull-down node, respectively, and is configured to control the connection of the third node and the pull-down node under the control of a low-voltage signal provided by the fourth low-voltage input terminal; the fourth low-voltage input terminal is different from at least one of the first low-voltage input terminal, the second low-voltage input terminal, and the third low-voltage input terminal.

[0011] Optionally, the driver circuit according to at least one embodiment of the present disclosure further comprises a fifth node control circuit and a pull-up node control circuit; the fifth node control circuit is electrically connected to the second node, a fifth node, and a second clock signal line, respectively, and is configured to control the connection of the second clock signal line and the fifth node under the control of the potential of the second node, and to control a potential of the fifth node according to the potential of the second node;the pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line, and the pull-up node, respectively, and is configured to control the connection of the fifth node and the pull-up node under the control of a second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node under the control of the second clock signal provided by the second clock signal line;

[0012] Optionally, the driver circuit further comprises a third node control circuit; the third node control circuit is electrically connected to a start voltage terminal, the first clock signal line, and the third node, respectively, and is configured to control the connection of the start voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line; the first node control circuit is also electrically connected to the third node, the first node, and the first clock signal line, respectively, and is configured to control the connection of the first node and the first clock signal line under the control of the potential of the third node;the fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line, respectively, and configured to control the connection of the fourth node and the second clock signal line under the control of the potential of the pull-down node and to control the potential of the fourth node according to the potential of the pull-down node;

[0013] Optionally, the first node control circuit comprises a first transistor and the second node control circuit comprises a second transistor; a control electrode of the first transistor is electrically connected to the first clock signal line, a first electrode of the first transistor is electrically connected to the second low-voltage input terminal, and a second electrode of the first transistor is electrically connected to the first node; a control electrode of the second transistor is electrically connected to the first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node; the first output circuit comprises an output reset transistor;a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low-voltage input terminal;

[0014] Optionally, the second output circuit comprises an output transistor, and the pull-up node control circuit comprises a third transistor and a first capacitor; a control electrode of the output transistor is electrically connected to the pull-up node, a first electrode of the output transistor is electrically connected to the first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to the drive signal output terminal; a control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node;a first electrode plate of the first capacitor is electrically connected to the pull-up node, and a second electrode plate of the first capacitor is electrically connected to the first high-voltage input terminal;

[0015] Optionally, the third node reset circuit comprises a fourth transistor; a control electrode of the fourth transistor is electrically connected to the reset line, a first electrode of the fourth transistor is electrically connected to the third high-voltage input terminal, and a second electrode of the fourth transistor is electrically connected to the third node.

[0016] Optionally, the fourth node control circuit comprises a fifth transistor; a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth high-voltage input terminal, and a second electrode of the fifth transistor is electrically connected to the fourth node.

[0017] Optionally, the pull-down node control circuit comprises a sixth transistor; a control electrode of the sixth transistor is electrically connected to the fourth low-voltage input terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node.

[0018] Optionally, the fifth node control circuit comprises a seventh transistor and a second capacitor; the pull-up node control circuit further comprises an eighth transistor; a control electrode of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the second clock signal line, and a second electrode of the seventh transistor is electrically connected to a fifth node; a first electrode plate of the second capacitor is electrically connected to the second node, and a second electrode plate of the second capacitor is electrically connected to the fifth node; a control electrode of the eighth transistor is electrically connected to the second clock signal line, a first electrode of the eighth transistor is electrically connected to the fifth node, and a second electrode of the eighth transistor is electrically connected to the pull-up node.

[0019] Optionally, the first node control circuit further comprises a ninth transistor; a control electrode of the ninth transistor is electrically connected to the third node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first node; the fourth node control circuit further comprises a tenth transistor and a third capacitor; a control electrode of the tenth transistor is electrically connected to the pull-down node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the fourth node; a first electrode plate of the third capacitor is electrically connected to the pull-down node, and a second electrode plate of the third capacitor is electrically connected to the fourth node;the third node control circuit includes an eleventh transistor; a control electrode of the eleventh transistor is electrically connected to the first clock signal line, a first electrode of the eleventh transistor is electrically connected to the start voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the third node.

[0020] In a second aspect, an embodiment of the present disclosure provides a driver circuit comprising a first transistor, a second transistor, an output reset transistor, and a sixth transistor; a control electrode of the first transistor is electrically connected to a first clock signal line, a first electrode of the first transistor is electrically connected to a second low-voltage input terminal, and a second electrode of the first transistor is electrically connected to a first node; a control electrode of the second transistor is electrically connected to a first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to a second node;the first output circuit comprises the output reset transistor, a control electrode of the output reset transistor is electrically connected to a pull-down node, a first electrode of the output reset transistor is electrically connected to a drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to a third low-voltage input terminal; a control electrode of the sixth transistor is electrically connected to a fourth low-voltage input terminal, a first electrode of the sixth transistor is electrically connected to a third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node; wherein the first low-voltage input terminal, the second low-voltage input terminal, the third low-voltage input terminal, and the fourth low-voltage input terminal are not completely the same.

[0021] In a third aspect, an embodiment of the present disclosure provides a driver circuit comprising an output transistor, a third transistor, a fourth transistor, and a fifth transistor; a control electrode of the output transistor is electrically connected to a pull-up node, a first electrode of the output transistor is electrically connected to a first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to a drive signal output terminal; a control electrode of the third transistor is electrically connected to a third node, a first electrode of the third transistor is electrically connected to a second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node;a control electrode of the fourth transistor is electrically connected to a reset line, a first electrode of the fourth transistor is electrically connected to a third high-voltage input terminal, and a second electrode of the fourth transistor is electrically connected to a third node; a control electrode of the fifth transistor is electrically connected to a first node, a first electrode of the fifth transistor is electrically connected to a fourth high-voltage input terminal, and a second electrode of the fifth transistor is electrically connected to a fourth node; the first high-voltage input terminal, the second high-voltage input terminal, the third high-voltage input terminal, and the fourth high-voltage input terminal are not completely the same.;

[0022] In a fourth aspect, an embodiment of the present disclosure provides a display panel comprising the driver circuit as described above; the display panel further comprises a display driver chip;the first low-voltage input terminal is electrically connected to a first low-voltage line, the second low-voltage input terminal is electrically connected to a second low-voltage line, the third low-voltage input terminal is electrically connected to a third low-voltage line, and the first low-voltage line, the second low-voltage line, and the third low-voltage line are electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide a first low-voltage signal to the first low-voltage line, provide a second low-voltage signal to the second low-voltage line, and provide a third low-voltage signal to the third low-voltage line;or the first low-voltage input terminal is electrically connected to the first low-voltage line, the second low-voltage input terminal and the third low-voltage input terminal are both electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line;or both the first low-voltage input terminal and the second low-voltage input terminal are electrically connected to the first low-voltage line, the third low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line;or both the first low-voltage input terminal and the third low-voltage input terminal are electrically connected to the first low-voltage line, the second low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line.;

[0023] In a sixth aspect, an embodiment of the present disclosure provides a display panel comprising the driver circuit as described above; the display panel further comprises a display driver chip; the first high-voltage input terminal is electrically connected to a first high-voltage line, and the second high-voltage input terminal is electrically connected to a second high-voltage line; the first high-voltage line and the second high-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide a first high-voltage signal to the first high-voltage line, and the display driver chip is configured to provide a second high-voltage signal to the second high-voltage line.

[0024] In a seventh aspect, an embodiment of the present disclosure provides a display substrate comprising a base substrate and the driver circuit disposed on the base substrate.

[0025] Optionally, the driver circuit includes a first low-voltage line, a second low-voltage line, a first high-voltage line, a second high-voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit; the second low-voltage line is disposed on a side of the driver circuit remote from a display area, and the first low-voltage line is disposed on a side of the driver circuit close to the display area; the first high-voltage line and the second high-voltage line are disposed between a first circuit part included in the driver circuit and a second circuit part included in the driver circuit;The first circuit part includes the first node control circuit, the second node control circuit, the pull-up node control circuit, the fourth node control circuit, the pull-down node control circuit, the fifth node control circuit, and the third node control circuit. The second circuit part includes the first output circuit and the second output circuit. The first circuit part is arranged between the second low-voltage line and the second high-voltage line, and the second circuit part is arranged between the first high-voltage line and the first low-voltage line.

[0026] Optionally, the driver circuit further comprises a third node reset circuit, and the first circuit part comprises the third node reset circuit.

[0027] In an eighth aspect, an embodiment of the present disclosure provides a display device including the driving circuit as described above. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1 is a structural diagram of a driver circuit according to an embodiment of the present disclosure; Fig. 2 is a structural diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 3 is a structural diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 4 is a structural diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 5 is a structural diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 6 is a structural diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 7 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 8A is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 8B is a working time diagram of the Fig. 8A driver circuit of at least one embodiment of the present disclosure; Fig. 9 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 10 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 11 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 12 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 13 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 14 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 15 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 16 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 17 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 18 is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 19A is a circuit diagram of a driver circuit according to at least one embodiment of the present disclosure; Fig. 19B is a structural diagram of a display panel according to at least one embodiment of the present disclosure; Fig. 20 is a circuit diagram of a corresponding pixel circuit; Fig. 21 is a layout diagram of the Fig. 15 shown driver circuit of at least one embodiment of the present disclosure; Fig. 22 is a layout diagram of the active layer in Fig. 21; Fig. 23 is a layout diagram of the first gate metal layer in Fig. 21; Fig. 24 is a layout diagram of the second gate metal layer in Fig. 21; Fig. 25 is a layout diagram of the source-drain metal layer in Fig. 21; Fig. 26 is a layout diagram of the Fig. 19 shown driver circuit of at least one embodiment of the present disclosure; Fig. 27 is a layout diagram of the active layer in Fig. 26; Fig. 28 is a layout diagram of the first gate metal layer in Fig. 26; Fig. 29 is a layout diagram of the second gate metal layer in Fig. 26; Fig. 30 is a layout diagram of the source-drain metal layer in Fig. 26; Fig. 31 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; Fig. 32 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; Fig. 33 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; Fig. 34 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; Fig. 35 is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF REVELATION

[0028] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Starting from the embodiments in the present disclosure, all other embodiments achieved by those skilled in the art without creative effort are within the scope of the present disclosure.

[0029] The transistors used in all embodiments of the present disclosure may be thin-film transistors or field-effect transistors or other devices with the same properties. To distinguish the two electrodes of the transistor, with the exception of the control electrode, one electrode is referred to as the first electrode and the other electrode as the second electrode in the embodiments of the present disclosure.

[0030] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode may be a gate electrode, the first electrode a drain electrode, and the second electrode a source electrode; or the control electrode may be a gate electrode, the first electrode a source electrode, and the second electrode a drain electrode.

[0031] As in Fig. 1, the driver circuit described in the present embodiment includes a first node control circuit 11, a second node control circuit 12, and a first output circuit 13;

[0032] The second node control circuit 12 is electrically connected to a first low-voltage input terminal VL1, a first node N1, and a second node N2, respectively, and is configured to control the connection of the first node N1 and the second node N2 under the control of a low-voltage signal provided from the first low-voltage input terminal VL1;

[0033] The first node control circuit 11 is electrically connected to a second low-voltage input terminal VL2, a first clock signal line CK, and the first node N1, respectively, and is configured to control the connection of the first node N1 and the second low-voltage input terminal VL2 under the control of a first clock signal provided from the first clock signal line CK;

[0034] The first output circuit 13 is electrically connected to a pull-down node PD, a drive signal output terminal O1, and a third low-voltage input terminal VL3, respectively, and is configured to control the connection of the drive signal output terminal O1 and the third low-voltage input terminal VL3 under the control of a potential of the pull-down node PD;

[0035] At least two of the first low-voltage input terminal VL1, the second low-voltage input terminal VL2 and the third low-voltage input terminal VL3 are different from each other.

[0036] In at least one embodiment of the present disclosure, the fact that the two low voltage input terminals are different may refer to the low voltage signals provided by the two low voltage input terminals, respectively, being different.

[0037] In the Fig. In the embodiment of the driver circuit shown in Figure 1, the low-voltage signal provided by the first low-voltage input terminal VL1 may be different from the low-voltage signal provided by the second low-voltage input terminal VL2.

[0038] In at least one embodiment of the present disclosure, the voltage value of the low voltage signal may be a negative voltage.

[0039] For example, when the transistors in the first node control circuit 11 and the transistors in the second node control circuit 12 are p-type transistors, an absolute value of the low voltage signal provided from the second low voltage input terminal VL2 is larger than that of the low voltage signal provided from the first low voltage input terminal VL1, so that the potential of N1 and the potential of N2 are lower.

[0040] In at least one embodiment of the present disclosure, the first low voltage input terminal may provide a first low voltage signal, and the second low voltage input terminal may provide a second low voltage signal, but is not limited thereto.

[0041] In at least one embodiment of the present disclosure, the first low voltage signal may be provided by the first low voltage line VGL, and the second low voltage signal may be provided by the second low voltage line VGL2.

[0042] In the Fig. 1, the first low-voltage input terminal VL1 may provide a first low-voltage signal, the second low-voltage input terminal VL2 may provide a second low-voltage signal, and the third low-voltage input terminal VL3 may provide a first low-voltage signal; or,

[0043] The first low-voltage input terminal VL1 may provide a second low-voltage signal, the second low-voltage input terminal VL2 may provide a second low-voltage signal, and the third low-voltage input terminal VL3 may provide a first low-voltage signal; or,

[0044] The first low-voltage input terminal VL1 may provide a first low-voltage signal, the second low-voltage input terminal VL2 may provide a first low-voltage signal, and the third low-voltage input terminal VL3 may provide a second low-voltage signal; or,

[0045] The first low voltage input terminal VL1 may provide a first low voltage signal, the second low voltage input terminal VL2 may provide a second low voltage signal, and the third low voltage input terminal VL3 may provide a second low voltage signal;

[0046] But not limited to this.

[0047] As in Fig. 2 on the basis of Fig. 1, the driver circuit described in at least one embodiment of the present disclosure further comprises a second output circuit 21 and a fourth node control circuit 41;

[0048] The second output circuit 21 is electrically connected to the pull-up node PU, the first high-voltage input terminal VH1, and the drive signal output terminal O1, respectively, and is configured to control the connection of the first high-voltage input terminal VH1 and the drive signal output terminal O1 under the control of the potential of the pull-up node PU;

[0049] The fourth node control circuit 41 is electrically connected to the first node N1, the fourth node N4, and the fourth high-voltage input terminal VH4, respectively, and is configured to control the connection of the fourth node N4 and the fourth high-voltage input terminal VH4 under the control of the potential of the first node N1; the first high-voltage input terminal VH1 is different from the fourth high-voltage input terminal VH4.

[0050] In at least one embodiment of the present disclosure, the two different high voltage input terminals may refer to: the high voltage signals provided by the two high voltage input terminals are different.

[0051] In at least one embodiment of the present disclosure, the first high voltage input terminal VH1 may provide a first high voltage signal, and the second high voltage input terminal VH2 may provide a second high voltage signal.

[0052] In at least one embodiment of the present disclosure, the first high voltage signal may be provided by the first high voltage line VGH, and the second high voltage signal may be provided by the second high voltage line VGH2.

[0053] In a specific implementation, when the transistors in the second output circuit 21 are p-type transistors, the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be smaller than that of the high voltage signal provided by the second high voltage input terminal, so that when the transistor in the pull-up node control circuit 22 is turned on, the transistor in the second output circuit 21 can be better turned off;

[0054] When the transistors included in the second output circuit 21 are n-type transistors, the voltage value of the high-voltage signal provided from the first high-voltage input terminal can be set to be greater than the voltage value of the high-voltage signal provided from the second high-voltage input terminal, so that when the transistor included in the pull-up node control circuit 22 is turned on, the transistor included in the second output circuit 21 can be better turned off;

[0055] However, this is not limited to that.

[0056] In at least one embodiment of the present disclosure, the driver circuit further comprises a third node reset circuit;

[0057] The third node reset circuit is electrically connected to a reset line, a third high-voltage input terminal, and a third node, respectively, and is configured to control the connection of the third high-voltage input terminal and the third node under the control of a reset signal provided by the reset line;

[0058] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0059] As in Fig. 3, the driver circuit described in at least one embodiment of the present disclosure may be based on at least one embodiment of the Fig. 2 further comprise a third node reset circuit 31;

[0060] The third node reset circuit 31 is electrically connected to the reset line VEL, the third high-voltage input terminal VH3, and the third node N3, respectively, and is configured to control the connection of the third high-voltage input terminal VH3 and the third node N3 under the control of a reset signal provided from the reset line VEL.

[0061] In at least one in Fig. 3, the third high voltage input terminal VH3 may be configured to provide the second high voltage signal, or the third high voltage input terminal VH3 may be configured to provide the first high voltage signal, but not limited thereto.

[0062] In at least one embodiment of the present disclosure, the voltage value of the first low-voltage signal may be greater than the voltage value of the second low-voltage signal; or the voltage value of the first low-voltage signal may be less than the voltage value of the second low-voltage signal;

[0063] The voltage value of the first high-voltage signal may be greater than the voltage value of the second high-voltage signal; or the voltage value of the first high-voltage signal may be smaller than the voltage value of the second high-voltage signal.

[0064] The driver circuit described in at least one embodiment of the present disclosure further comprises a pull-up node control circuit;

[0065] The pull-up node control circuit is electrically connected to the third node, the second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of the potential of the third node;

[0066] The second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

[0067] The driver circuit described in at least one embodiment of the present disclosure further comprises a pull-up node control circuit;

[0068] The pull-up node control circuit is electrically connected to the third node, the second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of the potential of the third node;

[0069] The second high voltage input terminal is different from the third high voltage input terminal.

[0070] As in Fig. 4, the driver circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 3 further comprises a pull-up node control circuit 22;

[0071] The pull-up node control circuit 22 is electrically connected to the third node N3, the second high-voltage input terminal VH2, and the pull-up node PU, respectively, and is configured to control the connection of the second high-voltage input terminal VH2 and the pull-up node PU under the control of the potential of the third node N3;

[0072] The second high voltage input terminal VH2 is different from at least one of the first high voltage input terminal VH1, the fourth high voltage input terminal VH4 and the third high voltage input terminal VH3.

[0073] In a specific implementation, the fourth high voltage input terminal VH4 may provide, but is not limited to, the first high voltage signal or the second high voltage signal.

[0074] In at least one embodiment of the present disclosure, the driver circuit further comprises a pull-down node control circuit;

[0075] The pull-down node control circuit is electrically connected to a fourth low-voltage input terminal, a third node, and the pull-down node, respectively, and is configured to control the connection of the third node and the pull-down node under the control of the fourth low-voltage signal provided by the fourth low-voltage input terminal;

[0076] The fourth low-voltage input terminal is different from at least one of the first low-voltage input terminal, the second low-voltage input terminal, and the third low-voltage input terminal.

[0077] As in Fig. 5, the driver circuit described in at least one embodiment of the present disclosure comprises, based on at least one embodiment of the Fig. 4 further comprises a pull-down node control circuit 51;

[0078] The pull-down node control circuit 51 is electrically connected to the fourth low-voltage input terminal VL4, the third node N3, and the pull-down node PD, respectively, and is configured to control the connection of the third node N3 and the pull-down node PD under the control of the fourth low-voltage signal provided from the fourth low-voltage input terminal VL4;

[0079] The fourth low-voltage input terminal VL4 is different from at least one of the first low-voltage input terminal VL1, the second low-voltage input terminal VL2 and the third low-voltage input terminal VL3.

[0080] In at least one embodiment of the present disclosure, the fourth low voltage input terminal VL4 may provide, but is not limited to, a first low voltage signal or a second low voltage signal.

[0081] In at least one embodiment of the present disclosure, the driver circuit further comprises a fifth node control circuit and a pull-up node control circuit;

[0082] The fifth node control circuit is electrically connected to the second node, a fifth node, and a second clock signal line, respectively, and is configured to control the connection of the second clock signal line and the fifth node under the control of the potential of the second node and to control a potential of the fifth node according to the potential of the second node;

[0083] The pull-up node control circuit is also electrically connected to a fifth node, a second clock signal line, and the pull-up node, respectively, and configured to control the connection of the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node under the control of the second clock signal provided by the second clock signal line.

[0084] In a specific implementation, the driver circuit further comprises a fifth node control circuit, wherein the fifth node control circuit is configured to control a potential of the fifth node, and the pull-up node control circuit is configured to control the potential of the pull-up node.

[0085] In at least one embodiment of the present disclosure, the driver circuit further comprises a third node control circuit;

[0086] The third node control circuit is electrically connected to a star voltage terminal, the first clock signal line, and the third node, respectively, and is configured to control the connection of the star voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line;

[0087] The first node control circuit is also electrically connected to the third node, the first node, and the first clock signal line, respectively, and is configured to control the connection of the first node and the first clock signal line under the control of the potential of the third node;

[0088] The fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line, respectively, and is configured to control the connection of the fourth node and the second clock signal line under the control of the potential of the pull-down node and to control the potential of the fourth node according to the potential of the pull-down node.

[0089] In a specific implementation, the driver circuit further comprises a third node control circuit, wherein the third node control circuit controls the potential of the third node, the first node control circuit controls the potential of the first node, and the fourth node control circuit controls the potential of the fourth node.

[0090] As in Fig. 6 based on at least one embodiment of the Fig. 5, the driver circuit further comprises a fifth node control circuit 71 and a third node control circuit 72;

[0091] The fifth node control circuit 71 is electrically connected to the second node N2, the fifth node N5, and the second clock signal line CB, respectively, and is configured to control the connection of the second clock signal line CB and the fifth node N5 under the control of the potential of the second node N2 and to control the potential of the fifth node N5 according to the potential of the second node N2;

[0092] The pull-up node control circuit 22 is also electrically connected to the fifth node N5, the second clock signal line CB, and the pull-up node PU, respectively, and is configured to control the connection of the fifth node N5 and the pull-up node PU under the control of the second clock signal provided by the second clock signal line CB and maintain the potential of the pull-up node PU;

[0093] The third node control circuit 72 is electrically connected to the start voltage terminal STV, the first clock signal line CK, and the third node N3, respectively, and is configured to control the connection of the start voltage terminal STV and the third node N3 under the control of the first clock signal provided from the first clock signal line CK;

[0094] The first node control circuit 11 is also electrically connected to the third node N3, the first node N1 and the first clock signal line CK, respectively, and is configured to control the connection of the first node N1 and the first clock signal line CK under the control of the potential of the third node N3;

[0095] The fourth node control circuit 41 is also electrically connected to the pull-down node PD and the second clock signal line CB, respectively, and is configured to control the connection of the fourth node N4 and the second clock signal line CB under the control of the potential of the pull-down node PD and to control the potential of the fourth node N4 according to the potential of the pull-down node PD.

[0096] Optionally, the first node control circuit comprises a first transistor and the second node control circuit comprises a second transistor;

[0097] A control electrode of the first transistor is electrically connected to the first clock signal line, a first electrode of the first transistor is electrically connected to the second low voltage input terminal, and a second electrode of the first transistor is electrically connected to the first node;

[0098] A control electrode of the second transistor is electrically connected to the first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node;

[0099] The first output circuit includes an output reset transistor;

[0100] A control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.

[0101] Optionally, the second output circuit comprises an output transistor, and the pull-up node control circuit comprises a third transistor and a first capacitor;

[0102] A control electrode of the output transistor is electrically connected to the pull-up node, a first electrode of the output transistor is electrically connected to the first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0103] A control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node;

[0104] A first electrode plate of the first capacitor is electrically connected to the pull-up node, and a second electrode plate of the first capacitor is electrically connected to the first high-voltage input terminal.

[0105] Optionally, the third node reset circuit includes a fourth transistor;

[0106] A control electrode of the fourth transistor is electrically connected to the reset line, a first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and a second electrode of the fourth transistor is electrically connected to the third node.

[0107] Optionally, the fourth node control circuit comprises a fifth transistor;

[0108] A control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and a second electrode of the fifth transistor is electrically connected to the fourth node.

[0109] Optionally, the pull-down node control circuit includes a sixth transistor;

[0110] A control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node.

[0111] Optionally, the fifth node control circuit comprises a seventh transistor and a second capacitor; the pull-up node control circuit further comprises an eighth transistor;

[0112] A control electrode of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the second clock signal line, and a second electrode of the seventh transistor is electrically connected to a fifth node;

[0113] A first electrode plate of the second capacitor is electrically connected to the second node, and a second electrode plate of the second capacitor is electrically connected to the fifth node;

[0114] A control electrode of the eighth transistor is electrically connected to the second clock signal line, a first electrode of the eighth transistor is electrically connected to the fifth node, and a second electrode of the eighth transistor is electrically connected to the pull-up node.

[0115] Optionally, the first node control circuit further comprises a ninth transistor;

[0116] A control electrode of the ninth transistor is electrically connected to the third node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first node;

[0117] The fourth node control circuit further comprises a tenth transistor and a third capacitor;

[0118] A control electrode of the tenth transistor is electrically connected to the pull-down node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the fourth node;

[0119] A first electrode plate of the third capacitor is electrically connected to the pull-down node, and a second electrode plate of the third capacitor is electrically connected to the fourth node;

[0120] The third node control circuit includes an eleventh transistor;

[0121] A control electrode of the eleventh transistor is electrically connected to the first clock signal line, a first electrode of the eleventh transistor is electrically connected to the start voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the third node.

[0122] As in Fig. 7 based on at least one embodiment of the Fig. 6, the first node control circuit comprises a first transistor T1 and the second node control circuit comprises a second transistor T2;

[0123] The gate electrode of the first transistor T1 is electrically connected to the first clock signal line CK, the source electrode of the first transistor T1 is electrically connected to the second low-voltage input terminal VL2, and the drain electrode of the first transistor T1 is electrically connected to the first node N1;

[0124] The gate electrode of the second transistor T2 is electrically connected to the first low-voltage input terminal VL1, the source electrode of the second transistor T2 is electrically connected to the first node N1, and the drain electrode of the second transistor T2 is electrically connected to the second node N2;

[0125] The first output circuit comprises an output reset transistor Tf;

[0126] The gate electrode of the output reset transistor Tf is electrically connected to the pull-down node PD, the source electrode of the output reset transistor Tf is electrically connected to the drive signal output terminal O1, and the drain electrode of the output reset transistor Tf is connected to the third low-voltage input terminal VL3;

[0127] The second output circuit comprises an output transistor To, and the pull-up node control circuit comprises a third transistor T3 and a first capacitor C1;

[0128] The gate electrode of the output transistor To is electrically connected to the pull-up node PU, the source electrode of the output transistor To is electrically connected to the first high-voltage input terminal VH1, and the drain electrode of the output transistor To is connected to the drive signal output terminal O1;

[0129] The gate electrode of the third transistor T3 is electrically connected to the third node N3, the source electrode of the third transistor T3 is electrically connected to the second high-voltage input terminal VH2, and the drain electrode of the third transistor T3 is electrically connected to the pull-up node PU;

[0130] The first electrode plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second electrode plate of the first capacitor C1 is electrically connected to the first high-voltage input terminal VH1;

[0131] The third node reset circuit includes a fourth transistor T4;

[0132] The gate electrode of the fourth transistor T4 is electrically connected to the reset line VEL, the source electrode of the fourth transistor T4 is electrically connected to the third high-voltage input terminal VH3, and the drain electrode of the fourth transistor T4 is electrically connected to the third node N3;

[0133] The fourth node control circuit comprises a fifth transistor T5;

[0134] The gate electrode of the fifth transistor T5 is electrically connected to the first node N1, the source electrode of the fifth transistor T5 is electrically connected to the fourth high-voltage input terminal VH4, and the drain electrode of the fifth transistor T5 is electrically connected to the fourth node N4;

[0135] The pull-down node control circuit includes a sixth transistor T6;

[0136] The gate electrode of the sixth transistor T6 is electrically connected to the fourth low-voltage input terminal VL4, the source electrode of the sixth transistor T6 is electrically connected to the third node N3, and the drain electrode of the sixth transistor T6 is electrically connected to the pull-down node PD;

[0137] The fifth node control circuit comprises a seventh transistor T7 and a second capacitor C2; the pull-up node control circuit further comprises an eighth transistor T8;

[0138] The gate electrode of the seventh transistor T7 is electrically connected to the second node N2, the source electrode of the seventh transistor T7 is electrically connected to the second clock signal line CB, and the drain electrode of the seventh transistor T7 is electrically connected to the fifth node N5;

[0139] The first electrode plate of the second capacitor C2 is electrically connected to the second node N2, and the second electrode plate of the second capacitor C2 is electrically connected to the fifth node N5;

[0140] The gate electrode of the eighth transistor T8 is electrically connected to the second clock signal line CB, the source electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and the drain electrode of the eighth transistor T8 is electrically connected to the pull-up node PU;

[0141] The first node control circuit further comprises a ninth transistor T9;

[0142] The gate electrode of the ninth transistor T9 is electrically connected to the third node N3, the source electrode of the ninth transistor T9 is electrically connected to the first clock signal line CK, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1;

[0143] The fourth node control circuit further comprises a tenth transistor T10 and a third capacitor C3;

[0144] The gate electrode of the tenth transistor T10 is electrically connected to the pull-down node PD, the source electrode of the tenth transistor T10 is electrically connected to the second clock signal line CB, and the drain electrode of the tenth transistor T10 is electrically connected to the fourth node N4;

[0145] The first electrode plate of the third capacitor C3 is electrically connected to the pull-down node PD, and the second electrode plate of the third capacitor C3 is electrically connected to the fourth node N4;

[0146] The third node control circuit comprises an eleventh transistor T11;

[0147] The gate electrode of the eleventh transistor T11 is electrically connected to the first clock signal line CK, the source electrode of the eleventh transistor T11 is electrically connected to the start voltage terminal STV, and the drain electrode of the eleventh transistor T11 is electrically connected to the third node N3.

[0148] In at least one embodiment of the Fig. In the driver circuit shown in Figure 7, all transistors are p-type transistors, but not limited to this. In actual operation, the transistors can be Fig. 7 can also be n-type transistors.

[0149] In at least one embodiment of the Fig. In the driver circuit shown in Figure 7, the first low-voltage input terminal VL1 may provide a first low-voltage signal, the second low-voltage input terminal VL2 may provide a second low-voltage signal, the third low-voltage input terminal VL3 may provide the first low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the first low-voltage signal; or,

[0150] The first low-voltage input terminal VL1 may provide the second low-voltage signal, the second low-voltage input terminal VL2 may provide the second low-voltage signal, the third low-voltage input terminal VL3 may provide the first low-voltage signal, and the fourth low-voltage input terminal VL4 may provide a second low-voltage signal; or,

[0151] The first low-voltage input terminal VL1 may provide the first low-voltage signal, the second low-voltage input terminal VL2 may provide the first low-voltage signal, the third low-voltage input terminal VL3 may provide the first low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the second low-voltage signal; or,

[0152] The first low-voltage input terminal VL1 may provide the second low-voltage signal, the second low-voltage input terminal VL2 may provide the first low-voltage signal, the third low-voltage input terminal VL3 may provide the first low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the first low-voltage signal; or,

[0153] The first low-voltage input terminal VL1 may provide the second low-voltage signal, the second low-voltage input terminal VL2 may provide the first low-voltage signal, the third low-voltage input terminal VL3 may provide the first low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the second low-voltage signal; or,

[0154] The first low-voltage input terminal VL1 may provide the second low-voltage signal, the second low-voltage input terminal VL2 may provide the second low-voltage signal, the third low-voltage input terminal VL3 may provide the second low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the first low-voltage signal; or,

[0155] The first low-voltage input terminal VL1 may provide the first low-voltage signal, the second low-voltage input terminal VL2 may provide the second low-voltage signal, the third low-voltage input terminal VL3 may provide the second low-voltage signal, and the fourth low-voltage input terminal VL4 may provide the first low-voltage signal; or,

[0156] The first low voltage input terminal VL1 can provide the first low voltage signal, the second low voltage input terminal VL2 can provide the first low voltage signal, the third low voltage input terminal VL3 can provide the second low voltage signal, and the fourth low voltage input terminal VL4 can provide the first low voltage signal;

[0157] But not limited to this.

[0158] In at least one embodiment of the Fig. 7 shown driver circuit,

[0159] The first high-voltage input terminal VH1 may provide the first high-voltage signal, the second high-voltage input terminal VH2 may provide the second high-voltage signal, the third high-voltage input terminal VH3 may provide the second high-voltage signal, and the fourth high-voltage input terminal VH4 may provide the first high-voltage signal; or,

[0160] The first high-voltage input terminal VH1 may provide the first high-voltage signal, the second high-voltage input terminal VH2 may provide the second high-voltage signal, the third high-voltage input terminal VH3 may provide the first high-voltage signal, and the fourth high-voltage input terminal VH4 may provide the first high-voltage signal; or,

[0161] The first high-voltage input terminal VH1 can provide the first high-voltage signal, the second high-voltage input terminal VH2 can provide the second high-voltage signal, the third high-voltage input terminal VH3 can provide the first high-voltage signal, and the fourth high-voltage input terminal VH4 can provide the second high-voltage signal; or,

[0162] The first high-voltage input terminal VH1 can provide the second high-voltage signal, the second high-voltage input terminal VH2 can provide the first high-voltage signal, the third high-voltage input terminal VH3 can provide the second high-voltage signal, and the fourth high-voltage input terminal VH4 can provide the first high-voltage signal; or,

[0163] The first high-voltage input terminal VH1 may provide the second high-voltage signal, the second high-voltage input terminal VH2 may provide the first high-voltage signal, the third high-voltage input terminal VH3 may provide the first high-voltage signal, and the fourth high-voltage input terminal VH4 may provide the first high-voltage signal; or,

[0164] The first high voltage input terminal VH1 can provide the second high voltage signal, the second high voltage input terminal VH2 can provide the first high voltage signal, the third high voltage input terminal VH3 can provide the first high voltage signal, and the fourth high voltage input terminal VH4 can provide the second high voltage signal;

[0165] But not limited to this.

[0166] As in Fig. 8A, based on at least one embodiment of the Fig. In the driver circuit shown in Figure 7, the first low-voltage input terminal VL1 provides a first low-voltage signal, and the second low-voltage input terminal VL2 provides a second low-voltage signal, the third low-voltage input terminal VL3 provides the first low-voltage signal, and the fourth low-voltage input terminal VL4 provides the first low-voltage signal; the first low-voltage signal is provided by the first low-voltage line VGL, and the second low-voltage signal is provided by the second low-voltage line VGL2;

[0167] The first high-voltage input terminal VH1 provides the first high-voltage signal, the second high-voltage input terminal VH2 provides the second high-voltage signal, the third high-voltage input terminal VH3 provides the second high-voltage signal, and the fourth high-voltage input terminal VH4 provides the first high-voltage signal; the first high-voltage signal is provided by the first high-voltage line VGH, and the second high-voltage signal is provided by the second high-voltage line VGH2.

[0168] If at least one embodiment of the Fig. 8A of the present disclosure is in operation, the voltage value of the second low-voltage signal provided by VGL2 may be smaller than the voltage value of the first low-voltage signal provided by VGL. For example, when the voltage value of the first low-voltage signal provided by VGL is -6V, the voltage value of the second low-voltage signal provided by VGL2 may be -6.5V. Since the p-type transistor has a threshold voltage loss when passing through a low level, the voltage value thereof may be set to be lower than this, so that when T1 and T2 are turned on, the potential of N1 and the potential of N2 may be lower, so that the pull-up node PU is turned on faster and the delay of the drive signal output from O1 is smaller.

[0169] In at least one embodiment of the present disclosure, the difference between the voltage value of the second low voltage signal and the voltage value of the first low voltage signal may be slightly greater than or equal to the threshold voltage of the p-type transistor.

[0170] At least one embodiment of the Fig. The driver circuit of the present disclosure shown in Figure 8A accepts two high voltage input terminals and two low voltage input terminals;

[0171] When low-frequency display is performed, the voltage value of the high-voltage signal provided from a high-voltage input terminal and the absolute value of the voltage value of the low-voltage signal provided from a low-voltage input terminal may be appropriately reduced to reduce power consumption;

[0172] For example, when performing low frequency display, the voltage value of the first high voltage signal and the voltage value of the first low voltage signal can be controlled to remain unchanged, but the voltage value of the second high voltage signal is reduced from 7V to 6V, and the voltage value of the second low voltage signal is adjusted from -7V to -6V to reduce power consumption.

[0173] At least one embodiment of the Fig. The driver circuit of the present disclosure shown in Fig. 8A can increase the voltage value of the second high voltage signal from 7 V to 10 V and adjust the voltage value of the second low voltage signal from -7 V to -10 V to improve the on-off capability of To and Tf.

[0174] As in Fig. 9, based on at least one embodiment of the method described in Fig. In the driver circuit shown in Figure 7, the first low-voltage input terminal VL1 provides a second low-voltage signal, and the second low-voltage input terminal VL2 provides a second low-voltage signal, the third low-voltage input terminal VL3 provides a first low-voltage signal, and the fourth low-voltage input terminal VL4 provides a second low-voltage signal; the first low-voltage signal is provided by the first low-voltage line VGL, and the second low-voltage signal is provided by the second low-voltage line VGL2;

[0175] The first high-voltage input terminal VH1 provides the first high-voltage signal, the second high-voltage input terminal VH2 provides the second high-voltage signal, the third high-voltage input terminal VH3 provides the second high-voltage signal, and the fourth high-voltage input terminal VH4 provides the first high-voltage signal; the first high-voltage signal is provided by the first high-voltage line VGH, and the second high-voltage signal is provided by the second high-voltage line VGH2.

[0176] In at least one embodiment of the present disclosure, the voltage value of VGH2 may be greater than the voltage value of VGH1 to compensate for leakage current effects caused by threshold voltage drift, but the present disclosure is not so limited.

[0177] In at least one embodiment of the Fig. In the driver circuit shown in Figure 9, the gate electrode of T2 and the gate electrode of T6 are both electrically connected to the second low-voltage line VGL2, which provides the second low-voltage signal, which facilitates the layout and improves space utilization.

[0178] The difference between at least one embodiment of the Fig. 10 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 8A of the present disclosure is that T4 is not provided.

[0179] The difference between at least one embodiment of the Fig. 11 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 9 of the present disclosure is that T4 is not provided.

[0180] The difference between at least one embodiment of the Fig. 12 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 8A of the present disclosure is that the source electrode of T3 is electrically connected to the second high voltage line VGH2 and the source electrode of T3 is electrically connected to the first high voltage line VGH.

[0181] The difference between at least one embodiment of the Fig. 13 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 12 of the present disclosure is that the source electrode of T4 is electrically connected to the first high voltage line VGH.

[0182] The difference between at least one embodiment of the Fig. 14 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 13 of the present disclosure is that the source electrode of T5 is electrically connected to the second high voltage line VGH2.

[0183] The difference between at least one embodiment of the Fig. 15 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 14 of the present disclosure is that the source electrode of T4 is electrically connected to the second high voltage line VGH2.

[0184] The difference between at least one embodiment of the Fig. 16 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 12 of the present disclosure is that the gate electrodes of T2 and T6 are both electrically connected to the second low voltage line VGL2.

[0185] The difference between at least one embodiment of the Fig. 17 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 16 of the present disclosure is that the gate electrode of T2 is electrically connected to the first low voltage line VGL.

[0186] The difference between at least one embodiment of the Fig. 18 of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 16 of the present disclosure is that the gate electrode of T6 is electrically connected to the first low voltage line VGL.

[0187] The difference between at least one embodiment of the Fig. 19A of the present disclosure and at least one embodiment of the driver circuit shown in Fig. 15 of the present disclosure is that T4 is not included.

[0188] The driver circuit described in at least one embodiment of the present disclosure includes a second output circuit and a pull-up node control circuit;

[0189] The second output circuit is electrically connected to the pull-up node, the first high-voltage input terminal, and the drive signal output terminal, respectively, and is configured to control the connection of the first high-voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;

[0190] The pull-up node control circuit is electrically connected to the third node, the second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of the potential of the third node;

[0191] The first high voltage input terminal is different from the second high voltage input terminal.

[0192] In at least one embodiment of the present disclosure, the driver circuit further comprises a third node reset circuit;

[0193] The third node reset circuit is electrically connected to the reset line, the third high-voltage input terminal, and the third node, respectively, and is configured to control the connection of the third high-voltage input terminal and the third node under the control of the reset signal provided by the reset line;

[0194] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0195] In at least one embodiment of the present disclosure, the driver circuit further comprises a fourth node control circuit;

[0196] The fourth node control circuit is electrically connected to the first node, the fourth node, and the fourth high-voltage input terminal, respectively, and configured to control the connection of the fourth node and the fourth high-voltage input terminal under the control of the potential of the first node;

[0197] The fourth high-voltage input terminal is different from at least one of the first high-voltage input terminal and the second high-voltage input terminal.

[0198] In at least one embodiment of the present disclosure, the driver circuit further comprises a fourth node control circuit;

[0199] The fourth node control circuit is electrically connected to the first node, the fourth node, and the fourth high-voltage input terminal, respectively, and configured to control the connection of the fourth node and the fourth high-voltage input terminal under the control of the potential of the first node;

[0200] The fourth high voltage input terminal is different from the third high voltage input terminal.

[0201] An embodiment of the present disclosure also provides a display panel including the above driver circuit; the display panel further includes a display driver chip;

[0202] The first high-voltage input terminal is electrically connected to the first high-voltage line, and the second high-voltage input terminal is electrically connected to the second high-voltage line; the first high-voltage line and the second high-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to supply the first high-voltage signal to the first high-voltage line, and the display driver chip is configured to supply the second high-voltage signal to the second high-voltage line.

[0203] In the display panel described in the embodiment of the present disclosure, the first high-voltage input terminal is electrically connected to the first high-voltage line, the second high-voltage input terminal is electrically connected to the second high-voltage line, and the first high-voltage line is electrically connected to the first pin of the display driver chip, the second high-voltage line is electrically connected to the second pin of the display driver chip, and the display driver chip supplies the first high-voltage signal to the first high-voltage line via the first pin, and the display driver chip supplies a second high-voltage signal to the second high-voltage line via a second pin.

[0204] As in Fig. 19B, the display panel includes a display driver chip 320;

[0205] The first high-voltage input terminal VH1 is electrically connected to the first high-voltage line LH1, and the second high-voltage input terminal VH2 is electrically connected to the second high-voltage line LH2;

[0206] The first high voltage line LH1 is electrically connected to the first pin P1 of the display driver chip 320, and the second high voltage line LH2 is electrically connected to the second pin P2 of the display driver chip 320;

[0207] The display driver chip 320 is configured to supply the first high voltage signal to the first high voltage line LH1, and the display driver chip 320 is configured to supply the second high voltage signal to the second high voltage line LH2.

[0208] As in Fig. 20, the relevant pixel circuit includes a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor C0, and an organic light-emitting diode E1;

[0209] In Fig. 20, the line labeled EM is the light-emitting control line, the line labeled R1 is the first reset control line, the line labeled R2 is the second reset control line, the line labeled NG is the first scan line, and the line labeled PG is the second scan line, the voltage labeled Vi1 is the first initial voltage, the voltage labeled Vi2 is the second initial voltage, the voltage labeled Vi3 is the third initial voltage, the line labeled VDD is the high level terminal, and the line labeled VSS is the low level terminal.

[0210] The driver circuit described in at least one embodiment of the present disclosure may be configured to provide the first scan signal to the first scan line NG, provide the light emitting control signal to the light emitting control line EM, provide the first reset control signal to the first reset control line R1, and provide a second reset control signal to the second reset control line R2.

[0211] The driver circuit described in at least one embodiment of the present disclosure includes a first transistor, a second transistor, an output reset transistor, and a sixth transistor;

[0212] A control electrode of the first transistor is electrically connected to the first clock signal line, a first electrode of the first transistor is electrically connected to the second low voltage input terminal, and a second electrode of the first transistor is electrically connected to the first node;

[0213] A control electrode of the second transistor is electrically connected to the first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node;

[0214] The first output circuit comprises an output reset transistor, wherein a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low-voltage input terminal;

[0215] A control electrode of the sixth transistor is electrically connected to the fourth low-voltage input terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node;

[0216] The first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the fourth low voltage input terminal are not completely the same.

[0217] In at least one embodiment of the present disclosure, the first low-voltage input terminal VL1, the second low-voltage input terminal VL2, the third low-voltage input terminal VL3, and the fourth low-voltage input terminal VL4 are not entirely equal, as follows: VL1 and VL2 are not the same; or, VL1 and VL3 are not the same; or, VL1 and VL4 are not the same; or, VL2 and VL3 are not the same; or, VL2 and VL4 are not the same; or, VL3 and VL4 are not the same; or, VL1, VL2 and VL3 are different from each other; or, VL1, VL2 and VL4 are different from each other; or, VL1, VL3 and VL4 are different from each other; or, VL2, VL3 and VL4 are different from each other; or, VL1, VL2, VL3 and VL4 are different from each other.

[0218] The driver circuit described in at least one embodiment of the present disclosure comprises an output transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0219] A control electrode of the output transistor is electrically connected to the pull-up node, a first electrode of the output transistor is electrically connected to the first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0220] A control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node;

[0221] A control electrode of the fourth transistor is electrically connected to the reset line, a first electrode of the fourth transistor is electrically connected to the third high-voltage input terminal, and a second electrode of the fourth transistor is electrically connected to the third node;

[0222] A control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth high-voltage input terminal, and a second electrode of the fifth transistor is electrically connected to the fourth node;

[0223] The first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.

[0224] In at least one embodiment of the present disclosure, the first high-voltage input terminal VH1, the second high-voltage input terminal VH2, the third high-voltage input terminal VH3, and the fourth high-voltage input terminal VH4 are not entirely the same, as follows: VH1 and VH2 are not the same; or, VH1 and VH3 are not the same; or, VH1 and VH4 are not the same; or, VH2 and VH3 are not the same; or, VH2 and VH4 are not the same; or, VH3 and VH4 are not the same; or, VH1, VH2 and VH3 are different from each other; or, VH1, VH2 and VH4 are different from each other; or, VH1, VH3 and VH4 are different from each other; or, VH2, VH3 and VH4 are different from each other; or, VH1, VH2, VH3 and VH4 are different from each other.

[0225] The display substrate described in the embodiment of the present disclosure includes a base substrate and the above-described driving circuit disposed on the base substrate.

[0226] Optionally, the driver circuit comprises a first low-voltage line, a second low-voltage line, a first high-voltage line, a second high-voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit;

[0227] The second low-voltage line is arranged on a side of the driver circuit remote from a display area, and the first low-voltage line is arranged on a side of the driver circuit close to the display area;

[0228] The first high-voltage line and the second high-voltage line are arranged between a first circuit part included in the driver circuit and a second circuit part included in the driver circuit;

[0229] The first circuit part comprises a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit, the second circuit part comprises a first output circuit and a second output circuit;

[0230] The first circuit part is arranged between the second low-voltage line and the second high-voltage line, and the second circuit part is arranged between the first high-voltage line and the first low-voltage line, so that the electrodes of the transistors in the driver circuit are electrically connected to corresponding voltage lines.

[0231] In at least one embodiment of the present disclosure, the driver circuit further comprises a third node reset circuit, and the first circuit portion comprises the third node reset circuit. Fig. 21 is a layout diagram of the Fig. 15 shown driver circuit of at least one embodiment of the present disclosure.

[0232] Fig. 22 is a layout diagram of the active layer in Fig. 21, Fig. 23 is a layout diagram of the first gate metal layer in Fig. 21, Fig. 24 is a layout diagram of the second gate metal layer in Fig. 21, Fig. 25 is a layout diagram of the source-drain metal layer in Fig. 21.

[0233] In Fig. 21 and Fig. 25, the line labeled ESTV is the start signal line, the line labeled CB is the second clock signal line, the line labeled CK is the first clock signal line, the line labeled VEL is the reset line, the line labeled VGL2 is the first low voltage line, the line labeled VGH2 is the second high voltage line, the line labeled VGH is the first high voltage line and the line labeled VGL is the first low voltage line.

[0234] As in Fig. 21, the start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL, the second low voltage line VGL2, the second high voltage line VGH2, the first high voltage line VGH and the first low voltage line VGL all extend in the vertical direction;

[0235] The start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged on the side of the driver circuit remote from the display area;

[0236] The start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged in a direction close to the display area.

[0237] The first low-voltage line VGL is arranged on the side of the driver circuit close to the display area;

[0238] As in Fig. 25, the first high-voltage line VGH is connected to the first electrode So of To, and the second high-voltage line VGH2 is arranged on the side of the first high-voltage line VGH remote from To;

[0239] The first low-voltage line VGL is connected to the second electrode Df of Tf.

[0240] In at least one embodiment according to Fig. 21, the driver circuit comprises a first circuit part and a second circuit part; the first circuit part comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; the second circuit part comprises an output transistor To and an output reset transistor Tf;

[0241] The first circuit part is arranged between the second low-voltage line VGL2 and the second high-voltage line VGH2, and the second circuit part is arranged between the second high-voltage line VGH2 and the first low-voltage line VGL.

[0242] As in Fig. As shown in Figures 21-25, T2 and T6 are adjacent to VGL2, which facilitates the electrical connection of the gate electrode G2 of T2 and the gate electrode G6 of T6 to VGL;

[0243] T1 is adjacent to VGL2, so the first electrode of T1 is electrically connected to VGL2.

[0244] In Fig. 23, the electrode labeled G1 is the gate electrode of T1, the electrode labeled G2 is the gate electrode of T2, the electrode labeled G3 is the gate electrode of T3, the electrode labeled G4 is the gate electrode of T4, and the electrode labeled G5 is the gate electrode of T5, the electrode labeled G6 is the gate electrode of T6, the electrode labeled G7 is the gate electrode of T7, the electrode labeled G8 is the gate electrode of T8, the electrode labeled G9 is the gate electrode of T9, the electrode labeled G10 is the gate electrode of T10, the electrode labeled G11 is the gate electrode of T11, the electrode labeled Go is the gate electrode of To and the electrode labeled Gf is the gate electrode of Tf;

[0245] In Fig. 23, the electrode plate labelled C2a is the first electrode plate of C2, and in Fig. 24, the electrode plate designated C2b is the second electrode plate of C2;

[0246] In Fig. 23, the electrode plate labelled C3a is the first electrode plate of C3, and in Fig. 24, the electrode plate designated C3b is the second electrode plate of C3;

[0247] In Fig. 23, the electrode plate designated C1a is the first electrode plate of C1, and in Fig. 24, the electrode plate labeled C1b is the second electrode plate of C2.

[0248] As in the Fig. As shown in Figures 21-25, the gate electrode G4 of T4 is electrically connected to VEL, the first electrode of T4 is electrically connected to VGH2 via a through-hole, and the first electrode of T5 is electrically connected to VGH2 via a through-hole.

[0249] In Fig. 22, the pattern labeled A1 is the active layer pattern of T1, the pattern labeled A2 is the active layer pattern of T2, the pattern labeled A3 is the active layer pattern of T3, the pattern labeled A4 is the active layer pattern of T4, the pattern labeled A5 is the active layer pattern of T5, the pattern labeled A6 is the active layer pattern of T6, the pattern labeled A7 is the active layer pattern of T7, and the pattern labeled A8 is the active layer pattern of T8, the pattern labeled A9 is the active layer pattern of T9, the pattern labeled A10 is the active layer pattern of T10, the pattern labeled A11 is the active layer pattern of T11, and the pattern labeled A0 is the first active layer pattern;

[0250] The first active layer pattern A0 includes an active layer pattern of To and an active layer pattern of Tf.

[0251] Fig. 26 is a layout diagram of the Fig. 19 of at least one embodiment of the present disclosure.

[0252] The difference between the Fig. 26 and at least one embodiment of the layout shown in Fig. The difference in the driver circuit shown in Figure 21 is that T4 is not provided.

[0253] Fig. 27 is a layout diagram of the active layer in Fig. 26, Fig. 28 is a layout diagram of the first gate metal layer in Fig. 26, Fig. 29 is a layout diagram of the second gate metal layer in Fig. 26, Fig. 30 is a layout diagram of the source-drain metal layer in Fig. 26.

[0254] The display panel described in the embodiment of the present disclosure includes the driver circuit described above; the display panel further includes a display driver chip;

[0255] The first low-voltage input terminal is electrically connected to the first low-voltage line, the second low-voltage input terminal is electrically connected to the second low-voltage line, the third low-voltage input terminal is electrically connected to the third low-voltage line, and the first low-voltage line, the second low-voltage line, and the third low-voltage line are electrically connected to each other, and the third low-voltage line is electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line, provide the second low-voltage signal to the second low-voltage line, and provide the third low-voltage signal to the third low-voltage line; or,

[0256] The first low-voltage input terminal is electrically connected to the first low-voltage line, the second low-voltage input terminal and the third low-voltage input terminal are both electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line; or,

[0257] Both the first low-voltage input terminal and the second low-voltage input terminal are electrically connected to the first low-voltage line, the third low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line; or,

[0258] Both the first low-voltage input terminal and the third low-voltage input terminal are electrically connected to the first low-voltage line, the second low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line.

[0259] As in Fig. 31, the display panel includes a display driver chip 320;

[0260] The first low-voltage input terminal VL1 is electrically connected to the first low-voltage line Ld1, the second low-voltage input terminal VL2 is electrically connected to the second low-voltage line Ld2, and the third low-voltage input terminal VL3 is electrically connected to the third low-voltage line Ld3, the first low-voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, the second low-voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320, and the third low-voltage line Ld3 is electrically connected to the third pin P3 of the display driver chip 320;

[0261] The display driver chip 320 is configured to provide the first low voltage signal to the first low voltage line Ld1, to provide the second low voltage signal to the second low voltage line Ld2, and to provide the third low voltage signal to the third low voltage line Ld3.

[0262] As in Fig. 32, the display panel includes a display driver chip 320;

[0263] The first low-voltage input terminal VL1 is electrically connected to the first low-voltage line Ld1, and the second low-voltage input terminal VL2 and the third low-voltage input terminal VL3 are both electrically connected to the second low-voltage line Ld2;

[0264] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;

[0265] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and to provide a second low voltage signal to the second low voltage line Ld2.

[0266] As in Fig. 33, the display panel includes a display driver chip 320;

[0267] Both the first low-voltage input terminal VL1 and the second low-voltage input terminal VL2 are electrically connected to the first low-voltage line Ld1, and the third low-voltage input terminal VL3 is electrically connected to the second low-voltage line Ld2;

[0268] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;

[0269] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and to provide a second low voltage signal to the second low voltage line Ld2.

[0270] As in Fig. 34, the display panel includes a display driver chip 320;

[0271] Both the first low-voltage input terminal VL1 and the third low-voltage input terminal VL3 are electrically connected to the first low-voltage line Ld1, and the second low-voltage input terminal VL2 is electrically connected to the second low-voltage line Ld2;

[0272] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;

[0273] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and to provide a second low voltage signal to the second low voltage line Ld2.

[0274] The display panel described in the embodiment of the present disclosure includes the driver circuit described above; the display panel further includes a display driver chip;

[0275] The first high-voltage input terminal is electrically connected to the first high-voltage line, and the second high-voltage input terminal is electrically connected to the second high-voltage line; the first high-voltage line and the second high-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first high-voltage signal to the first high-voltage line, and the display driver chip is configured to provide the second high-voltage signal to the second high-voltage line.

[0276] As in Fig. 35, the display panel includes a display driver chip 320;

[0277] Both the first low-voltage input terminal VL1 and the third low-voltage input terminal VL3 are electrically connected to the first low-voltage line Ld1, and the second low-voltage input terminal VL2 is electrically connected to the second low-voltage line Ld2;

[0278] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;

[0279] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and to provide a second low voltage signal to the second low voltage line Ld2.

[0280] The display device described in the embodiment of the present disclosure includes the driving circuit described above.

[0281] The display device provided by the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook, a digital photo frame, a navigation device, and the like.

[0282] The above descriptions are preferred embodiments of the present disclosure. It should be noted that those skilled in the art may make some improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications also fall within the scope of the present disclosure.

Claims

[1] A driver circuit comprising a first node control circuit, a second node control circuit and a first output circuit; wherein the second node control circuit is electrically connected to a first low-voltage input terminal, a first node, and a second node, respectively, and is configured to control the connection of the first node and the second node under the control of a low-voltage signal provided by the first low-voltage input terminal; the first node control circuit is electrically connected to a second low-voltage input terminal, a first clock signal line, and the first node, respectively, and is configured to control the connection of the first node and the second low-voltage input terminal under the control of a first clock signal provided by the first clock signal line; the first output circuit is electrically connected to a pull-down node, a drive signal output terminal, and a third low-voltage input terminal, respectively, and is configured to control the connection of the drive signal output terminal and the third low-voltage input terminal under the control of a potential of the pull-down node; at least two of the first low-voltage input terminal, the second low-voltage input terminal and the third low-voltage input terminal are different from each other. [2] The driver circuit of claim 1, further comprising a second output circuit and a fourth node control circuit; wherein the second output circuit is electrically connected to a pull-up node, a first high-voltage input terminal, and the drive signal output terminal, respectively, and is configured to control the connection of the first high-voltage input terminal and the drive signal output terminal under the control of a potential of the pull-up node; the fourth node control circuit is electrically connected to the first node, a fourth node, and a fourth high-voltage input terminal, respectively, and is configured to control the connection of the fourth node and the fourth high-voltage input terminal under the control of a potential of the first node; the first high-voltage input terminal is different from the fourth high-voltage input terminal. [3] The driver circuit of claim 2, further comprising a third node reset circuit; where the third node reset circuit is electrically connected to a reset line, a third high-voltage input terminal, and a third node, respectively, and is configured to control the connection of the third high-voltage input terminal and the third node under the control of a reset signal provided by the reset line; the third high-voltage input terminal is different from at least one of the first high-voltage input terminal and the fourth high-voltage input terminal. [4] The driver circuit of claim 2, further comprising a pull-up node control circuit; wherein the pull-up node control circuit is electrically connected to the third node, a second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of a potential of the third node; the second high-voltage input terminal is different from at least one of the first high-voltage input terminal and the fourth high-voltage input terminal. [5] The driver circuit of claim 3, further comprising a pull-up node control circuit; wherein the pull-up node control circuit is electrically connected to the third node, the second high-voltage input terminal, and the pull-up node, respectively, and is configured to control the connection of the second high-voltage input terminal and the pull-up node under the control of the potential of the third node; the second high-voltage input terminal is different from the third high-voltage input terminal. [6] Driver circuit according to one of claims 1 to 5, further comprising a pull-down node control circuit; wherein the pull-down node control circuit is electrically connected to a fourth low-voltage input terminal, a third node, and the pull-down node, respectively, and is configured to control the connection of the third node and the pull-down node under the control of a low-voltage signal provided by the fourth low-voltage input terminal; the fourth low-voltage input terminal is different from at least one of the first low-voltage input terminal, the second low-voltage input terminal, and the third low-voltage input terminal. [7] A driver circuit according to any one of claims 2 to 5, further comprising a fifth node control circuit and a pull-up node control circuit; wherein the fifth node control circuit is electrically connected to the second node, a fifth node, and a second clock signal line, respectively, and is configured to control the connection of the second clock signal line and the fifth node under the control of the potential of the second node and to control a potential of the fifth node according to the potential of the second node; the pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line, and the pull-up node, respectively, and is configured to control the connection of the fifth node and the pull-up node under the control of a second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node under the control of the second clock signal provided by the second clock signal line. [8] The driver circuit of claim 4, further comprising a third node control circuit; where the third node control circuit is electrically connected to a start voltage terminal, the first clock signal line, and the third node, respectively, and is configured to control the connection of the start voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line; the first node control circuit is also electrically connected to the third node, the first node, and the first clock signal line, respectively, and is configured to control the connection of the first node and the first clock signal line under the control of the potential of the third node; the fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line, respectively, and is configured to control the connection of the fourth node and the second clock signal line under the control of the potential of the pull-down node and to control the potential of the fourth node according to the potential of the pull-down node. [9] The driver circuit of claim 1, wherein the first node control circuit comprises a first transistor, and the second node control circuit comprises a second transistor; a control electrode of the first transistor is electrically connected to the first clock signal line, a first electrode of the first transistor is electrically connected to the second low-voltage input terminal, and a second electrode of the first transistor is electrically connected to the first node; a control electrode of the second transistor is electrically connected to the first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node; the first output circuit comprises an output reset transistor; a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low-voltage input terminal. [10] The driver circuit of claim 4 or 5, wherein the second output circuit comprises an output transistor, and the pull-up node control circuit comprises a third transistor and a first capacitor; a control electrode of the output transistor is electrically connected to the pull-up node, a first electrode of the output transistor is electrically connected to the first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to the drive signal output terminal; a control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node; a first electrode plate of the first capacitor is electrically connected to the pull-up node, and a second electrode plate of the first capacitor is electrically connected to the first high-voltage input terminal. [11] The driver circuit of claim 3, wherein the third node reset circuit comprises a fourth transistor; a control electrode of the fourth transistor is electrically connected to the reset line, a first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and a second electrode of the fourth transistor is electrically connected to the third node. [12] The driver circuit of claim 2, wherein the fourth node control circuit comprises a fifth transistor; a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and a second electrode of the fifth transistor is electrically connected to the fourth node. [13] The driver circuit of claim 6, wherein the pull-down node control circuit comprises a sixth transistor; a control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node. [14] The driver circuit of claim 7, wherein the fifth node control circuit comprises a seventh transistor and a second capacitor; the pull-up node control circuit further comprises an eighth transistor; a control electrode of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the second clock signal line, and a second electrode of the seventh transistor is electrically connected to a fifth node; a first electrode plate of the second capacitor is electrically connected to the second node, and a second electrode plate of the second capacitor is electrically connected to the fifth node; a control electrode of the eighth transistor is electrically connected to the second clock signal line, a first electrode of the eighth transistor is electrically connected to the fifth node, and a second electrode of the eighth transistor is electrically connected to the pull-up node. [15] The driver circuit of claim 8, wherein the first node control circuit further comprises a ninth transistor; a control electrode of the ninth transistor is electrically connected to the third node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first node; the fourth node control circuit further comprises a tenth transistor and a third capacitor; a control electrode of the tenth transistor is electrically connected to the pull-down node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the fourth node; a first electrode plate of the third capacitor is electrically connected to the pull-down node, and a second electrode plate of the third capacitor is electrically connected to the fourth node; the third node control circuit comprises an eleventh transistor; a control electrode of the eleventh transistor is electrically connected to the first clock signal line, a first electrode of the eleventh transistor is electrically connected to the start voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the third node. [16] A driver circuit comprising a first transistor, a second transistor, an output reset transistor and a sixth transistor; wherein a control electrode of the first transistor is electrically connected to a first clock signal line, a first electrode of the first transistor is electrically connected to a second low-voltage input terminal, and a second electrode of the first transistor is electrically connected to a first node; a control electrode of the second transistor is electrically connected to a first low-voltage input terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to a second node; the first output circuit includes the output reset transistor, a control electrode of the output reset transistor is electrically connected to a pull-down node, a first electrode of the output reset transistor is electrically connected to a drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to a third low-voltage input terminal; a control electrode of the sixth transistor is electrically connected to a fourth low-voltage input terminal, a first electrode of the sixth transistor is electrically connected to a third node, and a second electrode of the sixth transistor is electrically connected to the pull-down node; the first low-voltage input terminal, the second low-voltage input terminal, the third low-voltage input terminal and the fourth low-voltage input terminal are not completely identical. [17] A driver circuit comprising an output transistor, a third transistor, a fourth transistor and a fifth transistor; wherein a control electrode of the output transistor is electrically connected to a pull-up node, a first electrode of the output transistor is electrically connected to a first high-voltage input terminal, and a second electrode of the output transistor is electrically connected to a drive signal output terminal; a control electrode of the third transistor is electrically connected to a third node, a first electrode of the third transistor is electrically connected to a second high-voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node; a control electrode of the fourth transistor is electrically connected to a reset line, a first electrode of the fourth transistor is electrically connected to a third high-voltage input terminal, and a second electrode of the fourth transistor is electrically connected to a third node; a control electrode of the fifth transistor is electrically connected to a first node, a first electrode of the fifth transistor is electrically connected to a fourth high-voltage input terminal, and a second electrode of the fifth transistor is electrically connected to a fourth node; the first high-voltage input terminal, the second high-voltage input terminal, the third high-voltage input terminal, and the fourth high-voltage input terminal are not completely identical. [18] A display panel comprising the driver circuit according to any one of claims 1 to 15; wherein the display panel further comprises a display driver chip; the first low-voltage input terminal is electrically connected to a first low-voltage line, the second low-voltage input terminal is electrically connected to a second low-voltage line, the third low-voltage input terminal is electrically connected to a third low-voltage line, and the first low-voltage line, the second low-voltage line, and the third low-voltage line are each electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide a first low-voltage signal to the first low-voltage line, a second low-voltage signal to the second low-voltage line, and a third low-voltage signal to the third low-voltage line; or, the first low-voltage input terminal is electrically connected to the first low-voltage line, the second low-voltage input terminal and the third low-voltage input terminal are both electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line; or, both the first low-voltage input terminal and the second low-voltage input terminal are electrically connected to the first low-voltage line, the third low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line; or, both the first low-voltage input terminal and the third low-voltage input terminal are electrically connected to the first low-voltage line, the second low-voltage input terminal is electrically connected to the second low-voltage line, and the first low-voltage line and the second low-voltage line are each electrically connected to different pins of the display driver chip, and the display driver chip is configured to provide the first low-voltage signal to the first low-voltage line and to provide the second low-voltage signal to the second low-voltage line. [19] A display panel comprising the driver circuit according to any one of claims 4 to 15; wherein the display panel further comprises a display driver chip; the first high-voltage input terminal is electrically connected to a first high-voltage line, and the second high-voltage input terminal is electrically connected to a second high-voltage line; the first high-voltage line and the second high-voltage line are each electrically connected to different pins of the display driver chip, the display driver chip is configured to provide a first high-voltage signal to the first high-voltage line, and the display driver chip is configured to provide a second high-voltage signal to the second high-voltage line. [20] A display substrate comprising a base substrate and the driver circuit according to any one of claims 1 to 17 arranged on the base substrate. [21] The display substrate according to claim 20, wherein the drive circuit comprises a first low-voltage line, a second low-voltage line, a first high-voltage line, a second high-voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit; the second low-voltage line is arranged on a side of the driver circuit remote from a display area, and the first low-voltage line is arranged on a side of the driver circuit close to the display area; the first high-voltage line and the second high-voltage line are arranged between a first circuit part included in the driver circuit and a second circuit part included in the driver circuit; the first circuit part comprises the first node control circuit, the second node control circuit, the pull-up node control circuit, the fourth node control circuit, the pull-down node control circuit, the fifth node control circuit and the third node control circuit, the second circuit part comprises the first output circuit and the second output circuit; the first circuit part is arranged between the second low-voltage line and the second high-voltage line, and the second circuit part is arranged between the first high-voltage line and the first low-voltage line. [22] The display substrate according to claim 21, wherein the driver circuit further comprises a third node reset circuit, and the first circuit part comprises the third node reset circuit. [23] A display device comprising the driving circuit according to any one of claims 1 to 17.

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