Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate comprises: a substrate (10) and a driver structure layer arranged on the substrate (10), wherein the substrate comprises a display area (100) and a non-display area (200), wherein the driver structure layer comprises: a plurality of pixel circuits located in the display area (100), and a gate driver circuit and an electrostatic discharge (ER) circuit located in the non-display area (200), wherein the gate driver circuit is configured to provide a driver signal to the pixel circuit and comprises a plurality of driver circuits, wherein the plurality of driver circuits and the electrostatic discharge (ER) circuit are arranged in a direction close to the display area (100);wherein the electrostatic discharge (ER) circuit is arranged between two adjacent driver circuits and is electrically connected to at least one signal line from any one of the two adjacent driver circuits.

Description

TECHNICAL AREA

[0001] The present disclosure relates to, but is not limited to, the field of display technology and relates in particular to a display substrate and a display device. STATE OF THE ART

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display components offering advantages such as self-illumination, wide viewing angles, high contrast ratios, low power consumption, very fast response times, thin and lightweight designs, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as the light-emitting component and thin-film transistors (TFTs) for signal processing have become a major trend in the display industry. REVELATION OF THE INVENTION

[0003] The following is a summary of the subject matter described in detail in the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate comprising: a substrate and a driver structure layer arranged on the substrate, wherein the substrate comprises a display area and a non-display area, and wherein the driver structure layer comprises: a plurality of pixel circuits located in the display area, and a gate driver circuit and an electrostatic discharge circuit located in the non-display area, wherein the gate driver circuit is configured to provide a driver signal to the pixel circuit, and which comprises a plurality of driver circuits, wherein the plurality of driver circuits and the electrostatic discharge circuit are arranged in a direction close to the display area; wherein the electrostatic discharge circuit is arranged between two adjacent driver circuits and is electrically connected to at least one signal line from any one of the two adjacent driver circuits.

[0005] In an exemplary embodiment, the electrostatic discharge circuit comprises at least: a first discharge transistor and a second discharge transistor; wherein a gate electrode and a second electrode of the first discharge transistor are connected to a first signal terminal, and a first electrode of the first discharge transistor is connected to a second signal terminal; wherein a gate electrode and a first electrode of the second discharge transistor are connected to a third signal terminal, and a second electrode of the second discharge transistor is connected to the first signal terminal.

[0006] In an exemplary embodiment, the plurality of driver circuits comprises: a light emission driver circuit and a scanning driver circuit, wherein the scanning driver circuit is located on a side of the light emission driver circuit that is close to the display area; wherein the driver structure layer further comprises: a light emission start signal line, a first light emission clock signal line, a second light emission clock signal line, a first light emission power supply line, a second light emission power supply line, a sampling start signal line, a first sampling clock signal line, a second sampling clock signal line, a first sampling power supply line and a second sampling power supply line, which are located in the non-display area;wherein any one of the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the sampling initial signal line, the first sampling clock signal line, the second sampling clock signal line, the first sampling power supply line and the second sampling power supply line extends in a first direction; wherein the light emission driver circuit is electrically connected to the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line and the second light emission power supply line; wherein the sampling driver circuit is electrically connected to the sampling initial signal line, the second sampling clock signal line, the first sampling clock signal line, the first sampling power supply line and the second sampling power supply line; wherein the light emission start signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the first scanning power supply line, the first scanning clock signal line, the second scanning clock signal line, the scanning start signal line and the second scanning power supply line are arranged sequentially in a direction close to the display area.

[0007] In an exemplary embodiment, an orthographic projection of the electrostatic discharge circuit onto the substrate partially overlaps with the first scanning power supply line and the second light emission power supply line, and at least part of the electrostatic discharge circuit is located between the second light emission power supply line and the first scanning power supply line.

[0008] In an exemplary embodiment, the driver structure layer further comprises: a light emission output signal line and a sampling output signal line located in the non-display area, as well as a light emission signal line and a sampling signal line located at least partially in the display area; wherein any one of the sampling output signal line, the light emission signal line, and the sampling signal line extends at least partially in a second direction, the first direction and the second direction intersecting; wherein the pixel circuit is connected to the light emission signal line and the sampling signal line, respectively; wherein the light emission driver circuit comprises: a plurality of cascaded light emission shift registers, and the sampling driver circuit comprises: a plurality of cascaded sampling shift registers; wherein the light emission output signal line is electrically connected to the light emission shift register and to at least one light emission signal line; wherein the sampling output signal line is electrically connected to the sampling shift register and to the sampling signal line.

[0009] In an exemplary embodiment, the first signal terminal of the electrostatic discharge circuit is electrically connected to the light emission output signal line, the second signal terminal of the electrostatic discharge circuit is electrically connected to the second light emission power supply line, and the third signal terminal of the electrostatic discharge circuit is electrically connected to the first scanning power supply line.

[0010] In an exemplary embodiment, the distance between the second light emission power supply line and the first scanning power supply line is approximately 8 micrometers to 15 micrometers.

[0011] In an exemplary embodiment, the light emission shift register comprises a plurality of light emission transistors and a plurality of light emission capacitors, and the sampling shift register comprises a plurality of sampling transistors and a plurality of sampling capacitors, wherein the light emission capacitor and the sampling capacitor each comprise a first electrode plate and a second electrode plate; wherein the driver structure layer comprises: a semiconductor layer, a first electrically conductive layer, a second electrically conductive layer, a third electrically conductive layer, and a fourth electrically conductive layer, which are arranged sequentially; wherein the first sampling clock signal line comprises: a first sub-clock signal line and a second sub-clock signal line, which are electrically connected to each other;wherein the second sampling clock signal line comprises: a third sub-clock signal line and a fourth sub-clock signal line, which are electrically connected to each other; wherein the semiconductor layer comprises at least: active layers of the plurality of light-emitting transistors, active layers of the plurality of scanning transistors, an active layer of the first discharge transistor and an active layer of the second discharge transistor; wherein the first electrically conductive layer comprises at least: the light emission signal line, the sampling signal line, the gate electrodes of the plurality of light emission transistors, the first electrode plates of the plurality of light emission capacitors, the gate electrodes of the plurality of sampling transistors, the first electrode plates of the plurality of sampling capacitors, the gate electrode of the first discharge transistor and the gate electrode of the second discharge transistor; wherein the second electrically conductive layer comprises at least: the second electrode plates of the plurality of light emission capacitors, the second electrode plates of the plurality of sampling capacitors, the sampling output signal line and the light emission output signal line; wherein the third electrically conductive layer comprises at least: the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the sampling initial signal line, the first sub-clock signal line of the first sampling clock signal line, the third sub-clock signal line of the second sampling clock signal line, the first sampling power supply line, the second sampling power supply line, the first and second electrodes of the plurality of light emission transistors, the first and second electrodes of the plurality of sampling transistors, the first and second electrodes of the first discharge transistor, and the first and second electrodes of the second discharge transistor; wherein the fourth electrically conductive layer comprises at least: the second sub-clock signal line of the first sampling clock signal line and the fourth sub-clock signal line of the second sampling clock signal line.

[0012] In an exemplary embodiment, the first and second electrodes of the plurality of light-emitting transistors are located between the first light-emitting power supply line and the second light-emitting power supply line, wherein the first and second electrodes of the first discharge transistor up to the first and second electrodes of the second discharge transistor are located between the second light-emitting power supply line and the first sampling power supply line, wherein the first and second electrodes of some of the sampling transistors are located between the sampling initial signal line and the second sampling power supply line, and the first and second electrodes of other parts of the sampling transistors may be located on a side of the second sampling power supply line that is close to the display area.

[0013] In an exemplary embodiment, at least one of the light emission output signal lines comprises: an output connecting part and at least one output line, wherein the output connecting part extends in the first direction, and at least one of the output lines is arranged in the first direction; wherein the output connection part is electrically connected to the light emission shift register and at least one output line, wherein the output line corresponds one-to-one to a light emission signal line to which the light emission output signal line is connected, and the output line is electrically connected to the corresponding light emission signal line.

[0014] In an exemplary embodiment, the output line comprises: an output body part extending at least partially in the second direction and an output connection part extending in the first direction, wherein the output body part is electrically connected to the output connection part; wherein the second electrode of the first discharge transistor and the second electrode of the second discharge transistor are a single-piece structure and their orthographic projection onto the substrate overlaps at least partially with an orthographic projection of the output interconnection part onto the substrate, wherein the single-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor is electrically connected to the output interconnection part.

[0015] In an exemplary embodiment, the active layer of the first discharge transistor and the active layer of the second discharge transistor are a single-piece structure and run in the second direction; where the orthographic projection of the output interconnect part onto the substrate does not overlap with the orthographic projection of the single-piece structure of the active layer of the first discharge transistor and the active layer of the second discharge transistor onto the substrate.

[0016] In an exemplary embodiment, the active layer of the first discharge transistor and the active layer of the second discharge transistor are a single-piece structure and comprise: an active body part and an active interconnect part, wherein the active body part is electrically connected to the active interconnect part, and the active body part and the active interconnect part are arranged in the first direction; wherein the active body part extends in the second direction, and the active connecting part extends at least partially in the first direction; where the active connecting part has a bent shape.

[0017] In an exemplary embodiment, the output line extends at least partially in the second direction; wherein the second electrode of the first discharge transistor and the second electrode of the second discharge transistor are a single-piece structure; wherein an orthographic projection of the active interconnect onto the substrate overlaps at least partially with orthographic projections of the one-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor and the output line onto the substrate, and the active interconnect is electrically connected to the one-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor and the output line.

[0018] In one exemplary embodiment, the width of the active connecting part is smaller than the width of the active body part.

[0019] In an exemplary embodiment, the scanning shift register comprises a first scanning capacitor, wherein the second electrode plate of the first scanning capacitor is electrically connected to the first scanning power supply line, and the second electrode plate of the first scanning capacitor extends in the second direction; wherein an orthographic projection of the second electrode plate of the first sampling capacitor onto the substrate overlaps at least partially with orthographic projections of the first sampling power supply line, the second sampling power supply line, the first sampling clock signal line, the second sampling clock signal line and the sampling start signal line onto the substrate.

[0020] In an exemplary embodiment, the display area comprises: a first display area and a second display area located on at least one side of the first display area, the display substrate further comprising: a light-emitting device and an anode connecting line located in the display area, the pixel circuit being electrically connected to the light-emitting device; the pixel circuit comprising: a first pixel circuit and a second pixel circuit located in the second display area, the light-emitting device comprising: a first light-emitting device located in the first display area and a second light-emitting device located in the second display area, the first pixel circuit being electrically connected to the first light-emitting device and the second pixel circuit being electrically connected to the second light-emitting device;wherein an orthographic projection of the first pixel circuit onto the substrate overlaps at least partially with an orthographic projection of the first light emission element connected to the first pixel circuit onto the substrate; wherein the anode connecting line is electrically connected to the second light emission element and the second pixel circuit connected to the second light emission element.

[0021] In an exemplary embodiment, the driver structure layer further comprises: a first power supply line, a data signal line and a data link line, which are located at least partially in the display area; wherein the first power supply line and the data signal line extend at least partially in the first direction, and the data link line extends at least partially in the second direction; wherein the driver structure layer further comprises: a fourth electrically conductive layer and a fifth electrically conductive layer, which are stacked successively on a third electrically conductive layer; wherein the third electrically conductive layer includes at least: the data link line; wherein the fourth electrically conductive layer includes at least: the first power supply line and the data signal line; wherein the fifth electrically conductive layer includes at least the anode connecting conductor; wherein the fifth electrically conductive layer is a transparent electrically conductive layer.

[0022] In an exemplary embodiment, the driver structure layer further comprises: a flat layer located between the third electrically conductive layer and the fourth electrically conductive layer, wherein the flat layer has a groove; where an orthographic projection of the electrostatic discharge circuit onto the substrate overlaps at least partially with an orthographic projection of the groove onto the substrate.

[0023] In an exemplary embodiment, the driver structure layer further comprises: at least one initial power supply line located in the non-display area, and at least one initial signal line located at least partially in the display area; wherein the initial power supply line is located on a side of the sampling driver circuit that is close to the display area, wherein the initial power supply line extends at least partially in the first direction, and the initial signal line extends at least partially in the second direction; wherein the initial power supply line comprises a first sub-initial power supply line and a second sub-initial power supply line that are electrically connected to each other; wherein at least one initial power supply line corresponds one-to-one to at least one initial power supply line, wherein the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line; wherein the second electrically conductive layer comprises at least: the initial signal line; wherein the third electrically conductive layer comprises at least: the first sub-initial power supply line of the initial power supply line; wherein the fourth electrically conductive layer includes at least: the second first sub-initial power supply line of the initial power supply line.

[0024] In a second aspect, the present disclosure provides a display device comprising: a display substrate as described above and a light-sensitive sensor arranged within the display substrate.

[0025] After reading and understanding the characters and the detailed description, other aspects need to be grasped. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The figures are provided to aid in a deeper understanding of the technical solutions presented in this disclosure. They form part of the description and are used in conjunction with the embodiments presented in this disclosure to illustrate the technical solutions presented in this disclosure; however, they do not represent any limitation of the technical solutions presented in this disclosure. The shape(s) and size(s) of one or more components in the figures do not reflect the true proportions and serve only to schematically illustrate the content of this disclosure. Fig. Figure 1 shows a schematic diagram of the structure of a display substrate; Fig. Figure 2 shows another schematic diagram of the display substrate; Fig. Figure 3A shows a schematic equivalent circuit diagram of a pixel circuit; Fig. 3B shows a workflow diagram of the pixel circuit according to Fig. 3A; Fig. Figure 4 shows a schematic diagram of the structure of a display substrate; Fig. Figure 5A shows a partial schematic diagram of a display substrate according to an embodiment of the present disclosure; Fig. Figure 5B shows a section of the display substrate according to Fig. 5A along the direction AA; Fig. Figure 6A shows a further partial schematic diagram of the display substrate according to an embodiment of the present disclosure; Fig. Figure 6B shows a section of the display substrate according to Fig. 6A along the direction AA; Fig. Figure 7A shows a schematic diagram of the structure of a pixel circuit; Fig. Figure 7B shows a schematic diagram of the structure of another pixel circuit; Fig. Figure 7C shows a schematic diagram of the structure of another pixel circuit; Fig. Figure 8 shows an equivalent circuit diagram of the electrostatic discharge circuit; Fig. Figure 9A shows an equivalent circuit diagram of a sampling shift register; Fig. Figure 9B shows a timing diagram of the sample-shift register according to Fig. 9A; Fig. Figure 10A shows an equivalent circuit diagram of a light emission shift register; Fig. Figure 10B shows a timing diagram of the light emission shift register according to Fig. 10A; Fig. Figure 11 shows a schematic diagram of the structure of the semiconductor film layer and the second electrically conductive layer of Fig. 5A; Fig. Figure 12 shows a schematic diagram of the structure of the semiconductor film layer and the second electrically conductive layer of Fig. 6A; Fig. Figure 13 shows another schematic diagram of the structure of the display substrate; Fig. Figure 14 shows a schematic diagram of Fig. 5A after the formation of the semiconductor layer pattern; Fig. Figure 15 shows a schematic diagram of Fig. 6A after the formation of the semiconductor layer pattern; Fig. Figure 16 shows a schematic diagram of the pattern of the first electrically conductive layer of Fig. 5A and Fig. 6A; Fig. Figure 17 shows a schematic diagram of Fig. 5A after the formation of the pattern of the first electrically conductive layer; Fig. Figure 18 shows a schematic diagram of Fig. 6A after the formation of the pattern of the first electrically conductive layer; Fig. Figure 19 shows a schematic diagram of Fig. 6A after forming the pattern of the second insulating layer; Fig. Figure 20 shows a schematic diagram of the pattern of the second electrically conductive layer of Fig. 5A; Fig. Figure 21 shows a schematic diagram of Fig. 5A after the formation of the pattern of the second electrically conductive layer; Fig. Figure 22 shows a schematic diagram of the pattern of the second electrically conductive layer of Fig. 6A; Fig. Figure 23 shows a schematic diagram of Fig. 6A after the formation of the pattern of the second electrically conductive layer; Fig. Figure 24 shows a schematic diagram of Fig. 5A after forming the pattern of the third insulating layer; Fig. Figure 25 shows a schematic diagram of Fig. 6A after forming the pattern of the third insulating layer; Fig. Figure 26 shows a schematic diagram of the pattern of the third electrically conductive layer of Fig. 5A and Fig. 6A; Fig. Figure 27 shows a schematic diagram of Fig. 5A after the formation of the pattern of the third electrically conductive layer; Fig. Figure 28 shows a schematic diagram of Fig. 6A after forming the pattern of the third electrically conductive layer; Fig. Figure 29 shows a schematic diagram of Fig. 5A after forming the pattern of the flat layer; Fig. Figure 30 shows a schematic diagram of Fig. 6A after forming the pattern of the flat layer; Fig. Figure 31 shows a schematic diagram of the pattern of the fourth electrically conductive layer of Fig. 5A and Fig. 6A; Fig. Figure 32 shows a schematic diagram of Fig. 5A after the formation of the pattern of the fourth electrically conductive layer; Fig. Figure 33 shows a schematic diagram of Fig. 6A after forming the pattern of the fourth electrically conductive layer; Fig. Figure 34 shows a schematic diagram of Fig. 7B after the formation of the semiconductor layer pattern; Fig. Figure 35 shows a schematic diagram of Fig. 7C after the formation of the semiconductor layer pattern; Fig. Figure 36 shows a schematic diagram of the pattern of the first electrically conductive layer of Fig. 7B; Fig. Figure 37 shows a schematic diagram of Fig. 7B after forming the pattern of the first electrically conductive layer; Fig. Figure 38 shows a schematic diagram of the pattern of the first electrically conductive layer of Fig. 7C; Fig. Figure 39 shows a schematic diagram of Fig. 7C after the formation of the pattern of the first electrically conductive layer; Fig. Figure 40 shows a schematic diagram of the pattern of the second electrically conductive layer of Fig. 7B; Fig. Figure 41 shows a schematic diagram of Fig. 7B after forming the pattern of the second electrically conductive layer; Fig. Figure 42 shows a schematic diagram of the pattern of the second electrically conductive layer of Fig. 7C; Fig. Figure 43 shows a schematic diagram of Fig. 7C after the formation of the pattern of the second electrically conductive layer; Fig. Figure 44 shows a schematic diagram of Fig. 7B after forming the pattern of the third insulating layer; Fig. Figure 45 shows a schematic diagram of Fig. 7C after forming the pattern of the third insulating layer; Fig. Figure 46 shows a schematic diagram of the pattern of the third electrically conductive layer of Fig. 7B; Fig. Figure 47 shows a schematic diagram of Fig. 7B after forming the pattern of the third electrically conductive layer; Fig. Figure 48 shows a schematic diagram of the pattern of the third electrically conductive layer of Fig. 7C; Fig. Figure 49 shows a schematic diagram of Fig. 7C after the formation of the pattern of the third electrically conductive layer; Fig. Figure 50 shows a schematic diagram of Fig. 7B after forming the pattern of the fourth insulating layer; Fig. Figure 51 shows a schematic diagram of Fig. 7C after forming the pattern of the fourth insulating layer; Fig. Figure 52 shows a schematic diagram of the pattern of the fourth electrically conductive layer of Fig. 7B; Fig. Figure 53 shows a schematic diagram of Fig. 7B after forming the pattern of the fourth electrically conductive layer; Fig. Figure 54 shows a schematic diagram of Fig. 7C after the formation of the pattern of the fourth electrically conductive layer; Fig. Figure 55 shows a schematic diagram of Fig. 7C after the formation of the pattern of the fourth electrically conductive layer. FORMS OF EXECUTION OF THE INVENTION

[0027] To clarify the objectives, technical solutions, and advantages of this disclosure, the embodiments of this disclosure are explained in more detail below in conjunction with the drawings. It should be noted that the embodiments can be implemented in many different forms. It is readily apparent to a person skilled in the art that the nature and content can be varied without deviating from the meaning and scope of this disclosure. Therefore, this disclosure should not be interpreted as being limited solely to the content described in the following embodiments. Provided there are no conflicts, the embodiments and their features in this disclosure can be combined with one another in any way.To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components are omitted. The drawings of the embodiments of this disclosure relate only to the structures associated with the embodiments of this disclosure; for other structures, reference can be made to conventional designs.

[0028] The scales in the drawings of this disclosure can serve as a reference for the actual process, but are not limited to it. For example, the width-to-length ratio of the channel, the thickness and spacing of the individual film layers, and the width and spacing of the individual signal lines can be adjusted according to the actual requirements. The number of pixels in the display substrate and the number of subpixels in each pixel are also not limited to the quantities shown in the drawings. The drawings described in this disclosure are merely schematic structural representations, and the nature of this disclosure is not limited to the shapes or numerical values, etc., shown in the drawings.

[0029] In this description, terms such as "first", "second", "third", etc. are used to avoid mixing components, but they should not be understood as a quantitative restriction.

[0030] For convenience, this description uses terms such as "middle," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," "outside," or similar to indicate an orientation or positional relationship and to illustrate the positional relationships of the components with reference to the accompanying figures. These terms serve solely to facilitate the presentation of this description and are not intended to indicate or imply that a device or element in question must have a particular orientation or be designed and operated in a particular orientation. Therefore, they should not be understood as limiting the present disclosure. The positional relationship of the components varies accordingly, depending on the description of the directions of the respective components.Therefore, it is not limited to the words and expressions specified in the description; however, substitution may be made as appropriate depending on the circumstances.

[0031] In this description, terms such as "install," "connect," and "couple" are to be interpreted broadly, unless otherwise expressly stated and limited in the text. For example, they may refer to a permanent connection, a detachable connection, or a one-piece connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate part; or internal communication between two elements. The specific meanings of the aforementioned terms in this disclosure are readily apparent to the person skilled in the art, depending on the situation.

[0032] In this description, a transistor refers to an element that comprises at least these three terminals: a gate electrode, a drain electrode, and a source electrode. Between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), the transistor has a channel region, and current can flow through the drain electrode, the channel region, and the source electrode. It should be noted that, in this description, the channel region refers to the area through which the current predominantly flows.

[0033] In this description, the first electrode can be the drain electrode and the second electrode can be the source electrode, or alternatively, the first electrode can be the source electrode and the second electrode can be the drain electrode. The functions of the "source electrode" and the "drain electrode" can be reversed if transistors with opposite polarity are used or if the current direction changes during circuit operation. Therefore, in this description, "source electrode" and "drain electrode" are interchangeable.

[0034] The description should include a circumstance in the case of "electrical connection" where components are connected to one another using elements with a specific electrical effect. "Elements with a specific electrical effect" are not particularly limited as long as they can send and receive electrical signals between the connected components. Examples of "elements with a specific electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions, etc.

[0035] In the description, "parallel" refers to a state in which the angle formed by two straight lines is above -10° and below 10°, and thus also to a state in which the angle is above -5° and below 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is above 80° and below 100°, and thus also to a state in which the angle is above 85° and below 95°.

[0036] In the description, "film" and "layer" are interchangeable. For example, in some cases "electrically conductive layer" can be replaced by "electrically conductive film". Similarly, in some cases "insulating film" can be replaced by "insulating layer".

[0037] In this description, “arranged in the same layer” means that two (or more) structures are patterned and formed through a single patterning process. Their materials can be the same or different. For example, the precursor materials for the formation of several structures arranged in the same layer can be the same, and the materials ultimately formed can be the same or different.

[0038] In this disclosure, “approximately” refers to a non-strictly limited boundary that allows the numerical values ​​to fall within the acceptable range of manufacturing and measurement errors.

[0039] The display substrate offers advantages such as high resolution, fast response time, high brightness, and a high aperture ratio, and has broad application potential. Driver circuits are integrated into the display substrate to control the pixel circuitry for light emission, thus enabling the display. The display substrate is typically shaped like a rounded rectangle, with the four corners of the rounded rectangle referred to as rounded areas. The driver circuits are arranged within these rounded areas along their curved shape, resulting in some empty spaces between the driver circuits. If these empty spaces are too large, uneven etching can occur, which impairs the stability of the driver circuit's output signals and affects the display performance.

[0040] Fig. Figure 1 shows a schematic diagram of the structure of a display substrate and Fig. Figure 2 shows another schematic diagram of the display substrate. As in Fig. 1 and Fig. As shown in Figure 2, the display substrate can comprise a display area 100 and a non-display area 200. The display area 100 of the display substrate can comprise a first display area A1 and a second display area A2, which is located on at least one side of the first display area A1. In some examples, the first display area A1 is the transmissive display area. The first display area A1 can also be referred to as the under-display camera (UDC) area. The second display area A2 is the non-transmissive display area. The second display area A2 can also be referred to as the normal display area. For example, the orthographic projection of hardware such as light-sensitive sensors (e.g., cameras, infrared sensors) onto the display substrate can lie within the first display area A1 of the display substrate.

[0041] In an exemplary embodiment, as in Fig. As shown in Figure 1, the first display area A1 can be circular, and the size of the orthographic projection of the light-sensitive sensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the light-sensitive sensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area.

[0042] In an exemplary embodiment, as in Fig. As shown in Figure 1, the first display area A1 can be located at the top center of display area 100. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at the upper left corner, the upper right corner, or at other positions within display area 100.

[0043] In some exemplary embodiments, such as in Fig. As shown in Figure 1, the display area can be rectangular, for example, a rounded rectangle. The first display area A1 can be round or elliptical. However, this embodiment is not limited to these shapes. For example, the first display area can also have other shapes, such as rectangular, pentagonal, or hexagonal. The display substrate provided by the present disclosure allows for large-angle bendability on all four sides, improves the wrinkling problem during module adhesion, and increases the product yield.

[0044] In an exemplary embodiment, as in Fig. 1 and Fig. As shown in Figure 2, the display area can comprise: array-like pixel units, wherein at least one pixel unit comprises at least three subpixels P, and wherein at least one subpixel comprises: a pixel circuit and a light-emitting device. The pixel circuit arranged in the same subpixel is electrically connected to the light-emitting device and is designed to drive the light-emitting device to emit light.

[0045] In one exemplary embodiment, a pixel unit may comprise: a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, or it may comprise: a red subpixel, a green subpixel, a blue subpixel, and a white subpixel. The present disclosure does not constitute a limitation in this respect.

[0046] In an exemplary embodiment, the shape of the subpixels in the pixel unit can be rectangular, rhomboid, pentagonal, or hexagonal. If the pixel unit comprises three subpixels, these three subpixels can be horizontally parallel, vertically parallel, or arranged in a “ "-arranged in a manner that allows the pixel unit to comprise four subpixels, these four subpixels can be arranged horizontally parallel, vertically parallel, or in a square shape. The present disclosure does not impose any limitation in this respect."

[0047] In an exemplary embodiment, the light emission device can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), wherein the OLED can comprise a stacked first electrode (anode), an organic light emission layer and a second electrode (cathode).

[0048] In an exemplary embodiment, the organic light emission layer may comprise: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), which are arranged in a stacked configuration.In an exemplary embodiment, the hole injection layer of all subpixels can be a connected common layer, the electron injection layer of all subpixels can be a connected common layer, the hole transport layer of all subpixels can be a connected common layer, the electron transport layer of all subpixels can be a connected common layer, the hole blocking layer of all subpixels can be a connected common layer, the light emission layers of adjacent subpixels can have a small overlap or can be isolated from each other, and the electron blocking layers of adjacent subpixels can have a small overlap or can be isolated from each other.

[0049] In an exemplary embodiment, as in Fig. As shown in Figure 1, the non-display area 200 can include: a binding area located on one side of the display area 100, and a border area located on other sides of the display area 100.

[0050] In an exemplary embodiment, the binding area may comprise: a feed area, a bending area and a compound circuit area arranged successively in a direction away from the display area, wherein the feed area is connected to the display area 100, the bending area is connected to the feed area and the compound circuit area is connected to the bending area.

[0051] In an exemplary embodiment, the feed area can have a plurality of output lines, wherein a portion of the plurality of output lines is connected at one end to the multiple data fanout lines in the display area 100 in a corresponding manner, and another portion of the plurality of output lines is connected at one end to the plurality of data lines in the display area 100 in a corresponding manner, while the plurality of output lines is connected at the other end across the bending area to the integrated circuit in the compound circuit area, so that the integrated circuit applies data signals to the data lines via the output lines and data fanout lines.

[0052] In one exemplary embodiment, the bending area can be bent with a curvature, and the surface of the compound circuit area can be inverted; that is, the upward-facing surface of the compound circuit area can be transformed into a downward-facing surface by bending the bending area. In one exemplary embodiment, the compound circuit area can overlap with the display area 100 when the bending area is bent.

[0053] In an exemplary embodiment, the interconnection area can comprise an antistatic area, a driver chip area, and a bond pin area. The integrated circuit (IC) can be bonded in the driver chip area, and the flexible printed circuit (FPC) can be bonded in the bond pin area.

[0054] In an exemplary embodiment, the integrated circuit can generate the driver signals required to drive the subpixels and provide these driver signals to the subpixels in the display area 100. For example, the driver signal can be a data signal that drives the brightness of the subpixels. In an exemplary embodiment, the integrated circuit can be bonded in the driver chip area by means of an anisotropically conductive film or by other means. In an exemplary embodiment, the bonding pin area can have a pad with multiple pins (PINs), and the flexible printed circuit board can be bonded to the pad.

[0055] In an exemplary embodiment, as in Fig. As shown in Figure 2, the display substrate can include a timing controller, a data driver circuit, a gate driver circuit, and a pixel array. The timing controller is connected to both the data driver circuit and the gate driver circuit. The data driver circuit is connected to both the data signal lines. The gate driver circuit is connected to a gate line, which can include one or more of the light emission signal lines and the sample signal line. The pixel circuit is connected to both the gate line and the data signal line.

[0056] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the data driver circuit's specifications to the data driver circuit; clock signals, start signals, etc., suitable for the gate driver circuit's specifications to the gate driver circuit; and clock signals, emission stop signals, etc., suitable for the light emission driver circuit's specifications to the light emission driver circuit. The data driver circuit can use the grayscale values ​​and control signals received from the timing controller to generate the data voltages to be supplied to the data signal lines. For example, the data driver circuit can sample the grayscale values ​​using the clock signals and apply the data voltages corresponding to the grayscale values, in units of pixel lines, to the data signal lines.

[0057] In one exemplary embodiment, the gate driver circuit can generate the sampling signals to be delivered to the gate lines by receiving clock signals, start signals, etc., from the timing controller. For example, the gate driver circuit can sequentially provide signals with turn-on level pulses to the gate line. For instance, the gate driver circuit can be implemented as a shift register and, under the control of the clock signals, can sequentially transmit the start signal, provided in the form of turn-on level pulses, to a circuit in the next stage, thereby generating the sampling signals.

[0058] In an exemplary embodiment, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.

[0059] In an exemplary embodiment, Fig. 3A is a schematic equivalent circuit of a pixel circuit. As in Fig. As shown in Figure 3A, the pixel circuit can include seven transistors (the first transistor M1 to the seventh transistor M7), a capacitor C and eight signal lines (the data signal line Data, the sampling signal line Gate, the reset signal line Reset, the light emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, the high-level power supply line VDD and the low-level power supply line VSS).

[0060] In an exemplary embodiment, as in Fig. As shown in Figure 3A, the first electrode plate of capacitor C is connected to the high-level power supply line VDD, and the second electrode plate of capacitor C is connected to the first node N1. The gate electrode of the first transistor M1 is connected to the reset signal line Reset, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1. The gate electrode of the second transistor M2 is connected to the sample signal line Gate, the first electrode of the second transistor M2 is connected to the first node N1, and the second electrode of the second transistor M2 is connected to the second node N2.The gate electrode of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the second node N2, and the second electrode of the third transistor M3 is connected to the third node N3. The gate electrode of the fourth transistor M4 is connected to the sampling signal line Gate, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the second node N2. The gate electrode of the fifth transistor M5 is connected to the light emission signal line EM, the first electrode of the fifth transistor M5 is connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2.The gate electrode of the sixth transistor M6 is connected to the light emission signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emission component L. The gate electrode of the seventh transistor M7 is connected to the reset signal line Reset or the sampling signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the first electrode of the light emission component L. The second electrode of the light emission component is connected to the low-level power supply line VSS. Fig. 3A is illustrated using the example of the gate electrode of the seventh transistor M7 and the reset signal line Reset.

[0061] In an exemplary embodiment, the first transistor M1 can be called the node reset transistor. When the reset signal line Reset receives an active level signal, the first transistor M1 transmits the initialization voltage to the first node N1 to initialize the charge level of the first node N1.

[0062] In an exemplary embodiment, the second transistor M2 can be called a compensation transistor. When the control signal line SL receives an active-level signal, the second transistor M2 transmits the signal of the second node N2 to the first node N1 to compensate for the signal of the first node N1.

[0063] In an exemplary embodiment, the third transistor M3 can be referred to as the driver transistor. The third transistor M3 determines the driver current that flows between the high-level power supply line VDD and the low-level power supply line VSS, based on the potential difference between the gate electrode and the first electrode.

[0064] In an exemplary embodiment, the fourth transistor M4 can be designated as a write transistor, etc. When the sampling signal line Gate receives an active level signal, the fourth transistor M4 passes the data voltage of the data signal line Data to the third node N3.

[0065] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 can be designated as light-emitting transistors. When the light-emitting signal line EM receives an active level signal, the fifth transistor M5 and the sixth transistor M6 cause the light-emitting device to illuminate by forming a driver current path between the high-level power supply line VDD and the low-level power supply line VSS.

[0066] In an exemplary embodiment, the seventh transistor M7 can be designated as the anode reset transistor. When the reset signal line Reset or the sampling signal line Gate receives an active level signal, the seventh transistor M7 transmits the initialization voltage to the first electrode of the light-emitting device L to initialize the charge of the first electrode of the light-emitting device L.

[0067] In an exemplary embodiment, the high-level power supply line VDD signal is a continuously provided high-level signal and the low-level power supply line VSS signal is a low-level signal.

[0068] Based on their characteristics, transistors can be divided into N-type and P-type transistors. If the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages) and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). If the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages) and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0069] In one exemplary embodiment, the first transistor M1 through the seventh transistor M7 can be either P-type or N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulties of the display array, and increase product yield. In some possible embodiments, the first transistor M1 through the seventh transistor M7 can comprise both P-type and N-type transistors.

[0070] In an exemplary embodiment, the first transistor M1 through the seventh transistor M7 can be low-temperature polysilicon thin-film transistors or oxide thin-film transistors, or they can be both low-temperature polysilicon and oxide thin-film transistors. The active layer of a low-temperature polysilicon thin-film transistor consists of low-temperature polysilicon (LTPS), and the active layer of an oxide thin-film transistor consists of an oxide semiconductor (oxide). Low-temperature polysilicon thin-film transistors offer the advantages of high mobility and fast charging, while oxide thin-film transistors offer the advantages of low leakage current.By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors onto a display substrate, a low-temperature polycrystalline oxide (LTPO) display substrate is created, which can take advantage of both, thereby enabling a low-frequency drive, reducing power consumption and improving display quality.

[0071] In an exemplary embodiment, if the display substrate is an LTPO display substrate, the first transistor T1 and the second transistor T2 can be N-type transistors, while the remaining transistors are P-type transistors. If the display substrate is an LTPS display substrate, the first transistor M1 through the seventh transistor M7 are P-type transistors.

[0072] Fig. 3B shows a workflow diagram of the pixel circuit according to Fig. 3A. Fig. 3B explains the example where all transistors are in Fig. These are 3A P-type transistors. The following describes the operating process of the transistors in the... Fig. Figure 3B illustrates an exemplary embodiment of the present disclosure. In an exemplary embodiment, the working process of the pixel circuit may comprise the following steps: A first phase A1, referred to as the reset phase, in which the signals of the sampling signal line Gate and the light emission signal line EM are both high-level signals, and the signal of the reset signal line Reset is a low-level signal. When the reset signal line Reset is high-level, the first transistor M1 turns on, the signal of the first initial signal line INIT1 is supplied to the first node N1 to initialize capacitor C and clear the initial data voltage in capacitor C, the seventh transistor M7 turns on, and the initial voltage of the second initial signal line INIT2 is supplied to the first electrode of the light emission device L to initialize (reset) the first electrode of the light emission device L and clear the bias voltage stored in it, thus completing the initialization.The signals of the scanning signal line Gate and the light emission signal line EM are high-level signals; the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are switched off; in this phase the light emission element L does not light up.

[0073] A second phase A2, called the data write phase or threshold compensation phase, in which the Gate sampling signal line is a low-level signal, the EM and Reset signals are high-level signals, and the Data signal line outputs the data voltage. In this phase, the third transistor M3 is switched on because the first node N1 has a low-level signal. Since the Gate sampling signal is a low-level signal, the second transistor M2 and the fourth transistor M4 are switched on, thus (i.e.,By switching on the second transistor M2 and the fourth transistor M4, the data voltage output from the Data signal line is supplied via the second node N, the switched-on third transistor M3, the third node N3, and the switched-on second transistor M2 to the first node N1. The difference between the data voltage output from the Data signal line and the threshold voltage of the third transistor M3 is charged into capacitor C until the voltage at the first node N1 is Vd - |Vth|, where Vd is the data voltage output from the Data signal line and Vth is the threshold voltage of the third transistor M3. This ensures that the light-emitting device L does not illuminate. The Reset signal is a high-level signal, therefore the first transistor M1 is switched off.The signal from the light emission signal line EM is a high-level signal, therefore the fifth transistor M5 and the sixth transistor M6 are switched off.

[0074] A third phase A3, referred to as the light emission phase, in which the signals of the Gate sampling signal line and the Reset signal line are high-level signals, and the signal of the light emission signal line EM is a low-level signal. Because the signal of the light emission signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are switched on. This allows the supply voltage output by the high-level power supply line VDD to be fed, via the switched-on fifth transistor M5, the third transistor M3, and the switched-on sixth transistor M6, to the first electrode of the light emission device L as a drive voltage to cause the light emission device L to emit light.

[0075] During the driving process of the pixel driver circuit, the drive current flowing through the third transistor T3 (driver transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the drive current of the third transistor M3 is: I=K*(Vgs−Vth)2=K*[(Vdd−Vd+|Vth|)−Vth]2=K*(Vdd−Vd)2, where I is the driver current flowing through the third transistor M3, i.e., the driver current driving the light emission element L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the supply voltage output by the high-level power supply line VDD.

[0076] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate may consist of one or more of the following materials, but is not limited to: glass, metal foils; and the flexible substrate may consist of one or more of the following materials, but is not limited to: polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyaryl ester, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0077] In an exemplary embodiment, the display substrate can be an LTPO display substrate or an LTPS display substrate.

[0078] In an exemplary embodiment, the gate driver circuit in the display substrate can comprise two, three, or more types, depending on the structure of the display substrate. The present disclosure does not impose any limitations in this regard.

[0079] In FDC display products, some metallic electrically conductive layers comprise several insulated block-shaped structures, resulting in poorer dissipation of static electricity in the metallic conductive layers, preventing the static electricity from discharging and causing some transistors to burn out, thus impairing the display effect and reducing the reliability of the display substrate.

[0080] Fig. Figure 4 shows a schematic diagram of the structure of a display substrate, Fig. Figure 5A shows a partial schematic diagram of a display substrate according to an embodiment of the present disclosure, Fig. Figure 5B shows a section of the display substrate according to Fig. 5A along the direction AA, Fig. Figure 6A shows a further partial schematic diagram of the display substrate according to an embodiment of the present disclosure, and Fig. Figure 6B shows a section of the display substrate according to Fig. 6A along the direction AA. As in Fig. 4, Fig. 5A, Fig. 5B, Fig. 6A and Fig. As shown in Figure 6B, the display substrate according to the embodiments of this disclosure can comprise: a substrate 10 and a driver structure layer arranged on the substrate 10. The substrate comprises a display area 100 and a non-display area 200. The driver structure layer comprises: multiple pixel circuits located in the display area, as well as a gate driver circuit and an electrostatic discharge circuit ER located in the non-display area. The gate driver circuit is configured to provide a driver signal to the pixel circuit. The gate driver circuit comprises a plurality of driver circuits. The plurality of driver circuits and the electrostatic discharge circuit are arranged in a direction close to the display area.The electrostatic discharge circuit ER is arranged between two adjacent driver circuits and is electrically connected to at least one signal line from any one of the two adjacent driver circuits.

[0081] In an exemplary embodiment, the display substrate may further comprise: a light-emitting structure layer arranged on a side of the driver structure layer facing away from the substrate, and an encapsulation structure layer arranged on a side of the light-emitting structure layer facing away from the substrate. In some possible implementations, the display substrate may comprise further film layers, such as a contact structure layer, etc. The present disclosure does not impose any limitations in this regard.

[0082] In an exemplary embodiment, the substrate can be a flexible or a rigid substrate. The driver layer of each subpixel can comprise several transistors and storage capacitors forming the pixel circuitry. The light emission layer can comprise an anode, a pixel definition layer, an organic light emission layer, and a cathode, wherein the anode is connected to the pixel circuitry via a through-hole, the organic light emission layer is connected to the anode, the cathode is connected to the organic light emission layer, and the organic light emission layer emits light of the corresponding color when driven by the anode and cathode.The encapsulation layer can comprise a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer arranged in stacks, wherein the first and third encapsulation layers can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is positioned between the first and third encapsulation layers to ensure that no moisture from the outside can penetrate into the light-emitting structure layer.

[0083] In an exemplary embodiment, the contact structure layer can comprise: a first contact insulating layer arranged on the encapsulation structure layer, a first contact metal layer arranged on the first contact insulating layer, a second contact insulating layer 43 covering the first contact metal layer, a second contact metal layer arranged on the second contact insulating layer, and a contact protection layer covering the second contact metal layer. The first contact metal layer can comprise multiple bridge electrodes, and the second contact metal layer can comprise multiple first contact electrodes and second contact electrodes. The first contact electrodes or the second contact electrodes can be connected to the bridge electrodes via through-holes.

[0084] The electrostatic discharge circuit arranged between adjacent driver circuits and electrically connected to these adjacent driver circuits, as described in the present disclosure, can discharge the static electricity in the gate driver circuit, improve the electrostatic dissipation capability of the display substrate, and increase the display effect and the reliability of the display substrate.

[0085] In an exemplary embodiment, where the display substrate is an LTPO display substrate, the plurality of driver circuits may include: a light emission driver circuit, a control driver circuit, and a sampling driver circuit arranged sequentially in the direction closest to the display area, wherein the control driver circuit is connected to the N-type transistors in the pixel circuit, and the sampling driver circuit is connected to the P-type transistors in the pixel circuit.For example, the electrostatic discharge circuit can be located between the light emission driver circuit and the control driver circuit and be electrically connected to at least one signal line of either of the two circuits, the light emission driver circuit or the control driver circuit, or the electrostatic discharge circuit can be arranged between the control driver circuit and the sampling driver circuit and be electrically connected to at least one signal line of either of the two circuits, the control driver circuit or the sampling driver circuit.

[0086] In an exemplary embodiment, as in Fig. Figure 4 shows that if the display substrate is an LTPS display substrate, the driver circuitry can include a light emission driver circuit and a sampling driver circuit. The sampling driver circuit is located on one side of the light emission driver circuit, close to the display area of ​​100.

[0087] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the driver structure layer may further comprise: a light emission start signal line ESTV, a first light emission clock signal line ECK1, a second light emission clock signal line ECK2, a first light emission power supply line EVGH, a second light emission power supply line EVGL, a sampling start signal line GSTV, a first sampling clock signal line GCK1, a second sampling clock signal line GCK2, a first sampling power supply line GVGH and a second sampling power supply line GVGL, which are located in the non-display area.

[0088] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, any one of the light emission initial signal line ESTV, the first light emission clock signal line ECK1, the second light emission clock signal line ECK2, the first light emission power supply line EVGH, the second light emission power supply line EVGL, the sampling initial signal line GSTV, the first sampling clock signal line GCK1, the second sampling clock signal line GCK2, the first sampling power supply line GVGH and the second sampling power supply line GVGL extends in the first direction D1.

[0089] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the light emission driver circuit can each be electrically connected to the light emission start signal line ESTV, the first light emission clock signal line ECK1, the second light emission clock signal line ECK2, the first light emission power supply line EVGH and the second light emission power supply line EVGL.

[0090] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the sampling driver circuit can each be electrically connected to the sampling initial signal line GSTV, the second sampling clock signal line GCK2, the first sampling clock signal line GCK1, the first sampling power supply line GVGH and the second sampling power supply line GVGL.

[0091] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, at least one of the first sampling clock signal line GCK1 and the second sampling clock signal line GCK2 can have a double-layer structure.

[0092] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the first sampling clock signal line can comprise a first sub-clock signal line and a second sub-clock signal line, which are electrically connected. The first sub-clock signal line and the second sub-clock signal line can be located in different layers.

[0093] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the second sampling clock signal line can comprise a third sub-clock signal line and a fourth sub-clock signal line, which are electrically connected. The third sub-clock signal line and the fourth sub-clock signal line can be located in different layers.

[0094] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the light emission start signal line ESTV, the first light emission clock signal line ECK1, the second light emission clock signal line ECK2, the first light emission power supply line EVGH, the second light emission power supply line EVGL, the first scanning power supply line GVGH, the first scanning clock signal line GCK1, the second scanning clock signal line GCK2, the scanning start signal line GSTV and the second scanning power supply line GVGL are arranged sequentially in a direction close to the display area.

[0095] In an exemplary embodiment, the signals of the first light emission power supply line EVGH and the first scanning power supply line GVGH are high-level signals, and the signals of the second light emission power supply line EVGL and the second scanning power supply line GVGL are low-level signals.

[0096] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the orthographic projection of the electrostatic discharge circuit ER onto the substrate partially overlaps with the first scanning power supply line GVGH and the second light emission power supply line EVGL, with at least part of the electrostatic discharge circuit being located between the second light emission power supply line EVGL and the first scanning power supply line GVGH.

[0097] In an exemplary embodiment, Fig. 7A a schematic diagram of the structure of a pixel circuit, Fig. 7B another schematic diagram of the structure of a pixel circuit and Fig. 7C is another schematic diagram of the structure of a pixel circuit. As in Fig. 5A, Fig. 6A, Fig. 7A to Fig. As shown in Figure 7C, the driver structure layer can further comprise: a light emission output signal line EOL and a sample output signal line GOL located in the non-display region, as well as a light emission signal line EM and a sample signal line Gate located at least partially in the display region. Any one of the sample output signal line GOL, the light emission signal line EM, and the sample signal line Gate extends at least partially in the second direction D2, with the first direction D1 and the second direction D2 intersecting.

[0098] In an exemplary embodiment, the pixel circuit is connected to the light emission signal line EM and the scanning signal line Gate.

[0099] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the light emission driver circuit can include multiple cascaded light emission shift registers EM-GOA, and the sampling driver circuit can include multiple cascaded sampling shift registers Gate-GOA.

[0100] In an exemplary embodiment, the light emission output signal line EOL is electrically connected to the light emission shift register EM-GOA and to at least one light emission signal line. Fig. 5A and Fig. Section 6A is explained using the example of one light emission output signal line and two light emission signal lines.

[0101] In an exemplary embodiment, the sampling output signal line GOL is electrically connected to the sampling shift register Gate-GOA and the sampling signal line.

[0102] Fig. Figure 8 shows an equivalent circuit diagram of the electrostatic discharge circuit. As in Fig. As shown in Figure 8, the electrostatic discharge circuit in an exemplary embodiment may comprise at least: a first discharge transistor R1 and a second discharge transistor R2, wherein the gate electrode and the second electrode of the first discharge transistor R1 are connected to a first signal terminal S1, the first electrode of the first discharge transistor R1 is connected to a second signal terminal S2; the gate electrode and the first electrode of the second discharge transistor R2 are connected to a third signal terminal S3, and the second electrode of the second discharge transistor R2 is connected to the first signal terminal S1.

[0103] In an exemplary embodiment, the signal of the second signal terminal S2 can be a low-level signal, and the signal of the third signal terminal S3 can be a high-level signal.

[0104] In one exemplary embodiment, the first discharge transistor R1 and the second discharge transistor R2 can be either P-type or N-type transistors. Using the same transistor type in the electrostatic discharge circuit can simplify the process flow, reduce the process difficulties of the display panel, and improve product yield. In some possible implementations, the first discharge transistor R1 and the second discharge transistor R2 can be either a P-type or an N-type transistor, respectively.

[0105] In an exemplary embodiment, the first discharge transistor R1 and the second discharge transistor R2 can be low-temperature polysilicon thin-film transistors or oxide thin-film transistors, or they can be a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0106] In one exemplary embodiment, the electrostatic discharge circuit operates according to the following principle: If the voltage value of the signal at the first signal terminal S1 is too high (e.g., higher than the voltage value of the signal at the third signal terminal S3), the second discharge transistor R2 switches on. At this point, the voltage value of the signal at the first signal terminal S1 approaches the voltage value of the signal at the third signal terminal S3 and is no longer too high. Similarly, if the voltage value of the signal at the first signal terminal S1 is too low (e.g., lower than the voltage value of the signal at the second signal terminal S2), the first discharge transistor R1 switches on. At this point, the voltage value of the signal at the first signal terminal S1 approaches the voltage value of the signal at the second signal terminal S2 and is no longer too low.

[0107] In an exemplary embodiment, the first signal terminal of the electrostatic discharge circuit can be electrically connected to the light emission output signal line EOL, the second signal terminal of the electrostatic discharge circuit can be electrically connected to the second light emission power supply line EVGL, and the third signal terminal of the electrostatic discharge circuit can be electrically connected to the first scanning power supply line GVGH.

[0108] In one exemplary embodiment, the distance between the second light emission power supply line EVGL and the first scanning power supply line GVGH is approximately 8 to 15 micrometers. Alternatively, the distance between the second light emission power supply line EVGL and the first scanning power supply line GVGH can be 10 micrometers.

[0109] In an exemplary embodiment, the pixel circuit comprises: a plurality of transistors and capacitors. The light emission shift register comprises a plurality of light emission transistors and a plurality of light emission capacitors. The sampling shift register comprises a plurality of sampling transistors and a plurality of sampling capacitors. The light emission capacitor and the sampling capacitor each comprise a first electrode plate and a second electrode plate. The driver structure layer comprises: a semiconductor layer, a first electrically conductive layer, a second electrically conductive layer, a third electrically conductive layer, and a fourth electrically conductive layer, arranged sequentially.

[0110] In an exemplary embodiment, the semiconductor layer can comprise at least: active layers of the plurality of transistors, active layers of the plurality of light-emitting transistors, active layers of the plurality of scanning transistors, an active layer of the first discharge transistor, and an active layer of the second discharge transistor.

[0111] In an exemplary embodiment, the first electrically conductive layer may comprise at least: the light emission signal line, the sampling signal line, the gate electrodes of the plurality of transistors, the gate electrodes of the plurality of light emission transistors, the first electrode plate of the capacitor, the first electrode plates of the plurality of light emission capacitors, the gate electrodes of the plurality of sampling transistors, the first electrode plates of the plurality of sampling capacitors, the gate electrode of the first discharge transistor, and the gate electrode of the second discharge transistor.

[0112] In an exemplary embodiment, the second electrically conductive layer can comprise at least: the second electrode plate of the capacitor, the second electrode plates of the plurality of light-emitting capacitors, the second electrode plates of the plurality of scanning capacitors, the scanning output signal line, and the light-emitting output signal line.

[0113] In an exemplary embodiment, the third electrically conductive layer may comprise at least: the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the sampling initial signal line, the first sub-clock signal line of the first sampling clock signal line, the third sub-clock signal line of the second sampling clock signal line, the first sampling power supply line, the second sampling power supply line, the first and second electrodes of the plurality of transistors, the first and second electrodes of the plurality of light emission transistors, the first and second electrodes of the plurality of sampling transistors, the first and second electrodes of the first discharge transistor, and the first and second electrodes of the second discharge transistor.

[0114] In an exemplary embodiment, the fourth electrically conductive layer can comprise at least: the second sub-clock signal line of the first sampling clock signal line and the fourth sub-clock signal line of the second sampling clock signal line.

[0115] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the first and second electrodes of the multitude of light-emitting transistors are located between the first light-emitting power supply line EVGH and the second light-emitting power supply line EVGL; the first and second electrodes of the first discharge transistor up to the first and second electrodes of the second discharge transistor are located between the second light-emitting power supply line EVGL and the first sampling power supply line GVGH; the first and second electrodes of some of the sampling transistors are located between the sampling initial signal line GSTV and the second sampling power supply line GVGL; and the first and second electrodes of other parts of the sampling transistors may be located on one side of the second sampling power supply line GVGL that is close to the display area.

[0116] In an exemplary embodiment, the scanning shift register can have an 8T2C circuit structure, and the light emission shift register can have a 10T3C or 12T3C circuit structure. The present disclosure does not impose any restrictions in this regard.

[0117] In an exemplary embodiment, Fig. 9A is an equivalent circuit diagram of a sample-shift register. As in Fig. As shown in Figure 9A, the sampling shift register can include: a first to eighth sampling transistor GT1 to GT8, a first sampling capacitor GC1 and a second sampling capacitor GC2.

[0118] In an exemplary embodiment, as in Fig. As shown in Figure 9A, the gate electrode of the first sampling transistor GT1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first sampling transistor GT1 is electrically connected to the input terminal GIN, and the second electrode of the first sampling transistor GT1 is electrically connected to the first node N1; the gate electrode of the second sampling transistor GT2 is electrically connected to the first node N1, the first electrode of the second sampling transistor GT2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second sampling transistor GT2 is electrically connected to the second node N2;The gate electrode of the third sampling transistor GT3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third sampling transistor GT3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third sampling transistor GT3 is electrically connected to the second node N2; the gate electrode of the fourth sampling transistor GT4 is electrically connected to the second node N2, the first electrode of the fourth sampling transistor GT4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth sampling transistor GT4 is electrically connected to the output terminal GOUT;The gate electrode of the fifth sampling transistor GT5 is electrically connected to the third node N3, the first electrode of the fifth sampling transistor GT5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fifth sampling transistor GT5 is electrically connected to the output terminal GOUT; the gate electrode of the sixth sampling transistor GT6 is electrically connected to the second node N2, the first electrode of the sixth sampling transistor GT6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth sampling transistor GT6 is electrically connected to the first electrode of the seventh sampling transistor GT7; the gate electrode of the seventh sampling transistor GT7 is electrically connected to the second clock signal terminal CK2, and the second electrode of the seventh sampling transistor GT7 is electrically connected to the first node N1;The gate electrode of the eighth sampling transistor GT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth sampling transistor GT8 is electrically connected to the first node N1, and the second electrode of the eighth sampling transistor GT8 is electrically connected to the third node N3; the first electrode plate GC11 of the first sampling capacitor GC1 is electrically connected to the second node N2, and the second electrode plate GC12 of the first sampling capacitor GC1 is electrically connected to the first power supply terminal VGH; the first electrode plate GC21 of the second sampling capacitor GC2 is electrically connected to the third node N3, and the second electrode plate GC22 of the second sampling capacitor GC2 is electrically connected to the output terminal GOUT.

[0119] In an exemplary embodiment, the first sampling transistor GT1 up to the eighth sampling transistor GT8 can be P-type transistors or can be N-type transistors.

[0120] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0121] Fig. Figure 9B shows a timing diagram of the sample-shift register according to Fig. 9A. Fig. 9B assumes an example where the first sampling transistor GT1 through the eighth sampling transistor GT8 are P-type transistors. As in Fig. As shown in Figure 9B, the working process of the sample-shift register provided in an exemplary embodiment comprises the following phases: In input phase B1, the signals from the first clock signal terminal CK1 and the input terminal GIN are low-level signals, and the signal from the second clock signal terminal CK2 is a high-level signal. Since the signal from the first clock signal terminal CK1 is low-level, the first sampling transistor GT1 is switched on, and the signal from the input terminal GIN is passed through the first sampling transistor GT1 to the first node N1. Since the eighth sampling transistor GT8 receives the low-level signal from the second power supply terminal VGL, the eighth sampling transistor GT8 is switched on. The level of the third node N3 can switch on the fifth sampling transistor GT5, and the signal from the second clock signal terminal CK2 is passed through the fifth sampling transistor GT5 to the output terminal GOUT. That is, in input phase B1, the signal at the output terminal GOUT is the high-level signal from the second clock signal terminal CK2.Furthermore, since the signal from the first clock signal terminal CK1 is a low-level signal, the third sampling transistor GT3 is switched on, and the low-level signal from the second power supply terminal VGL is passed through the third sampling transistor GT3 to the second node N2. At this point, both the fourth sampling transistor GT4 and the sixth sampling transistor GT6 are switched on. Since the signal from the second clock signal terminal CK2 is a high-level signal, the seventh sampling transistor GT7 is switched off.

[0122] In output phase B2, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal GIN is a high-level signal. The fifth sampling transistor GT5 is switched on, and the signal from the second clock signal terminal CK2 is output via the fifth sampling transistor GT5 as the signal at the output terminal GOUT. In output phase B2, the signal at one end of the second sampling capacitor GC2 connected to the output terminal GOUT changes to the signal at the second power supply terminal VGL. Due to the bootstrap effect of the second sampling capacitor GC2, the eighth sampling transistor GT8 is switched off, allowing the fifth sampling transistor GT5 to switch on more effectively, resulting in a low-level signal at the output terminal GOUT.Furthermore, the signal from the first clock signal terminal CK1 is a high-level signal, so both the first sampling transistor GT1 and the third sampling transistor GT3 are switched off. The second sampling transistor GT2 is switched on, and the high-level signal from the first clock signal terminal CK1 is passed through the second sampling transistor GT2 to the second node N2, thereby switching off both the fourth sampling transistor GT4 and the sixth sampling transistor GT6. Since the signal from the second clock signal terminal CK2 is a low-level signal, the seventh sampling transistor GT7 is switched on.

[0123] In buffer phase B3, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, the signal at input terminal GIN is a high-level signal, the fifth sampling transistor GT5 is switched on, and the signal from the second clock signal terminal CK2 is output via the fifth sampling transistor GT5. Since the signal at the first clock signal terminal CK1 is a high-level signal, both the first sampling transistor GT1 and the third sampling transistor GT3 are switched off, the eighth sampling transistor GT8 is switched on, the second sampling transistor GT2 is switched on, and the high-level signal from the first clock signal terminal CK1 is passed via the second sampling transistor GT2 to the second node N2, thereby switching off both the fourth sampling transistor GT4 and the sixth sampling transistor GT6.Since the signal from the second clock signal terminal CK2 is a high-level signal, the seventh sampling transistor GT7 is switched off.

[0124] In the first sub-phase B41 of the stabilization phase B4, the signal at the first clock signal terminal CK1 is a low-level signal, while the signals at the second clock signal terminal CK2 and the input terminal GIN are high-level signals. Since the signal at the first clock signal terminal CK1 is a low-level signal, the first sampling transistor GT1 is switched on, and the signal from the input terminal GIN is passed through the first sampling transistor GT1 to the first node N1, while the second sampling transistor GT2 is switched off. Since the eighth sampling transistor GT8 is switched on, the fifth sampling transistor GT5 is switched off.Since the signal from the first clock signal terminal CK1 is a low-level signal, the third sampling transistor GT3 is switched on, both the fourth sampling transistor GT4 and the sixth sampling transistor GT6 are switched on, and the high-level signal from the first power supply terminal VGH is transferred via the fourth sampling transistor GT4 to the output terminal GOUT, that is, the signal from the output terminal GOUT is a high-level signal.

[0125] In the second sub-phase B42 of the stabilization phase B4, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal GIN is a high-level signal. The fifth sampling transistor GT5 and the second sampling transistor GT2 are both switched off. Since the signal at the first clock signal terminal CK1 is a high-level signal, both the first sampling transistor GT1 and the third sampling transistor GT3 are switched off. Due to the holding effect of the first sampling capacitor GC1, both the fourth sampling transistor GT4 and the sixth sampling transistor GT6 are switched on, and the high-level signal is passed through the fourth sampling transistor GT4 to the output terminal GOUT. That is, the signal at the output terminal GOUT is a high-level signal.

[0126] In the second sub-phase B42, since the signal of the second clock signal terminal CK2 is a low-level signal, the seventh sampling transistor GT7 is switched on, thereby transferring the high-level signal via the sixth sampling transistor GT6 and the seventh sampling transistor GT7 to the third node N3 and the first node N1, in order to keep the signals of the third node N3 and the first node N1 at a high-level level.

[0127] In the third sub-phase B43, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high-level signals, and the signal at the input terminal GIN is also high-level. The fifth sampling transistor GT5 and the second sampling transistor GT2 are off. Since the signal at the first clock signal terminal CK1 is high-level, both the first sampling transistor GT1 and the third sampling transistor GT3 are off, and both the fourth sampling transistor GT4 and the sixth sampling transistor GT6 are on. The high-level signal is passed through the fourth sampling transistor GT4 to the output terminal GOUT; that is, the signal at the output terminal GOUT is high-level.

[0128] Fig. Figure 10A shows an equivalent circuit diagram of a light emission shift register. As in Fig. As shown in Figure 10A, the light emission shift register can comprise: a first light emission transistor ET1 to a tenth light emission transistor ET10, as well as a first light emission capacitor EC1 to a third light emission capacitor EC3.

[0129] In an exemplary embodiment, as in Fig. As shown in Figure 10A, the gate electrode of the first light-emitting transistor ET1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first light-emitting transistor ET1 is electrically connected to the input terminal EIN, and the second electrode of the first light-emitting transistor ET1 is electrically connected to the first node N1; the gate electrode of the second light-emitting transistor ET2 is electrically connected to the first node N1, the first electrode of the second light-emitting transistor ET2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second light-emitting transistor ET2 is electrically connected to the second node N2;The gate electrode of the third light-emitting transistor ET3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third light-emitting transistor ET3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third light-emitting transistor ET3 is electrically connected to the second node N2; the gate electrode of the fourth light-emitting transistor ET4 is electrically connected to the second clock signal terminal CK2, the first electrode of the fourth light-emitting transistor ET4 is electrically connected to the first node N1, and the second electrode of the fourth light-emitting transistor ET4 is electrically connected to the first electrode of the fifth light-emitting transistor ET5;The gate electrode of the fifth light-emitting transistor ET5 is electrically connected to the second node N2, and the second electrode of the fifth light-emitting transistor ET5 is electrically connected to the first power supply terminal VGH; the first electrode of the sixth light-emitting transistor ET6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth light-emitting transistor ET6 is electrically connected to the third node N3; the gate electrode of the seventh light-emitting transistor ET7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh light-emitting transistor ET7 is electrically connected to the third node N3, and the second electrode of the seventh light-emitting transistor ET7 is electrically connected to the gate electrode of the ninth light-emitting transistor ET9;The gate electrode of the eighth light-emitting transistor ET8 is electrically connected to the first node N1, the first electrode of the eighth light-emitting transistor ET8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth light-emitting transistor ET8 is electrically connected to the gate electrode of the ninth light-emitting transistor ET9; the first electrode of the ninth light-emitting transistor ET9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth light-emitting transistor ET9 is electrically connected to the output terminal EOUT; the first electrode of the tenth light-emitting transistor ET10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth light-emitting transistor ET10 is electrically connected to the output terminal EOUT;The first electrode plate of the first light-emitting capacitor EC1 is electrically connected to the gate electrode of the sixth light-emitting transistor ET6, and the second electrode plate of the first light-emitting capacitor EC1 is electrically connected to the third node N3; the first electrode plate EC21 of the second light-emitting capacitor EC2 is electrically connected to the gate electrode of the ninth light-emitting transistor ET9, and the second electrode plate EC22 of the second light-emitting capacitor EC2 is electrically connected to the first power supply terminal VGH; the first electrode plate EC31 of the third light-emitting capacitor EC3 is electrically connected to the gate electrode of the tenth light-emitting transistor ET10, and the second electrode plate EC32 of the third light-emitting capacitor EC3 is electrically connected to the second power supply terminal VGL.

[0130] In an exemplary embodiment, the first light emission transistor ET1 to the tenth light emission transistor ET10 can be either P-type transistors or N-type transistors.

[0131] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0132] Fig. Figure 10B shows a timing diagram of the light emission shift register according to Fig. 10A. Fig. Section 10B considers an example where the first light-emitting transistor ET1 through the tenth light-emitting transistor ET10 are P-type transistors. The operating process of the light-emitting shift register provided in an exemplary embodiment can comprise the following phases: In the first phase, C1, the signal from the first clock signal terminal, CK1, is a low-level signal, turning on the first light-emitting transistor, ET1, and the third light-emitting transistor, ET3. The turned-on first light-emitting transistor, ET1, transmits the high-level signal from its input terminal, EIN, to the first node, N1, making the signal at N1 high-level and turning off the second light-emitting transistor, ET2, the eighth light-emitting transistor, ET8, and the tenth light-emitting transistor, ET10. Simultaneously, the turned-on third light-emitting transistor, ET3, transmits the low-level signal from the second power supply terminal, VGL, to the second node, N2, making the signal at N2 low-level and turning on the fifth light-emitting transistor, ET5, and the sixth light-emitting transistor, ET6.Since the signal at the second clock signal terminal CK2 is a high-level signal, the seventh light-emitting transistor ET7 is switched off. Furthermore, due to the storage effect of the third light-emitting capacitor EC3, the ninth light-emitting transistor ET9 is switched off. In the first phase C1, because both the ninth light-emitting transistor ET9 and the tenth light-emitting transistor ET10 are switched off, the signal at the output terminal EOUT remains at the previous low-level level.

[0133] A second phase C2, in which the signal from the second clock signal terminal CK2 is a low-level signal, turns on the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7. Since the signal from the first clock signal terminal CK1 is a high-level signal, the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are off. Due to the memory effect of the first light-emitting capacitor EC1, the second node N2 can maintain the low-level signal from the previous phase; therefore, the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.The high-level signal from the first power supply terminal VGH is transmitted to the first node N1 via the switched-on fifth light-emitting transistor ET5 and the switched-on fourth light-emitting transistor ET4, thus maintaining the high-level level of the first node N1 in the previous phase, so that the second light-emitting transistor ET2, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are switched off.Furthermore, the low-level signal of the second clock signal terminal CK2 is transferred via the switched-on sixth light-emitting transistor ET6 and the switched-on seventh light-emitting transistor ET7 to the gate electrode of the ninth light-emitting transistor ET9, thereby switching on the ninth light-emitting transistor ET9, and the switched-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so that the signal of the output terminal EOUT is a high-level signal.

[0134] A third phase, C3, in which the signal from the first clock signal terminal, CK1, is a low-level signal, so the first light-emitting transistor, ET1, and the third light-emitting transistor, ET3, are switched on. The signal from the second clock signal terminal, CK2, is a high-level signal, so the fourth light-emitting transistor, ET4, and the seventh light-emitting transistor, ET7, are switched off. Due to the memory effect of the third light-emitting capacitor, EC3, the ninth light-emitting transistor, ET9, remains switched on, and the switched-on ninth light-emitting transistor, ET9, outputs the high-level signal from the first power supply terminal, VGH, so the signal at the output terminal, EOUT, remains a high-level signal.

[0135] A fourth phase, C4, in which the signal from the first clock signal terminal, CK1, is a high-level signal, so the first light-emitting transistor, ET1, and the third light-emitting transistor, ET3, are off. The signal from the second clock signal terminal, CK2, is a low-level signal, so the fourth light-emitting transistor, ET4, and the seventh light-emitting transistor, ET7, are on. Due to the memory effect of the second light-emitting capacitor, EC2, the first node, N1, maintains the high-level signal from the previous phase, so the second light-emitting transistor, ET2, the eighth light-emitting transistor, ET8, and the tenth light-emitting transistor, ET10, are off. Due to the memory effect of the first light-emitting capacitor, EC1, the second node, N2, continues to maintain the low-level signal from the previous phase, so the fifth light-emitting transistor, ET5, and the sixth light-emitting transistor, ET6, are on.Furthermore, the low-level signal of the second clock signal terminal CK2 is passed via the switched-on sixth light-emitting transistor ET6 and the switched-on seventh light-emitting transistor ET7 to the gate electrode of the ninth light-emitting transistor ET9, thereby switching on the ninth light-emitting transistor ET9, and the switched-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so that the signal of the output terminal EOUT remains a high-level signal.

[0136] A fifth phase, C5, in which the signal from the first clock signal terminal, CK1, is a low-level signal, so the first light-emitting transistor, ET1, and the third light-emitting transistor, ET3, are switched on. The signal from the second clock signal terminal, CK2, is a high-level signal, so the fourth light-emitting transistor, ET4, and the seventh light-emitting transistor, ET7, are switched off. The switched-on first light-emitting transistor, ET1, passes the high-level signal from input terminal EIN to the first node, N1, which makes the signal at the first node N1 a low-level signal, so the second light-emitting transistor, ET2, the eighth light-emitting transistor, ET8, and the tenth light-emitting transistor, ET10, are switched on.The second light-emitting transistor, ET2, is switched on and transmits the low-level signal from the first clock signal terminal, CK1, to the second node, N2. This lowers the level of the second node, allowing it to maintain the low level from the previous phase. The fifth light-emitting transistor, ET5, and the sixth light-emitting transistor, ET6, are then switched on. Simultaneously, the eighth light-emitting transistor, ET8, is switched on and transmits the high-level signal from the first power supply terminal, VGH, to the gate electrode of the ninth light-emitting transistor, ET9, thus switching it off. The tenth light-emitting transistor, ET10, is switched on and outputs the low-level signal from the second power supply terminal, VGL, reducing the output signal at terminal EOUT to a low level.

[0137] In an exemplary embodiment, they show Fig. 11 a schematic diagram of the structure of the semiconductor layer and the second electrically conductive layer in which in Fig. 5A provided display substrate, and Fig. Figure 12 shows a schematic diagram of the structure of the semiconductor layer and the second electrically conductive layer in which in Fig. 6A provided display substrate. As in Fig. 11 and Fig. Figure 12 shows a light emission output signal line comprising at least one output connection part COL and at least one output line OL, wherein the output connection part COL extends in the first direction D1 and at least one output line OL is arranged along the first direction D1.

[0138] The output connection part COL is electrically connected to the light emission shift register and at least one output line OL, wherein the output line OL corresponds one-to-one to a light emission signal line to which the light emission output signal line is connected, and the output line is electrically connected to the corresponding light emission signal line.

[0139] In an exemplary embodiment, as in Fig. Shown in 11, the output line OL includes the one shown in Fig. 5A provided display substrate: an output body part OLA extending at least partially in the second direction D2 and an output connection part OLB extending in the first direction D1, wherein the output body part OLA is electrically connected to the output connection part OLB.

[0140] In an exemplary embodiment, as in Fig. As shown in Figure 5A, the second electrode of the first discharge transistor and the second electrode of the second discharge transistor form a single structure, and their orthographic projection onto the substrate overlaps at least partially with an orthographic projection of the output interconnect onto the substrate. The single structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor is electrically connected to the output interconnect.

[0141] In an exemplary embodiment, as in Fig. Figure 11 shows the active layer RT11 of the first discharge transistor and the active layer RT21 of the second discharge transistor in the diagram. Fig. The 5A provided display substrate is a one-piece structure and extends along the second direction D2. The orthographic projection of the output interconnect part OLB onto the substrate does not overlap with the orthographic projection of the one-piece structure of the active layer RT11 of the first discharge transistor and the active layer RT21 of the second discharge transistor onto the substrate.

[0142] In an exemplary embodiment, as in Fig. Figure 12 shows the active layer RT11 of the first discharge transistor and the active layer RT21 of the second discharge transistor in the diagram. Fig. The display substrate provided in 6A is a one-piece structure and comprises: an active body part R1 and an active connecting part R2, wherein the active body part R1 is electrically connected to the active connecting part R2, and the active body part R1 and the active connecting part R2 are arranged in the first direction D1.

[0143] In an exemplary embodiment, as in Fig. As shown in Figure 12, the active body part R1 extends in the second direction D2, and the active connecting part R2 extends at least partially in the first direction D1.

[0144] In an exemplary embodiment, as in Fig. As shown in Figure 12, the active interconnect R2 has a bent shape. The bent shape of the active interconnect R2 can increase its resistance, thereby increasing the dissipation of static electricity, preventing burnout of the gate driver circuit, and improving the display effect and the reliability of the display substrate.

[0145] In an exemplary embodiment, as in Fig. As shown in Figure 12, the output line OL extends at least partially in the second direction D2; the second electrode of the first discharge transistor and the second electrode of the second discharge transistor are a single-piece structure. The orthographic projection of the active interconnect R2 onto the substrate overlaps at least partially with the orthographic projections of the single-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor, as well as the output line OL, onto the substrate, and the active interconnect is electrically connected to the single-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor, as well as to the output line OL.

[0146] In an exemplary embodiment, as in Fig. As shown in Figure 12, the width of the active connecting part R2 is smaller than the width of the active body part R1.

[0147] In an exemplary embodiment, as in Fig. 11 and Fig. As shown in Figure 12, the sampling shift register comprises: a first sampling capacitor, wherein the second electrode plate GC12 of the first sampling capacitor is electrically connected to the first sampling power supply line, and the second electrode plate GC21 of the first sampling capacitor extends in the second direction D2.

[0148] In an exemplary embodiment, as in Fig. 5A, Fig. 6A, Fig. 11 and Fig. As shown in Figure 12, the orthographic projection of the second electrode plate GC21 of the first scanning capacitor onto the substrate overlaps at least partially with the orthographic projections of the first scanning current supply line GVGH, the second scanning current supply line GVGL, the first scanning clock signal line GCK1, the second scanning clock signal line GCK2 and the scanning initial signal line GSTV onto the substrate.

[0149] In an exemplary embodiment, Fig. 13 Another schematic diagram of the structure of the display substrate. As in Fig. As shown in Figure 13, the display area can comprise: a first display area A1 and a second display area A2, which is located on at least one side of the first display area A1, wherein the display substrate further comprises: a light-emitting device and an anode connecting line AL, which are located in the display area 100. The pixel circuit is electrically connected to the light-emitting device. The pixel circuit comprises: a first pixel circuit 11 and a second pixel circuit 12, which are located in the second display area A2; and the light-emitting devices comprise: a first light-emitting device 21, which is located in the first display area A1, and a second light-emitting device 22, which is located in the second display area, wherein the first pixel circuit 11 is electrically connected to the first light-emitting device 21, and the second pixel circuit 12 is electrically connected to the second light-emitting device 22.

[0150] As in Fig. As shown in Figure 13, the orthographic projection of the first pixel circuit 11 onto the substrate overlaps at least partially with the orthographic projection of the first light emission element 21 connected to the first pixel circuit 11 onto the substrate.

[0151] As in Fig. As shown in Figure 13, the anode connecting line AL is electrically connected to the second light emission element 22 and to the second pixel circuits 12 connected to the second light emission element.

[0152] In an exemplary embodiment, the anode connecting line AL can be a transparent, electrically conductive line.

[0153] In an exemplary embodiment, as in Fig. 7A to Fig. As shown in Figure 7C, the driver structure layer can further comprise: a first power supply line VDD and a data signal line Data, which are located at least partially in the display area. The first power supply line VDD and the data signal line Data extend at least partially in the first direction D1.

[0154] In an exemplary embodiment, the data signal lines Data, which are connected to the columns of the pixel circuits on the left and right side of the first display area, extend in the first direction D1.

[0155] In an exemplary embodiment, as in Fig. As shown in Figure 7B, the driver structure layer may further comprise: a data link line DL located in the display area, wherein the data link line DL extends at least partially in the second direction D2.

[0156] In an exemplary embodiment, to ensure the display effect of the first display area, the data signal lines, the data signal lines connected to the columns of the pixel circuits on the top and bottom of the first display area, are arranged around the first display area, i.e., the data signal lines connected to the columns of the pixel circuits on the top and bottom of the first display area have a bent shape.The data signal lines connected to the columns of the pixel circuits on the top and bottom of the first display area comprise: several spaced-apart data main lines running in the first direction, and several spaced-apart data link lines running in the second direction, with adjacent data main lines being interconnected via data link lines and adjacent data link lines being interconnected via data main lines. To prevent crosstalk of the data signals, the data main lines and the data link lines are arranged in different layers.

[0157] In the display substrate, the structure of some pixel circuits includes data link lines, and the structure of some pixel circuits does not include data link lines. Fig. 7B is explained using the example of the structure of pixel circuits with data connection lines, and Fig. 7A and Fig. 7C will be explained using the example of the structure of pixel circuits without data connection lines.

[0158] In an exemplary embodiment, the driver structure layer further comprises: a fourth electrically conductive layer and a fifth electrically conductive layer, which are stacked successively on a third electrically conductive layer.

[0159] In an exemplary embodiment, the third electrically conductive layer comprises at least the data connection line.

[0160] In an exemplary embodiment, the fourth electrically conductive layer comprises at least the first power supply line and the data signal line.

[0161] In an exemplary embodiment, the fifth electrically conductive layer comprises at least the anode connecting conductor.

[0162] In an exemplary embodiment, as in Fig. 5A, Fig. 6A and Fig. 7A to Fig. As shown in Figure 7C, the driver structure layer may further comprise: at least one initial power supply line located in the non-display area, and at least one initial signal line located at least partially in the display area; wherein the initial power supply line is located on a side of the sampling driver circuit that is close to the display area, the initial power supply line extends at least partially in the first direction D1, and the initial signal line extends at least partially in the second direction D2. Fig. 5 and Fig. 6 are described using the example of two initial power supply lines, for example a first initial power supply line INITL1 and a second initial power supply line INITL2. Fig. 7A and Fig. 7B are described using the example of two initial signal lines, namely a first initial signal line INIT1 and a second initial signal line INIT2.

[0163] In an exemplary embodiment, the initial signal line corresponds one-to-one with the initial power supply line, wherein the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line, respectively.

[0164] In one exemplary embodiment, the initial power supply line can have a two-layer structure. The initial power supply line can comprise: a first sub-initial power supply line and a second sub-initial power supply line, which are electrically connected to each other.

[0165] In an exemplary embodiment, the second electrically conductive layer comprises at least the initial signal line.

[0166] In an exemplary embodiment, the third electrically conductive layer comprises at least the first sub-initial power supply line of the initial power supply line.

[0167] In an exemplary embodiment, the fourth electrically conductive layer comprises at least the second sub-initial power supply line of the initial power supply line.

[0168] In an exemplary embodiment, as in Fig. 5B and Fig. As shown in Figure 6B, the driver structure layer may further comprise: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a flat layer 15, a fifth insulating layer 16 and a sixth insulating layer 17.The first insulating layer 11 is arranged between the semiconductor layer and the first electrically conductive layer, the second insulating layer 12 is arranged between the first electrically conductive layer and the second electrically conductive layer, the third insulating layer 13 is arranged between the second electrically conductive layer and the third electrically conductive layer, the fourth insulating layer 14 and the flat layer 15 are arranged between the third electrically conductive layer and the fourth electrically conductive layer, the fifth insulating layer 16 is arranged between the fourth electrically conductive layer and the fifth electrically conductive layer, and the sixth insulating layer 17 is arranged on a side of the fifth electrically conductive layer that faces away from the substrate.

[0169] In an exemplary embodiment, as in Fig. 5A and Fig. As shown in Figure 6A, the flat layer 15 has a groove X. The depth of the groove X can be less than or equal to the thickness of the flat layer. The present disclosure does not impose any restrictions in this regard.

[0170] In an exemplary embodiment, the orthographic projection of the electrostatic discharge circuit ER onto the substrate overlaps at least partially with the orthographic projection of the groove X onto the substrate. The present disclosure, by arranging the electrostatic discharge circuit at the location of the groove in the flat layer, ensures that the area occupied by the display frame is not increased, thereby enabling the realization of a narrow frame.

[0171] In an exemplary embodiment, the length of the groove X in the second direction is less than or equal to the distance between the second light emission power supply line EVGL and the first scanning power supply line GVGH.

[0172] In an exemplary embodiment, the driver structure layer can further comprise: a second power supply connection line and a second power supply line. The second power supply line and the second power supply connection line are electrically connected to each other. The second power supply line is electrically connected to the cathode of the light-emitting device.

[0173] In an exemplary embodiment, the second power supply connection line can be arranged in the third electrically conductive layer, and the second power supply line can be arranged in the fourth electrically conductive layer.

[0174] In an exemplary embodiment, the orthographic projection of the second power supply connection line onto the substrate and the orthographic projection of the second power supply line onto the substrate overlap at least partially. The second power supply line is connected to the second power supply connection line through a through-hole between the fourth insulating layer and the flat layer.

[0175] In an exemplary embodiment, the second power supply connection line can have a linear shape extending in the second direction D2 and be located on a side of the light emission initial signal line that is facing away from the first light emission clock signal line.

[0176] In an exemplary embodiment, the second power supply line can have a linear shape extending in the second direction D2, and its orthographic projection onto the substrate also overlaps at least partially with the orthographic projections of the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, and the first light emission power supply line onto the substrate.

[0177] In one exemplary embodiment, the second power supply line has several through-holes.

[0178] In an exemplary embodiment, the distance between the orthographic projection of the second power supply line onto the substrate and the orthographic projection of the second light emission power supply line onto the substrate is smaller than the distance between the first light emission power supply line and the second light emission power supply line.

[0179] The following is an exemplary explanation based on the manufacturing process of the display substrate. The “patterning process” mentioned in the present disclosure includes treatments such as the application of a photoresist, exposure of a mask, development, etching, and removal of the photoresist, or the like, for a metallic material, an inorganic material, or a transparent, electrically conductive material. For an organic material, treatments such as the application of an organic material, exposure of a mask, development, or the like may be used. One or more of the following processes may be used for deposition: sputtering, evaporation, or chemical vapor deposition; one or more of the following may be used for application: spray coating, spin coating, and inkjet printing; and one or more of the following may be used for etching: dry etching or wet etching, which is not limited in the present disclosure."Film" refers to a membrane produced from a material by deposition, application, or other means onto the substrate. If the "film" does not require a patterning process during the entire manufacturing process, it may also be referred to as a "layer." If the "film" does require a patterning process during the entire manufacturing process, it will be referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In the present disclosure, the phrase "A and B are provided in one and the same layer" means that A and B are formed simultaneously by the same patterning process, and the "thickness" of a film layer is a dimension of the film layer in a direction perpendicular to a display substrate.The statements "the orthographic projection of B lies within the scope of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" mean that the boundary of the orthographic projection of B falls within the scope of the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A and the boundary of the orthographic projection of B are superimposed. Fig. 14 to Fig. 33 are based on the in Fig. 5A and Fig. The structures shown in section 6A are explained in the non-display area. Fig. 34 to Fig. 55 are based on the in Fig. 7B and Fig. The pixel circuits shown in section 7C are explained in the display area.

[0180] (1) Forming a semiconductor layer pattern on the substrate, comprising: depositing a semiconductor layer on the substrate, and patterning the semiconductor layer by means of a patterning process to form the semiconductor layer pattern. As described in Fig. 14, Fig. 15, Fig. 34 and Fig. 35 shown, shows Fig. 14 a schematic diagram of Fig. 5A after the formation of the semiconductor layer pattern, Fig. Figure 15 shows a schematic diagram of Fig. 6A after the formation of the semiconductor layer pattern, Fig. Figure 34 shows a schematic diagram of Fig. 7B after the formation of the semiconductor layer pattern, and Fig. Figure 35 shows a schematic diagram of Fig. 7C after the formation of the semiconductor layer pattern.

[0181] In an exemplary embodiment, as in Fig. 14, Fig. 15, Fig. 34 and Fig. As shown in Figure 35, the semiconductor layer pattern can include: the active layer ET 11 of the first light emission transistor to the active layer ET101 of the tenth light emission transistor in the light emission shift register, the active layer RT11 of the first discharge transistor to the active layer RT21 of the second discharge transistor in the electrostatic discharge circuit, the active layer GT11 of the first sampling transistor to the active layer GT81 of the eighth sampling transistor in the sampling shift register, and the active layer M11 of the first transistor to an active layer M71 of the seventh transistor in the pixel circuit.

[0182] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate may consist of one or more of the following materials, but is not limited to: glass, metal foils; and the flexible substrate may consist of one or more of the following materials, but is not limited to: polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyaryl ester, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0183] In an exemplary embodiment, the flexible substrate can comprise: a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, arranged in a stacked configuration. Polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc., can be used as materials for the first and second flexible material layers, while silicon nitride (SiNx) or silicon dioxide (SiOx), etc., can be used as materials for the first and second inorganic material layers to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers.and amorphous silicon (a-si) can be used as the material for the semiconductor layer. In an exemplary embodiment, the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 is used as an example, the fabrication process of which can comprise the following steps: First, a layer of polyimide is applied to a glass support, which, after curing, forms a first flexible layer (PI1); then, a barrier film is deposited on the first flexible layer to form a first barrier layer (Barrier1) that covers the first flexible layer; then, an amorphous silicon film is deposited on the first barrier layer to form an amorphous silicon layer (a-si) that covers the first barrier layer; subsequently, another layer of polyimide is applied to the amorphous silicon layer, which, after curing, forms a second flexible layer (PI2); then, a barrier film is deposited on the second flexible layer,to form a second barrier layer (Barrier2) that covers the second flexible layer, thus completing the production of the substrate.

[0184] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, the active layer ET41 of the fourth light emission transistor and the active layer ET51 of the fifth light emission transistor are an interconnected one-piece structure, and the active layer ET91 of the ninth light emission transistor and the active layer ET101 of the tenth light emission transistor are an interconnected one-piece structure.

[0185] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, in the second direction D2, the active layer ET11 of the first light-emitting transistor is located on the side of the active layer ET91 of the ninth light-emitting transistor (also the active layer ET101 of the tenth light-emitting transistor) facing away from the display area. The active layer ET71 of the seventh light-emitting transistor is located on the side of the active layer ET81 of the eighth light-emitting transistor facing away from the display area.The active layer ET11 of the first light emission transistor and the active layer ET41 of the fourth light emission transistor (also the active layer ET51 of the fifth light emission transistor) are located on one side of the active layer ET21 of the second light emission transistor that is facing away from the display area, and the active layer ET31 of the third light emission transistor and the active layer ET61 of the sixth light emission transistor are located on one side of the active layer ET21 of the second light emission transistor that is facing the active layer ET91 of the ninth light emission transistor (the active layer ET101 of the tenth light emission transistor).In the first direction D1, the active layer ET51 of the fifth light emission transistor of the light emission shift register in the current stage is located on one side of the active layer ET41 of the fourth light emission transistor, which faces the light emission shift register in the next stage, and the active layer ET11 of the first light emission transistor up to the active layer ET61 of the sixth light emission transistor of the shift register in the current stage are located on one side of the active layer ET81 of the eighth light emission transistor, which faces the light emission shift register in the previous stage.

[0186] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, the active layer ET11 of the first light-emitting transistor up to the active layer ET71 of the seventh light-emitting transistor, and the active layer ET91 of the ninth light-emitting transistor up to the active layer ET101 of the tenth light-emitting transistor, can have a strip-like shape extending in the first direction D1. The active layer ET81 of the eighth light-emitting transistor can have a strip-like shape extending in the second direction D2.

[0187] In an exemplary embodiment, the active layer of each light-emitting transistor can comprise a first region, a second region, and a channel region arranged between the first and second regions. In an exemplary embodiment, the first region ET41-1 of the active layer ET41 of the fourth light-emitting transistor can simultaneously serve as the second region ET51-2 of the active layer ET51 of the fifth light-emitting transistor, while the first region ET11-1 and second region ET11-2 of the active layer ET11 of the first light-emitting transistor, the first region ET21-1 and second region ET21-2 of the active layer ET21 of the second light-emitting transistor, the first region ET31-1 and second region ET31-2 of the active layer ET31 of the third light-emitting transistor, and the second region ET41-2 of the active layer ET41 of the fourth light-emitting transistor,The first region ET51-1 of the active layer ET51 of the fifth light-emitting transistor, the first region ET61-1 and second region ET61-2 of the active layer ET61 of the sixth light-emitting transistor, the first region ET71-1 and second region ET71-2 of the active layer ET71 of the seventh light-emitting transistor, the first region ET81-1 and second region ET81-2 of the active layer ET81 of the eighth light-emitting transistor, the first region ET91-1 and second region ET91-2 of the active layer ET91 of the ninth light-emitting transistor, and the first region ET101-1 and second region ET101-2 of the active layer ET101 of the tenth light-emitting transistor can each be formed separately.

[0188] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, the active layer RT11 of the first discharge transistor and the active layer RT21 of the second discharge transistor form an interconnected, single-piece structure. The active layer RT11 of the first discharge transistor and the active layer RT21 of the second discharge transistor are located on one side of the active layer ET91 of the ninth light-emitting transistor (also the active layer ET101 of the tenth light-emitting transistor), which is close to the display area.

[0189] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, in the second direction D2 the active layer RT21 of the second discharge transistor is located on one side of the active layer RT11 of the first discharge transistor, which is close to the display area.

[0190] In an exemplary embodiment, as in Fig. As shown in Figure 14, the active layer RT11 of the first discharge transistor (also the active layer RT21 of the second discharge transistor) can be located in the Fig. The display substrate provided in 3B has a strip-shaped form extending in the second direction D2.

[0191] In an exemplary embodiment, as in Fig. As shown in Figure 15, the active layer RT11 of the first discharge transistor (also the active layer RT21 of the second discharge transistor) can be located in the Fig. The display substrate provided by 3C comprises: an active body part R1 and an active connecting part R2. The active body part R1 and the active connecting part R2 are an interconnected, one-piece structure and are arranged in the first direction D1.

[0192] In an exemplary embodiment, as in Fig. As shown in Figure 15, the active body part R1 can have a strip-shaped form extending in the second direction D2, and the active connecting part R2 can have a bent form extending at least partially in the first direction D1.

[0193] In an exemplary embodiment, as in Fig. As shown in Figure 15, the width of the active connecting part R2 can be smaller than the width of the active body part R1.

[0194] In an exemplary embodiment, the active layer of each discharge transistor can comprise a first region, a second region, and a channel region arranged between the first and second regions. In an exemplary embodiment, the second region RT11-2 of the active layer RT11 of the first discharge transistor can simultaneously serve as the second region RT21-2 of the active layer RT21 of the second discharge transistor. The first region RT11-1 of the active layer RT11 of the first discharge transistor and the first region RT21-1 of the active layer RT21 of the second discharge transistor can each be configured separately.

[0195] In an exemplary embodiment, as in Fig. As shown in Figure 15, the second region RT11-2 of the active layer RT11 of the first discharge transistor (the second region RT21-2 of the active layer RT21 of the second discharge transistor) comprises a central section of the active body part as well as the active connecting part R2.

[0196] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, the active layer GT11 of the first sampling transistor, the active layer GT61 of the sixth sampling transistor, and the active layer GT71 of the seventh sampling transistor form an interconnected, single-piece structure. The active layer GT21 of the second sampling transistor and the active layer GT31 of the third sampling transistor form an interconnected, single-piece structure, and the active layer GT41 of the fourth sampling transistor and the active layer GT51 of the fifth sampling transistor form an interconnected, single-piece structure.

[0197] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, in the second direction D2, the active layer GT11 of the first sampling transistor up to the active layer GT31 of the third sampling transistor, as well as the active layer GT51 of the fifth sampling transistor up to the active layer GT81 of the eighth sampling transistor, are located on one side of the active layer GT41 of the fourth sampling transistor (also the active layer GT51 of the fifth transistor) facing away from the display area, and on one side of the active layer RT11 of the first discharge transistor (also the active layer RT21 of the second discharge transistor) facing the display area. The active layer GT21 of the second sampling transistor (also the active layer GT31 of the third sampling transistor) is located between the active layer GT11 of the first sampling transistor (the active layer GT61 of the sixth sampling transistor and the active layer GT71 of the seventh sampling transistor) and the active layer GT81 of the eighth sampling transistor.The active layer GT11 of the first sampling transistor (the active layer GT61 of the sixth sampling transistor and the active layer GT71 of the seventh sampling transistor) is located on one side of the active layer GT21 of the second sampling transistor (also the active layer GT31 of the third sampling transistor), which faces the active layer RT11 of the first discharge transistor (also the active layer RT21 of the second discharge transistor), and the active layer GT81 of the eighth sampling transistor is located on one side of the active layer GT21 of the second sampling transistor (also the active layer GT31 of the third sampling transistor), which faces the active layer GT41 of the fourth sampling transistor (also the active layer GT51 of the fifth transistor).In the first direction D1, the active layer GT41 of the fourth sampling transistor of the sampling shift register in the current stage is located on one side of the active layer GT51 of the fifth transistor, which faces the sampling shift register in the next stage.

[0198] In an exemplary embodiment, as in Fig. 14 and Fig. As shown in Figure 15, the active layer GT11 of the first sampling transistor, the active layer GT41 of the fourth sampling transistor, the active layer GT51 of the fifth transistor, the active layer GT61 of the sixth sampling transistor, the active layer GT71 of the seventh sampling transistor, and the active layer GT81 of the eighth sampling transistor can have a linear shape extending in the first direction D1. The active layer GT21 of the second sampling transistor can have a linear shape extending in the second direction D2. The active layer GT31 of the third sampling transistor can have a horizontally inverted "7" shape.

[0199] In an exemplary embodiment, the active layer of each sampling transistor can comprise a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region GT11-2 of the active layer GT11 of the first sampling transistor can serve as the second region GT71-2 of the active layer GT71 of the seventh sampling transistor; the second region GT21-2 of the active layer GT21 of the second sampling transistor can serve as the second region GT31-2 of the active layer GT31 of the third sampling transistor; the second region GT41-2 of the active layer GT41 of the fourth sampling transistor can simultaneously serve as the second region GT51-2 of the active layer GT51 of the fifth sampling transistor; and the second region GT61-2 of the active layer GT61 of the sixth sampling transistor can serve as the second region GT71-1 of the active layer GT71 of the seventh sampling transistor.

[0200] In an exemplary embodiment, as in Fig. 34 and Fig. As shown in Figure 35, the active layer M11 of the first transistor to the active layer M71 of the seventh transistor within the same subpixel are an interconnected, single-piece structure.

[0201] In an exemplary embodiment, as in Fig. 34 and Fig. As shown in Figure 35, in the second direction D2, the active layer M21 of the second transistor and the active layer M61 of the sixth transistor can be on the same side of the active layer M31 of the third transistor in this subpixel, the active layer M41 of the fourth transistor and the active layer M51 of the fifth transistor can be on the same side of the active layer M31 of the third transistor in this subpixel, and the active layer M21 of the second transistor and the active layer M41 of the fourth transistor can be on different sides of the active layer M31 of the third transistor in this subpixel.In the first direction D1, the active layer M11 of the first transistor, the active layer M21 of the second transistor and the active layer M41 of the fourth transistor in the current row of subpixels can be located on one side of the active layer M31 of the third transistor in this subpixel, which is facing away from the previous row of subpixels, and the active layer M51 of the fifth transistor, the active layer M61 of the sixth transistor and the active layer M71 of the seventh transistor in this subpixel can be located on one side of the active layer M31 of the third transistor in this subpixel, which is facing towards the previous row of subpixels.

[0202] In an exemplary embodiment, as in Fig. 34 and Fig. As shown in Figure 35, the active layer M11 of the first transistor can have an “n”-shaped shape; the active layer M51 of the fifth transistor and the active layer M61 of the sixth transistor can have an “L”-shaped shape; the active layer M31 of the third transistor can have an “Ω”-shaped shape; and the active layer M41 of the fourth transistor and the active layer M71 of the seventh transistor can have an “I”-shaped shape.

[0203] In an exemplary embodiment, as in Fig. As shown in Figure 34, the active layer M21 of the second transistor can have a bent shape with two kinks.

[0204] In an exemplary embodiment, as in Fig. As shown in Figure 35, the active layer M21 of the second transistor can have an “L”-shaped form.

[0205] In an exemplary embodiment, as in Fig. 34 and Fig. As shown in Figure 35, the active layer of each transistor can comprise a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region M11-2 of the active layer M11 of the first transistor can serve as the first region M21-1 of the active layer M21 of the second transistor; the first region M31-1 of the active layer M31 of the third transistor can simultaneously serve as the second region M41-2 of the active layer M41 of the fourth transistor and the second region M51-2 of the active layer M51 of the fifth transistor; the second region M31-2 of the active layer M31 of the third transistor can simultaneously serve as the second region M21-2 of the active layer M21 of the second transistor and the first region M61-1 of the active layer M61 of the sixth transistor.The second region M61-2 of the active layer M61 of the sixth transistor can serve as the second region M71-2 of the active layer M71 of the seventh transistor; and the first region M11-1 of the active layer of the first transistor, the first region M41-1 of the active layer M41 of the fourth transistor, the first region M51-1 of the active layer M51 of the fifth transistor, and the first region M71-1 of the active layer M71 of the seventh transistor can each be formed separately.

[0206] (2) Forming a pattern of the first electrically conductive layer, comprising: depositing a first insulating film and a first electrically conductive layer on the substrate on which the aforementioned pattern is formed, and patterning the first insulating film and the first electrically conductive layer by means of a patterning process to form a pattern of the first insulating layer and a pattern of the first electrically conductive layer provided on the pattern of the first insulating layer, as in Fig. 16 to Fig. 18 as well Fig. 36 to Fig. 39 shown, whereby Fig. 16 a schematic diagram of the pattern of the first electrically conductive layer of Fig. 5A and Fig. 6A shows, Fig. 17 a schematic diagram of Fig. 5A after the formation of the pattern of the first electrically conductive layer shows, Fig. 18 a schematic diagram of the in Fig. 6A provided display substrate after forming the pattern of the first electrically conductive layer shows, Fig. 36 a schematic diagram of the pattern of the first electrically conductive layer of Fig. 7B shows, Fig. 37 a schematic diagram of Fig. Figure 7B shows the formation of the pattern of the first electrically conductive layer. Fig. 38 a schematic diagram of the pattern of the first electrically conductive layer of Fig. 7C shows, and Fig. 39 a schematic diagram of Fig. 7C after forming the pattern of the first electrically conductive layer. In an exemplary embodiment, the first electrically conductive layer can be referred to as the first gate metal layer (GATE1).

[0207] In an exemplary embodiment, as in Fig. 16 to Fig. 18 as well Fig. 36 to Fig. As shown in Figure 39, the first electrically conductive layer pattern can at least comprise: the gate electrode ET12 of the first light-emitting transistor to the gate electrode ET102 of the tenth light-emitting transistor, as well as the first electrode plate EC11 of the first light-emitting capacitor to the first electrode plate EC31 of the third light-emitting capacitor, which are located in the light-emitting shift register; the gate electrode RT12 of the first discharge transistor and the gate electrode RT22 of the second discharge transistor, which are located in the electrostatic discharge circuit; the gate electrode GT12 of the first sampling transistor to the gate electrode GT82 of the sampling light-emitting transistor, as well as the first electrode plate GC11 of the first sampling capacitor and the first electrode plate GC21 of the second sampling capacitor, which are located in the sampling shift register; the first signal connection line L1 and the second signal connection line L2;the reset signal line; the gate signal line; the light emission signal line; the gate electrode M11 of the first transistor to the gate electrode M71 of the seventh transistor, and the first electrode plate C1 of the capacitor.

[0208] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET12 of the first light-emitting transistor and the gate electrode ET32 of the third light-emitting transistor form an interconnected, single-piece structure. The gate electrode ET22 of the second light-emitting transistor, the gate electrode ET82 of the eighth light-emitting transistor, the gate electrode ET102 of the tenth light-emitting transistor, and the first electrode plate EC31 of the third light-emitting capacitor form an interconnected, single-piece structure. The gate electrode ET52 of the fifth light-emitting transistor, the gate electrode ET62 of the sixth light-emitting transistor, and the first electrode plate EC11 of the first light-emitting capacitor form an interconnected, single-piece structure. The gate electrode ET92 of the ninth light emission transistor and the first electrode plate EC21 of the second light emission capacitor form an interconnected, one-piece structure.The gate electrode ET42 of the fourth light emission transistor and the gate electrode ET72 of the seventh light emission transistor can be designed separately.

[0209] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, in the second direction D2, the first electrode plate EC31 of the third light-emitting capacitor is located on one side of the first electrode plate EC11 of the first light-emitting capacitor, which faces the display area; the gate electrode ET22 of the second light-emitting transistor is located on one side of the first electrode plate EC31 of the third light-emitting capacitor, which faces away from the display area; the gate electrode ET102 of the tenth light-emitting transistor is located on one side of the first electrode plate EC31 of the third light-emitting capacitor, which faces the display area; the gate electrode ET92 of the ninth light-emitting transistor is located on one side of the first electrode plate EC21 of the second light-emitting capacitor, which faces the display area;The gate electrode ET52 of the fifth light emission transistor is located on one side of the first electrode plate EC11 of the first light emission capacitor, which is facing away from the display area;and the gate electrode ET62 of the sixth light-emitting transistor is located on one side of the first electrode plate EC11 of the first light-emitting capacitor, which faces the display area. In the first direction D1, the gate electrode ET82 of the eighth light-emitting transistor of the light-emitting shift register in the current stage is located on one side of the first electrode plate EC31 of the third light-emitting capacitor, which faces the light-emitting shift register in the next stage. The first electrode plate EC11 of the first light-emitting capacitor and the first electrode plate EC31 of the third light-emitting capacitor of the light-emitting shift register in the current stage are located on one side of the first electrode plate EC21 of the second light-emitting capacitor, which faces the light-emitting shift register in the previous stage.

[0210] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET12 of the first light emission transistor, the gate electrode ET42 of the fourth light emission transistor, the gate electrode ET52 of the fifth light emission transistor, the gate electrode ET62 of the sixth light emission transistor and the gate electrode ET72 of the seventh light emission transistor can have a strip-shaped form that extends at least partially in the second direction D2.

[0211] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET22 of the second light emission transistor can have a rectangular shape, wherein an opening is provided on the gate electrode ET22 of the second light emission transistor, the shape of which can be rectangular and which can be located in the middle of the gate electrode ET22 of the second light emission transistor, so that the gate electrode ET22 of the second light emission transistor forms a ring-shaped structure.

[0212] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET32 of the third light emission transistor can have an inverted “T”-shaped form.

[0213] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET82 of the eighth light emission transistor can have a strip-shaped form that extends at least partially in the first direction D1 and can represent a kinked line.

[0214] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET92 of the ninth light-emitting transistor can have a shape comprising a first connecting section extending in the first direction D1 and several first branching sections extending in the second direction D2, wherein the first connecting section is connected to the first electrode plate of the second capacitor, and the first branching sections are located on one side of the first connecting section facing the display area. The gate electrode ET92 of the ninth light-emitting transistor can have a comb-like shape, with the first connecting section acting as the comb's spine and the first branching sections acting as the comb's teeth.

[0215] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode ET102 of the tenth light emission transistor can have a shape comprising several second branching sections extending in the second direction D2, wherein the several second branching sections and the first electrode plate EC31 of the third light emission capacitor can form a comb-like structure, with the first electrode plate of the third light emission capacitor acting as the comb's back and the several second branching sections acting as the comb's teeth.

[0216] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the first electrode plate EC11 of the first light emission capacitor can have a strip-shaped form which extends at least partially in the first direction D1 and is provided with a bulge on a side facing away from the display area.

[0217] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the first electrode plate EC21 of the second light emission capacitor can have a strip-shaped form extending in the second direction D2.

[0218] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the first electrode plate EC31 of the third light emission capacitor can have a strip-shaped form extending in the first direction D1.

[0219] In an exemplary embodiment, as in Fig. 16 to Fig. Figure 18 shows the gate electrode ET12 of the first light-emitting transistor spanning the channel region of the active layer of the first light-emitting transistor, the gate electrode ET22 of the second light-emitting transistor spanning the channel region of the active layer of the second light-emitting transistor, the gate electrode ET32 of the third light-emitting transistor spanning the channel region of the active layer of the third light-emitting transistor, the gate electrode ET42 of the fourth light-emitting transistor spanning the channel region of the active layer of the fourth light-emitting transistor, the two first branch sections ET55 of the gate electrode ET52 of the fifth light-emitting transistor spanning the channel region of the active layer of the fifth light-emitting transistor, and the gate electrode ET62 of the sixth light-emitting transistor spanning the channel region of the active layer of the first light-emitting transistor.the gate electrode ET72 of the seventh light-emitting transistor across the channel region of the active layer of the seventh light-emitting transistor, the gate electrode ET82 of the eighth light-emitting transistor across the channel region of the active layer of the eighth light-emitting transistor, the several first branch sections of the gate electrode ET92 of the ninth light-emitting transistor across the channel region of the active layer of the ninth light-emitting transistor, the gate electrode ET102 of the tenth light-emitting transistor across the channel region of the active layer of the tenth light-emitting transistor, that is, the direction of extension of the gate electrode of at least one light-emitting transistor and the direction of extension of the channel region of the active layer are perpendicular to each other.

[0220] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, since the gate electrode ET22 of the second light emission transistor has a ring-shaped structure, the second light emission transistor has a double-gate structure.

[0221] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode RT12 of the first discharge transistor and the gate electrode RT22 of the second discharge transistor can have a strip-shaped form extending in the first direction D1.

[0222] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode RT12 of the first discharge transistor spans the channel area of ​​the active layer of the first transistor and the gate electrode RT22 of the second discharge transistor spans the channel area of ​​the active layer of the second transistor, that is, the extension direction of the gate electrode of at least one discharge transistor and the extension direction of the active layer are perpendicular to each other.

[0223] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the gate electrode GT12 of the first sampling transistor and the gate electrode GT32 of the third sampling transistor form an interconnected, single-piece structure. The gate electrode GT42 of the fourth sampling transistor, the gate electrode GT62 of the sixth sampling transistor, and the first electrode plate GC31 of the first sampling capacitor form an interconnected, single-piece structure. The gate electrode GT52 of the fifth sampling transistor and the first electrode plate EC21 of the second sampling capacitor form an interconnected, single-piece structure. The gate electrode GT22 of the second sampling transistor, the gate electrode GT72 of the seventh sampling transistor, and the gate electrode GT82 of the eighth sampling transistor can be formed separately.

[0224] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, in the second direction D2, the first electrode plate GC11 of the first sampling capacitor is located on one side of the first electrode plate GC21 of the second sampling capacitor that is away from the display area, the gate electrode GT52 of the fifth sampling transistor is located on one side of the first electrode plate EC21 of the second sampling capacitor that is away from the display area, the gate electrode GT42 of the fourth sampling transistor is located on one side of the first electrode plate GC31 of the first sampling capacitor that is facing the display area, and the gate electrode GT62 of the sixth sampling transistor is located on one side of the first electrode plate GC31 of the first sampling capacitor that is away from the display area.

[0225] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the shape of the gate electrode GT12 of the first sampling transistor can comprise: a second connecting section and two third branching sections, wherein the third branching sections are located on one side of the second connecting section that is away from the display area, and the second connecting section is connected to the gate electrode GT32 of the third sampling transistor, wherein the lengths of the two branching sections are different.

[0226] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the shape of the gate electrode GT22 of the second sampling transistor can include: a gate body part extending in the second direction D2, and a gate interconnect part extending in the first direction D1.

[0227] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the shapes of the gate electrode GT32 of the third sampling transistor, the gate electrode GT42 of the fourth sampling transistor, the gate electrode GT62 of the sixth sampling transistor, the gate electrode GT72 of the seventh sampling transistor and the gate electrode GT82 of the eighth sampling transistor can be strip-shaped, extending at least partially in the second direction D2.

[0228] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the shape of the gate electrode GT52 of the fifth sampling transistor can include several fourth branching sections extending in the second direction D2, wherein the shape of the gate electrode GT52 of the fifth sampling transistor can be comb-shaped, with the first electrode plate GC21 of the second sampling capacitor serving as the comb's back and the several fourth branching sections serving as the comb's teeth.

[0229] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in 18, the shape of the first electrode plate GC11 of the first scanning capacitor can be strip-shaped, extending at least partially in the second direction D2.

[0230] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the shape of the first electrode plate ECG1 of the second scanning capacitor can be strip-shaped, extending in the first direction D1.

[0231] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the two third branch sections of the gate electrode GT12 of the first sampling transistor span the channel area of ​​the active layer of the first sampling transistor, the gate connection part of the gate electrode GT22 of the second sampling transistor spans the channel area of ​​the active layer of the second sampling transistor, the gate electrode GT32 of the third sampling transistor spans the channel area of ​​the active layer of the third sampling transistor, the gate electrode GT42 of the fourth sampling transistor spans the channel area of ​​the active layer of the fourth sampling transistor, the two first branch sections GT55 of the gate electrode GT52 of the fifth sampling transistor span the channel area of ​​the active layer of the fifth sampling transistor, and the gate electrode GT62 of the sixth sampling transistor spans the channel area of ​​the active layer of the first sampling transistor.The gate electrode GT72 of the seventh scanning transistor spans the channel area of ​​the active layer of the seventh scanning transistor, the gate electrode GT82 of the eighth scanning transistor spans the channel area of ​​the active layer of the eighth scanning transistor, that is, the direction of extension of the gate electrode of at least one scanning transistor is perpendicular to the direction of extension of the channel area of ​​the active layer.

[0232] In an exemplary embodiment, as in Fig. 16 to Fig. As shown in Figure 18, the two third branching sections of the gate electrode GT12 of the first sampling transistor span the channel area of ​​the active layer of the first sampling transistor, the first sampling transistor having a double-gate structure.

[0233] In an exemplary embodiment, as in Fig. 16 and Fig. As shown in Figure 17, the first signal connection line L1 and the second signal connection line L2 can extend at least partially in the second direction D2.

[0234] In an exemplary embodiment, as in Fig. 36 to Fig. As shown in Figure 39, the shape of the first electrode plate C1 of the capacitor can be rectangular, with the corners of the rectangle being chamfered, and the orthographic projection of the first electrode plate C1 of the capacitor onto the substrate overlaps at least partially with the orthographic projection of the active layer of the third transistor onto the substrate. In an exemplary embodiment, the first electrode plate C1 of the capacitor can simultaneously serve as the gate electrode M32 of the third transistor.

[0235] In an exemplary embodiment, as in Fig. 36 to Fig. As shown in Figure 39, the reset signal line can have a linear shape, the main part of which extends in the second direction D2, and the reset signal line connected to the subpixel in this row can be located on one side of the first electrode plate C1 of this subpixel, facing the subpixel in the previous row. The area where the reset signal line overlaps with the active layer of the first transistor serves as the gate electrode MT12 of the first transistor with a double-gate structure.

[0236] In an exemplary embodiment, as in Fig. 36 to Fig. As shown in Figure 39, the Gate sampling signal line can have a linear shape, the main part of which extends in the second direction D2, and the Gate sampling signal line connected to the subpixel in this row can be located on one side of the Reset signal line connected to this subpixel, which faces the first electrode plate C1, wherein the area where the Gate sampling signal line overlaps with the active layer of the second transistor of this subpixel serves as the gate electrode MT22 of the second transistor with a double-gate structure, and the area where the Gate sampling signal line overlaps with the active layer of the fourth transistor serves as the gate electrode MT42 of the fourth transistor.

[0237] In an exemplary embodiment, as in Fig. 36 to Fig. As shown in Figure 39, the sampling signal line Gate comprises a signal body part 21 and a signal connection part 22. One end of the signal connection part 22 is electrically connected to the signal body part 21. The signal body part 21 extends in the second direction D2 and the signal connection part 22 extends in the first direction D1.

[0238] In an exemplary embodiment, as in Fig. 36 and Fig. As shown in Figure 37, the signal connection part 22 is located on a side of the signal body part 21 that faces the first electrode plate of the capacitor.

[0239] In an exemplary embodiment, as in Fig. 38 and Fig. As shown in Figure 39, the signal connection part 22 is located on a side of the signal body part 21 that is away from the first electrode plate of the capacitor.

[0240] In an exemplary embodiment, the light emission signal line EM can have a linear shape, the main part of which extends in the second direction D2, wherein the light emission signal line EM can be located on one side of the first electrode plate C1 of the capacitor of this subpixel, which faces the subpixel in the next row, wherein the area in which the light emission signal line EM overlaps with the active layer of the fifth transistor of this subpixel serves as the gate electrode MT52 of the fifth transistor, and the area in which the light emission signal line EM overlaps with the active layer of the sixth transistor of this subpixel serves as the gate electrode MT62 of the sixth transistor.

[0241] In an exemplary embodiment, the reset signal line, the gate signal line, and the light emission signal line EM can be designed with either the same width or different widths; they can be straight lines or bent lines, which not only simplifies the layout of the pixel structure but can also reduce the parasitic capacitance between the signal lines, and the present disclosure does not impose any restrictions in this regard.

[0242] In an exemplary embodiment, after forming the pattern of the first electrically conductive layer, the first electrically conductive layer can be used as a shield to perform a conductive treatment on the semiconductor layer.The semiconductor layer in an area shielded by the first electrically conductive layer forms channel regions of the first light-emitting transistor through the tenth light-emitting transistor, the channel regions of the first light-emitting transistor through the second discharge transistor, and the channel regions of the first sampling transistor through the eighth sampling transistor. Meanwhile, the semiconductor layer in an area not shielded by the first electrically conductive layer is made conductive; that is, the first and second regions of the active layer of the first through tenth transistors, the first and second regions of the active layer of the first through second discharge transistors, and the first and second regions of the active layer of the first through eighth sampling transistors are all made conductive. In an exemplary embodiment, as shown in... Fig. 16 and Fig. As shown in Figure 17, the first region of the active layer of the fourth light-emitting transistor (also the second region of the active layer of the fifth light-emitting transistor) is reused as the first electrode of the fourth light-emitting transistor (also as the second electrode of the fifth light-emitting transistor), the second region of the active layer of the sixth sampling transistor (also the first region of the active layer of the seventh sampling transistor) is reused as the second electrode of the sixth sampling transistor (also as the first electrode of the seventh sampling transistor), the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor and the first region of the active layer of the sixth transistor) is reused as the second electrode of the second transistor (also as the second electrode of the third transistor and the first electrode of the sixth transistor).The first region of the active layer of the third transistor (also the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) is reused as the first electrode of the third transistor (also as the second electrode of the fourth transistor and second electrode of the fifth transistor).

[0243] (3) Forming a pattern of the second insulating layer, comprising: In an exemplary embodiment, forming a pattern of the third insulating layer may comprise: Depositing a second insulating film on the substrate on which the aforementioned patterns are formed, and patterning the second insulating film by means of a patterning process to form a second insulating layer covering the first electrically conductive layer, the second insulating layer being provided with through-holes as shown in Fig. 19 shown. Fig. Figure 19 shows a schematic diagram of the in Fig. 6A provided display substrate after forming the pattern of the second insulating layer.

[0244] In an exemplary embodiment, the through-holes comprise at least one through-hole V0 located at least within the electrostatic discharge circuit. The orthographic projection of the through-hole V0 onto the substrate lies within the area of ​​the orthographic projection of the active interconnect onto the substrate and exposes the surface of the active interconnect, wherein the through-hole V0 is configured such that the subsequently formed light emission output signal line is connected to the active interconnect through this through-hole.

[0245] In an exemplary embodiment, in Fig. 5A, Fig. 7B and Fig. 7C also forms a second insulating layer, however, no through holes are provided in the second insulating layer.

[0246] (4) Forming a pattern of the second electrically conductive layer, comprising: depositing a second electrically conductive film on the substrate on which the aforementioned patterns are formed, and patterning the second electrically conductive film by means of a patterning process to form a pattern of the second electrically conductive layer that is superimposed on the pattern of the second insulating layer, as in Fig. 20 to Fig. 23 as well Fig. 40 to Fig. 43 shown, whereby Fig. 20 a schematic diagram of the pattern of the second electrically conductive layer of Fig. 5A shows, Fig. 21 a schematic diagram of Fig. 5A after the formation of the pattern of the second electrically conductive layer shows, Fig. 22 a schematic diagram of the second electrically conductive layer of Fig. 6A shows, Fig. 23 a schematic diagram of Fig. 6A shows after the formation of the pattern of the second electrically conductive layer, Fig. 40 a schematic diagram of the pattern of the second electrically conductive layer of Fig. 7B shows, Fig. 41 a schematic diagram of Fig. Figure 7B shows the formation of the pattern of the second electrically conductive layer. Fig. 42 a schematic diagram of the pattern of the second electrically conductive layer of Fig. 7C shows, and Fig. 43 a schematic diagram of Fig. Figure 7C shows the formation of the pattern of the second electrically conductive layer. In an exemplary embodiment, the second electrically conductive layer can be referred to as the second gate metal layer (GATE2).

[0247] In an exemplary embodiment, as in Fig. 20 to Fig. 23 as well Fig. 40 to Fig. As shown in Figure 43, the pattern of the second electrically conductive layer can include at least: the second electrode plate EC12 of the first light emission capacitor to the second electrode plate EC32 of the third light emission capacitor in the light emission shift register, the first electrode plate GC12 of the first sampling capacitor and the second electrode plate GC22 of the second sampling capacitor in the sampling shift register, the second electrode plate C2 of the capacitor in the pixel circuit, the sampling output signal line GOL, the light emission output signal line EOL, the third signal link line L3, the first initial signal line INIT1 and the second initial signal line INIT2.

[0248] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the pattern of the second electrically conductive layer can still include a shielding electrode SL.

[0249] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the orthographic projection of the second electrode plate EC12 of the first light-emitting capacitor onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the first light-emitting capacitor onto the substrate. The orthographic projection of the second electrode plate EC22 of the second light-emitting capacitor onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the second light-emitting capacitor onto the substrate. The orthographic projection of the second electrode plate EC32 of the third light-emitting capacitor onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the third light-emitting capacitor onto the substrate.

[0250] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the sampling output signal line GOL and the second electrode plate GC22 of the second sampling capacitor are an interconnected one-piece structure and are located on one side of the second electrode plate GC22 of the second sampling capacitor that faces the display area.

[0251] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the orthographic projection of the second electrode plate GC12 of the first scanning capacitor onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the first scanning capacitor onto the substrate. The orthographic projection of the second electrode plate GC22 of the second scanning capacitor onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the second scanning capacitor onto the substrate.

[0252] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the sampling output signal line GOL extends at least partially in the second direction D2.

[0253] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the third signal connection line L3 has a strip-shaped form that extends in the second direction D2.

[0254] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the light emission output signal line can comprise: an output connector COL and at least one output line OL. Several output lines OL are arranged in the first direction D1. At least one output line OL is located on a side of the output connector COL facing the display area.

[0255] In an exemplary embodiment, as in Fig. 20 to Fig. As shown in Figure 23, the output connection part COL extends in the first direction D1, and the output line OL extends at least partially in the second direction D2.

[0256] In an exemplary embodiment, as in Fig. 20 and Fig. Shown in 21, the output line OL includes Fig. 5A: a starting body part OLA and a starting connecting part OLB, wherein the starting body part OLA and the starting connecting part OLB are a connected one-piece structure.

[0257] In an exemplary embodiment, as in Fig. 20 and Fig. As shown in Figure 21, the output body part OLA extends in the second direction D2, and the output connection part OLB extends in the first direction D1.

[0258] In an exemplary embodiment, as in Fig. 22 and Fig. As shown in 23, the orthographic projection of the output line OL overlaps in Fig. 6A onto the substrate at least partially with the orthographic projection of the active connecting part onto the substrate, and the output line is connected to the active connecting part through a through hole.

[0259] In an exemplary embodiment, as in Fig. 40 to Fig. As shown in Figure 43, the second electrode plates C2 of the capacitors of neighboring subpixels in the same row are electrically connected to each other.

[0260] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the second electrode plate C2 of the capacitor comprises: a capacitor body part 50, a first capacitor connection part 51, a second capacitor connection part 52, and a third capacitor connection part 53. In the second direction D2, the first capacitor connection part 51 and the second capacitor connection part 52 are each located on two sides of the capacitor body part 50, and in the first direction D1, the third capacitor connection part 53 is located on one side of the capacitor body part 50 that faces the first initial signal line.

[0261] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the outline of the capacitor body part 50 can be rectangular, with the corners of the rectangle being chamfered, and the orthographic projection of the capacitor body part 50 onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the capacitor onto the substrate. The capacitor body part 50 is provided with an opening K, the shape of which can be arbitrary and which can be located in the center of the capacitor body part 50, such that the capacitor body part 50 forms an annular structure. The opening K exposes the third insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate onto the substrate includes the orthographic projection of the opening K onto the substrate.In an exemplary embodiment, the opening K is configured to expose the first electrode plate of the capacitor, so that the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) is connected to the first electrode plate of the capacitor.

[0262] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the first capacitor connection part of this subpixel is electrically connected to the second capacitor connection part of an adjacent subpixel in the same row, and the second capacitor connection part of this subpixel is electrically connected to the first capacitor connection part of another adjacent subpixel in the same row.

[0263] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the orthographic projection of the third capacitor connection part onto the substrate overlaps at least partially with the orthographic projection of the capacitor of the second transistor onto the substrate.

[0264] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the first initial signal line INIT1 can be located on one side of the second electrode plate C2 of the capacitor of this subpixel, facing the subpixel in the previous row. The orthographic projection of the first initial signal line INIT1 onto the substrate lies between the orthographic projection of the reset signal line onto the substrate and the orthographic projection of the scan signal line onto the substrate.

[0265] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the first initial signal line INIT1 comprises: an initial signal body part 41, a first initial connection block 42, and a second initial connection block 43. The first initial connection block 42 and the second initial connection block 43 are each electrically connected to the initial signal body part 41. The first initial connection block 42 is located on a side of the initial signal body part 41 that is away from the second electrode plate C2 of the capacitor, and the second initial connection block 43 is located on a side of the initial signal body part 41 that faces the second electrode plate C2 of the capacitor. The initial signal body part 41 may have a linear shape extending in the second direction D2.The first initial connection block 42 and the second initial connection block 43 can correspond to shielding electrodes configured to effectively shield the effects of data voltage jumps on critical nodes in the pixel circuit, prevent the data voltage jumps from affecting the potential of critical nodes in the pixel driver circuit, and improve the display effect.

[0266] In an exemplary embodiment, as in Fig. 40 and Fig. As shown in Figure 41, the second initial signal line INIT2 can have a linear shape extending in the second direction D2, and the second initial signal line INIT2 associated with the subpixels in this row can be located on one side of the second electrode plate C2 of the capacitor of the subpixel in this row, facing the subpixels in the next row. The orthographic projection of the second initial signal line INIT2 associated with the subpixels in this row onto the substrate lies between the orthographic projection of the light emission signal line associated with the subpixels in this row onto the substrate and the orthographic projection of the reset signal line associated with the subpixels in the next row onto the substrate.

[0267] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the second electrode plate C2 of the capacitor comprises: a capacitor body part 50, a first capacitor connection part 51, and a second capacitor connection part 52. In the second direction D2, the first capacitor connection part 51 and the second capacitor connection part 52 are each located on two sides of the capacitor body part 50.

[0268] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the outline of the capacitor body part 50 can be rectangular, with the corners of the rectangle being chamfered, and the orthographic projection of the capacitor body part 50 onto the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the capacitor onto the substrate. The capacitor body part 50 is provided with an opening K, the shape of which can be arbitrary and which can be located in the center of the capacitor body part 50, such that the capacitor body part 50 forms an annular structure. The opening K exposes the third insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate onto the substrate includes the orthographic projection of the opening K onto the substrate.In an exemplary embodiment, the opening K is configured to expose the first electrode plate of the capacitor, so that the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) is connected to the first electrode plate of the capacitor.

[0269] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the first capacitor connection part of this subpixel is electrically connected to the second capacitor connection part of an adjacent subpixel in the same row, and the second capacitor connection part of this subpixel is electrically connected to the first capacitor connection part of another adjacent subpixel in the same row.

[0270] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the first initial signal line INIT1 can have a linear shape extending in the second direction D2, and the first initial signal line INIT1 can be located on one side of the second electrode plate C2 of the capacitor of this subpixel, facing the subpixel in the previous row. The orthographic projection of the first initial signal line INIT1 onto the substrate is located on one side of the orthographic projection of the reset signal line onto the substrate, opposite the orthographic projection of the scan signal line onto the substrate.

[0271] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the shielding electrode SL can have an "n"-shaped form. The shielding electrode SL is located between the first initial signal line INIT1 and the second electrode plate C2 of the capacitor. The orthographic projection of the shielding electrode SL onto the substrate overlaps at least partially with the orthographic projections of the active layer of the first transistor and the active layer of the second transistor onto the substrate, and is located between the orthographic projection of the reset signal line onto the substrate and the orthographic projection of the sampling signal line onto the substrate. The shielding electrode is configured to effectively shield the effects of data voltage jumps on critical nodes in the pixel circuit, preventing the data voltage jumps from affecting the potential of critical nodes in the pixel driver circuit and improving the display effect.

[0272] In an exemplary embodiment, as in Fig. 42 and Fig. As shown in Figure 43, the second initial signal line INIT2 can have a linear shape extending in the second direction D2, and the second initial signal line INIT2 associated with the subpixels in this row can be located on one side of the second electrode plate C2 of the capacitor, facing the subpixels in the next row. The orthographic projection of the second initial signal line INIT2 associated with the subpixels in this row onto the substrate lies between the orthographic projection of the sampling signal line associated with the subpixels in this row onto the substrate and the orthographic projection of the first initial signal line associated with the subpixels in the next row onto the substrate.

[0273] (5) Forming a pattern of the third insulating layer, comprising: depositing a third insulating film onto the substrate on which the aforementioned patterns are formed, and patterning the third insulating film by means of a patterning process to form a pattern of the third insulating layer covering the previous structures, the third insulating layer being provided with multiple through-hole patterns as shown in Fig. 24, Fig. 25, Fig. 44 and Fig. 45 shown, whereby Fig. 24 a schematic diagram of Fig. 5A after forming the pattern of the third insulating layer shows, Fig. 25 a schematic diagram of Fig. 6A shows after the formation of the pattern of the third insulating layer, Fig. 44 a schematic diagram of Fig. 7B shows after the formation of the pattern of the third insulating layer, and Fig. 45 a schematic diagram of Fig. 7C shows after the formation of the pattern of the third insulating layer.

[0274] In an exemplary embodiment, as in Fig. As shown in 24, the multiple through-hole patterns in Fig. 5A shall include at least: a first through hole V1 to a fifty-seventh through hole V57.

[0275] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the first through-hole V1 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the first through-hole V1 to expose the surface of the first region of the active layer of the first light-emitting transistor, and the first through-hole V1 is configured to connect the first electrode of the subsequently formed first light-emitting transistor to the first region of the active layer of the first light-emitting transistor through this through-hole.

[0276] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the second through-hole V2 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the second through-hole V2 to expose the surface of the second region of the active layer of the first light-emitting transistor, and the second through-hole V2 is configured to connect the second electrode of the subsequently formed first light-emitting transistor (also the second electrode of the fourth light-emitting transistor) through this through-hole to the second region of the active layer of the first light-emitting transistor.

[0277] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the third through-hole V3 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the second light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the third through-hole V3 to expose the surface of the first region of the active layer of the second light-emitting transistor, and the third through-hole V3 is configured to connect the first electrode of the subsequently formed second light-emitting transistor to the first region of the active layer of the second light-emitting transistor through this through-hole.

[0278] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fourth through-hole V4 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the second light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the fourth through-hole V4 are etched to expose the surface of the second region of the active layer of the second light-emitting transistor, and the fourth through-hole V4 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (also the second electrode of the third light-emitting transistor) through this through-hole to the second region of the active layer of the second light-emitting transistor.

[0279] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifth through-hole V5 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the third light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the fifth through-hole V5 to expose the surface of the first region of the active layer of the third light-emitting transistor, and the fifth through-hole V5 is configured to connect the first electrode of the subsequently formed third light-emitting transistor (also the first electrode of the tenth light-emitting transistor) through this through-hole to the first region of the active layer of the third light-emitting transistor.

[0280] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the sixth through-hole V6 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the third light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the sixth through-hole V6 are etched to expose the surface of the second region of the active layer of the third light-emitting transistor, and the sixth through-hole V6 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (also the second electrode of the third light-emitting transistor) through this through-hole to the second region of the active layer of the third light-emitting transistor.

[0281] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the seventh through-hole V7 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the fourth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the seventh through-hole V7 are etched to expose the surface of the second region of the active layer of the fourth light-emitting transistor, and the seventh through-hole V7 is configured to connect the second electrode of the subsequently formed first light-emitting transistor (also the second electrode of the fourth light-emitting transistor) through this through-hole to the second region of the active layer of the fourth light-emitting transistor.

[0282] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the eighth through-hole V8 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fifth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the eighth through-hole V8 are etched to expose the surface of the first region of the active layer of the fifth light-emitting transistor, and the eighth through-hole V8 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor to the first region of the active layer of the fifth light-emitting transistor through this through-hole.

[0283] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the ninth through-hole V9 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the sixth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the ninth through-hole V9 are etched to expose the surface of the first region of the active layer of the sixth light-emitting transistor, and the ninth through-hole V9 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the first region of the active layer of the sixth light-emitting transistor through this through-hole.

[0284] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the tenth through-hole V10 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the sixth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the tenth through-hole V10 are etched to expose the surface of the second region of the active layer of the sixth light-emitting transistor, and the tenth through-hole V10 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (also the first electrode of the seventh light-emitting transistor) through this through-hole to the second region of the active layer of the sixth light-emitting transistor.

[0285] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the eleventh through-hole V11 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the seventh light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the eleventh through-hole V11 are etched to expose the surface of the first region of the active layer of the seventh light-emitting transistor, and the eleventh through-hole V11 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (also the first electrode of the seventh light-emitting transistor) through this through-hole to the first region of the active layer of the seventh light-emitting transistor.

[0286] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twelfth through-hole V12 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the seventh light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the twelfth through-hole V12 are etched to expose the surface of the second region of the active layer of the seventh light-emitting transistor, and the twelfth through-hole V12 is configured to allow the second electrode of the subsequently formed seventh light-emitting transistor (also the second electrode of the eighth light-emitting transistor) to be connected through this through-hole to the second region of the active layer of the seventh light-emitting transistor.

[0287] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirteenth through-hole V13 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the eighth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirteenth through-hole V13 to expose the surface of the first region of the active layer of the eighth light-emitting transistor, and the thirteenth through-hole V13 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (also the first electrode of the ninth light-emitting transistor) through this through-hole to the first region of the active layer of the eighth light-emitting transistor.

[0288] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fourteenth through-hole V14 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the eighth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the fourteenth through-hole V14 are etched to expose the surface of the second region of the active layer of the eighth light-emitting transistor, and the fourteenth through-hole V14 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (also the second electrode of the eighth light-emitting transistor) through this through-hole to the second region of the active layer of the eighth light-emitting transistor.

[0289] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifteenth through-hole V15 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the ninth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the fifteenth through-hole V15 to expose the surface of the first region of the active layer of the ninth light-emitting transistor, and the fifteenth through-hole V15 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (also the first electrode of the ninth light-emitting transistor) through this through-hole to the first region of the active layer of the ninth light-emitting transistor.

[0290] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the sixteenth through-hole V16 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the ninth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the sixteenth through-hole V16 are etched to expose the surface of the second region of the active layer of the ninth light-emitting transistor, and the sixteenth through-hole V16 is configured to allow the second electrode of the subsequently formed ninth light-emitting transistor to be connected through this through-hole to the second region of the active layer of the ninth light-emitting transistor.

[0291] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the seventeenth through-hole V17 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the tenth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the seventeenth through-hole V17 are etched to expose the surface of the first region of the active layer of the tenth light-emitting transistor, and the seventeenth through-hole V17 is configured to connect the first electrode of the subsequently formed tenth light-emitting transistor to the first region of the active layer of the tenth light-emitting transistor through this through-hole.

[0292] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the eighteenth through-hole V18 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the tenth light-emitting transistor onto the substrate, wherein the first insulating layer and the second insulating layer in the eighteenth through-hole V18 are etched to expose the surface of the second region of the active layer of the tenth light-emitting transistor, and the eighteenth through-hole V18 is configured to allow the second electrode of the subsequently formed tenth light-emitting transistor to be connected through this through-hole to the second region of the active layer of the tenth light-emitting transistor.

[0293] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the nineteenth through-hole V19 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor) onto the substrate, wherein the second insulating layer in the nineteenth through-hole V19 is etched to expose the surface of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor), and the nineteenth through-hole V19 is configured to allow the first electrode of the subsequently formed second light-emitting transistor and one of the two light-emitting clock signal lines (first or second light-emitting clock signal line) to be connected through this through-hole to the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor).

[0294] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twentieth through-hole V20 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fourth light-emitting transistor onto the substrate, the second insulating layer being etched in the twentieth through-hole V20 to expose the surface of the gate electrode of the fourth light-emitting transistor, and the twentieth through-hole V20 being configured to allow the other of the two light-emitting clock signal lines (first or second light-emitting clock signal line) to be connected through this through-hole to the gate electrode of the fourth light-emitting transistor.

[0295] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-first through-hole V21 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor) onto the substrate, wherein the second insulating layer in the twenty-first through-hole V21 is etched to expose the surface of the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor), and the twenty-first through-hole V21 is configured tothat the second electrode of the second light-emitting transistor formed later (also the second electrode of the third light-emitting transistor) is connected through this through-hole to the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor).

[0296] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-second through-hole V22 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the seventh light-emitting transistor onto the substrate, wherein the second insulating layer in the twenty-second through-hole V22 is etched to expose the surface of the gate electrode of the seventh light-emitting transistor, and the twenty-second through-hole V22 is configured to allow the other of the two light-emitting clock signal lines (first or second light-emitting clock signal line) to be connected through this through-hole to the gate electrode of the seventh light-emitting transistor.

[0297] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-third through-hole V23 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor) onto the substrate, wherein the second insulating layer is etched in the twenty-third through-hole V23 to expose the surface of the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor), and the twenty-third through-hole V23 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (also the second electrode of the eighth light-emitting transistor) through this through-hole to the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor).

[0298] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-fourth through-hole V24 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the first light-emitting capacitor onto the substrate, exposing the surface of the second electrode plate of the first light-emitting capacitor, and the twenty-fourth through-hole V24 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (also the first electrode of the seventh light-emitting transistor) to the second electrode plate of the first light-emitting capacitor through this through-hole.

[0299] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-fifth through-hole V25 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the second light-emitting capacitor onto the substrate, exposing the surface of the second electrode plate of the second light-emitting capacitor, and the twenty-fifth through-hole V25 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (also the first electrode of the ninth light-emitting transistor) to the second electrode plate of the second light-emitting capacitor through this through-hole.

[0300] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-sixth through-hole V26 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the third light-emitting capacitor onto the substrate, exposing the surface of the second electrode plate of the third light-emitting capacitor, and the twenty-sixth through-hole V26 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the second electrode plate of the third light-emitting capacitor through this through-hole.

[0301] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-seventh through-hole V27 onto the substrate is located within the area of ​​the orthographic projection of the output body part of the output conduit onto the substrate, exposing the surface of the output body part of the output conduit, and the twenty-seventh through-hole V27 is configured to allow the second connecting conduit formed subsequently to be connected to the output body part of the output conduit through this through-hole.

[0302] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-eighth through-hole V28 onto the substrate is located within the area of ​​the orthographic projection of the output connection part of the output line onto the substrate, exposing the surface of the output connection part of the output line, and the twenty-eighth through-hole V28 is configured to connect the second electrode of the subsequently formed first discharge transistor (also the second electrode of the second discharge transistor) to the output connection part of the output line through this through-hole.

[0303] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the twenty-ninth through-hole V29 onto the substrate is located within the area of ​​the orthographic projection of the output interconnection line onto the substrate, exposing the surface of the output interconnection line, and the twenty-ninth through-hole V29 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output interconnection line through this through-hole.

[0304] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirtieth through-hole V30 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first discharge transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirtieth through-hole V30 to expose the surface of the first region of the active layer of the first discharge transistor, and the thirtieth through-hole V30 is configured to allow the first electrode of the subsequently formed first discharge transistor (also the second light emission power supply line) to be connected through this through-hole to the first region of the active layer of the first discharge transistor.

[0305] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-first through-hole V31 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first discharge transistor (also the second region of the active layer of the second discharge transistor) onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-first through-hole V31 to expose the surface of the second region of the active layer of the first discharge transistor (also the second region of the active layer of the second discharge transistor), and the thirty-first through-hole V31 is configured tothat the second electrode of the subsequently formed first discharge transistor (also the second electrode of the second discharge transistor) is connected through this through-hole to the second region of the active layer of the first discharge transistor (also the second region of the active layer of the second discharge transistor).

[0306] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-second through-hole V32 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the second discharge transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-second through-hole V32 to expose the surface of the first region of the active layer of the second discharge transistor, and the thirty-second through-hole V32 is configured to connect the first electrode of the subsequently formed second discharge transistor to the first region of the active layer of the second discharge transistor via this through-hole.

[0307] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-third through-hole V33 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first discharge transistor onto the substrate, wherein the second insulating layer is etched in the thirty-third through-hole V33 to expose the surface of the gate electrode of the first discharge transistor, and the thirty-third through-hole V33 is configured to allow the second electrode of the subsequently formed first discharge transistor (also the second electrode of the second discharge transistor) to be connected to the gate electrode of the first discharge transistor through this through-hole.

[0308] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-fourth through-hole V34 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first discharge transistor onto the substrate, the second insulating layer being etched in the thirty-fourth through-hole V34 to expose the surface of the gate electrode of the first discharge transistor, and the thirty-fourth through-hole V34 being configured to connect the first electrode of the subsequently formed second discharge transistor (also the first sampling current supply line) to the gate electrode of the second discharge transistor through this through-hole.

[0309] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-fifth through-hole V35 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-fifth through-hole V35 to expose the surface of the first region of the active layer of the first scanning transistor, and the thirty-fifth through-hole V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first region of the active layer of the first scanning transistor via this through-hole.

[0310] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-sixth through-hole V36 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first scanning transistor (also of the second region of the active layer of the seventh scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the thirty-sixth through-hole V36 are etched to expose the surface of the second region of the active layer of the first scanning transistor (also of the second region of the active layer of the seventh scanning transistor), and the thirty-sixth through-hole V36 is configured tothat the second electrode of the subsequently formed first scanning transistor (also the second electrode of the seventh scanning transistor) is connected through this through-hole to the second region of the active layer of the first scanning transistor (also the second region of the active layer of the seventh scanning transistor).

[0311] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-seventh through-hole V37 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the second scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-seventh through-hole V37 to expose the surface of the first region of the active layer of the second scanning transistor, and the thirty-seventh through-hole V37 is configured to connect the first electrode of the subsequently formed second scanning transistor to the first region of the active layer of the second scanning transistor via this through-hole.

[0312] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-eighth through-hole V38 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the second scanning transistor (also of the second region of the active layer of the third scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the thirty-eighth through-hole V38 are etched to expose the surface of the second region of the active layer of the second scanning transistor (also of the second region of the active layer of the third scanning transistor), and the thirty-eighth through-hole V38 is configured tothat the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) is connected through this through-hole to the second region of the active layer of the second scanning transistor (also the second region of the active layer of the third scanning transistor).

[0313] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the thirty-ninth through-hole V39 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the third scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-ninth through-hole V39 to expose the surface of the first region of the active layer of the third scanning transistor, and the thirty-ninth through-hole V39 is configured to connect the first electrode of the subsequently formed third scanning transistor (also the second scanning power supply line) to the first region of the active layer of the third scanning transistor via this through-hole.

[0314] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fortieth through-hole V40 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fourth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the fortieth through-hole V40 to expose the surface of the first region of the active layer of the fourth scanning transistor, and the fortieth through-hole V40 is configured to connect the first electrode of the subsequently formed fourth scanning transistor to the first region of the active layer of the fourth scanning transistor via this through-hole.

[0315] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-first through-hole V41 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the forty-first through-hole V41 are etched to expose the surface of the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor), and the forty-first through-hole V41 is configured tothat the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) is connected through this through-hole to the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor).

[0316] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-second through-hole V42 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fifth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-second through-hole V42 to expose the surface of the first region of the active layer of the fifth scanning transistor, and the forty-second through-hole V42 is configured to connect the first electrode of the subsequently formed fifth scanning transistor to the first region of the active layer of the fifth scanning transistor via this through-hole.

[0317] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-third through-hole V43 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the sixth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-third through-hole V43 to expose the surface of the first region of the active layer of the sixth scanning transistor, and the forty-third through-hole V43 is configured to connect the first electrode of the subsequently formed sixth scanning transistor to the first region of the active layer of the sixth scanning transistor via this through-hole.

[0318] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-fourth through-hole V44 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the eighth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-fourth through-hole V44 to expose the surface of the first region of the active layer of the eighth scanning transistor, and the forty-fourth through-hole V44 is configured to connect the first electrode of the subsequently formed eighth scanning transistor to the first region of the active layer of the eighth scanning transistor via this through-hole.

[0319] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-fifth through-hole V45 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the eighth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-fifth through-hole V45 to expose the surface of the second region of the active layer of the eighth scanning transistor, and the forty-fifth through-hole V45 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the second region of the active layer of the eighth scanning transistor via this through-hole.

[0320] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-sixth through-hole V46 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor) onto the substrate, wherein the second insulating layer in the forty-sixth through-hole V46 is etched to expose the surface of the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor), and the forty-sixth through-hole V46 is configured to connect the first electrode of the subsequently formed second sampling transistor and one of the first sampling clock signal lines and the second sampling clock signal line to the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor) via this through-hole.

[0321] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-seventh through-hole V47 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the second sampling transistor onto the substrate, the second insulating layer being etched in the forty-seventh through-hole V47 to expose the surface of the gate electrode of the fourth sampling transistor, and the forty-seventh through-hole V47 being configured to connect the second electrode of the subsequently formed first sampling transistor (also the second electrode of the seventh sampling transistor) and the first electrode of the eighth sampling transistor to the gate electrode of the second sampling transistor via this through-hole.

[0322] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-eighth through-hole V48 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor) onto the substrate, wherein the second insulating layer in the forty-eighth through-hole V48 is etched to expose the surface of the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor), and the forty-eighth through-hole V48 is configured tothat the second electrode of the second sampling transistor formed later (also the second electrode of the third sampling transistor) is connected via this through-hole to the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor).

[0323] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the forty-ninth through-hole V49 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor) onto the substrate, wherein the second insulating layer in the forty-ninth through-hole V49 is etched to expose the surface of the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor), and the forty-ninth through-hole V49 is configured to connect the second electrode of the subsequently formed eighth sampling transistor to the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor) via this through-hole.

[0324] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fiftieth through-hole V50 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the seventh scanning transistor onto the substrate, wherein the second insulating layer in the fiftieth through-hole V50 is etched to expose the surface of the gate electrode of the seventh scanning transistor, and the fiftieth through-hole V50 is configured to connect the first electrode of the subsequently formed fifth light emission transistor, as well as the other electrode of the first scanning clock signal line and the second scanning clock signal line, to the gate electrode of the seventh scanning transistor via this through-hole.

[0325] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-first through-hole V51 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the eighth scanning transistor onto the substrate, wherein the second insulating layer is etched in the fifty-first through-hole V51 to expose the surface of the gate electrode of the eighth scanning transistor, and the fifty-first through-hole V51 is configured to allow the subsequently formed second scanning power supply line to be connected to the gate electrode of the eighth scanning transistor via this through-hole.

[0326] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-second through-hole V52 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the first scanning capacitor onto the substrate, exposing the surface of the second electrode plate of the first scanning capacitor, and the fifty-second through-hole V52 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second electrode plate of the first scanning capacitor via this through-hole.

[0327] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-third through-hole V53 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the second scanning capacitor onto the substrate, exposing the surface of the second electrode plate of the second scanning capacitor, and the fifty-third through-hole V53 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) to the second electrode plate of the second scanning capacitor via this through-hole.

[0328] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-fourth through-hole V54 onto the substrate is located within the area of ​​the orthographic projection of the third signal link line onto the substrate, exposing the surface of the third signal link line, and the fifty-fourth through-hole V54 is configured to connect the second electrode of the subsequently formed first sampling transistor of the current sampling shift register and the second electrode of the fourth sampling transistor of the previous sampling shift register (also the second electrode of the fifth sampling transistor) to the third signal link line via this through-hole.

[0329] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-fifth through-hole V55 onto the substrate is located within the area of ​​the orthographic projection of the scanning output signal line onto the substrate, exposing the surface of the scanning output signal line, and the fifty-fifth through-hole V55 is configured to connect the subsequently formed first interconnect line to the scanning output signal line via this through-hole.

[0330] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-sixth through-hole V56 onto the substrate is located within the area of ​​the orthographic projection of the first signal interconnection line onto the substrate, wherein the second insulating layer is etched in the fifty-sixth through-hole V56 to expose the surface of the first signal interconnection line, and the fifty-sixth through-hole V56 is configured to allow the subsequently formed first initial power supply line to be connected to the first signal interconnection line via this through-hole.

[0331] In an exemplary embodiment, as in Fig. As shown in Figure 24, the orthographic projection of the fifty-seventh through-hole V57 onto the substrate is located within the area of ​​the orthographic projection of the second signal link line onto the substrate, wherein the second insulating layer is etched in the fifty-seventh through-hole V57 to expose the surface of the second signal link line, and the fifty-seventh through-hole V57 is configured to allow the subsequently formed second initial power supply line to be connected to the second signal link line via this through-hole.

[0332] In an exemplary embodiment, as in Fig. As shown in 25, the multiple through-hole patterns of the Fig. The display substrate provided in 6A shall include at least: a first through hole V1 to a fifty-sixth through hole V56.

[0333] In an exemplary embodiment, the first through hole V1 to the twenty-sixth through hole V26 are in Fig. 6A identical to the first through hole V1 to the twenty-sixth through hole V26 in the Fig. 5A provided display substrate, which will not be discussed further here.

[0334] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the twenty-seventh through-hole V27 onto the substrate is located within the area of ​​the orthographic projection of the output line onto the substrate, exposing the surface of the output line, and the twenty-seventh through-hole V27 is configured to allow the second connecting line formed later to be connected to the output line through this through-hole.

[0335] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the twenty-eighth through-hole V28 onto the substrate is located within the area of ​​the orthographic projection of the output interconnection line onto the substrate, exposing the surface of the output interconnection line, and the twenty-eighth through-hole V28 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output interconnection line through this through-hole.

[0336] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the twenty-ninth through-hole V29 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first discharge transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the twenty-ninth through-hole V29 to expose the surface of the first region of the active layer of the first discharge transistor, and the twenty-ninth through-hole V29 is configured to connect the first electrode of the subsequently formed first discharge transistor (also the second light emission power supply line) through this through-hole to the first region of the active layer of the first discharge transistor.

[0337] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirtieth through-hole V30 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first discharge transistor (also of the second region of the active layer of the second discharge transistor) onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirtieth through-hole V30 to expose the surface of the second region of the active layer of the first discharge transistor (also of the second region of the active layer of the second discharge transistor), and the thirtieth through-hole V30 is configured tothat the second electrode of the subsequently formed first discharge transistor (also the second region of the active layer of the second discharge transistor) is connected through this through-hole to the second region of the active layer of the first discharge transistor (also the second region of the active layer of the second discharge transistor).

[0338] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-first through-hole V31 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the second discharge transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-first through-hole V31 to expose the surface of the first region of the active layer of the second discharge transistor, and the thirty-first through-hole V31 is configured to connect the first electrode of the subsequently formed second discharge transistor to the first region of the active layer of the second discharge transistor through this through-hole.

[0339] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-second through-hole V32 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first discharge transistor onto the substrate, wherein the second insulating layer is etched in the thirty-second through-hole V32 to expose the surface of the gate electrode of the first discharge transistor, and the thirty-second through-hole V32 is configured such that the second electrode of the subsequently formed first discharge transistor (also the second area of ​​the active layer of the second discharge transistor) is connected through this through-hole to the gate electrode of the first discharge transistor.

[0340] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-third through-hole V33 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first discharge transistor onto the substrate, the second insulating layer being etched in the thirty-third through-hole V33 to expose the surface of the gate electrode of the first discharge transistor, and the thirty-third through-hole V33 being configured to connect the first electrode of the subsequently formed second discharge transistor (also the first sampling current supply line) to the gate electrode of the second discharge transistor through this through-hole.

[0341] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-fourth through-hole V34 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-fourth through-hole V34 to expose the surface of the first region of the active layer of the first scanning transistor, and the thirty-fifth through-hole V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first region of the active layer of the first scanning transistor through this through-hole.

[0342] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-fifth through-hole V35 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first scanning transistor (also of the second region of the active layer of the seventh scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the thirty-fifth through-hole V35 are etched to expose the surface of the second region of the active layer of the first scanning transistor (also of the second region of the active layer of the seventh scanning transistor), and the thirty-fifth through-hole V35 is configured tothat the second electrode of the subsequently formed first scanning transistor (also the second electrode of the seventh scanning transistor) is connected through this through-hole to the second region of the active layer of the first scanning transistor (also the second region of the active layer of the seventh scanning transistor).

[0343] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-sixth through-hole V36 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the second scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-sixth through-hole V36 to expose the surface of the first region of the active layer of the second scanning transistor, and the thirty-sixth through-hole V36 is configured to connect the first electrode of the subsequently formed second scanning transistor to the first region of the active layer of the second scanning transistor through this through-hole.

[0344] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-seventh through-hole V37 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the second scanning transistor (also of the second region of the active layer of the third scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the thirty-seventh through-hole V37 are etched to expose the surface of the second region of the active layer of the second scanning transistor (also of the second region of the active layer of the third scanning transistor), and the thirty-seventh through-hole V37 is configured tothat the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) is connected through this through-hole to the second region of the active layer of the second scanning transistor (also the second region of the active layer of the third scanning transistor).

[0345] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-eighth through-hole V38 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the third scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-eighth through-hole V38 to expose the surface of the first region of the active layer of the third scanning transistor, and the thirty-eighth through-hole V38 is configured to connect the first electrode of the subsequently formed third scanning transistor (also the second scanning power supply line) through this through-hole with the first region of the active layer of the third scanning transistor.

[0346] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the thirty-ninth through-hole V39 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fourth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the thirty-ninth through-hole V39 to expose the surface of the first region of the active layer of the fourth scanning transistor, and the thirty-ninth through-hole V39 is configured to connect the first electrode of the subsequently formed fourth scanning transistor through this through-hole with the first region of the active layer of the fourth scanning transistor.

[0347] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fortieth through-hole V40 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor) onto the substrate, wherein the first insulating layer and the second insulating layer in the fortieth through-hole V40 are etched to expose the surface of the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor), and the fortieth through-hole V40 is configured tothat the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) is connected through this through-hole to the second region of the active layer of the fourth scanning transistor (the second region of the active layer of the fifth scanning transistor).

[0348] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-first through-hole V41 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fifth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-first through-hole V41 to expose the surface of the first region of the active layer of the fifth scanning transistor, and the forty-first through-hole V41 is configured to connect the first electrode of the subsequently formed fifth scanning transistor through this through-hole with the first region of the active layer of the fifth scanning transistor.

[0349] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-second through-hole V42 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the sixth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-second through-hole V42 to expose the surface of the first region of the active layer of the sixth scanning transistor, and the forty-second through-hole V42 is configured to connect the first electrode of the subsequently formed sixth scanning transistor through this through-hole with the first region of the active layer of the sixth scanning transistor.

[0350] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-third through-hole V43 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the eighth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-third through-hole V43 to expose the surface of the first region of the active layer of the eighth scanning transistor, and the forty-third through-hole V43 is configured to connect the first electrode of the subsequently formed eighth scanning transistor through this through-hole with the first region of the active layer of the eighth scanning transistor.

[0351] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-fourth through-hole V44 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the eighth scanning transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the forty-fourth through-hole V44 to expose the surface of the second region of the active layer of the eighth scanning transistor, and the forty-fourth through-hole V44 is configured to connect the second electrode of the subsequently formed eighth scanning transistor through this through-hole with the second region of the active layer of the eighth scanning transistor.

[0352] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-fifth through-hole V45 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor) onto the substrate, wherein the second insulating layer in the forty-fifth through-hole V45 is etched to expose the surface of the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor), and the forty-fifth through-hole V45 is configured to connect the first electrode of the subsequently formed second sampling transistor and one of the first sampling clock signal lines and the second sampling clock signal line through this through-hole with the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor).

[0353] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-sixth through-hole V46 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the second scanning transistor onto the substrate, wherein the second insulating layer is etched in the forty-sixth through-hole V46 to expose the surface of the gate electrode of the fourth scanning transistor, and the forty-sixth through-hole V46 is configured to connect the second electrode of the subsequently formed first scanning transistor (also the second electrode of the seventh scanning transistor) and the first electrode of the eighth scanning transistor through this through-hole with the gate electrode of the second scanning transistor.

[0354] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-seventh through-hole V47 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor) onto the substrate, wherein the second insulating layer in the forty-seventh through-hole V47 is etched to expose the surface of the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor), and the forty-seventh through-hole V47 is configured tothat the second electrode of the second sampling transistor formed later (also the second electrode of the third sampling transistor) is connected through this through-hole to the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor).

[0355] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-eighth through-hole V48 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor) onto the substrate, wherein the second insulating layer in the forty-eighth through-hole V48 is etched to expose the surface of the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor), and the forty-eighth through-hole V48 is configured to connect the second electrode of the subsequently formed eighth sampling transistor through this through-hole with the gate electrode of the fifth sampling transistor (also the first electrode plate of the second sampling capacitor).

[0356] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the forty-ninth through-hole V49 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the seventh scanning transistor onto the substrate, wherein the second insulating layer in the forty-ninth through-hole V49 is etched to expose the surface of the gate electrode of the seventh scanning transistor, and the forty-ninth through-hole V49 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor, as well as the other electrode of the first scanning clock signal line and the second scanning clock signal line, through this through-hole with the gate electrode of the seventh scanning transistor.

[0357] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fiftieth through-hole V50 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the eighth scanning transistor onto the substrate, wherein the second insulating layer is etched in the fiftieth through-hole V50 to expose the surface of the gate electrode of the eighth scanning transistor, and the fiftieth through-hole V50 is configured to allow the subsequently formed second scanning power supply line to be connected through this through-hole to the gate electrode of the eighth scanning transistor.

[0358] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-first through-hole V51 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the first scanning capacitor onto the substrate, exposing the surface of the second electrode plate of the first scanning capacitor, and the fifty-first through-hole V51 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second electrode plate of the first scanning capacitor through this through-hole.

[0359] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-second through-hole V52 onto the substrate is located within the area of ​​the orthographic projection of the second electrode plate of the second scanning capacitor onto the substrate, exposing the surface of the second electrode plate of the second scanning capacitor, and the fifty-second through-hole V52 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) to the second electrode plate of the second scanning capacitor through this through-hole.

[0360] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-third through-hole V53 onto the substrate is located within the area of ​​the orthographic projection of the third signal link line onto the substrate, exposing the surface of the third signal link line, and the fifty-third through-hole V53 is configured to connect the second electrode of the subsequently formed first sampling transistor of the current sampling shift register and the second electrode of the fourth sampling transistor of the previous sampling shift register (also the second electrode of the fifth sampling transistor) to the third signal link line through this through-hole.

[0361] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-fourth through-hole V54 onto the substrate is located within the area of ​​the orthographic projection of the scanning output signal line onto the substrate, exposing the surface of the scanning output signal line, and the fifty-fourth through-hole V54 is configured to allow the subsequently formed first interconnect line to be connected to the scanning output signal line through this through-hole.

[0362] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-fifth through-hole V55 onto the substrate is located within the area of ​​the orthographic projection of the first signal link line onto the substrate, wherein the second insulating layer is etched in the fifty-fifth through-hole V55 to expose the surface of the first signal link line, and the fifty-fifth through-hole V55 is configured to allow the subsequently formed first initial power supply line to be connected to the first signal link line through this through-hole.

[0363] In an exemplary embodiment, as in Fig. As shown in Figure 25, the orthographic projection of the fifty-sixth through-hole V56 onto the substrate is located within the area of ​​the orthographic projection of the second signal link line onto the substrate, wherein the second insulating layer is etched in the fifty-sixth through-hole V56 to expose the surface of the second signal link line, and the fifty-sixth through-hole V56 is configured to allow the subsequently formed second initial power supply line to be connected to the second signal link line through this through-hole.

[0364] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in 45, the multiple through-hole patterns in Fig. 7B and Fig. 7C shall include at least: a fifty-eighth through hole V58 to a sixty-seventh through hole V67.

[0365] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the fifty-eighth through-hole V58 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the first transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the fifty-eighth through-hole V58 to expose the surface of the first region of the active layer of the first transistor, and the fifty-eighth through-hole V58 is configured to allow the first electrode of the subsequently formed first transistor to be connected through this through-hole to the first region of the active layer of the first transistor.

[0366] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the fifty-ninth through-hole V59 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the fifty-ninth through-hole V59 to expose the surface of the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor), and the fifty-ninth through-hole V59 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) through this through-hole to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor).

[0367] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the sixtieth through-hole V60 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the fourth transistor onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the sixtieth through-hole V60 to expose the surface of the first region of the active layer of the fourth transistor, and the sixtieth through-hole V60 is configured to connect the first electrode of the subsequently formed fourth transistor through this through-hole with the first region of the active layer of the fourth transistor.

[0368] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the sixty-first through-hole V61 onto the substrate lies within the area of ​​the orthographic projection of the first region of the active layer of the fifth transistor onto the substrate, with the first insulating layer and the second insulating layer being etched in the sixty-first through-hole V61 to expose the surface of the second region of the active layer of the fifth transistor. The sixty-first through-hole V61 in Fig. 44 is configured so that the first electrode of the subsequently formed fifth transistor is connected through this through-hole to the first region of the active layer of the fifth transistor. The sixty-first through-hole V61 in Fig. 45 is configured so that the subsequently formed first sub-power supply line is connected through this through-hole to the first area of ​​the active layer of the fifth transistor.

[0369] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the sixty-second through-hole V62 onto the substrate is located within the area of ​​the orthographic projection of the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor) onto the substrate, wherein the first insulating layer and the second insulating layer are etched in the sixty-second through-hole V62 to expose the surface of the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor), and the sixty-second through-hole V62 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) through this through-hole with the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor).

[0370] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the sixty-third through-hole V63 onto the substrate is located within the area of ​​the orthographic projection of the first region of the active layer of the seventh transistor onto the substrate, with the first insulating layer being etched to the second insulating layer in the sixty-third through-hole V63 to expose the surface of the first region of the active layer of the seventh transistor. The sixty-third through-hole V63 in Fig. 44 is configured so that the first electrode of the subsequently formed seventh transistor is connected through this through-hole to the first region of the active layer of the seventh transistor. The sixty-third through-hole V63 in Fig. 45 is configured so that the first electrode of the later formed seventh transistor, or the fourth signal link line, is connected through this through-hole to the first area of ​​the active layer of the seventh transistor.

[0371] In an exemplary embodiment, as in Fig. As shown in Figure 44, the orthographic projection of the sixty-fourth through-hole V64 onto the substrate is located within the area of ​​the orthographic projection of the gate electrode of the third transistor (also the first electrode plate of the capacitor) onto the substrate, wherein the second insulating layer is etched in the sixty-fourth through-hole V64 to expose the surface of the gate electrode of the third transistor (also the first electrode plate of the capacitor), and the sixty-fourth through-hole V64 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) through this through-hole with the gate electrode of the third transistor (also the first electrode plate of the capacitor).

[0372] In an exemplary embodiment, as in Fig. As shown in Figure 44, the orthographic projection of the sixty-fifth through-hole V65 onto the substrate is located within the area of ​​the orthographic projection of the first initial signal line onto the substrate, exposing the first initial signal line, and the sixty-fifth through-hole V65 is configured to connect the first electrode of the first transistor through this through-hole with the first initial signal line.

[0373] In an exemplary embodiment, as in Fig. 44 and Fig. As shown in Figure 45, the orthographic projection of the sixty-sixth through-hole V66 onto the substrate lies within the area of ​​the orthographic projection of the second electrode plate of the capacitor onto the substrate, exposing the surface of the second electrode plate of the capacitor. The sixty-sixth through-hole V66 in Fig. 44 is configured so that the first electrode of the subsequently formed fifth transistor is connected through this through-hole to the second electrode plate of the capacitor. The sixty-sixth through-hole V66 in Fig. 45 is configured so that the subsequently formed first sub-power supply line is connected through this through-hole to the second electrode plate of the capacitor.

[0374] In an exemplary embodiment, as in Fig. As shown in Figure 44, the orthographic projection of the sixty-seventh through-hole V67 onto the substrate is located within the area of ​​the orthographic projection of the second initial signal line onto the substrate, exposing the surface of the second initial signal line, and the sixty-seventh through-hole V67 is configured such that the first electrode of the subsequently formed seventh transistor is connected through this through-hole to the second initial signal line.

[0375] (6) Forming a pattern of the third electrically conductive layer, comprising: depositing a third electrically conductive film on the substrate on which the aforementioned patterns are formed, and patterning the third electrically conductive film by means of a patterning process to form a pattern of the third electrically conductive layer, as in Fig. 26 to Fig. 28 as well Fig. 46 to Fig. 49 shown, whereby Fig. 26 a schematic diagram of the pattern of the third electrically conductive layer of Fig. 5A and Fig. 6A shows, Fig. 27 a schematic diagram of Fig. 5A after the formation of the pattern of the third electrically conductive layer shows, Fig. 28 a schematic diagram of Fig. 6A shows after the formation of the pattern of the third electrically conductive layer, Fig. 46 a schematic diagram of the pattern of the third electrically conductive layer of Fig. 7B shows, Fig. 47 a schematic diagram of Fig. Figure 7B shows the formation of the pattern of the third electrically conductive layer. Fig. 48 a schematic diagram of the pattern of the third electrically conductive layer of Fig. 7C shows, and Fig. 49 a schematic diagram of Fig. Figure 7C shows the formation of the pattern of the third electrically conductive layer. In an exemplary embodiment, the third electrically conductive layer can be designated as the first source-drain metal layer (SD1).

[0376] In an exemplary embodiment, as in Fig. 26 to Fig. 28 as well Fig. 46 to Fig. As shown in Figure 49, the pattern of the third electrically conductive layer can include at least: the light emission initial signal line ESTV, the first light emission clock signal line ECK1, the second light emission clock signal line ECK2, the first light emission power supply line EVGH, the second light emission power supply line EVGL, the sampling initial signal line GSTV, the first sub-clock signal line GCK1A of the first sampling clock signal line, the third sub-clock signal line GCK2A of the second sampling clock signal line, the first sampling power supply line GVGH, the second sampling power supply line GVGL, the first sub-initial power supply line INITL1A of the first initial power supply line, the first sub-initial power supply line INITL2A of the second initial power supply line, the first connecting line CL1 to the fourth connecting line CL4, the first and second electrodes several light-emitting transistors,the first and second electrodes of several discharge transistors as well as the first and second electrodes of several sampling transistors, the first electrode MT13 and the second electrode MT14 of the first transistor, the first electrode MT23 of the second transistor, the first electrode MT43 of the fourth transistor, the first electrode MT53 of the fifth transistor, the second electrode MT64 of the sixth transistor as well as the first electrode MT73 and the second electrode MT74 of the seventh transistor.

[0377] In an exemplary embodiment, as in Fig. 46 and Fig. As shown in Figure 47, the pattern of the third electrically conductive layer still includes at least the data link line DL.

[0378] In an exemplary embodiment, as in Fig. 48 and Fig. As shown in Figure 49, the pattern of the third electrically conductive layer further comprises at least the first sub-power supply line VDDA and the electrode connection line CL.

[0379] In an exemplary embodiment, as in Fig. As shown in Figure 26, the first light emission clock signal line ECK1 can be located on one side of the light emission start signal line ESTV facing the display area, the second light emission clock signal line ECK2 can be located on one side of the first light emission clock signal line ECK1 facing the display area, the first light emission power supply line EVGH can be located on one side of the second light emission clock signal line ECK2 facing the display area, the second light emission power supply line EVGL is located on one side of the first light emission power supply line EVGH facing the display area, and the first scanning power supply line GVGH is located on one side of the second light emission power supply line EVGL facing the display area.The first sub-clock signal line GCK1A of the first sample clock signal line is located on one side of the first sample power supply line GVGH facing the display area; the third sub-clock signal line GCK2A of the second sample clock signal line is located on one side of the first sample clock signal line GCK1 facing the display area; the sample start signal line GSTV is located on one side of the second sample clock signal line GCK2 facing the display area; the second sample power supply line GVGL is located on one side of the sample start signal line GSTV facing the display area.

[0380] In an exemplary embodiment, any one of the following lines extends at least partially in the first direction D1 and is linear: the light emission start signal line ESTV, the first light emission clock signal line ECK1, the second light emission clock signal line ECK2, the first light emission power supply line EVGH, the second light emission power supply line EVGL, the sampling start signal line GSTV, the first sub-clock signal line GCK1A of the first sampling clock signal line, the third sub-clock signal line GCK2A of the second sampling clock signal line, the first sampling power supply line GVGH, the second sampling power supply line GVGL, the first sub-start power supply line INITL1A of the first start power supply line, and the first sub-start power supply line INITL2A of the second start power supply line.

[0381] In an exemplary embodiment, as in Fig. As shown in Figure 26, the first electrode ET13 and the second electrode ET14 of the first light-emitting transistor, up to the first electrode ET103 and the second electrode ET104 of the tenth light-emitting transistor, can be located between the first light-emitting power supply line EVGH and the second light-emitting power supply line EVGL. The first electrode RT11 and the second electrode RT14 of the first discharge transistor, up to the first electrode RT21 and the second electrode RT24 of the second discharge transistor, are located between the second light-emitting power supply line EVGL and the first sampling power supply line GVGH.The first electrode GT13 and the second electrode GT14 of the first sampling transistor up to the first electrode GT33 and the second electrode of the third sampling transistor, as well as the first electrode GT63 of the sixth sampling transistor and the second electrode GT74 of the seventh sampling transistor, can be located between the sampling start signal line GSTV and the second sampling power supply line GVGL, and the first electrode GT43 and the second electrode GT44 of the fourth sampling transistor up to the first electrode GT53 and the second electrode GT54 of the fifth sampling transistor, as well as the first electrode GT83 and second electrode GT84 of the eighth sampling transistor, can be located between the second sampling power supply line GVGL and the first start power supply line INITL1.

[0382] In an exemplary embodiment, the orthographic projection of the second electrode plate of the second scanning capacitor onto the substrate overlaps at least partially with the orthographic projections of the second scanning power supply line, the first scanning clock signal line, the second scanning clock signal line, the scanning start signal line and the first scanning power supply line onto the substrate.

[0383] In an exemplary embodiment, as in Fig. As shown in Figure 26, the first initial power supply line INITL1 and the second initial power supply line INITL2 are located on one side of the second scanning power supply line GVGL facing the display area, and the first initial power supply line INITL1 is located on one side of the second initial power supply line INITL2 facing the display area.

[0384] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode ET13 of the first light-emitting transistor can have a strip-shaped form extending in the first direction D1. The first electrode ET13 of the first light-emitting transistor is connected to the first region of the active layer of the first light-emitting transistor through the first through-hole.

[0385] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET14 of the first light-emitting transistor and the second electrode ET44 of the fourth light-emitting transistor form an interconnected, one-piece structure and can have a strip-like shape extending in the first direction D1. The second electrode ET14 of the first light-emitting transistor (also the second electrode ET44 of the fourth light-emitting transistor) is connected to the second region of the active layer of the first light-emitting transistor via the second through-hole and to the second region of the active layer of the fourth light-emitting transistor via the seventh through-hole.

[0386] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode ET23 of the second light emission transistor can have a strip-shaped form extending in the first direction D1, wherein the first electrode ET23 of the second light emission transistor is connected through the third through-hole to the first region of the active layer of the second light emission transistor and is connected through the nineteenth through-hole to the gate electrode of the first light emission transistor (also the gate electrode of the third light emission transistor).

[0387] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET24 of the second light-emitting transistor and the second electrode ET34 of the third light-emitting transistor form an interconnected, single-piece structure and extend at least partially in the first direction D and may be bent. The second electrode ET24 of the second light-emitting transistor (also the second electrode ET34 of the third light-emitting transistor) is connected through the fourth through-hole to the second region of the active layer of the second light-emitting transistor, through the sixth through-hole to the second region of the active layer of the third light-emitting transistor, and through the twenty-first through-hole to the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor).

[0388] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode ET33 of the third light emission transistor, the first electrode ET103 of the tenth light emission transistor and the second light emission power supply line EVGL are an interconnected one-piece structure, and the first electrode ET33 of the third light emission transistor can have a strip-shaped form extending in the second direction D2, and the first electrode ET103 of the tenth light emission transistor can have the form of an “n” whose opening faces the second light emission power supply line EVGL.The first electrode ET33 of the third light emission transistor (also the first electrode ET103 of the tenth light emission transistor) is connected through the fifth through-hole to the first area of ​​the active layer of the third light emission transistor and through the seventeenth through-hole to the first area of ​​the active layer of the tenth light emission transistor.

[0389] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode ET53 of the fifth light-emitting transistor and the first light-emitting power supply line EVGH form an interconnected, single-piece structure. The shape of the first electrode ET53 of the fifth light-emitting transistor can be block-shaped. The first electrode ET53 of the fifth light-emitting transistor is connected to the first region of the active layer of the fifth light-emitting transistor via the eighth through-hole.

[0390] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the shape of the first electrode ET63 of the sixth light-emitting transistor can be block-shaped. The first electrode ET63 of the sixth light-emitting transistor is connected to the first region of the active layer of the sixth light-emitting transistor via the ninth through-hole and to the second electrode plate of the third light-emitting capacitor via the twenty-sixth through-hole.

[0391] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET64 of the sixth light-emitting transistor and the first electrode ET73 of the seventh light-emitting transistor form an interconnected, single-piece structure. The second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) extends at least partially in the first direction D1. The second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) is connected through the tenth through-hole to the second region of the active layer of the sixth light-emitting transistor, through the eleventh through-hole to the first region of the active layer of the seventh light-emitting transistor, and through the twenty-fourth through-hole to the second electrode plate of the first light-emitting capacitor.

[0392] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET74 of the seventh light-emitting transistor and the second electrode ET84 of the eighth light-emitting transistor are a connected, single-piece structure. The second electrode ET74 of the seventh light-emitting transistor (also the second electrode ET84 of the eighth light-emitting transistor) can have the shape of a horizontally inverted "7". The second electrode ET74 of the seventh light emission transistor (also the second electrode ET84 of the eighth light emission transistor) is connected through the twelfth through-hole to the second area of ​​the active layer of the seventh light emission transistor, through the fourteenth through-hole to the second area of ​​the active layer of the eighth light emission transistor and through the twenty-third through-hole to the gate electrode of the ninth light emission transistor (also the first electrode plate of the second light emission capacitor).

[0393] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode ET83 of the eighth light-emitting transistor, the first electrode ET93 of the ninth light-emitting transistor, and the first light-emitting power supply line EVGH form an interconnected, single-piece structure. The first electrode ET83 of the eighth light-emitting transistor may have a block-like shape, and the first electrode ET93 of the ninth light-emitting transistor may have a comb-like shape. The first electrode ET83 of the eighth light-emitting transistor (and also the first electrode ET93 of the ninth light-emitting transistor) is connected through the thirteenth through-hole to the first active region of the eighth light-emitting transistor, through the fifteenth through-hole to the first active region of the ninth light-emitting transistor, and through the twenty-fifth through-hole to the second electrode plate of the second light-emitting capacitor.

[0394] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET94 of the ninth light-emitting transistor can have a comb-like shape, with the comb teeth of the second electrode ET94 of the ninth light-emitting transistor being arranged alternately with the comb teeth of the first electrode ET93 of the ninth light-emitting transistor. The second electrode ET94 of the ninth light-emitting transistor is connected to the second region of the active layer of the ninth light-emitting transistor through the sixteenth through-hole. As shown in Fig. Figure 27 shows the second electrode ET94 of the ninth light-emitting transistor in Fig. 5A is connected to the output connection line through the twenty-ninth through-hole. As in Fig. Figure 28 shows the second electrode ET94 of the ninth light-emitting transistor in Fig. 6A is connected to the output connection line through the twenty-eighth through-hole.

[0395] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET104 of the tenth light-emitting transistor can have the shape of an “n”, the opening of which faces away from the second light-emitting power supply line EVGL. The second electrode ET104 of the tenth light-emitting transistor is connected to the second region of the active layer of the tenth light-emitting transistor through the eighteenth through-hole. As shown in Fig. Figure 27 shows the second electrode ET104 of the tenth light-emitting transistor in Fig. 5A is connected to the output connection line through the twenty-ninth through-hole. As in Fig. Figure 28 shows the second electrode ET104 of the tenth light-emitting transistor in Fig. 6A is connected to the output connection line through the twenty-eighth through-hole.

[0396] in an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, one of the first light emission clock signal lines ECK1 and the second light emission clock signal line ECK2 is connected through the nineteenth through hole to the gate electrode of the first light emission transistor (also the gate electrode of the third light emission transistor).

[0397] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the other of the first light emission clock signal line ECK1 and the second light emission clock signal line ECK2 is connected through the twentieth through hole to the gate electrode of the fourth light emission transistor and through the twenty-second through hole to the gate electrode of the seventh light emission transistor.

[0398] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in 28, the second connecting line CL2 can have a block-shaped form. As in Fig. Shown in 27, the second connecting line is in Fig. 5A is connected through the twenty-seventh through-hole to the output body part of the output line.

[0399] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the region where the second light emission power supply line EVGL overlaps with the first region of the active layer of the first discharge transistor can be reused as the first electrode of the first discharge transistor. As shown in Fig. Figure 27 shows the first electrode of the first discharge transistor in Fig. 5A is connected through the thirtieth through-hole to the first region of the active layer of the first discharge transistor, and in Fig. 6A is the first electrode of the first discharge transistor connected through the twenty-ninth through-hole to the first area of ​​the active layer of the first discharge transistor.

[0400] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET14 of the first discharge transistor and the second electrode ET24 of the second discharge transistor are an interconnected, one-piece structure and can have the shape of a horizontally inverted “L”. As shown in Fig. As shown in Figure 27, the orthographic projection of the second electrode ET14 of the first discharge transistor (and also the second electrode of the second discharge transistor) onto the substrate overlaps at least partially with the orthographic projection of the output connection part onto the substrate. The orthographic projection of the second electrode ET14 of the first discharge transistor (and also the second electrode of the second discharge transistor) in Fig. 5A onto the substrate does not overlap with the orthographic projection of the output line onto the substrate.

[0401] In an exemplary embodiment, as in Fig. Figure 27 shows the second electrode ET14 of the first discharge transistor (also the second electrode of the second discharge transistor) in Fig. 5A is connected through the twenty-eighth through-hole to the output connection part of the output line, through the thirty-first through-hole to the second active layer of the first discharge transistor (also the second active layer of the second discharge transistor), and through the thirty-third through-hole to the gate electrode of the first discharge transistor. As in Fig. Figure 28 shows the second electrode ET14 of the first discharge transistor (also the second electrode of the second discharge transistor) in Fig. 6A is connected through the thirtieth through-hole to the second area of ​​the active layer of the first discharge transistor (also the second area of ​​the active layer of the second discharge transistor) and through the thirty-second through-hole to the gate electrode of the first discharge transistor.

[0402] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode ET21 of the second discharge transistor and the first sampling current supply line GVGH are an interconnected, one-piece structure and can have the shape of a horizontally inverted “L”. As shown in Fig. Figure 27 shows the second electrode ET21 of the second discharge transistor in Fig. 5A is connected through the thirty-second through-hole to the first region of the active layer of the second discharge transistor and through the thirty-fourth through-hole to the gate electrode of the second discharge transistor. As in Fig. Figure 28 shows the second electrode ET21 of the second discharge transistor in Fig. 6A is connected through the thirty-first through-hole to the first area of ​​the active layer of the second discharge transistor and through the thirty-third through-hole to the gate electrode of the second discharge transistor.

[0403] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT13 of the first scanning transistor can have a strip-shaped form extending in the second direction D2. As shown in Fig. Figure 27 shows the first electrode GT13 of the first sampling transistor in Fig. 5A is connected through the thirty-fifth through-hole to the first active layer of the first sampling transistor and through the fifty-fourth through-hole to the third signal connection line. As in Fig. Figure 28 shows the first electrode GT13 of the first sampling transistor in Fig. 6A is connected through the thirty-fourth through-hole to the first area of ​​the active layer of the first sampling transistor and through the fifty-third through-hole to the third signal connection line.

[0404] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode GT14 of the first scanning transistor and the second electrode GT74 of the seventh scanning transistor are an interconnected, one-piece structure and can have a strip-like shape extending in the second direction D2. As shown in Fig. Figure 27 shows the second electrode GT14 of the first sampling transistor (also the second electrode GT74 of the seventh sampling transistor) in Fig. 5A is connected through the thirty-sixth through-hole to the second active layer of the first sampling transistor (also the second active layer of the seventh sampling transistor) and through the forty-seventh through-hole to the gate electrode of the second sampling transistor. As in Fig. Figure 28 shows the second electrode GT14 of the first sampling transistor (also the second electrode GT74 of the seventh sampling transistor) in Fig. 6A is connected through the thirty-fifth through-hole to the second area of ​​the active layer of the first sampling transistor (also the second area of ​​the active layer of the seventh sampling transistor) and through the forty-sixth through-hole to the gate electrode of the second sampling transistor.

[0405] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT23 of the second scanning transistor can have a strip-shaped form extending in the first direction D1. As shown in Fig. As shown in Figure 27, the first electrode GT23 of the second scanning transistor is located in the Fig. The 5A provided display substrate is connected through the thirty-seventh through-hole to the first active layer of the second sampling transistor and through the forty-sixth through-hole to the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor). As shown in Fig. Figure 28 shows the first electrode GT23 of the second scanning transistor in Fig. 6A is connected through the thirty-sixth through-hole to the first area of ​​the active layer of the second sampling transistor and through the forty-fifth through-hole to the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor).

[0406] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode GT24 of the second scanning transistor and the second electrode GT34 of the third scanning transistor are an interconnected, one-piece structure and can have a strip-like shape extending in the second direction D2. As shown in Fig. Figure 27 shows the second electrode GT24 of the second scanning transistor (also the second electrode GT34 of the third scanning transistor) in the Fig. The indicator substrate provided by 5A is connected through the thirty-eighth through-hole to the second active layer of the second sampling transistor (also the second active layer of the third sampling transistor) and through the forty-eighth through-hole to the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor). As shown in Fig. Figure 28 shows the second electrode GT24 of the second sampling transistor (also the second electrode GT34 of the third sampling transistor) in Fig. 6A is connected through the thirty-seventh through-hole to the second area of ​​the active layer of the second sampling transistor (also the second area of ​​the active layer of the third sampling transistor) and through the forty-seventh through-hole to the gate electrode of the fourth sampling transistor (also the gate electrode of the sixth sampling transistor and the first electrode plate of the first sampling capacitor).

[0407] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the area where the second sampling current supply line GVGL overlaps with the first area of ​​the active layer of the third sampling transistor is reused as the first electrode GT33 of the third sampling transistor. As shown in Fig. Figure 27 shows the first electrode GT33 of the third scanning transistor in Fig. 5A is connected through the thirty-ninth through-hole to the first area of ​​the active layer of the third scanning transistor.

[0408] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT43 of the fourth scanning transistor can have a strip-shaped form extending in the second direction D2. As shown in Fig. As shown in Figure 27, the first electrode GT43 of the fourth scanning transistor is located in the Fig. The 5A provided display substrate is connected through the fortieth through-hole to the first active layer of the fourth sampling transistor and through the fifty-second through-hole to the second electrode plate of the first sampling capacitor. As in Fig. Figure 28 shows the first electrode GT23 of the second scanning transistor in Fig. 6A is connected through the thirty-ninth through-hole to the first area of ​​the active layer of the fourth sampling transistor and through the fifty-first through-hole to the second electrode plate of the first sampling capacitor.

[0409] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode GT44 of the fourth scanning transistor and the second electrode GT54 of the fifth scanning transistor are an interconnected, one-piece structure and can have the shape of an “m”, the opening of which faces the second scanning current supply line GVGH. As shown in Fig. Figure 27 shows the second electrode GT44 of the fourth scanning transistor (also the second electrode GT54 of the fifth scanning transistor) in Fig. 5A is connected through the forty-first through-hole to the second active layer of the fourth sampling transistor (the second active layer of the fifth sampling transistor) and through the fifty-third through-hole to the second electrode plate of the second sampling capacitor. As in Fig. Figure 28 shows the second electrode GT44 of the fourth scanning transistor (also the second electrode GT54 of the fifth scanning transistor) in Fig. 6A is connected through the fortieth through-hole to the second area of ​​the active layer of the fourth sampling transistor (the second area of ​​the active layer of the fifth sampling transistor) and through the fifty-second through-hole to the second electrode plate of the second sampling capacitor.

[0410] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT53 of the fifth scanning transistor can have an "F"-shaped form. Fig. Figure 27 shows the first electrode GT53 of the fifth scanning transistor in Fig. 5A is connected through the forty-second through-hole to the first region of the active layer of the fifth sampling transistor and through the fiftieth through-hole to the gate electrode of the seventh sampling transistor. As in Fig. Figure 28 shows the first electrode GT53 of the fifth scanning transistor in Fig. 6A is connected through the forty-first through-hole to the first area of ​​the active layer of the fifth sampling transistor and through the forty-ninth through-hole to the gate electrode of the seventh sampling transistor.

[0411] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT63 of the sixth scanning transistor can have a strip-shaped form extending in the second direction D2. As shown in Fig. Figure 27 shows the first electrode GT63 of the sixth scanning transistor in Fig. 5A is connected through the forty-third through-hole to the first active layer of the sixth sampling transistor and through the fifty-second through-hole to the second electrode plate of the second sampling capacitor. As in Fig. Figure 28 shows the first electrode GT63 of the sixth scanning transistor in Fig. 6A is connected through the forty-second through-hole to the first area of ​​the active layer of the sixth sampling transistor and through the fifty-first through-hole to the second electrode plate of the second sampling capacitor.

[0412] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the first electrode GT83 of the eighth scanning transistor can have a block-shaped form. Fig. Figure 27 shows the first electrode GT83 of the eighth scanning transistor in Fig. 5A is connected through the forty-fourth through-hole to the first active layer of the eighth sampling transistor and through the forty-ninth through-hole to the gate electrode of the fifth sampling transistor (also the second electrode plate of the second sampling capacitor). As in Fig. Figure 28 shows the first electrode GT63 of the sixth scanning transistor in Fig. 6A is connected through the forty-third through-hole to the first area of ​​the active layer of the eighth sampling transistor and through the forty-eighth through-hole to the gate electrode of the fifth sampling transistor (also the second electrode plate of the second sampling capacitor).

[0413] In an exemplary embodiment, as in Fig. 26 to Fig. As shown in Figure 28, the second electrode GT84 of the eighth scanning transistor can have a block-shaped form. Fig. Figure 27 shows the second electrode GT84 of the eighth sampling transistor in Fig. 5A is connected through the forty-fifth through-hole to the second active layer of the eighth sampling transistor and through the forty-seventh through-hole to the gate electrode of the second sampling transistor. As in Fig. Figure 28 shows the second electrode GT84 of the eighth sampling transistor in Fig. 6A is connected through the forty-fourth through-hole to the second area of ​​the active layer of the eighth sampling transistor and through the forty-sixth through-hole to the gate electrode of the second sampling transistor.

[0414] In an exemplary embodiment, as in Fig. Figure 27 shows one of the first sub-clock signal lines GCK1A of the first sampling clock signal line and the third sub-clock signal line GCK2A of the second sampling clock signal line in Fig. 5A is connected through the forty-sixth through-hole to the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor). As in Fig. Figure 28 shows one of the first sub-clock signal lines GCK1A of the first sampling clock signal line and the third sub-clock signal line GCK2A of the second sampling clock signal line in Fig. 6A is connected through the forty-fifth through-hole to the gate electrode of the first sampling transistor (also the gate electrode of the third sampling transistor).

[0415] In an exemplary embodiment, as in Fig. As shown in Figure 27, the other of the first sub-clock signal line GCK1A is the first sampling clock signal line and the third sub-clock signal line GCK2A is the second sampling clock signal line in Fig. 5A is connected through the fiftieth through-hole to the gate electrode of the seventh scanning transistor. As in Fig. As shown in Figure 28, the other of the first sub-clock signal line GCK1A is the first sampling clock signal line and the third sub-clock signal line GCK2A is the second sampling clock signal line in Fig. 6A is connected through the forty-ninth through-hole to the gate electrode of the seventh scanning transistor.

[0416] In an exemplary embodiment, as in Fig. As shown in 27, the second sampling power supply line GVGH is in Fig. 5A is connected through the fifty-first through-hole to the gate electrode of the eighth sampling transistor. As in Fig. As shown in 28, the second sampling power supply line GVGH is in Fig. 6A is connected through the fiftieth through-hole to the gate electrode of the eighth sampling transistor.

[0417] In an exemplary embodiment, as in Fig. As shown in 27, the first connecting line CL1 is in Fig. 5A is connected through the fifty-fifth through-hole to the sampling output signal line. As shown in Fig. 28 shows the first connecting line CL1 in Fig. 6A is connected to the sampling output signal line through the fifty-fourth through-hole.

[0418] In an exemplary embodiment, as in Fig. Figure 27 shows the first sub-initial power supply line INITL1A of the first initial power supply line and the fourth connecting line CL4 in Fig. 5A is connected through the fifty-sixth through-hole to the first signal connection line. As in Fig. Figure 28 shows the first sub-initial power supply line INITL1A of the first initial power supply line and the fourth connecting line CL4 in Fig. 6A is connected to the first signal connection line through the fifty-fifth through-hole.

[0419] In an exemplary embodiment, as in Fig. Figure 27 shows the first sub-initial power supply line INITL2A, the second initial power supply line, and the third connecting line CL3. Fig. 5A is connected to the second signal connection line through the fifty-seventh through-hole. As in Fig. Figure 28 shows the first sub-initial power supply line INITL2A, the second initial power supply line, and the third connecting line CL3 in Fig. 6A is connected to the second signal connection line through the fifty-sixth through-hole.

[0420] In an exemplary embodiment, as in Fig. 46 and Fig. As shown in Figure 47, the first electrode MT13 of the first transistor has a strip-shaped form that extends in the second direction D2. As in Fig. 48 and Fig. As shown in Figure 49, the first electrode MT13 of the first transistor has a strip-shaped form extending in the first direction D1. As in Fig. 46 to Fig. As shown in Figure 49, the first electrode MT13 of the first transistor is electrically connected to the first area of ​​the active layer of the first transistor through the fifty-eighth through hole and electrically connected to the first initial signal line through the sixty-fifth through hole.

[0421] In an exemplary embodiment, as in Fig. 46 to Fig. As shown in Figure 49, the second electrode MT14 of the first transistor and the first electrode MT23 of the second transistor form a single structure and have a strip-like shape extending in the first direction D1. The second electrode MT14 of the first transistor (also the first electrode MT23 of the second transistor) is electrically connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) via the fifty-ninth through-hole and to the gate electrode of the third transistor (also the first electrode plate of the capacitor) via the sixty-fourth through-hole.

[0422] In an exemplary embodiment, as in Fig. 46 to Fig. As shown in Figure 49, the first electrode MT43 of the fourth transistor has a block-like shape. The first electrode MT43 of the fourth transistor is electrically connected to the first region of the active layer of the fourth transistor via the sixtieth through-hole.

[0423] In an exemplary embodiment, as in Fig. 46 and Fig. As shown in Figure 47, the first electrode M53 of the fifth transistor extends at least partially in the first direction D1. The first electrode M53 of the fifth transistor is electrically connected to the first region of the active layer of the fifth transistor via the sixty-first through-hole and to the second electrode plate of the capacitor via the sixty-sixth through-hol...

Claims

[1] Display substrate comprising: a substrate and a driver structure layer arranged on the substrate, wherein the substrate comprises a display area and a non-display area, wherein the driver structure layer comprises: a plurality of pixel circuits located in the display area, and a gate driver circuit and an electrostatic discharge circuit located in the non-display area, wherein the gate driver circuit comprises a plurality of driver circuits, wherein the plurality of driver circuits and the electrostatic discharge circuit are arranged in a direction close to the display area; wherein the electrostatic discharge circuit is arranged between two adjacent driver circuits and is electrically connected to at least one signal line from any one of the two adjacent driver circuits. [2] Display substrate according to claim 1, wherein the electrostatic discharge circuit comprises at least: a first discharge transistor and a second discharge transistor; wherein a gate electrode and a second electrode of the first discharge transistor are connected to a first signal terminal, and a first electrode of the first discharge transistor is connected to a second signal terminal; wherein a gate electrode and a first electrode of the second discharge transistor are connected to a third signal terminal, and a second electrode of the second discharge transistor is connected to the first signal terminal. [3] Display substrate according to claim 2, wherein the plurality of driver circuits comprises: a light emission driver circuit and a sampling driver circuit, wherein the sampling driver circuit is located on a side of the light emission driver circuit that is close to the display area; wherein the driver structure layer further comprises: a light emission start signal line, a first light emission clock signal line, a second light emission clock signal line, a first light emission power supply line, a second light emission power supply line, a sampling start signal line, a first sampling clock signal line, a second sampling clock signal line, a first sampling power supply line and a second sampling power supply line, which are located in the non-display area;wherein any one of the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the sampling initial signal line, the first sampling clock signal line, the second sampling clock signal line, the first sampling power supply line and the second sampling power supply line extends in a first direction; wherein the light emission driver circuit is electrically connected to the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line and the second light emission power supply line; wherein the sampling driver circuit is electrically connected to the sampling initial signal line, the second sampling clock signal line, the first sampling clock signal line, the first sampling power supply line and the second sampling power supply line; wherein the light emission start signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the first scanning power supply line, the first scanning clock signal line, the second scanning clock signal line, the scanning start signal line and the second scanning power supply line are arranged sequentially in a direction close to the display area. [4] Display substrate according to claim 3, wherein an orthographic projection of the electrostatic discharge circuit onto the substrate partially overlaps with the first scanning power supply line and the second light emission power supply line, and at least part of the electrostatic discharge circuit is located between the second light emission power supply line and the first scanning power supply line. [5] Display substrate according to claim 4, wherein the driver structure layer further comprises: a light emission output signal line and a sampling output signal line located in the non-display area, and a light emission signal line and a sampling signal line located at least partially in the display area; wherein any one of the sampling output signal line, the light emission signal line and the sampling signal line extends at least partially in a second direction, the first direction and the second direction intersecting; wherein the pixel circuit is connected to the light emission signal line and the sampling signal line, respectively; wherein the light emission driver circuit comprises: a plurality of cascaded light emission shift registers, and the sampling driver circuit comprises: a plurality of cascaded sampling shift registers; wherein the light emission output signal line is electrically connected to the light emission shift register and to at least one light emission signal line; wherein the sampling output signal line is electrically connected to the sampling shift register and to the sampling signal line. [6] Display substrate according to claim 5, wherein the first signal terminal of the electrostatic discharge circuit is electrically connected to the light emission output signal line, the second signal terminal of the electrostatic discharge circuit is electrically connected to the second light emission power supply line, and the third signal terminal of the electrostatic discharge circuit is electrically connected to the first scanning power supply line. [7] Display substrate according to any one of claims 3 to 6, wherein the distance between the second light emission power supply line and the first scanning power supply line is about 8 micrometers to 15 micrometers. [8] Display substrate according to claim 6, wherein the light emission shift register comprises a plurality of light emission transistors and a plurality of light emission capacitors, and the sampling shift register comprises a plurality of sampling transistors and a plurality of sampling capacitors, wherein the light emission capacitor and the sampling capacitor each comprise a first electrode plate and a second electrode plate; wherein the driver structure layer comprises: a semiconductor layer, a first electrically conductive layer, a second electrically conductive layer, a third electrically conductive layer and a fourth electrically conductive layer, which are arranged stacked one after the other; wherein the first sampling clock signal line comprises: a first sub-clock signal line and a second sub-clock signal line, which are electrically connected to each other; wherein the second sampling clock signal line comprises: a third sub-clock signal line and a fourth sub-clock signal line, which are electrically connected to each other; wherein the semiconductor layer comprises at least: active layers of the plurality of light-emitting transistors, active layers of the plurality of scanning transistors, an active layer of the first discharge transistor and an active layer of the second discharge transistor; wherein the first electrically conductive layer comprises at least: the light emission signal line, the sampling signal line, the gate electrodes of the plurality of light emission transistors, the first electrode plates of the plurality of light emission capacitors, the gate electrodes of the plurality of sampling transistors, the first electrode plates of the plurality of sampling capacitors, the gate electrode of the first discharge transistor and the gate electrode of the second discharge transistor; wherein the second electrically conductive layer comprises at least: the second electrode plates of the plurality of light emission capacitors, the second electrode plates of the plurality of sampling capacitors, the sampling output signal line and the light emission output signal line; wherein the third electrically conductive layer comprises at least: the light emission initial signal line, the first light emission clock signal line, the second light emission clock signal line, the first light emission power supply line, the second light emission power supply line, the sampling initial signal line, the first sub-clock signal line of the first sampling clock signal line, the third sub-clock signal line of the second sampling clock signal line, the first sampling power supply line, the second sampling power supply line, the first and second electrodes of the multitude of light emission transistors, the first and second electrodes of the multitude of sampling transistors, the first and second electrode of the first discharge transistor, and the first and second electrode of the second discharge transistor; wherein the fourth electrically conductive layer comprises at least: the second sub-clock signal line of the first sampling clock signal line and the fourth sub-clock signal line of the second sampling clock signal line. [9] Display substrate according to claim 8, wherein the first and second electrodes of the plurality of light emission transistors are located between the first light emission power supply line and the second light emission power supply line, wherein the first and second electrodes of the first discharge transistor up to the first and second electrodes of the second discharge transistor are located between the second light emission power supply line and the first sampling power supply line, wherein the first and second electrodes of some of the sampling transistors are located between the sampling initial signal line and the second sampling power supply line, and the first and second electrodes of another part of the sampling transistors may be located on a side of the second sampling power supply line that is close to the display area. [10] Display substrate according to claim 8, wherein at least one of the light emission output signal lines comprises: an output connection part and at least one output line, wherein the output connection part extends in the first direction, and at least one of the output lines is arranged in the first direction; wherein the output connection part is electrically connected to the light emission shift register and at least one output line, wherein the output line corresponds one-to-one to a light emission signal line to which the light emission output signal line is connected, and the output line is electrically connected to the corresponding light emission signal line. [11] Display substrate according to claim 10, wherein the output line comprises: an output body part extending at least partially in the second direction and an output connection part extending in the first direction, wherein the output body part is electrically connected to the output connection part; wherein the second electrode of the first discharge transistor and the second electrode of the second discharge transistor are a one-piece structure and their orthographic projection onto the substrate overlaps at least partially with an orthographic projection of the output connection part onto the substrate, wherein the one-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor is electrically connected to the output connection part. [12] Display substrate according to claim 11, wherein the active layer of the first discharge transistor and the active layer of the second discharge transistor are a single-piece structure and extend in the second direction; wherein the orthographic projection of the output interconnect part onto the substrate does not overlap with the orthographic projection of the single-piece structure of the active layer of the first discharge transistor and the active layer of the second discharge transistor onto the substrate. [13] Display substrate according to claim 10, wherein the active layer of the first discharge transistor and the active layer of the second discharge transistor are a one-piece structure and comprise: an active body part and an active connecting part, wherein the active body part is electrically connected to the active connecting part, and the active body part and the active connecting part are arranged in the first direction; wherein the active body part extends in the second direction, and the active connecting part extends at least partially in the first direction; wherein the active connecting part has a bent shape. [14] Display substrate according to claim 13, wherein the output line extends at least partially in the second direction; wherein the second electrode of the first discharge transistor and the second electrode of the second discharge transistor are a one-piece structure; wherein an orthographic projection of the active interconnect onto the substrate overlaps at least partially with orthographic projections of the one-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor and the output line onto the substrate, and the active interconnect is electrically connected to the one-piece structure of the second electrode of the first discharge transistor and the second electrode of the second discharge transistor and the output line. [15] Display substrate according to claim 13 or 14, wherein the width of the active connecting part is smaller than the width of the active body part. [16] Display substrate according to claim 8, wherein the scanning shift register comprises a first scanning capacitor, wherein the second electrode plate of the first scanning capacitor is electrically connected to the first scanning power supply line, and the second electrode plate of the first scanning capacitor extends in the second direction; wherein an orthographic projection of the second electrode plate of the first scanning capacitor onto the substrate overlaps at least partially with orthographic projections of the first scanning power supply line, the second scanning power supply line, the first scanning clock signal line, the second scanning clock signal line and the scanning initial signal line onto the substrate. [17] Display substrate according to claim 1, wherein the display area comprises: a first display area and a second display area located on at least one side of the first display area, wherein the display substrate further comprises: a light-emitting device and an anode connecting line located in the display area, wherein the pixel circuit is electrically connected to the light-emitting device; wherein the pixel circuit comprises: a first pixel circuit and a second pixel circuit located in the second display area, wherein the light-emitting device comprises: a first light-emitting device located in the first display area and a second light-emitting device located in the second display area, wherein the first pixel circuit is electrically connected to the first light-emitting device and the second pixel circuit is electrically connected to the second light-emitting device; wherein an orthographic projection of the first pixel circuit onto the substrate overlaps at least partially with an orthographic projection of the first light emission element associated with the first pixel circuit onto the substrate; wherein the anode connecting line is electrically connected to the second light emission element and the second pixel circuit connected to the second light emission element. [18] Display substrate according to claim 17, wherein the driver structure layer further comprises: a first power supply line, a data signal line and a data connection line, which are located at least partially within the display area; wherein the first power supply line and the data signal line extend at least partially in the first direction, and the data link line extends at least partially in the second direction; wherein the driver structure layer further comprises: a fourth electrically conductive layer and a fifth electrically conductive layer, which are stacked successively on a third electrically conductive layer; wherein the third electrically conductive layer includes at least: the data link line; wherein the fourth electrically conductive layer includes at least: the first power supply line and the data signal line; the fifth electrically conductive layer includes at least the anode connecting conductor; where the fifth electrically conductive layer is a transparent electrically conductive layer. [19] Display substrate according to claim 18, wherein the driver structure layer further comprises: a flat layer located between the third electrically conductive layer and the fourth electrically conductive layer, wherein the flat layer has a groove; where an orthographic projection of the electrostatic discharge circuit onto the substrate overlaps at least partially with an orthographic projection of the groove onto the substrate. [20] Display substrate according to claim 19, wherein the driver structure layer further comprises: at least one initial power supply line located in the non-display area, and at least one initial signal line located at least partially in the display area; wherein the initial power supply line is located on a side of the sampling driver circuit that is close to the display area, and wherein the initial power supply line extends at least partially in the first direction, and the initial signal line extends at least partially in the second direction; wherein the initial power supply line comprises a first sub-initial power supply line and a second sub-initial power supply line which are electrically connected to each other; wherein at least one initial power supply line corresponds one-to-one to at least one initial power supply line, wherein the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line; wherein the second electrically conductive layer includes at least: the initial signal line; wherein the third electrically conductive layer comprises at least: the first sub-initial power supply line of the initial power supply line; wherein the fourth electrically conductive layer includes at least: the second first sub-initial power supply line of the initial power supply line. [21] Display device comprising: a display substrate according to any one of claims 1 to 20 and a light-sensitive sensor arranged within the display substrate.

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