Thin-film transmitter and its manufacturing process as well as display board

Abstract

The present disclosure provides a thin-film transistor and its fabrication process, as well as a display panel. The thin-film transistor comprises a substrate, an active layer, and a first gate electrode arranged on the substrate. The active layer comprises a first film layer and a second film layer arranged one above the other on the substrate. The second film layer is located between the first film layer and the first gate electrode. The first film layer comprises oxygen elements, the second film layer comprises a crystalline oxide, and the first and second film layers are formed by simultaneous annealing. In the thin-film transistor, annealing allows some of the oxygen elements originally present in the first film layer to penetrate into the second film layer to supplement the existing oxygen, so that the second film layer is not exposed to a high-oxygen environment (e.g.,at high oxygen partial pressure). This prevents the second film layer from making the thin-film transistor channel conductive due to an insufficient oxygen content, while it also prevents the second film layer from causing etching residue due to high etching difficulty caused by an excessive oxygen content during the etching process.

Description

Thin film transistor, manufacturing method thereof, and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202310790822.3, filed on June 29, 2023, entitled “Thin Film Transistor, Method for Making Same, Display Panel,” and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, and a display panel. Background Art

[0004] With the development of information technology, electronic display products are increasingly used in daily life. Thin-film transistors (TFTs) are the primary switching elements in the drive circuits of these electronic display products. However, the active layers of current TFTs, limited by their structural design and fabrication processes, struggle to maintain both high mobility and stability while ensuring effective film formation. This, in turn, limits further improvements in TFT performance.

[0005] Summary of the Invention

[0006] A first aspect of the present disclosure provides a thin film transistor, which includes a substrate and an active layer and a first gate electrode located on the substrate, the active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer includes oxygen elements, the second film layer includes crystalline oxide, and the first film layer and the second film layer are formed by synchronous annealing.

[0007] In the above scheme, part of the oxygen elements originally present in the first film layer can be supplemented into the second film layer through annealing. Therefore, the second film layer does not need to be prepared in a high oxygen environment (such as high oxygen partial pressure). This can avoid the second film layer from causing the channel of the thin film transistor to be turned on due to too low oxygen content, and can also avoid the second film layer from having etching residues due to the difficulty of etching the second film layer during the etching process due to too high oxygen content.

[0008] A second aspect of the present disclosure provides a display panel, which may include the thin film transistor in the first aspect.

[0009] A third aspect of the present disclosure provides a method for preparing a thin film transistor, which includes: providing a substrate; forming a first pattern layer having an oxygen element on the substrate, depositing a semiconductor thin film on the substrate and patterning the semiconductor thin film to form a second pattern layer, the first pattern layer and the second pattern layer being stacked on the substrate and in contact with each other; annealing the first pattern layer and the second pattern layer so that the oxygen element in the first pattern layer diffuses into the second pattern layer, forming a first film layer after annealing the first pattern layer, and forming a second film layer after annealing the second pattern layer; depositing a conductive material thin film, and patterning the conductive material thin film to form a first gate electrode, the second film layer being located between the first film layer and the first gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a cross-sectional view of a thin film transistor provided in one embodiment of the present disclosure;

[0011] FIG2 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0012] FIG3 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0013] FIG4 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0014] FIG5 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0015] FIG6 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0016] FIG7 is a cross-sectional view of another thin film transistor provided in accordance with an embodiment of the present disclosure.

[0017] FIG8 is a cross-sectional view of an array substrate provided in accordance with an embodiment of the present disclosure.

[0018] FIG9 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure.

[0019] FIG10 is a cross-sectional view of the display panel shown in FIG9 along line MN.

[0020] FIG11 is a flow chart of a method for manufacturing a thin film transistor provided in one embodiment of the present disclosure.

[0021] 12 to 17 are process diagrams of a method for manufacturing a thin film transistor provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] During the preparation process of thin-film transistors, crystalline oxides with high mobility and high stability are selected as channel materials because: crystalline oxide materials have a higher dielectric constant, which can increase the capacitance of the transistor to improve the performance of the thin-film transistor; crystalline oxide materials have a higher carrier mobility, which can improve the response speed and output power of the thin-film transistor; in addition, crystalline oxide materials have higher chemical stability and thermal stability, which can ensure the long-term stability and reliability of thin-film transistors; in addition, crystalline oxide materials can be prepared through modern manufacturing processes such as chemical vapor deposition, which can achieve high-precision and high-quality production.

[0023] However, in the current process, in order to ensure the high mobility and high stability of the crystalline oxide, it will be formed in a high oxygen partial pressure environment. However, the etching (patterning) of the film layer formed in this way is difficult and can easily cause residues and cause device failures. If the film layer is prepared in a low oxygen partial pressure environment, the channel will be easily turned on, making the thin film transistor prone to leakage current.

[0024] The embodiments of the present disclosure provide a thin film transistor, a method for preparing the same, and a display panel to at least solve the above-mentioned technical problems. The thin film transistor includes a substrate and an active layer and a first gate electrode located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate. The second film layer is located between the first film layer and the first gate electrode. The first film layer includes oxygen elements, and the second film layer includes a crystalline oxide. In this design, the active layer is to be annealed. During the annealing, the oxygen elements originally present in the first film layer can be supplemented into the second film layer. Therefore, the second film layer does not need to be prepared in a high oxygen environment (such as a high oxygen partial pressure). This can avoid the second film layer from being turned on due to the low oxygen content in the second film layer, while avoiding the second film layer from being difficult to etch due to the high oxygen content in the etching process.

[0025] Below, in conjunction with the accompanying drawings, a thin film transistor and its manufacturing method, and the structures involved in the display panel according to at least one embodiment of the present disclosure are described. In these embodiments, a spatial rectangular coordinate system is established with the surface of the substrate in the thin film transistor (for example, or the display surface of the display panel) as a reference to describe the positions of various structures in the thin film transistor and the display panel. In this spatial rectangular coordinate system, the X-axis and Y-axis are parallel to the substrate, and the Z-axis is perpendicular to the substrate.

[0026] As shown in Figure 1, a thin film transistor 100 includes an active layer 120, a first gate electrode 131, a source electrode 141, and a drain electrode 142. The source electrode 141 and the drain electrode 142 are connected to the active layer 120, and the first gate electrode 131 is spaced apart from the active layer 120. A substrate 110 supports the active layer 120, the first gate electrode 131, the source electrode 141, and the drain electrode 142. By controlling the voltage on the first gate electrode 131, the active layer 120 can be caused to generate voltage fluctuations, generating carriers and thus forming a current channel. In this way, the switching and degree of the thin film transistor 100 can be controlled.

[0027] The active layer 120 includes a first film layer 121 and a second film layer 122 stacked together. The second film layer 122 includes a crystalline oxide (semiconductor layer), the first film layer 121 includes oxygen, and the first film layer 121 and the second film layer 122 are formed by simultaneous annealing. In this way, during the annealing, the oxygen in the first film layer 121 will diffuse into the second film layer 122, so that the oxygen content in the second film layer 122 reaches the desired level, so that the second film layer 122 has high mobility and high stability. Accordingly, this reduces the oxygen content required for the second film layer 122 before annealing. In this way, before annealing, when preparing the second film layer 122, it is easy to etch because of its low oxygen content, thereby avoiding the second film layer 122 from causing residue during etching.

[0028] In the embodiment of the present disclosure, the second film layer 122 serves as the main film layer constituting the channel in the active layer 120. When the second film layer 122 is located between the first film layer 121 and the first gate electrode 131, the second film layer 122 is closer to the first gate electrode 131, thereby improving the sensitivity of the thin film transistor when driven.

[0029] For example, in at least one embodiment of the present disclosure, as shown in Figure 1, the thin film transistor 100 may further include a first gate insulating layer 151 and an interlayer dielectric layer 160 to define various structures in the thin film transistor 100. For example, the first gate insulating layer 151 is located between the first gate electrode 131 and the active layer 120 to separate the first gate electrode 131 and the active layer 120, and the interlayer dielectric layer 160 is located between the source-drain electrode layer (including the source electrode 141 and the drain electrode 142) and the active layer 120 to separate the source-drain electrode layer and the active layer 120.

[0030] For example, in at least one embodiment of the present disclosure, as shown in FIG. 1 , the thin film transistor 100 may further include a buffer layer 170 between the substrate 110 and the active layer 120 . The buffer layer 170 may block harmful ions that invade from the substrate 110 into the active layer 120 .

[0031] It should be noted that in the embodiments of the present disclosure, as long as the first film layer provides oxygen to the second film layer during annealing, the specific material of the first film layer is not limited. Below, examples are provided for different choices of materials for the first film layer and the structures of thin-film transistors under these choices.

[0032] In some embodiments of the present disclosure, as shown in FIG1 , the first film layer 121 can be set as a semiconductor layer, and the first film layer is a film layer formed by annealing an amorphous oxide film layer, that is, the first film layer 121 is a semiconductor layer formed of an amorphous oxide material.

[0033] Under annealing, the chemical bonds within the molecules in the amorphous oxide become unstable, leading to the release of oxygen ions; in addition, high temperature also increases the active sites on the oxide surface, making it easier to chemically react with other molecules, resulting in the loss of oxygen ions.

[0034] It should be noted that the mobility of the first film layer composed of an amorphous oxide is lower than that of the second film layer composed of a crystalline oxide. Therefore, the second film layer is used to form a channel. That is, when the thin film transistor is in operation (e.g., turned on), a two-dimensional electron gas (carriers) is formed in the second film layer. For example, the two-dimensional electron gas accumulates on the surface of the second film layer facing the gate electrode (e.g., the first gate electrode).

[0035] For example, as shown in Figure 1, when the first film layer 121 is a semiconductor layer, the first film layer 121 and the second film layer 122 can be prepared under the same composition process to reduce the preparation process flow of the active layer 120. In this case, the patterns of the first film layer 121 and the second film layer 122 roughly overlap, that is, the orthographic projection of the first film layer 121 on the substrate 110 overlaps with the orthographic projection of the second film layer 122 on the substrate 110.

[0036] In the embodiment of the present disclosure, the two objects whose projections "coincide" have the same planar shape and equal area, and along the direction of projection (the direction of orthographic projection is the direction of the Z axis), the two objects are positioned opposite each other.

[0037] It should be noted that in the embodiments of the present disclosure, when the first film layer is a semiconductor layer and the thin film transistor includes only one gate electrode (first gate electrode), the thin film transistor can be set as a top-gate thin film transistor, or it can be set as a bottom-gate thin film transistor, as follows.

[0038] For example, in some embodiments of the present disclosure, as shown in FIG1 , when the first film layer 121 is a semiconductor layer, the first film layer 121 is located between the second film layer 122 and the substrate 110 , that is, the thin film transistor 100 is a top-gate thin film transistor.

[0039] For example, in some other embodiments of the present disclosure, as shown in FIG2 , when the first film layer 121 is a semiconductor layer, the second film layer 122 is located between the first film layer 121 and the substrate 110 , that is, the thin film transistor 100 is a bottom-gate thin film transistor.

[0040] For example, as shown in Figure 2, when the thin film transistor 100 is a bottom-gate thin film transistor, the positive projection of the active layer 120 on the substrate 110 is located within the positive projection of the first gate electrode 131 on the substrate 110. In this way, the setting of the first gate electrode 131 can avoid adverse effects on the flatness of the active layer 120; in addition, the first gate electrode 131 can block the light passing through the side of the substrate 110 to reduce the problem of photogenerated carriers in the active layer 120; in addition, the first gate electrode 131 can block harmful ions invading from the substrate 110 to the active layer 120.

[0041] When the first film layer is composed of amorphous oxide, the first film layer and the second film layer are both formed under a certain oxygen partial pressure environment (such as physical vapor deposition, physical chemical vapor deposition, etc.). Therefore, by controlling the oxygen partial pressure environment during the deposition of the first film layer and the second film layer, the oxygen content of the first film layer and the second film layer in the initial state of film formation can be controlled, and the amount of oxygen elements that can diffuse out of the first film layer under annealing conditions can be controlled.

[0042] For example, in some embodiments of the present disclosure, when the first film layer includes an amorphous oxide, the oxygen partial pressure of the amorphous oxide film formed by annealing the first film layer is greater than the oxygen partial pressure of the semiconductor film formed by annealing the second film layer. As a result, the first film layer formed under high oxygen partial pressure conditions will contain more easily separable oxygen elements, which are easily lost during annealing, allowing the oxygen elements in the first film layer to diffuse into the second film layer.

[0043] For example, the oxygen partial pressure of the amorphous oxide film layer formed by annealing as the first film layer is 30% to 90%, and the oxygen partial pressure of the semiconductor film layer formed by annealing as the second film layer (such as the second pattern layer described below) is 10% to 60%.

[0044] "Oxygen partial pressure" refers to the partial pressure of oxygen in a gas mixture at a specific temperature and environment. For example, in some embodiments of the present disclosure, the oxygen partial pressure is a mixture of oxygen and an inert gas (e.g., argon). The oxygen partial pressure represents the ratio of the pressure provided by the oxygen to the pressure of the gas mixture.

[0045] When the material of the first film layer includes an amorphous oxide, the specific type of the amorphous oxide is not limited and can be determined based on actual process requirements. For example, the material of the first film layer can include at least one of In, Ga, and Zn. For example, the first film layer can be a quaternary material, i.e., a material including four elements. Exemplarily, the material of the first film layer can include IGZO. For example, the material of the first film layer can also be doped with at least one of Fe, Cu, Al, Zr, and Ti.

[0046] In the case where the material of the second film layer includes a crystalline oxide, there is no restriction on the specific type of the crystalline oxide, and it can be determined according to the actual process requirements. For example, the material of the second film layer may include at least one of In, Sn, Ga, Zn, etc. For example, the second film layer may be a ternary material, that is, including three elemental materials. Exemplarily, the material of the second film layer may include ITO, IZO or IGO. For example, optionally, the material of the second film layer may also be doped with at least one of Fe, Cu, Al, Zr, and Ti. The material film layer used to prepare the second film layer may be an amorphous oxide film layer or a crystalline oxide film layer before annealing.

[0047] It should be noted that in the embodiments of the present disclosure, the thickness range of the first film layer and the second film layer can be 40 to 250 angstroms, such as 150 angstroms, 200 angstroms, etc. The specific thickness can be designed according to actual process requirements and is not limited to the above range.

[0048] In other embodiments of the present disclosure, as shown in Figure 3, the first film layer 121 is formed by annealing an oxygen-rich oxide film layer. The oxygen element in the oxygen-rich oxide is easily separated to form oxygen ions, which diffuse to the surroundings.

[0049] It should be noted that in the embodiments of the present disclosure, when the first film layer is an oxygen-rich oxide before annealing and the thin film transistor includes only one gate electrode (first gate electrode), the thin film transistor can be set as a top-gate thin film transistor, or it can be set as a bottom-gate thin film transistor, as follows.

[0050] For example, in some embodiments of the present disclosure, as shown in Figure 3, when the first film layer 121 is an oxygen-rich oxide film layer before annealing, the first film layer 121 is located between the second film layer 122 and the substrate 110, and the orthographic projection of the second film layer 122 on the substrate 110 is located within the orthographic projection of the first film layer 121 on the substrate 110, that is, the thin film transistor 100 is a top-gate thin film transistor.

[0051] For example, in some other embodiments of the present disclosure, if the first film layer is an oxygen-rich oxide film layer before annealing, the second film layer can be located between the first film layer and the substrate, that is, the thin film transistor is a bottom-gate thin film transistor. For example, in this case, the first film layer can only cover the channel portion of the second film layer (overlapping with the first gate electrode) so that the source electrode and the drain electrode are in direct contact with the second film layer; or the first film layer can completely cover the second film layer, but a via is provided in the first film layer, and the source electrode and the drain electrode are connected to the second film layer through the via.

[0052] "Oxygen-rich oxides" refer to compounds containing a high oxygen content. These compounds typically contain a large number of oxygen atoms and are chemically active, making them susceptible to oxygen loss during the annealing process. In the embodiments of the present disclosure, the material of the oxygen-rich oxide is not limited and can be selected based on actual process requirements. For example, the oxygen-rich oxide may include at least one of iron oxide, copper oxide, aluminum oxide, aluminum oxide, zirconium oxide, titanium oxide, and the like.

[0053] In other embodiments of the present disclosure, as shown in FIG4 , the first film layer 121 is configured as a substrate layer including oxygen ions. The substrate layer covers the substrate 110 and includes oxygen ions in at least a portion of the substrate layer. The region of the substrate layer including oxygen ions can serve as the first film layer 121. That is, the orthographic projection of the second film layer 122 on the substrate 110 at least partially overlaps with the orthographic projection of the region of the substrate layer including oxygen ions on the substrate 110. For example, oxygen ions can be implanted into the substrate layer by ion implantation, thereby causing the region of the substrate layer overlapping with the second film layer 122 to contain oxygen ions.

[0054] For example, in some embodiments, as shown in FIG4 , when the first film layer 121 is configured as a substrate layer including oxygen ions, the entire region of the substrate layer includes oxygen ions. For example, when manufacturing a thin film transistor, an entire substrate layer is deposited on a substrate, oxygen ions are then included in the substrate layer, and then the second film layer 122 is formed. In this case, the first film layer 121 can be considered to be a film layer covering the entire surface of the substrate 110.

[0055] For example, in some embodiments, as shown in FIG5 , when the first film layer 121 is configured as a substrate layer including oxygen ions, the region of the substrate layer that overlaps with the second film layer 122 includes oxygen ions, and the portion of the substrate layer that includes oxygen ions is the first film layer 121. For example, when preparing a thin film transistor, an entire substrate layer is deposited on a substrate, and then a portion of the substrate layer includes oxygen ions, and then the second film layer 122 is prepared, wherein the region including oxygen ions substantially overlaps with the second film layer 122. In this case, the first film layer 121 overlaps with the second film layer 122; furthermore, during annealing, all of the oxygen ions included in the substrate layer can be used to diffuse into the second film layer 122, rather than invading and becoming free in other film layers, thereby adversely affecting the performance of the thin film transistor or other devices (e.g., components in a display panel).

[0056] For example, as shown in Figure 5, when the first film layer 121 is configured as a substrate layer including oxygen ions, the first film layer 121 is located between the second film layer 122 and the substrate 110, that is, the thin film transistor is at least a top-gate thin film transistor (for example, it can be further designed as a dual-gate thin film transistor).

[0057] For example, as shown in Figure 5, when the first film layer 121 is configured as a substrate layer containing oxygen ions, the substrate layer can be designed as an inorganic layer. The inorganic layer has a high density, which can improve the surface defects of the substrate 110 and block harmful ions in the substrate 110. In this case, the substrate layer actually acts as a buffer layer 170. That is, in this design, the first film layer 121 and the buffer layer 170 are integrated together to reduce module design.

[0058] For example, when the base material layer serves as a buffer layer, the material of the base material layer may be silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0059] In at least one embodiment of the present disclosure, as shown in FIG6 , the active layer 120 may further include a third film layer 123. The third film layer 123 is located between the second film layer 122 and the first gate electrode 131, and the third film layer 123 is an amorphous oxide film layer formed by annealing. Thus, during annealing, oxygen elements in the first film layer 121 and the third film layer 123 located on both sides of the second film layer 122 can simultaneously diffuse into the second film layer 122, thereby increasing the efficiency of oxygen elements entering the second film layer 122. In addition, the first film layer 121 and the third film layer 123 can block both sides of the second film layer 122, thereby reducing the risk of harmful ions invading the second film layer 122.

[0060] It should be noted that the mobility of the third film layer composed of amorphous oxide is lower than the mobility of the second film layer composed of crystalline oxide. Therefore, the second film layer is still used to form the channel.

[0061] For example, in some embodiments of the present disclosure, as shown in FIG6 , when the third film layer is a semiconductor material (amorphous oxide film layer), the third film layer 123 and the second film layer 122 can be prepared using the same patterning process to reduce the preparation process flow of the active layer 120. In this case, the orthographic projection of the third film layer 123 on the substrate 110 coincides with the orthographic projection of the second film layer 122 on the substrate 110. For example, further, the orthographic projections of the first film layer 121, the second film layer 122, and the third film layer 123 on the substrate 110 coincide, that is, the first film layer 121, the second film layer 122, and the third film layer 123 are formed using the same patterning process. In this way, the second film layer 122 can be prevented from coming into contact with other materials (e.g., photoresist) and being contaminated (e.g., by ion intrusion).

[0062] It should be noted that both ends of the second film layer need to be doped (for example, heavily doped) to make it conductive, so as to ensure the electrical connection between the active layer and the source electrode and the drain electrode. In this case, the setting of the first film layer and the third film layer needs to ensure that it will not have an adverse effect on the doping of the second film layer.

[0063] For example, in at least one embodiment of the present disclosure, as shown in FIG6 , when the first film layer 121, the second film layer 122, and the third film layer 123 are sequentially stacked on the substrate 110, the oxygen partial pressure of the amorphous oxide film layer formed by annealing the third film layer 123 is greater than the oxygen partial pressure of the semiconductor film layer formed by annealing the second film layer 122, and less than the oxygen partial pressure of the amorphous oxide film layer formed by annealing the first film layer 121. In this way, it is possible to avoid the oxygen content in the third film layer 123 being too high, which would make it difficult to heavily dope both ends of the second film layer 122.

[0064] For example, the oxygen partial pressure of the amorphous oxide film formed as the third film layer by annealing is 15% to 85%.

[0065] When the material of the third film layer includes an amorphous oxide, the specific type of the amorphous oxide is not limited and can be determined based on actual process requirements. For example, the material of the third film layer can include at least one of In, Ga, and Zn. For example, the third film layer can be a quaternary material, and illustratively, the material of the third film layer can include IGZO. For example, the material of the third film layer can also be doped with at least one of Fe, Cu, Al, Zr, and Ti.

[0066] It should be noted that in the embodiments of the present disclosure, the thickness of the third film layer can range from 40 to 250 angstroms, such as 150 angstroms, 200 angstroms, etc. The specific thickness can be designed according to actual process requirements and is not limited to the above range.

[0067] It should be noted that in the embodiments of the present disclosure, the active layer can also be configured as a stack of four or more film layers. The properties of the additional film layers can be similar to those of the first and third film layers, so that more oxygen can diffuse into the second film layer. For example, these additional film layers can be located between the second film layer and the substrate to avoid hindering the doping process of the second film layer.

[0068] In at least one embodiment of the present disclosure, as shown in FIG7 , the thin film transistor 100 can be designed as a dual-gate thin film transistor to improve the response speed of the thin film transistor. For example, the thin film transistor 100 can include a second gate electrode 132 located on a side of the active layer 120 away from the first gate electrode 131.

[0069] It should be noted that for the first gate electrode and the second gate electrode, the area of ​​the side located between the active layer and the substrate must be larger than the area of ​​the active layer to shield the active layer and ensure the flatness of the active layer. For example, as shown in FIG7 , the second gate electrode 132 is located between the active layer 120 and the substrate 110, and the orthographic projection of the active layer 120 on the substrate 110 is located within the orthographic projection of the second gate electrode 132 on the substrate 110.

[0070] For example, as shown in FIG. 7 , in the case where the second gate electrode 132 is provided, the thin film transistor 100 may further include a second gate insulating layer 152 located between the active layer 120 and the second gate electrode 132 .

[0071] It should be noted that in the embodiments of the present disclosure, whether or not two gate electrodes are provided in a thin-film transistor is not limited by the number of film layers in the active layer and can be selected based on actual needs. For example, if a second gate electrode is not provided, a second gate electrode can still be provided on the side of the active layer facing away from the first gate electrode to improve the response speed of the thin-film transistor.

[0072] At least one embodiment of the present disclosure provides an array substrate, as shown in Figure 8, the array substrate may include a driving circuit layer 10, the driving circuit layer includes a plurality of pixel driving circuits, each pixel driving circuit includes a plurality of thin film transistors 100, and at least one thin film transistor is the thin film transistor in the above embodiment.

[0073] For example, the pixel driving circuit may include multiple transistors TFT (thin film transistors), capacitors, etc., and may be formed in various forms such as 2T1C (i.e., two transistors (TFT) and one capacitor (C)), 3T1C, or 7T1C. The pixel driving circuit is connected to a light-emitting device (see the light-emitting device 200 in the following embodiment) to control the switching state and the light-emitting brightness of the light-emitting device.

[0074] For example, in at least one embodiment of the present disclosure, as shown in Figure 8, the array substrate may further include a planar layer 180 and an anode 210 located on the planar layer 180, a via is provided in the planar layer 180, a pixel driving circuit is provided corresponding to the anode 210, and a source electrode or a drain electrode of a thin film transistor in the pixel driving circuit is connected to the corresponding anode 210 through the via.

[0075] At least one embodiment of the present disclosure provides a display panel, as shown in Figures 9 and 10, which includes a display function layer 20 and the array substrate 10 in the above embodiment. The display panel can be divided into a display area 1 and a frame area 2 located on at least one side of the display area, and a plurality of sub-pixels R, G, and B are arranged in the display area 1. The display function layer 20 is located on the array substrate 10 and includes a plurality of light-emitting devices 200, which are physical light-emitting structures of sub-pixels R, G, and B. For example, the light-emitting devices 200 respectively located in the sub-pixels R, G, and B are respectively designed to emit red light (R), green light (G), and blue light (B). For example, the light-emitting devices 200 are connected to the pixel driving circuit in the array substrate 100.

[0076] The light-emitting device 200 may include an anode 210, a light-emitting functional layer 230, and a cathode 220 stacked in sequence on an array substrate. The light-emitting functional layer 230 may include a first common layer 231, a light-emitting layer 232, and a second common layer 233 stacked in sequence on the anode 210. For example, the first common layer 231 may include a hole injection layer, a hole transport layer, and may further include an electron blocking layer. For example, the second common layer 233 may include an electron injection layer, an electron transport layer, and may further include a hole blocking layer.

[0077] For example, as shown in FIG. 10 , the display panel may further include a pixel defining layer 300 , wherein the pixel defining layer 300 includes a plurality of openings to define positions of the light emitting devices. For example, the light emitting layer of each light emitting device 200 is located in the opening.

[0078] 10 , the display panel may further include an encapsulation layer 30 to cover the display function layer 20 to protect the light-emitting device 200. For example, the encapsulation layer 30 may include a first inorganic encapsulation layer 31, an organic encapsulation layer 32, and a second inorganic encapsulation layer 33 sequentially stacked on the display function layer 20.

[0079] For example, in an embodiment of the present disclosure, the display panel may further include functional structures such as a touch function layer, a polarizer, a lens layer, and a cover plate located on the display side (eg, on the encapsulation layer).

[0080] For example, in the embodiments of the present disclosure, the display panel may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, or a navigator.

[0081] At least one embodiment of the present disclosure provides a method for manufacturing the thin film transistor mentioned in the above embodiment. As shown in FIG11 , the method may include the following steps S100 to S300 .

[0082] S100, providing a substrate; forming a first pattern layer having oxygen elements on the substrate, and depositing a semiconductor film on the substrate and patterning the semiconductor film to form a second pattern layer, the first pattern layer and the second pattern layer are stacked on the substrate and in contact with each other.

[0083] S200, annealing the first pattern layer and the second pattern layer so that the oxygen element in the first pattern layer diffuses into the second pattern layer, and the first pattern layer is annealed to form a first film layer, and the second pattern layer is annealed to form a second film layer, and the second film layer includes crystalline oxide.

[0084] It should be noted that whether a semiconductor material crystallizes during annealing depends on the structure and chemical composition of the material. That is, for amorphous semiconductor materials, some amorphous semiconductor materials will not crystallize during the annealing process, while other amorphous semiconductor layer materials will cause the crystals to rearrange and recrystallize during the annealing process to form grains with orderly arrangement. Therefore, in the embodiments of the present disclosure, according to the actual process requirements, the material of the second pattern layer (semiconductor film) is selected to be a crystalline oxide, or it can be an amorphous oxide. In the case of selecting an amorphous oxide, the material selection of the second pattern layer needs to enable it to complete crystallization during annealing.

[0085] S300 , depositing a conductive material film, and patterning the conductive material film to form a first gate electrode, wherein the second film layer is located between the first film layer and the first gate electrode.

[0086] In this preparation method, oxygen elements can be added to the second film layer (second pattern layer) through annealing. Therefore, the second film layer does not need to be prepared in a high-oxygen environment (such as high oxygen partial pressure). This can avoid the second film layer from causing the channel of the thin film transistor to be turned on due to too low oxygen content, and can also avoid the second film layer from having etching residues due to the difficulty of etching the second film layer during the etching process due to too high oxygen content.

[0087] For example, in at least one embodiment of the present disclosure, step S100 may include depositing a first amorphous oxide thin film and patterning the first amorphous oxide thin film to obtain a first pattern layer. Specifically, the material of the first pattern layer used to form the first film layer is a semiconductor material (amorphous oxide). In this design, the specific materials and formation environment of the first and second film layers can be found in the description of the aforementioned embodiments and are not further elaborated here.

[0088] For example, in some embodiments of the present disclosure, when performing the above-mentioned step S100, the conditions provided are: depositing a first amorphous oxide film in a first oxygen partial pressure environment, and depositing a semiconductor film in a second oxygen partial pressure environment, the first oxygen partial pressure being greater than the second oxygen partial pressure.

[0089] For example, the first oxygen partial pressure is 30% to 90%, and the second oxygen partial pressure is 10% to 60%.

[0090] For example, in some embodiments of the present disclosure, the step of forming a first patterned layer having an oxygen element on a substrate may include depositing an oxygen-rich oxide film layer and patterning the first amorphous oxide film to obtain the first patterned layer. Regarding the description of the first film layer being formed from an oxygen-rich oxide film layer via annealing, reference may be made to the description in the aforementioned embodiments and will not be repeated here.

[0091] For example, in at least one embodiment of the present disclosure, the preparation method may further include: depositing a second amorphous oxide thin film, and patterning the second amorphous oxide thin film to obtain a third pattern layer, wherein the first pattern layer, the second pattern layer, and the third pattern layer are stacked on the substrate, and the second pattern layer is located between the first pattern layer and the third pattern layer and in contact with the third pattern layer; and during the annealing process of the first pattern layer and the second pattern layer, the third pattern layer is simultaneously annealed to form a third film layer from the third pattern layer. In this design, the specific materials and formation environment of the third film layer can be found in the relevant description of the aforementioned embodiments and are not further described here.

[0092] For example, the second amorphous oxide film can be deposited in a third oxygen partial pressure environment, wherein the first oxygen partial pressure is greater than the third oxygen partial pressure, and the third oxygen partial pressure is greater than the second oxygen partial pressure. For example, the third oxygen partial pressure is 15% to 85%.

[0093] In at least one embodiment of the present disclosure, the preparation method may further include: depositing a conductive material thin film on a substrate, and patterning the conductive material thin film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer facing away from the first gate electrode. Regarding the structure of the thin film transistor when it is formed as a dual-gate thin film transistor, please refer to the relevant description in the aforementioned embodiments and will not be repeated here.

[0094] Next, the process of preparing the thin film transistor shown in FIG. 7 is taken as an example to describe the process of the thin film transistor in at least one embodiment of the present disclosure. For details, please refer to the process steps shown in FIG. 12 to FIG. 17 below.

[0095] As shown in FIG12 , a substrate 110 is provided and an insulating material layer and a conductive material film are sequentially deposited on the substrate 110 , wherein the insulating material layer forms a buffer layer 170 ; and the conductive material film is patterned to form a second gate electrode 132 .

[0096] In an embodiment of the present disclosure, the patterning process may be a photolithography patterning process, which may include, for example, coating a photoresist on a structural layer to be patterned, exposing the photoresist using a mask, developing the exposed photoresist to obtain a photoresist pattern, etching the structural layer using the photoresist pattern (optionally wet etching or dry etching), and then optionally removing the photoresist pattern. It should be noted that when the material of the structural layer includes photoresist, the structural layer may be directly exposed through a mask to form the desired pattern.

[0097] As shown in Figures 12 and 13, an insulating material film is deposited on the substrate 110 having the second gate electrode 132 formed thereon to form a second gate insulating layer 152. A first amorphous oxide film 121a, a semiconductor film 122a, and a second amorphous oxide film 123a are then sequentially deposited on the second gate insulating layer 152. The first amorphous oxide film 121a, the semiconductor film 122a, and the second amorphous oxide film 123a are formed under oxygen partial pressures of 30% to 90%, 10% to 60%, and 15% to 85%, respectively.

[0098] As shown in FIG. 13 and FIG. 14 , the first amorphous oxide film 121 a , the semiconductor film 122 a , and the second amorphous oxide film 123 a are patterned to form a first pattern layer 121 b , a second pattern layer 122 b , and a third pattern layer 123 b , respectively.

[0099] As shown in Figures 14 to 15, the first pattern layer 121b, the second pattern layer 122b and the third pattern layer 123b are annealed to form a first film layer 121, a second film layer 122 and a third film layer 123, respectively. The first film layer 121, the second film layer 122 and the third film layer 123 stacked together constitute an active layer 120.

[0100] For example, in the step shown in FIG. 15 , a doping process may be performed to make both ends of the second film layer 122 conductive.

[0101] As shown in FIG. 15 and FIG. 16 , an insulating material is deposited on the active layer 120 to form a first gate insulating layer 151 ; then a conductive material film is deposited on the first gate insulating layer 151 , and the conductive material film is patterned to form a first gate electrode 131 .

[0102] As shown in FIG. 16 and FIG. 17 , an insulating material film layer is deposited on the substrate 110 on which the first gate electrode 131 is formed to form an interlayer dielectric layer 160 .

[0103] As shown in Figures 17 and 7, the interlayer dielectric layer 160 is patterned to form vias; a conductive material film is deposited on the interlayer dielectric layer 160, and the conductive material film is patterned to form a source electrode 141 and a drain electrode 142. The source electrode 141 and the drain electrode 142 are connected to the active layer 120 through the vias in the interlayer dielectric layer 160.

Claims

1. A thin film transistor, comprising a substrate, an active layer and a first gate electrode located on the substrate, wherein: The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, and The first film layer includes oxygen element, and the second film layer includes crystalline oxide.

2. The thin film transistor according to claim 1, wherein: The first film layer is a semiconductor layer, and the first film layer is an amorphous oxide film layer, and The second film layer is located between the first film layer and the substrate, or the first film layer is located between the second film layer and the substrate.

3. The thin film transistor according to claim 2, wherein: The orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the second film layer on the substrate.

4. The thin film transistor according to claim 2 or 3, wherein: The material of the first film layer includes at least one of In, Ga, and Zn; and / or The material of the second film layer includes at least one of In, Sn, Ga, and Zn.

5. The thin film transistor according to claim 4, wherein: The first film layer is doped with at least one of Fe, Cu, Al, Zr and Ti; and / or The second film layer is doped with at least one of Fe, Cu, Al, Zr and Ti.

6. The thin film transistor according to claim 5, wherein: The first film layer is configured as a substrate layer including oxygen ions, the substrate layer covers the substrate and the substrate layer includes the oxygen ions in at least a partial region, The orthographic projection of the second film layer on the substrate at least partially overlaps with the orthographic projection of the region of the base material layer including the oxygen ions on the substrate, and The entire region of the substrate layer includes the oxygen ions, or a region of the substrate layer overlapping with the second film layer includes the oxygen ions, and a portion of the substrate layer including the oxygen ions is the first film layer.

7. The thin film transistor according to claim 6, wherein: The first film layer is located between the second film layer and the substrate, and the base material layer is an inorganic layer.

8. The thin film transistor according to claim 7, wherein: The active layer further comprises: The third film layer is located between the second film layer and the first gate electrode, and the third film layer is a non-crystalline oxide film layer.

9. The thin film transistor according to claim 8, wherein: The orthographic projection of the third film layer on the substrate coincides with the orthographic projection of the second film layer on the substrate.

10. The thin film transistor according to claim 8, wherein: The material of the third film layer includes at least one of In, Ga, and Zn.

11. The thin film transistor according to claim 10, wherein: The material of the third film layer is doped with at least one of Fe, Cu, Al, Zr, and Ti.

12. The thin film transistor according to any one of claims 1 to 11, wherein: A second gate electrode is also included, wherein the second gate electrode is located on a side of the active layer away from the first gate electrode.

13. A display panel, wherein: A thin film transistor comprising the thin film transistor as claimed in any one of claims 1 to 12.

14. A method for preparing a thin film transistor, comprising: providing a substrate; forming a first pattern layer having oxygen elements on the substrate, and depositing a semiconductor film on the substrate and patterning the semiconductor film to form a second pattern layer, wherein the first pattern layer and the second pattern layer are stacked on the substrate and contact each other; Annealing the first pattern layer and the second pattern layer so that oxygen elements in the first pattern layer diffuse into the second pattern layer, wherein the first pattern layer forms a first film layer after annealing, and the second pattern layer forms a second film layer after annealing, and the second film layer includes a crystalline oxide; Depositing a conductive material film and patterning the conductive material film to form a first gate electrode, wherein the second film layer Located between the first film layer and the first gate electrode.

15. The preparation method according to claim 14, wherein: The step of forming a first pattern layer having oxygen elements on the substrate comprises: depositing a first non-crystalline oxide film, and patterning the first non-crystalline oxide film to obtain the first pattern layer; The first non-crystalline oxide film is deposited in a first oxygen partial pressure environment, and the semiconductor film is deposited in a second oxygen partial pressure environment, and the first oxygen partial pressure is greater than the second oxygen partial pressure.

16. The preparation method according to claim 15, wherein: The first oxygen partial pressure is 30% to 90%, and the second oxygen partial pressure is 10% to 60%.

17. The preparation method according to claim 16, wherein: Also includes: depositing a second non-crystalline oxide thin film, and patterning the second non-crystalline oxide thin film to obtain a third pattern layer, wherein the first pattern layer, the second pattern layer and the third pattern layer are stacked on the substrate, and the second pattern layer is located between the first pattern layer and the third pattern layer and contacts the third pattern layer; and In the process of annealing the first pattern layer and the second pattern layer, the third pattern layer is annealed simultaneously so that the third pattern layer forms a third film layer; The second non-crystalline oxide film is deposited in a third oxygen partial pressure environment, the first oxygen partial pressure is greater than the third oxygen partial pressure, and the third oxygen partial pressure is greater than the second oxygen partial pressure.

18. The preparation method according to claim 17, wherein: The third oxygen partial pressure is 15% to 85%.

19. The preparation method according to claim 14, wherein: The step of forming a first pattern layer having oxygen elements on the substrate comprises: depositing an oxygen-rich oxide film layer, and patterning the first non-crystalline oxide film to obtain the first pattern layer; The second film layer is formed between the first film layer and the substrate; or the first film layer is formed between the second film layer and the substrate, and the orthographic projection of the second film layer on the substrate is within the orthographic projection of the first film layer on the substrate.

20. The preparation method according to any one of claims 14 to 19, wherein Also includes: A conductive material film is deposited, and the conductive material film is patterned to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode.

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