SYSTEM AND METHOD FOR CALCULATING PARITY INFORMATION IN A RAID ARRAY

Abstract

A redundant disk array can contain redundant information to facilitate array reconstruction in the event of a disk failure. A host processor can allocate buffers in an accelerator. Data can be moved into the buffers from one or more storage devices. An accelerator can perform parity calculations necessary to rebuild the array based on data in the buffers, without requiring a host CPU to perform the parity calculations.

Description

PRIORITY

[0001] This application claims priority over the jointly held Indian patent application No. 202311052018, filed on 2 August 2023, the entire contents of which are hereby incorporated by reference for all purposes. AREA OF INVENTION

[0002] The present disclosure relates to systems and methods for calculating parity information in an array of storage devices. BACKGROUND

[0003] In high-density data storage applications, redundant data can be stored to protect against data loss. Furthermore, a data block can be written across multiple drives in so-called strips, and parity information can be stored along with the data. In the event of a drive failure, the parity information can be used to recover the lost data.

[0004] In one of several examples, a high-density storage application can be implemented as a Redundant Array of Independent Disks (RAID), such as RAID-5, without limitation. In one RAID array example, individual hard drives can be partitioned into strips, and consecutive data segments can be stored on different storage devices. In one of several examples, M individual drives, numbered 1 through M, can be partitioned into N strips, with the strips numbered 1 through N. In this example, to calculate parity information for the first strip, a parity calculation can be performed using the data in strip #1 for drives 1 through M-1, and the result can be stored in drive M.

[0005] If a drive fails, the stored parity information can be used to calculate the missing data and prevent data loss. However, this calculation of parity information requires significant processing power from the CPU.

[0006] There is a need for a system and method for calculating parity information in a RAID array that relieves the CPU of the processing burden. SUMMARY

[0007] The examples herein provide a system and a method for calculating parity information in a RAID array, relieving the CPU of the processing overhead.

[0008] According to one of the various aspects, a system can include a central processing unit (CPU), a non-volatile processor memory device coupled to the CPU, and one or more memory devices. The one or more memory devices can include a memory array and a Direct Memory Access (DMA) circuit. The system can include an accelerator processor, non-volatile accelerator memory, and a shared bus, the shared bus being coupled to the CPU, the accelerator processor, the non-volatile accelerator memory, and the one or more memory devices. The CPU can instruct the one or more memory devices to move data between the one or more memory devices and the non-volatile accelerator memory.The CPU can instruct the accelerator processor to perform a parity calculation of the data stored in the non-volatile accelerator memory and write the parity information to one or more storage devices.

[0009] According to one of several aspects, a procedure may include the following operations: allocating a source buffer and a result buffer in an accelerator memory in an accelerator device, moving data from one or more storage devices into the source buffer, issuing an interrupt from the one or more storage devices to a host processor, calculating parity information based on data in the source buffer, writing the parity information to the result buffer in the accelerator memory, and writing the parity information to the one or more storage devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates one of several examples of a RAID array device. Fig. Figure 2 illustrates one of several examples of a system for calculating parity information in a RAID array. Fig. Figure 3 illustrates a method for calculating parity information in a RAID array. DETAILED DESCRIPTION

[0010] Fig. Figure 1 illustrates one of several examples of a RAID array device 100. The RAID array device 100 can have four storage devices 101, 102, 103, and 104. The in Fig. The RAID array shown in Device 100 can have four storage devices, but this is not intended as a limitation. Other examples may include more than four storage devices or fewer than four.

[0011] Storage devices 101, 102, 103, and 104 may be non-volatile storage devices, including, but not limited to, dynamic random access memory (DRAM), non-volatile memory (NVM), embedded non-volatile memory (eNVM), non-volatile memory express (NVMe), or another type of non-volatile memory not explicitly mentioned. Storage devices 101, 102, 103, and 104 may each include a DMA (Direct Memory Access) circuit for moving data to and from the storage device.

[0012] Storage devices 101, 102, 103, and 104 can each be connected to the storage bus 105, which can be a Peripheral Component Interconnect Express (PCIe) bus. The storage bus 105 can be connected to the host processor 108. The host processor 108 can be a central processing unit (CPU) or another device. The host processor 108 can send signals to the storage bus 105 to read data from the storage devices 101, 102, 103, and 104, and can send signals to the storage bus 105 to write data to the storage devices 101, 102, 103, and 104. The storage bus 105 can be a PCIe (Peripheral Component Interconnect Express) bus or another bus type not explicitly specified.

[0013] Storage devices 101, 102, 103, and 104 can be divided into strips. Each strip can contain a predetermined number of bytes within the storage device. The strips within a storage device can contain the same number of bytes or different numbers of bytes. As one of several examples, storage device 101 can be divided into strips 111, 121, 131, and 141; storage device 102 into strips 112, 122, 132, and 142; storage device 103 into strips 113, 123, 133, and 143; and storage device 104 into strips 114, 124, 134, and 144.

[0014] In operation, a data block can be stored across multiple storage devices via strips. In the Fig. In the illustrated example 1, a data block, called Block A, can be divided into parts A1, A2, and A3. The first part, A1, can be stored in storage device 101 in strip 111, the second part, A2, can be stored in storage device 102 in strip 112, and the third part, A3, can be stored in storage device 103 in strip 113.

[0015] In storage device 104, strip 114 can store parity information based on the data stored in strips 111, 112, and 113, with the parity information labeled Ap. In one of several examples, the parity information can be calculated as a bitwise XOR of the data stored in strips 111, 112, and 113. In other examples, the parity information can be calculated using a different logical operation or algorithmic procedure. The parity information can be calculated by the host processor 108. If any of the storage devices 101, 102, 103, or 104 is damaged, the damaged data can be recovered based on the data in the undamaged storage devices.

[0016] In the Fig. In the illustrated example 1, another data block, block B, can be divided into parts B1, B2, and B3. The first part, B1, can be stored in storage device 101 on strip 121, the second part, B2, can be stored in storage device 102 on strip 122, and the third part, B3, can be stored in storage device 104 on strip 124.

[0017] In storage device 103, parity information can be stored on strip 123. This information is based on the data stored in strips 121, 122, and 124 and is labeled Bp. In one of several examples, the parity information can be calculated as a bitwise XOR of the data stored in strips 121, 122, and 124. In other examples, the parity information can be calculated using a different logical operation or algorithmic procedure. The parity information can also be calculated by the host processor 108. If any of the storage devices 101, 102, 103, or 104 is damaged, the damaged data can be recovered based on the data in the undamaged storage devices.

[0018] In the Fig. In the illustrated example 1, another data block, block C, can be divided into parts C1, C2, and C3. The first part, C1, can be stored in storage device 101 at strip 131, the second part, C2, can be stored in storage device 103 at strip 133, and the third part, C3, can be stored in storage device 104 at strip 134.

[0019] Storage device 102 can store strip 132 parity information based on the data stored in strips 131, 133, and 134, where the parity information is labeled Cp. In one of several examples, the parity information can be calculated as a logical XOR of the data stored in strips 131, 133, and 134. In other examples, the parity information can be calculated using a different logical operation or algorithmic procedure. The parity information can be calculated by the host processor 108. If any of the storage devices 101, 102, 103, or 104 is damaged, the damaged data can be recovered based on the data in the undamaged storage devices.

[0020] In the Fig. In the illustrated example 1, another data block, block D, can be divided into parts D1, D2, and D3. The first part, D1, can be stored in storage device 102 at strip 142, the second part, D2, can be stored in storage device 103 at strip 143, and the third part, D3, can be stored in storage device 104 at strip 144, with the data being labeled D3.

[0021] In storage device 101, strip 141 can store parity information based on the data stored in strips 142, 143, and 144, where the parity information is denoted by Dp. In one of several examples, the parity information can be calculated as a logical XOR of the data stored in strips 142, 143, and 144. In other examples, the parity information can be calculated by a different logical operation or algorithmic procedure. The parity information can be calculated by the host processor 108. If any of the storage devices 101, 102, 103, or 104 is damaged, the damaged data can be recovered based on the data in the undamaged storage devices.

[0022] In the Fig. The illustrated example shows the parity information in specific strips in specific storage devices, but this is not intended to be a limitation. The position of the parity information can be located in randomly arranged strips or in a deterministic arrangement.

[0023] Fig. Figure 2 illustrates one of several examples of a System 200 for calculating parity information in a RAID array.

[0024] The CPU 210 can be connected to a shared bus 250. The shared bus 250 can receive data from the CPU 210 and transmit data to one or more circuits connected to the shared bus 250. The CPU 210 can be connected to the processor memory 220. The CPU 210 can write data to and read data from the processor memory 220. The shared bus 250 can be a PCIe bus or another type of shared bus not explicitly mentioned.

[0025] The accelerator memory 230 can be coupled to the shared bus 250. The accelerator memory 230 can be non-volatile memory. The accelerator memory 230 can be dedicated memory hardware or a memory-mapped memory space allocated to a larger device. The shared bus 250 can write data to and read data from the accelerator memory 230. The accelerator processor 240 can receive data from and send data to the shared bus 250. The accelerator memory 230 and the accelerator processor 240 can include an accelerator device.

[0026] The storage device 281 can be a non-volatile storage device, which may include, among other things, DRAM, NVM, eNVM, NVMe, or another type of non-volatile memory not explicitly mentioned. The storage device 281 can be connected to the shared bus 250. The shared bus 250 can facilitate data transfer to and from the storage device 281. The CPU 210 can transfer data to the storage device 281 over the shared bus 250, and the CPU 210 can receive data from the storage device 281 over the shared bus 250. The storage device 281 can include a DMA circuit 286. The DMA circuit 286 can control data reads from the storage device 281. In particular, data read from the storage device 281 can be moved to a destination address provided by a read instruction received from the storage device 281.The CPU 210 can transfer data to the storage device 281 via the shared bus 250, and the CPU 210 can receive data from the storage device 281 via the shared bus 250. The storage device 281 can be divided into strips, as described in section 2. Fig. 1 illustrated and described.

[0027] The storage device 281 can include a DMA circuit 286. The CPU 210 can send an instruction to the storage device 281 to instruct the DMA circuit 286 to read data from or write data to the storage device 281. Based on the address sent in the instruction, data can be written to or read from the processor memory 220 or the accelerator memory 230.

[0028] The storage device 282 can be a non-volatile storage device that includes DRAM, NVM, eNVM, NVMe, or another type of non-volatile memory not explicitly mentioned. The storage device 282 can be coupled to the shared bus 250. The shared bus 250 can facilitate data transfer to and from the storage device 282. The CPU 210 can transfer data to the storage device 282 over the shared bus 250, and the CPU 210 can receive data from the storage device 282 over the shared bus 250. The storage device 282 can be divided into strips, as described in relation to Fig. 1 illustrated and described.

[0029] The storage device 282 can include a DMA circuit 287. The CPU 210 can send an instruction to the storage device 282 to instruct the DMA circuit 287 to read data from or write data to the storage device 282. Based on the address sent in the instruction, data can be written to or read from the processor memory 220 or the accelerator memory 230.

[0030] The storage device 283 can be a non-volatile storage device that includes DRAM, NVM, eNVM, NVMe, or another type of non-volatile memory not explicitly mentioned. The storage device 283 can be coupled to the shared bus 250. The shared bus 250 can facilitate data transfer to and from the storage device 283. The CPU 210 can transfer data to the storage device 283 over the shared bus 250, and the CPU 210 can receive data from the storage device 283 over the shared bus 250. The storage device 283 can be divided into strips, as described in relation to Fig. 1 illustrated and described.

[0031] The storage device 283 can include a DMA circuit 288. The CPU 210 can send an instruction to the storage device 283 to instruct the DMA circuit 288 to read data from or write data to the storage device 283. Based on the address sent in the instruction, data can be written to or read from the processor memory 220 or the accelerator memory 230.

[0032] The storage device 284 can be a non-volatile storage device that includes DRAM, NVM, eNVM, NVMe, or another type of non-volatile memory not explicitly mentioned. The storage device 284 can be coupled to the shared bus 250. The shared bus 250 can facilitate data transfer to and from the storage device 284. The CPU 210 can transfer data to the storage device 284 over the shared bus 250, and the CPU 210 can receive data from the storage device 284 over the shared bus 250. The storage device 284 can be divided into strips, as described in relation to... Fig. 1 illustrated and described.

[0033] The storage device 284 can include a DMA circuit 289. The CPU 210 can send an instruction to the storage device 284 to instruct the DMA circuit 289 to read data from or write data to the storage device 284. Based on the address sent in the instruction, data can be written to or read from the processor memory 220 or the accelerator memory 230.

[0034] The storage devices 281, 282, 283, and 284 can form a RAID array 280. This is in Fig. The illustrated example can form a RAID 5 array, but this should not be interpreted as a limitation. Storage elements 281, 282, 283, and 284 can represent a different type of storage array.

[0035] During operation, the system can calculate 200 parity information in RAID array 280 and recover damaged storage devices in RAID array 280. Data can be read from one or more of the storage devices 281, 282, 283, and 284 and stored in a source buffer in accelerator memory 230, based on an address provided in the read instruction issued by CPU 210 as part of a recovery routine. The source buffer can be a memory-mapped portion of a device or a dedicated memory circuit. DMA circuit 286 can move data from storage device 281 to a predefined location in the source buffer of accelerator memory 230. DMA circuit 287 can move data from storage device 282 to a predefined source buffer location in accelerator memory 230.DMA circuit 288 can move data from storage devices 283 to a predefined source buffer position in accelerator memory 230. DMA circuit 289 can move data from storage devices 284 to a predefined source buffer position in accelerator memory 230, where the predefined source buffer position is defined in the read instruction provided by CPU 210. In this way, CPU 210 and processor memory 220 can store data from one or more storage devices 281, 282, 283, and 284 for the recovery routine. The resources of CPU 210 can be reserved for other operations. Data reads from the one or more storage devices 281, 282, 283, and 284 can involve one or more strips of storage devices 281, 282, 283, and 284.

[0036] After the data transfer of the read data from one or more storage devices 281, 282, 283, and 284 is complete, an interrupt can be issued to the CPU 210 by the respective one or more storage devices 281, 282, 283, and 284. The CPU 210 can issue an instruction to the accelerator processor 240 via the shared bus 250, instructing the accelerator processor 240 to perform a parity calculation of the data stored at the position in the accelerator memory 230 where the read data moved from the one or more storage devices 281, 282, 283, and 284 was stored. The accelerator processor 240 can directly access the data in the accelerator memory 230 without requiring instructions or control from the CPU 210. After the parity information has been calculated, the parity information can be stored in a result buffer in the acceleration memory 230.The result buffer can be a memory-mapped area or a dedicated memory circuit. After the parity calculation is complete, the parity information stored in the accelerator memory 230 can be written to one of the storage devices 281, 282, 283, and 284 by one of the DMA circuits 286, 287, 288, and 289. In this way, parity information for a RAID array can be calculated without using the CPU 210 to move data between the storage devices 281, 282, 283, 284, and the accelerator memory 230.

[0037] Fig. Figure 3 illustrates a procedure 300 for calculating parity information in a RAID array that the System 200 can use.

[0038] In Operation 310, a host processor can allocate source and result buffers in the memory-mapped area of ​​the host belonging to the accelerator. The host processor can be a CPU or another processing device. The buffers in the accelerator memory can be memory-mapped input and output memories. The host processor can be connected to the accelerator memory via a PCIe bus or another unspecified bus architecture.

[0039] In operation 320, the host processor can issue a command to read data from one or more storage devices into the source buffer. The data movement can be performed by a DMA circuit in the respective storage devices.

[0040] In Operation 330, one or more storage devices can send an interrupt to the host processor when data transfer is complete. In Operation 340, the host processor can issue an instruction that directs the accelerator processor to calculate parity information about the data stored in the source buffers.

[0041] In operation 350, the accelerator processor can perform parity calculations on the data in the source buffers. In one of several examples, the parity information is calculated bit by bit using an exclusive OR (XOR) operation on the data shifted into the source buffers. In operation 360, the accelerator processor can write the parity result to the result buffer.

[0042] In Operation 370, the host can issue a command to move the parity result from the result buffer to one or more storage devices. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] IN 202311052018

[0001]

Claims

[1] System that features: a central processing unit (CPU); a non-volatile processor memory device coupled to the CPU; one or more storage devices, wherein the one or more storage devices comprise a memory array and a Direct Memory Access (DMA) circuit; an acceleration processor; a non-volatile acceleration memory; a shared bus, wherein the shared bus is coupled to the CPU, the accelerator processor, the non-volatile accelerator memory and the one or more storage devices, and wherein the CPU instructs the one or more storage devices to move data between the one or more storage devices and the non-volatile accelerator memory, and wherein the CPU instructs the accelerator processor to perform a parity calculation on the data stored in the non-volatile accelerator memory and to write the parity information to the one or more storage devices. [2] System according to claim 1, wherein the one or more storage devices are divided into one or more strips, the respective strips having a predetermined number of bytes. [3] System according to claim 2, wherein the strips comprise parts of data blocks. [4] System according to one of claims 2 to 3, wherein the strips have parity information. [5] System according to any one of claims 1 to 4, wherein the non-volatile acceleration memory comprises a source buffer and a result buffer. [6] System according to claim 5, wherein the CPU instructs the DMA circuit in one or more storage devices to move data between the one or more storage devices and the source buffer within the non-volatile accelerator memory. [7] System according to one of claims 5 to 6, wherein the CPU instructs the accelerator processor to write the parity information to the result buffer within the non-volatile accelerator memory. [8] System according to any one of claims 1 to 7, wherein the system is provided for reconstructing the storage array based on the data stored in the one or more storage devices. [9] Method which features: Assigning a source buffer and a result buffer to an acceleration buffer in an acceleration device; Moving data from one or more storage devices to the source buffer; Outputting an interrupt from one or more memory devices to a host processor; Calculating parity information based on the data in the source buffer; Writing the parity information to the result buffer in the accelerator memory, and Writing the parity information to one or more storage devices. [10] Method according to claim 9, wherein the one or more storage devices are divided into one or more strips, each strip having a predetermined number of bytes. [11] Method according to claim 10, wherein the strips comprise parts of data blocks. [12] Method according to any one of claims 10 to 11, wherein the strips have parity information. [13] Method according to any one of claims 9 to 12, wherein the transfer of data from one or more storage devices to the source buffer is carried out by a corresponding DMA circuit of the one or more storage devices. [14] Method according to any one of claims 9 to 13, wherein the writing of the parity information to the one or more storage devices is performed by a respective DMA circuit of the one or more storage devices. [15] Method according to any one of claims 9 to 14, wherein the calculation of the parity information is performed on the basis of the data in the source buffer by an acceleration processor.

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