Display field and display device

Abstract

The present application discloses a display panel and a display device and relates to the technical field of display technology. The display panel comprises: a base substrate, a plurality of pixel circuits, a plurality of light-emitting components, a plurality of data signal lines, and a plurality of redundant signal lines. A redundant signal line may comprise a first line segment connected to a data signal line. The first line segment may function as part of a fan-out line that is electrically connected to the data signal line.Since the redundant signal line is located within the display area, the portion of the fan-out line electrically connected to the data signal line can also be located within the display area. This means that the remaining portion of the fan-out line occupies less space in the non-display area than the first section, effectively reducing the width of the area where the fan-out line is located. This significantly improves the screen-to-body ratio of a display device equipped with a display panel, resulting in excellent display performance.

Description

[0001] The present application claims priority over the Chinese patent application with file number 202310974470.7 and titled “DISPLAY FIELD AND DISPLAY DEVICE”, which was filed on August 3, 2023, and the entire contents of which are hereby incorporated by reference. TECHNICAL AREA

[0002] The present application relates to the field of display technologies, in particular a display field and a display device. STATE OF THE ART

[0003] Currently, screens (also called display panels) in display devices are becoming increasingly larger and offer full-screen display to provide users with a better visual experience.

[0004] The display device can generally comprise a display array and a driver chip. The display array includes a display area and a non-display area. The display array can include: a plurality of subpixels and a plurality of data signal lines arranged in the display area, and a plurality of fan-out lines arranged in the non-display area. Each of the plurality of data signal lines can be electrically connected to a column of subpixels, and each of the plurality of data signal lines can be electrically connected to the driver chip via one of the plurality of fan-out lines. Thus, the driver chip can transmit a control signal via the fan-out lines to the data signal lines so that the display array can display images.

[0005] However, the fan-out lines take up a lot of space in the display area, so the width of the fan-out line area in the non-display area is large, which results in a small screen ratio of the display device and impairs the display quality of the display device. REVELATION OF THE INVENTION

[0006] Embodiments of the present application provide a display field and a display device with which the problem of the low screen-to-body ratio of the display device in the prior art can be solved. The technical solutions are as follows: According to a first aspect, a display field is provided which has a display area, the display field comprising: a base substrate; a plurality of pixel circuits arranged in an array on one side of the base substrate, wherein the plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of dummy pixel circuits; a plurality of light-emitting components on a side of the plurality of pixe circuits facing away from the base substrate, wherein the plurality of light-emitting components is electrically connected in a one-to-one correspondence to the plurality of first pixe circuits; and a multitude of data signal lines and a multitude of redundant signal lines arranged in the display area, wherein one direction of the data signal lines coincides with one direction of the redundant signal lines; wherein one of the data signal lines is connected to a column of the first pixel circuits, one of the redundant signal lines is arranged in the area of ​​a column of the dummy pixel circuits, and at least a part of the plurality of redundant signal lines is first redundant signal lines, wherein one of the first redundant signal lines comprises a first line section that is connected to one of the data signal lines.

[0007] Optionally, the display field also includes a multitude of auxiliary signal lines in the display area, wherein one direction of the auxiliary signal lines intersects the direction of the redundant signal lines. wherein one of the auxiliary signal lines is arranged in the area of ​​a series of pixel circuits and at least a part of the plurality of auxiliary signal lines is a first auxiliary signal line, wherein one of the first auxiliary signal lines comprises a second line section, wherein one end of the second line section is electrically connected to one of the data signal lines and the other end of the second line section is electrically connected to an end of the first line section.

[0008] Optionally, one of the first redundant signal lines further comprises a redundant conductor body that is separate from the first conductor section, and one of the first auxiliary signal lines further comprises an auxiliary conductor body that is separate from the second conductor section. wherein the redundant conductor body is electrically connected to the auxiliary conductor body at a crossing between the redundant conductor body and the auxiliary conductor body.

[0009] Optionally, a portion of the multiple redundant signal lines is the first redundant signal lines and the other portion of the multiple redundant signal lines is the second redundant signal lines, wherein the first line segment is not arranged within the second redundant signal lines and the second redundant signal line is electrically connected to the auxiliary line body at a junction between the second redundant signal line and the auxiliary line body; and / or wherein a portion of the plurality of auxiliary signal lines is the first auxiliary signal lines and the other portion of the plurality of auxiliary signal lines is the second auxiliary signal lines, wherein the second line section is not arranged in the second auxiliary signal lines and the second auxiliary signal line is electrically connected to the redundant line body at a crossing between the second auxiliary signal line and the redundant line body.

[0010] Optionally, in a case where the display field simultaneously includes the second redundant signal lines and the second auxiliary signal lines, the second redundant signal line is electrically connected to the second auxiliary signal line at a crossing between the second redundant signal line and the second auxiliary signal line.

[0011] Optionally, the display field also includes a first power signal line, wherein the second redundant signal lines are electrically connected to the first power signal line and / or the second auxiliary signal lines are electrically connected to the first power signal line.

[0012] Optionally, the light-emitting device comprises an anode, a light-emitting layer, and a cathode layer arranged one above the other, with the anode being closer to the base substrate than the cathode layer. wherein the first pixel circuit is electrically connected to the anode in the corresponding light-emitting component and the cathode layer is electrically connected to the first current signal line.

[0013] Optionally, the display field also has a non-display area surrounding the display area; wherein the display field further comprises a plurality of connecting lines in the non-display area which are electrically connected in a one-to-one correspondence to the plurality of data signal lines, wherein a part of the plurality of connecting lines is electrically connected to corresponding data signal lines via the first line section and the second line section, and wherein the other part of the plurality of connecting lines is directly electrically connected to corresponding data signal lines; the multitude of connecting lines are designed in such a way that they can be connected to and linked with a driver assembly.

[0014] Optionally, the redundant signal lines and the data signal lines are arranged in the same layer and made of the same material, or the redundant signal lines and the auxiliary signal lines are arranged in different layers.

[0015] Optionally, the display field further includes a GOA (Gate Driver On Array) circuit, wherein the light-emitting component comprises an anode, a light-emitting layer and a cathode layer arranged one above the other, with the anode being closer to the base substrate than the cathode layer. where an orthographic projection of the GOA circuit on the base substrate overlaps with an orthographic projection of the anode on the base substrate.

[0016] Optionally, the display area includes a first display sub-area, a second display sub-area, and a third display sub-area, with the second display sub-area being positioned between the first display sub-area and the third display sub-area. wherein the multitude of pixel circuits are arranged in the first display sub-area and in the second display sub-area and are arranged outside the third display sub-area; at least part of the GOA circuit is arranged in the third display sub-area; and wherein the pixel circuits arranged in the first display sub-area comprise the first pixel circuits and the dummy pixel circuits from the plurality of pixel circuits, wherein the pixel circuits arranged in the second display sub-area are the first pixel circuits from the plurality of pixel circuits, wherein a part of the first pixel circuits located in the second display sub-area is electrically connected to the light-emitting components in the second display sub-area, and the other part of the first pixel circuits located in the second display sub-area is electrically connected to the light-emitting components in the third display sub-area.

[0017] Optionally, in the first display sub-area, a large number of columns of first pixel circuits and a large number of columns of dummy pixel circuits are arranged in an offset pattern.

[0018] Optionally, N columns of first pixel circuits are arranged between two adjacent columns of dummy pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6.

[0019] Optionally, the density of light-emitting components in the first display sub-area corresponds to the density of light-emitting components in the second display sub-area.

[0020] Optionally, a multitude of columns of first pixel circuits in the second display sub-area are each electrically connected to anodes of a multitude of columns of light-emitting components in the second display sub-area and in the third display sub-area.

[0021] Optionally, the display field also includes a variety of transparent connecting lines in the second and third display sub-areas. wherein the anodes of at least some of the light-emitting components in the second display sub-area and in the third display sub-area are electrically connected to corresponding first pixel circuits via the transparent connecting lines.

[0022] Optionally, the display field also includes a variety of auxiliary signal lines, with some of the auxiliary signal lines being arranged in the second display sub-area and the third display sub-area; wherein the transparent connecting line comprises a first transparent line section and a second transparent line section which are connected to each other, wherein a direction of travel of the first transparent line section coincides with a direction of travel of the auxiliary signal line and a direction of travel of the second transparent line section intersects the direction of travel of the auxiliary signal line; wherein an orthographic projection of the first transparent conductor section on the base substrate does not overlap with an orthographic projection of the auxiliary signal line on the base substrate and an orthographic projection of the second transparent conductor section overlaps with the orthographic projection of the auxiliary signal line on the base substrate in at least part of the transparent connecting lines.

[0023] Optionally, the ratio of the overlapping area of ​​an orthographic projection of at least one transparent connecting line on the base substrate and an orthographic projection of at least one auxiliary signal line on the base substrate to the total area of ​​the orthographic projection of the at least one transparent connecting line on the base substrate is less than or equal to 30%.

[0024] Optionally, an orthographic projection of each of the anodes of at least part of the light-emitting components in the second display sub-area and in the third display sub-area on the base substrate overlaps with orthographic projections of at least two transparent signal lines on the base substrate.

[0025] According to another aspect, a display device is provided, characterized in that the display device comprises: a power supply and a display field which is electrically connected to the power supply, wherein the display field is the display field mentioned above.

[0026] The technical solutions according to the embodiments of the present application have at least the following advantageous effects: A display array comprises a base substrate, a variety of pixel circuits, a variety of light-emitting components, a variety of data signal lines, and a variety of redundant signal lines. A redundant signal line may include a first line segment connected to a data signal line. This first line segment may function as part of a fan-out line electrically connected to the data signal line. Because the redundant signal line is located within the display area, the portion (i.e.,The first section of the fan-out line, which is electrically connected to the data signal line, can be positioned within the display area. This allows the remaining portion of the fan-out line to occupy less space in the non-display area than the first section, effectively reducing the width of the area containing the fan-out line. This effectively improves the screen-to-body ratio of a display device equipped with a display panel, resulting in excellent display performance. Furthermore, the data signal lines and redundant signal lines can be arranged in the same conductive pattern, which can be evenly distributed throughout the display area.If part of the first redundant signal lines in the area of ​​a column of dummy pixel circuits acts as part of the fan-out line in the display area, it can be ensured that the conductive layer patterns in the display field are evenly distributed in the display area, provided that the part of the fan-out line can be distributed in the display area, so that the probability of color distortion in the display field is effectively reduced and the display effects of the display field are excellent. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To clarify the technical solutions in the embodiments of the present application, the drawings required to illustrate these embodiments are briefly described below. It is understood that the drawings in the following description show only some embodiments of the present application and that a person skilled in the art in the relevant technical field can derive further drawings from these drawings without any inventive effort. Fig. 1 is a top view of a display field according to an embodiment of the present application; Fig. 2 is a locally enlarged representation of the display field in Fig. 1 to A1; Fig. Figure 3 is a schematic structure diagram of the film layers of the display field in Fig. 2 to B-B'; Fig. Figure 4 is a schematic diagram of the connection between a plurality of light-emitting components and a plurality of first pixel circuits according to an embodiment of the present application; Fig. 5 is a local top view of another display field according to an embodiment of the present application; Fig. Figure 6 is a schematic structure diagram of the film layers of the display field in Fig. 5 to C-C'; Fig. 7 is a top view of another display field according to an embodiment of the present application; Fig. Figure 8 is a schematic distribution diagram of redundant signal lines and auxiliary signal lines according to an embodiment of the present application; Fig. Figure 9 is a schematic structure diagram of the film layers of the display field in Fig. 8 to D-D'; Fig. 10 is a schematic structure diagram of film layers of a display field in a display area according to an embodiment of the present application; Fig. 11 is a local top view of a display field according to an embodiment of the present application; Fig. 12 is a top view of a display field according to an embodiment of the present application; Fig. 13 is a top view of another display field according to an embodiment of the present application; Fig. 14 is a locally enlarged representation of the display field in Fig. 12 on A2; Fig. Figure 15 is a further schematic diagram of the connection between a plurality of light-emitting components and a plurality of first pixel circuits according to an embodiment of the present application; Fig. Figure 16 is a schematic diagram of the electrical connection between light-emitting components and the first pixel circuits at A3 in the display field in Fig. 12; Fig. Figure 17 is a schematic diagram of the connection between anodes of light-emitting devices and first pixel circuits according to an embodiment of the present application; Fig. Figure 18 is a schematic distribution diagram of a transparent connecting line and an auxiliary signal line according to an embodiment of the present application; Fig. Figure 19 is a schematic diagram of a relative positional relationship between an anode of a light-emitting device and transparent signal lines according to an embodiment of the present application; and Fig. Figure 20 is a schematic structure diagram of film layers of the display field in Fig. 19 on E-E'. SPECIFIC EXECUTION FORMS

[0028] In order to clarify the tasks, technical solutions and advantages of the present application, the embodiments of the present application are described in more detail below with reference to the drawings.

[0029] With reference to Fig. 1, Fig. 2 and Fig. 3 is Fig. 1 a top view of a display field according to an embodiment of the present application, Fig. 2 is a locally enlarged representation of the display field in Fig. 1 to A1 and Fig. Figure 3 is a schematic structure diagram of the film layers of the display field in Fig. 2 an B-B'. The display field 000 can have a display area 00a and a non-display area 00b located around the display area 00a. The display field 000 can comprise a base substrate 100, a plurality of pixel circuits 200, a plurality of light-emitting components 300, a plurality of data signal lines D10, and a plurality of redundant signal lines D20.

[0030] The plurality of pixel circuits 200 in the display field 000 can be arranged in an array on one side of the base substrate 100 and be located in the display area 00a. The plurality of pixel circuits 200 can comprise a plurality of first pixel circuits 201 and a plurality of dummy pixel circuits 202. The plurality of first pixel circuits 201 can be arranged in a plurality of columns. The plurality of dummy pixel circuits 202 can also be arranged in a plurality of columns. The plurality of columns of the dummy pixel circuits 202 can be distributed among the plurality of columns of the first pixel circuits 201. The number of columns of the first pixel circuits 201 is greater than the number of columns of the dummy pixel circuits 202. Furthermore, at least two columns of first pixel circuits 201 can be arranged between two adjacent columns of dummy pixel circuits 202. It should be noted that in Fig. 2. The light-emitting components 300 in the display field 000 are not shown in order to make the distribution relationship of the multitude of pixel circuits 200 in the display field 000 clearer. Furthermore, in Fig. 2 each box P1 represents a first pixel circuit 201, and each box P2 represents a dummy pixel circuit 202.

[0031] The multitude of light-emitting components 300 in the display field 000 can be arranged on a side of the multitude of pixel circuits 200 facing away from the base substrate 100 and be located in the display area 00a. To clarify the connection between the multitude of light-emitting components 300 and the multitude of first pixel circuits 201, see Fig. Reference is made to Figure 4, which is a schematic diagram of the connection between a plurality of light-emitting components and a plurality of first pixel circuits according to an embodiment of the present application. The plurality of light-emitting components 300 can be electrically connected to the plurality of first pixel circuits 201 in a one-to-one correspondence. Each of the plurality of first pixel circuits 201 is configured such that it controls a corresponding light-emitting component 300 to emit light, so that the display area 00a of the display field 00 can display a corresponding image. It should be noted that the dummy pixel circuit 202 must be isolated from the light-emitting component 300. That is, the dummy pixel circuit 202 is not electrically connected to the light-emitting component 300.

[0032] The multiple data signal lines D10 and the multiple redundant signal lines D20 in display field 000 can be arranged in display area 00a. The direction of the data signal lines D10 can coincide with the direction of the redundant signal lines D20.

[0033] The multitude of data signal lines D1 can correspond one-to-one to the multitude of columns of the first pixel circuits 201. Each of the multitude of data signal lines D10 can be arranged in the area of ​​a corresponding column of first pixel circuits 201 and electrically connected to the first pixel circuits 201 in the corresponding column of first pixel circuits 201. Furthermore, the data signal line D10 can be isolated from the dummy pixel circuit 202. That is, the data signal line D10 is not electrically connected to the dummy pixel circuit 202.

[0034] The plurality of redundant signal lines D20 can correspond one-to-one to the plurality of columns of the dummy pixel circuits 202. Each of the plurality of redundant signal lines D20 can be located in the area of ​​a corresponding column of dummy pixel circuits 202 and must be isolated from the dummy pixel circuits in the corresponding column of dummy pixel circuits 202. That is, the redundant signal line D20 is not electrically connected to the dummy pixel circuit 202.

[0035] It should be noted that the multitude of first pixel circuits 201 and the multitude of dummy pixel circuits 202 in the display field 000 are formed simultaneously by the same process, and that a data signal line D10, which is electrically connected to a column of first pixel circuits 201, is formed simultaneously with the formation of the multitude of first pixel circuits 201. Thus, a redundant signal line D20 is formed simultaneously in the area of ​​a column of dummy pixel circuits 202 during the process of forming the multitude of dummy pixel circuits 202. However, the redundant signal line D20 must be isolated from the dummy pixel circuits in the column of dummy pixel circuits 202.

[0036] In the present application, at least some of the plurality of redundant signal lines D20 in display area 000 can be first redundant signal lines D201. A first redundant signal line D201 can comprise a first line section D21 connected to a data signal line D10. The first line section D21 can function as part of a fan-out line electrically connected to the data signal line D10. Since the redundant signal line D20 is located in display area 00a, the part (i.e.,The first conductor section D21 in the fan-out line, which is electrically connected to the data signal line D10, is arranged in the display area 00a, so that the other part of the fan-out line occupies less space in the non-display area 00b than the first conductor section D21, and the width of the area in which the fan-out line is arranged in the non-display area 00b is effectively reduced. In this way, the screen ratio of a display device equipped with display field 00 is effectively improved, so that the display effects of the display device are excellent.

[0037] It should be noted that in the technology in question, an additional signal line, electrically connected to the data signal line, can be located between two adjacent columns of subpixels, and this signal line can function as part of the fan-out line in the display area. However, some areas of the display area require signal lines, while others do not. Consequently, the conductive patterns used to form the signal lines in the display area are not evenly distributed, making the display area susceptible to poor display results such as color distortion.

[0038] In the embodiment of the present application, the data signal lines D10 and the redundant signal lines D20 in the display field 000 are arranged in the same layer and made of the same material. That is, the data signal lines D10 and the redundant signal lines D20 are formed by a single structuring process. This means that the data signal lines D10 and the redundant signal lines D20 in the display field 000 can be located in the same conductive pattern. Since the plurality of columns of the dummy pixel circuits 202 is distributed within the plurality of columns of the first pixel circuits 201, the plurality of redundant signal lines D20 in the display field 000 is also distributed within the plurality of data signal lines D10. Furthermore, the conductive pattern comprising the data signal lines D10 and the redundant signal lines D20 can be evenly distributed within the display area 00a.If part of the first redundant signal lines D201 in the area of ​​a column of dummy pixel circuits 202 functions as part of the fan-out line in the display area 00a, it can be ensured that the conductive layer patterns in the display field 000 are evenly distributed in the display area 00a, provided that the part of the fan-out line in the display area 00a can be distributed so that the probability of color distortion in the display field 000 is effectively reduced and the display effects of the display field 000 are excellent.

[0039] In summary, the display field according to the embodiment of the present application comprises a base substrate, a plurality of pixel circuits, a plurality of light-emitting components, a plurality of data signal lines, and a plurality of redundant signal lines. A redundant signal line may comprise a first line segment connected to a data signal line. The first line segment may function as part of a fan-out line electrically connected to the data signal line. Since the redundant signal line is located in the display area, the part (i.e.,The first section of the fan-out line, which is electrically connected to the data signal line, can be positioned within the display area. This allows the remaining portion of the fan-out line to occupy less space in the non-display area than the first section, thus efficiently reducing the width of the area occupied by the fan-out line within the non-display area. This effectively improves the screen-to-body ratio of a display device equipped with a display panel, resulting in excellent display performance. Furthermore, the multiple data signal lines and redundant signal lines can be arranged in the same conductive pattern. This conductive pattern, encompassing both the data signal lines and the redundant signal lines, can be evenly distributed throughout the display area.If part of the first redundant signal lines in the area of ​​a column of dummy pixel circuits acts as part of the fan-out line in the display area, it can be ensured that the conductive layer patterns in the display field are evenly distributed in the display area, provided that the part of the fan-out line can be distributed in the display area, so that the probability of color distortion in the display field is effectively reduced and the display effects of the display field are excellent.

[0040] In the embodiment of the present application, as in Fig. 5 shown, is Fig. 5. A local top view of another display field according to an embodiment of the present application. The display field 000 further comprises a plurality of gate lines G10. The orientation of the gate lines G10 can intersect the orientation of the data signal lines D10. For example, the orientation of the gate lines G10 can be perpendicular to the orientation of the data signal lines D10.

[0041] The plurality of pixel circuits 200 in the display field 000 can furthermore be arranged in a plurality of rows. The plurality of rows of pixel circuits 200 can correspond one-to-one to the plurality of gate lines G10. Each of the plurality of gate lines G10 can be arranged in the area of ​​a corresponding row of pixel circuits 200. Each of the plurality of gate lines G10 can be electrically connected to the first pixel circuits 201 in the corresponding row of pixel circuits 200. In addition, the gate line G10 can be isolated from the dummy pixel circuit 202. That is, the gate line G10 is not electrically connected to the dummy pixel circuit 202.

[0042] Optionally, the display field can be set to 000, as in Fig. Figure 5 shows that the system also includes a multitude of auxiliary signal lines G20 in the display area 00a. The direction of the auxiliary signal lines G20 can intersect the direction of the redundant signal lines D20. For example, the direction of the auxiliary signal lines G20 can be perpendicular to the direction of the redundant signal lines D20.

[0043] In the present application, the orientation of the auxiliary signal lines G20 can be identical to that of the gate lines G10. It should be noted that, due to the high density of the gate lines G10 in display field 000, the auxiliary signal lines G20 and the gate lines G10 must be arranged in different layers, even if the orientation of the auxiliary signal lines G20 is identical to that of the gate lines G10. That is, the conductive pattern of the auxiliary signal lines G20 and the conductive pattern of the gate lines G10 are different conductive patterns, and an insulating layer is arranged between the conductive pattern of the auxiliary signal lines G20 and the conductive pattern of the gate lines G10.

[0044] The auxiliary signal lines G20 and the redundant signal lines D20 are arranged in different layers. That is, the conductive patterns of the auxiliary signal lines G20 and the conductive patterns of the redundant signal lines D20 are different, and an insulating layer is placed between the conductive patterns of the auxiliary signal lines G20 and the conductive patterns of the redundant signal lines D20. This ensures that no short circuit occurs between the auxiliary signal lines G20 and the data signal lines D10, and also no short circuit occurs between the gate lines G10 and the data signal lines D10.

[0045] The multitude of auxiliary signal lines G20 in the display field 000 can correspond one-to-one to the multitude of rows of pixel circuits 200. Each of the multitude of auxiliary signal lines G20 can be arranged within the area of ​​a corresponding row of pixel circuits 200 and be isolated from the pixel circuits in the corresponding row of pixel circuits 200. That is, the auxiliary signal lines G20 are not electrically connected to the pixel signal circuits 200.

[0046] In the present application, at least some of the plurality of auxiliary signal lines G20 are first auxiliary signal lines G201. An auxiliary signal line G20 may include a second line section G21. One end of the second line section G21 may be electrically connected to a data signal line D10. Another end of the second line section G21 may be electrically connected to an end of the first line section D21. In this case, the portion of the fan-out line connected to the data signal line D10 in the display area 00a may include the second line section G21 and the first line section D21. After a plurality of fan-out lines in the display area is bonded and connected to a driver chip, a drive signal may sequentially transmit a data signal through the portion of the fan-out line in the non-display area 00b, the first line section D21, and the second line section G21 to the data signal line D10.

[0047] Since an auxiliary signal line G20 is arranged in each row of pixel circuits 200, the conductive patterns comprising the multitude of auxiliary signal lines G20 can be evenly distributed in display area 00a. The conductive patterns comprising the multitude of redundant signal lines D20 are also evenly distributed in display area 00a. If a portion of the auxiliary signal lines G20 and a portion of the redundant signal lines D20 function as part of the fan-out line in display area 00a, it can be ensured that the conductive layer patterns in display area 000 are evenly distributed in display area 00a, provided that the portion of the fan-out line can be distributed in display area 00a, thus further reducing the probability of color distortion in display area 000.

[0048] In one embodiment of the present application, as in Fig. 6 shown, is Fig. 6 a schematic structure diagram of film layers of the display field in Fig. 5 an C-C'. Since an insulating layer 001 is arranged between the conductive pattern of the data signal lines D10 and the conductive pattern of the auxiliary signal lines G20, a first via V1 and a second via V2, penetrating the insulating layer 001, must be provided in the display field 000, so that one end of the second conductor section G21 in the first auxiliary signal line G201 can overlap with the data signal line D10 through the first via V1, and the other end of the second conductor section G21 in the first auxiliary signal line G201 can overlap with one end of the first conductor section G21 in the first redundant signal line D201 through the second via V2.

[0049] It should be noted that no control signal is loaded onto portions of the redundant signal lines D20 that do not belong to the first line sections D21, so these portions are in a suspended state. While these portions of the redundant signal lines D20 are in a suspended state, they interfere with a gate-scan signal loaded onto the gate line G10 that crosses them. Similarly, no control signal is loaded onto portions of the auxiliary signal lines G20 that do not belong to the second line sections G21, so these portions are also in a suspended state.If the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 are in the suspended state, these parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 interfere with a data signal that is loaded onto the data signal line D10, which crosses the parts.

[0050] Therefore, in the embodiments of the present application, the parts of the redundant signal lines D20 that do not belong to the first line sections D21 and the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 must be further processed to ensure that these signal lines do not interfere with the signals loaded onto other signal lines.

[0051] Fig. Figure 7 is a top view of a further display field according to an embodiment of the present application. The display field 000 may further comprise a first current signal line 400 in the non-display area 00b. The first current signal line 400 may be a low-level current signal line (i.e., a VSS current signal line). The first current signal line 400 may be a ring-shaped current signal line.

[0052] The portions of the redundant signal lines D20 that do not belong to the first line sections D21 may be electrically connected to the first power signal line 400, and / or the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21 may be electrically connected to the first power signal line 400. It should be noted that Fig. 7 illustrates the embodiment by means of an example in which the parts of the redundant signal lines D20 that do not belong to the first line sections D21 and the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 are electrically connected to the first current signal line 400.

[0053] Since a VSS signal with a fixed potential is applied to the first power signal line 400, the VSS signal with a fixed potential can also be applied to the portions of the redundant signal lines D20 that do not belong to the first line sections D21, provided that these portions are electrically connected to the first power signal line 400. The VSS signal with a fixed potential can also be applied to the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21, provided that these portions are electrically connected to the first power signal line 400.In this way, it can be ensured that the parts of the redundant signal lines D20 that do not belong to the first line sections D21, and the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21, are no longer in the suspended state, so that the parts of the redundant signal lines D20 that do not belong to the first line sections D21 do not interfere with the gate line G10, and the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 do not interfere with the data line D1.

[0054] Optionally, the portions of the redundant signal lines D20 that do not belong to the first line sections D21 can be electrically connected to the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21. As long as one of the portions of the redundant signal lines D20 that do not belong to the first line sections D21 and one of the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21 is connected to the first power signal line 400, the first power signal line 400 can supply a VSS signal to the portions of the redundant signal lines D20 that are not the first line sections D21 and to the portions of the auxiliary signal lines G20 that are not the second line sections G21.

[0055] Fig. Figure 8 is a schematic distribution diagram of redundant signal lines and auxiliary signal lines according to an embodiment of the present application. In addition to the first line section D21, a first redundant signal line D200 may further comprise a redundant line body D22, which is separated from the first line section D21. For example, a first partition U1 is arranged between the first line section D21 and the redundant line body D22 in the first redundant signal line D201, and the first line section D21 may be isolated from the redundant line body D22 by the first partition U1. In addition to the second line section G21, a first auxiliary signal line G201 may further comprise an auxiliary body G22, which is separated from the second line section G21.For example, a second partition U2 is arranged between the second conductor section G21 and the auxiliary conductor body G22 in the first auxiliary signal line G201, and the second conductor section G21 can be isolated from the auxiliary conductor body G22 by the second partition U2.

[0056] The redundant conductor body D22 in the first redundant signal line D201 can be electrically connected to the auxiliary conductor body G22 in the first auxiliary signal line G201 at a crossing between the redundant conductor body D22 and the auxiliary conductor body G22, so that the part of the first redundant signal line D201 that does not belong to the first line section D21 can be electrically connected to the part of the first auxiliary signal line G201 that does not belong to the second line section G21.

[0057] It should be noted that not all redundant signal lines D20 in display field 000 need to be equipped with the first line section D21, and not all auxiliary signal lines G1 need to be equipped with the second line section G21.

[0058] Thus, a portion of the multiple redundant signal lines D20 in display field 000 can be first redundant signal lines D201, and the other portion of the multiple redundant signal lines D20 can be second redundant signal lines D202. The first redundant signal line D201 can simultaneously comprise the first line section D21 and the redundant line body D22, while the second redundant signal line D201 is not connected to the first line section D21 and is a single, continuous signal line without any partition. The second redundant signal line D202 can be electrically connected to the auxiliary line body G22 in the first auxiliary signal line G201 at a junction between the second redundant signal line D202 and the auxiliary line body G22.

[0059] Additionally or alternatively, a portion of the multiple auxiliary signal lines G20 in display field 000 can be first auxiliary signal lines G201, and the other portion of the multiple auxiliary signal lines G20 can be second auxiliary signal lines G202. The first auxiliary signal line G201 can simultaneously include the second line section G21 and the auxiliary signal line body G22, while the second auxiliary signal line G202 is not provided with the second line section G21 and is a complete signal line without a partition. The second auxiliary signal line G202 can be electrically connected at a junction between the second auxiliary signal line G202 and the redundant line body D22 in the first redundant signal line D201.

[0060] In one embodiment of the present application, in a case where the display field 000 simultaneously includes the second redundant signal line D202 and the second auxiliary signal line G202, the second redundant signal line D202 can be electrically connected to the second auxiliary signal line G202 at a crossing between the second redundant signal line D202 and the second auxiliary signal line G202.

[0061] In this case, it can be ensured that in display field 000, the portions of the redundant signal lines D20 that do not belong to the first line sections D21 are electrically connected to the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21 at the intersections between these portions. Furthermore, the portions of the redundant signal lines D20 that do not belong to the first line sections D21 and the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21 can form a grid-like, electrically conductive layer in display field 000.

[0062] Fig. Figure 9 is a schematic structure diagram of the film layers of the display field in Fig. 8 to DD. Since an insulating layer 001 is arranged between the conductive pattern of the redundant signal lines D20 and the conductive pattern of the auxiliary signal lines G20, a third via V3 must be provided in the display field 000, which penetrates the insulating layer 001, so that the parts of the redundant signal lines D20 that do not belong to the first connection sections D21 can overlap at the intersections with the parts of the auxiliary signal lines G20 that do not belong to the second connection sections G21 through the third via V3.

[0063] In the present application, an end section of the second redundant signal line D202 in display field 000 can be electrically connected to the first power signal line 400 and / or an end section of the second auxiliary signal line G202 can be electrically connected to the first power signal line 400. Naturally, an end section of the redundant conductor body D22 in the first redundant signal line D201 can also be electrically connected to the first power signal line 400, and / or an end section of the auxiliary conductor body G22 in the first auxiliary signal line G201 can also be electrically connected to the first power signal line 400.Thus, the grid-shaped electrically conductive layer formed in the display field 000 by the parts of the redundant signal lines D20 that do not belong to the first line sections D21 and the parts of the auxiliary signal lines G20 that do not belong to the second line sections G21 can be connected to the first current signal line 400.

[0064] In one embodiment of the present application, as in Fig. 10 shown, is Fig. Figure 10 shows a schematic structure diagram of film layers of a display field in a display area according to an embodiment of the present application. The light-emitting component 300 in the display field 000 can comprise an anode 301, a light-emitting layer 302, and a cathode layer 303 arranged one above the other. The anode 301 of the light-emitting component 300 is arranged closer to the base substrate 100 relative to the cathode layer 303.

[0065] Optionally, the display field 000 can further comprise a pixel definition layer 500. The conductive pattern of the anode 301 is arranged closer to the base substrate 100 relative to the pixel definition layer 500. The cathode layer 303 can be arranged on a side of the pixel definition layer 500 facing away from the base substrate 100. The light-emitting layer 302 can be located between the anode 301 and the cathode layer 303. In the pixel definition layer 500, pixel apertures 501 can be formed in a one-to-one correspondence to the plurality of light-emitting devices 300. An orthographic projection of each pixel aperture 501 onto the base substrate 100 can lie within an orthographic projection of the anode 301 of the corresponding light-emitting device 300 onto the base substrate 100.It should be noted that both the light-emitting layer 302 and the cathode layer 303 are film layer structures arranged throughout the entire layer. Therefore, in the display field 000, a portion of the anode 301 in the corresponding pixel aperture 501, a portion of the light-emitting layer 302 in the pixel aperture 501, and a portion of the cathode layer 303 in the pixel aperture 501 form a light-emitting device 300. For example, the light-emitting device 300 can be an organic light-emitting diode (OLED) device.

[0066] In the present application, each first pixel circuit 201 in the display field 000 can be electrically connected to the anode 301 in the corresponding light-emitting component 300. The cathode layer in the corresponding light-emitting component 300 can be electrically connected to the first current signal 400.

[0067] Since the cathode layer 303 in the display field 000 is a film layer structure arranged throughout the layer, the first current signal line 400 can supply a VSS signal to the light-emitting devices 300 when the cathode layer 303 is electrically connected to the first current signal line 400. Because the thickness of the cathode layer 303 is typically small, its resistance is generally high. If the lattice-shaped electrically conductive layer formed by the portions of the redundant signal lines D20 that do not belong to the first line sections D21 and the portions of the auxiliary signal lines G20 that do not belong to the second line sections G21 is electrically connected to the cathode layer 303, the lattice-shaped electrically conductive layer can act as an auxiliary electrode for the cathode layer 303.Therefore, the resistance of the cathode layer 303 can be reduced by the grid-shaped electrically conductive layer, so that the VSS signals are consistent at different points on the cathode layer 303 and the uniformity of the VSS signals applied to the cathode layer 303 is ensured.

[0068] Optionally, display field 000 may also include a second current signal line (not shown). At least part of the second current signal line may be located in display area 00a. The second current signal line may be electrically connected to various valid drive circuits 201 in display area 00a. The second current signal line may be a high-level current signal line (i.e., a VDD current signal line). A VDD signal may be supplied via the second current signal line to various valid drive circuits 201, so that the valid drive circuits 201 can control the corresponding light-emitting components 300 to emit light.

[0069] In one embodiment of the present application, as in Fig. 11 shown, is Fig. 11 A local top view of a display field according to an embodiment of the present application. The display field 000 may further comprise a plurality of connecting lines F in a one-to-one correspondence with the plurality of data signal lines D10. The plurality of connecting lines F may be arranged in the non-display area 00b of the display field 000. A portion of the plurality of connecting lines F may be electrically connected to a corresponding data signal line D10 via the first line section D21 and the second line section G21. In a case where the connecting line F must be electrically connected to a corresponding data signal line D10 via the first line section D21 and the second line section G21, the connecting line F, the first line section D21, and the second line section G21 form a fan-out line that corresponds to the data signal line D10.In this way, it can be ensured that part of the fan-out line is located in display area 00a, thus effectively reducing the space occupied by the fan-out line in non-display area 00b. The other part of the plurality of connecting lines F can be directly electrically connected to a corresponding data signal line D10. In a case where connecting line F is directly electrically connected to data signal line D10, connecting line F is a fan-out line corresponding to data signal line D10.

[0070] In the present application, the plurality of connecting lines F in the non-display area 00b is configured to be connected to a driver assembly. For example, the driver assembly can be located at a position B1 in the non-display area 00b, so that the driver assembly can supply a data signal via the connecting lines F to the corresponding data signal line D10.

[0071] For example, the multiple data signal lines D10 in display field 000 can be connected to the driver chip by bringing the multiple data signal lines D1 together from both sides towards the center and connecting them to the driver chip. Since the data signal lines D10 on both sides of the driver chip's bond point B1 are further away from the driver chip, and the data signal lines D10 in the center are closer to the driver signal, the data signal lines D10 on both sides must be connected to the corresponding connection lines F via the second connection section G21 and the first connection section D21, and the data signal lines D10 in the center can be connected directly to the corresponding connection lines F.

[0072] For the data signal lines D10 on both sides, the driver assembly can supply data signals to the data signal lines D10 via the corresponding connecting line F, the first line section D21, and the second line section G21. For the data signal lines D10 in the middle, the driver assembly can supply data signals directly to the data signal lines D10 via the corresponding connecting line F.

[0073] In one embodiment of the present application, as in Fig. 12 shown, is Fig. Figure 12 shows a top view of a display field according to an embodiment of the present application. The display field 000 may further comprise a GOA (Gate Driver On Array) circuit 600. At least part of the GOA circuit 600 may be arranged in the display area 00a of the display field 000. In general, two GOA circuits 600 are provided. The two GOA circuits 600 may typically be arranged on either side of the display field 000. The two ends of each gate line G10 in the display field 000 may be electrically connected to the two GOA circuits 600. Gate sampling signals may be supplied to the gate lines G10 via the GOA circuits 600. In the present application, since at least part of the GOA circuit 600 is located in the display field 000 in the display area 00a, the width of the non-display area 00b of the display field 000 can be further reduced.In this way, the screen ratio of the display device equipped with the display field can be further improved.

[0074] For example, Fig. 13, as in Fig. Figure 13 shows a top view of another display field according to an embodiment of the present application. An orthographic projection of the GOA circuit 600 in the display field 000 on the base substrate 100 can overlap with an orthographic projection of the anode 301 of the light-emitting component 300 on the base substrate 100. Thus, part of the light-emitting component 300 in the display field 000 can be arranged on a side of the GOA circuit 600 facing away from the base substrate 100, so that an area provided with the GOA circuit 600 can display images normally in the display field 000.

[0075] In the present application, the display area 00a in the display field 000 can comprise a first display sub-area 00a1, a second display sub-area 00a2, and a third display sub-area 00a3. The second display sub-area 00a2 can be located between the first display sub-area 00a1 and the third display sub-area 00a3. The light-emitting components 300 can be arranged in the first display sub-area 00a1, the second display sub-area 00a2, and the third display sub-area 00a3. Therefore, the light emission of the light-emitting components 300 in these three display sub-areas can ensure that all three display sub-areas can display the corresponding images.

[0076] The plurality of pixel circuits 200 in the display field 000 can be arranged in the first display sub-area 00a1 and the second display sub-area 00a2 and outside the third display sub-area 00a3. At least a part of the GOA circuit 600 in the display field 000 can be arranged in the third display sub-area 00a3. It should be noted that the pixel circuit 200 and the GOA circuit 600 can generally comprise a transistor, and the transistor in the pixel circuit 200 and the transistor in the GOA circuit 600 are generally formed simultaneously. In the present application, the pixel circuit 200 is arranged outside the third display sub-area 00a3, and at least a part of the GOA circuit 600 is arranged in the third display sub-area 00a3.This ensures that there is no mutual interference between the position of the GOA circuit 600 and the position of the pixel circuit 200, provided that the GOA circuit 600 is located in the display area 00a.

[0077] In the present application, the pixel circuits arranged in the first display sub-area 00a1 can comprise, from the plurality of pixel circuits 200, first pixel circuits 201 and dummy pixel circuits 202. The pixel circuits arranged in the second display sub-area 00a2, from the plurality of pixel circuits 200, can be first pixel circuits 201. Some of the first pixel circuits 201 arranged in the second display sub-area 00a2 can be electrically connected to the light-emitting components 300 in the second display sub-area 00a2. The other part of the first pixel circuits 201 arranged in the second display sub-area 00a2 can be electrically connected to the light-emitting components 300 in the third display sub-area 00a3.

[0078] It should be noted that in the first display sub-area 00a, a plurality of columns of first pixel circuits 201 and a plurality of columns of dummy pixel circuits 202 are arranged offset. The number of columns of first pixel circuits 201 is greater than the number of columns of dummy pixel circuits 202, so that at least two columns of first pixel circuits 201 can be arranged between two adjacent columns of dummy pixel circuits 202. In contrast to a display field in the technology in which a plurality of pixel circuits are electrically connected in a one-to-one correspondence with a plurality of light-emitting components, the plurality of pixel circuits 200 in the display field 000 according to the embodiment of the present application is obtained by compressing the plurality of pixel circuits in the display field in the technology in the technology in question in a row direction.Thus, in the embodiment of the present application, the number of pixel circuits 200 is greater than the number of light-emitting components 300, and the width of the pixel circuit 200 in the line direction in the display field 000 according to the embodiment of the present application is much smaller than the width of the light-emitting component 300.

[0079] For example, Fig. 14, as in Fig. Figure 14 shows a locally enlarged representation of the display field in Fig. 12 at A2. In the first display sub-area 00a of the display field 000, the ratio of the number of columns of first pixel circuits 201 to the number of columns of dummy pixel circuits 202 is N:1. That is, between two adjacent columns of dummy pixel circuits 202, N columns of dummy pixel circuits 202 can be arranged. N can be an integer greater than or equal to 2 and less than or equal to 6. See also Fig. 15. Fig. Figure 15 is a further schematic diagram of the connection between a plurality of light-emitting devices and a plurality of first pixel circuits according to an embodiment of the present application. In a case where N equals 4, four columns of first pixel circuits 201 and one column of dummy pixel circuits 202 can be arranged in a region of four adjacent columns of light-emitting devices 300 in the first display subregion 00a, wherein the four columns of first pixel circuits 201 are electrically connected in a one-to-one correspondence with the four adjacent columns of light-emitting devices 300.It should be noted that the four adjacent columns of light-emitting components 300 can be one column of light-emitting components for emitting red light, one column of light-emitting components for emitting blue light, and two columns of light-emitting components for emitting green light. Thus, the light-emitting components in the display field 000 are arranged in an RGBB mode. In the row direction of the multitude of light-emitting components 300, one light-emitting component R for emitting red light, one light-emitting component B for emitting blue light, and two light-emitting components G for emitting green light, arranged adjacent to each other, can form a pixel group.

[0080] In one embodiment of the present application, the density of the light-emitting components 300 in the first display sub-area 00a1, the density of the light-emitting components 300 in the second display sub-area 00a2, and the density of the light-emitting components 300 in the third display sub-area 00a3 are equal. This ensures that the display effect of the first display sub-area 00a1, the display effect of the second display sub-area 00a2, and the display effect of the third display sub-area 00a3 are essentially the same, thus effectively improving the overall display effect of the display field.

[0081] It should be noted that, since two GOA circuits 600 are provided in display field 000, two third display sub-areas 00a3 are required in display area 00a, so that the two GOA circuits are each arranged between the two third display sub-areas 00a3. Since the second display sub-area 00a2 must be arranged between the third display sub-area 00a3 and the first display sub-area 00a1, two second display sub-areas 00a2 are required in display area 00a. In this case, the first display area 00a1 must be arranged in display area 00a between two second display areas 00a2, and the third display area 00a3 must be arranged on the side of the second display area 00a2 facing away from the first display area 00a1.

[0082] In one embodiment of the present application, the density of the pixel circuits 200 in the first display sub-area 00a1 corresponds to the density of the pixel circuits 200 in the second display sub-area 00a2.

[0083] In this case, it will be applied to Fig. 16 referred. Fig. Figure 16 is a schematic diagram of the electrical connection between light-emitting components and the first pixel circuits at A3 in the display field in Fig. 12. Since the pixel circuits 200 in the second display sub-area 00a2 are first pixel circuits 201, and the width of the pixel circuit 200 in the row direction is significantly smaller than the width of the light-emitting component 300, the number of columns of first pixel circuits 201 is greater than the number of columns of light-emitting components 300 in the second display sub-area 00a2. In this way, a portion of the first pixel circuits 201 in the second display sub-area 00a2 can be electrically connected in a one-to-one correspondence with the multitude of light-emitting components 300 in the second display sub-area 00a2. The other part of the first pixel circuits 201 in the second display sub-area 00a2 does not need to be connected to the multitude of light-emitting components 300 in the second display sub-area 00a2 and can be electrically connected to the multitude of light-emitting components 300 in the third display sub-area 00a3.

[0084] For example, the number of columns of first pixel circuits 201 in the second display sub-area 00a2 corresponds to the number of columns of light-emitting components 300 in the second display sub-area 00a2 and in the third display sub-area 00a3. That is, the number of columns of first pixel circuits 201 in the second display sub-area 00a2 corresponds to the sum of the number of columns of light-emitting components 300 in the second display sub-area 00a2 and the number of columns of light-emitting components 300 in the third display sub-area 00a3. Thus, the multitude of columns of first pixel circuits 201 in the second display sub-area 00a2 can be electrically connected in a one-to-one correspondence with the multitude of columns of light-emitting components 300 in the second display sub-area 00a2 and in the third display sub-area 00a3. That is,The multitude of columns of first pixel circuits 201 in the second display sub-area 00a2 can be electrically connected to the anodes 301 of the multitude of columns of light-emitting components 300 in the second display sub-area 00a2 and in the third display sub-area 00a3. This ensures that the anodes 301 of the light-emitting components 300 in the third display sub-area 00a3 are connected to the first pixel circuits 201 in the second display sub-area 00a2, provided that no first pixel circuits 201 are arranged in the third display sub-area 00a3, allowing the GOA circuit 600 to be arranged in the third display sub-area 00a3. Thus, the GOA circuit 600 in the third display sub-area 00a3 can be hidden within the display area 00a.

[0085] In one embodiment of the present application, as in Fig. 17 shown, is Fig. Figure 17 shows a schematic diagram of the connection between anodes of light-emitting devices and first pixel circuits according to an embodiment of the present application. The display field 000 can further comprise a plurality of transparent connecting lines L in the second display sub-area 00a2 and in the third display sub-area 00a3. Anodes 301 of at least some of the light-emitting devices 300 in the second display sub-area 00a2 and in the third display sub-area 00a3 can be electrically connected to corresponding first pixel circuits 201 via the transparent connecting lines L.Since the transparent connecting lines L have a higher light transmittance and a lower light reflection, in a case where the anodes 301 of the light-emitting components 300 in the second display sub-area 00a2 and in the third display sub-area 00a3 are connected to the corresponding first pixel circuits 201 via the transparent connecting lines L, it can be ensured that the reflectivity of the second display sub-area 00a2 and the third display sub-area 00a3 to the ambient light corresponds essentially to the reflectivity of the first display sub-area 00a1 to the ambient light, provided that the light-emitting components 300 in the second display sub-area 00a2 and the third display sub-area 00a3 can be normally connected to the corresponding first pixel circuits 201, so that the reliability of the display field 000 is high.

[0086] In one embodiment of the present application, as in Fig. 18 shown, is Fig. Figure 18 shows a schematic distribution diagram of a transparent connecting line and an auxiliary signal line according to an embodiment of the present application. The transparent connecting line L can comprise a first transparent line section L1 and a second transparent line section L2, which are connected to each other. The direction of travel of the first transparent line section L1 in the transparent connecting line L coincides with the direction of travel of the auxiliary signal lines G20, and the direction of travel of the second transparent line section L2 intersects the direction of travel of the auxiliary signal lines G20.

[0087] In the present application, an orthographic projection of the first transparent conductor section L1 in the transparent connecting lines L in display field 000 on the base substrate 100 cannot overlap with an orthographic projection of the auxiliary signal line G20 on the base substrate 100, nor can it overlap with an orthographic projection of the second transparent conductor section L2 in at least a portion of the transparent connecting lines L in display field 000 on the base substrate 100. In this case, it can be ensured that the overlapping area of ​​the orthographic projection of the transparent connecting line L in display field 000 on the base substrate 100 and the orthographic projection of the auxiliary signal line G20 on the substrate 100 is small, so that the parasitic capacitance between the transparent connecting line L and the auxiliary signal line G20 is small.For example, the ratio of the overlapping area of ​​the orthographic projection of at least one transparent connecting line L on the base substrate 100 and the orthographic projection of at least one auxiliary signal line G20 on the base substrate 100 to the total area of ​​the orthographic projection of the at least one transparent connecting line L on the base substrate 100 is less than or equal to 30%. This ensures that, in a case where the first pixel circuit 201 transmits signals via the transparent connecting line L to the anode 301 of the corresponding light-emitting component 300, the transparent connecting line L is less affected by the auxiliary signal line G20, allowing the light-emitting components 300 to produce better lighting effects in the second display sub-area 00a2 and the third display sub-area 00a3.

[0088] Optionally, on Fig. 19 referred. Fig. Figure 19 is a schematic diagram of the relative positional relationship between an anode of a light-emitting device and transparent signal lines according to an embodiment of the present application. An orthographic projection of the anodes 301 of at least part of the light-emitting devices 300 in the second display sub-area 00a2 and in the third display sub-area 00a3 on the base substrate 100 overlaps with an orthographic projection of at least two transparent signal lines on the base substrate. The anodes 301 and the transparent signal lines L, whose orthographic projections on the base substrate 100 overlap, are not electrically connected to each other. That is, the transparent signal line L is electrically connected to the anode 301 of the corresponding light-emitting device 300 after passing through another light-emitting device 300.

[0089] In this case, it will be applied to Fig. 20 referred. Fig. Figure 20 is a schematic structure diagram of film layers of the display field in Fig. 19 on E-E'.

[0090] At least two transparent signal lines L are arranged below (i.e. on a side facing the base substrate 100) the anode 301 of the light-emitting device 300, so that the flatness of the anode 301 is large and the light-emitting device 300 can produce better light effects.

[0091] In one embodiment of the present application, as in Fig.Figure 20 shows a first planarization layer 701 arranged between a conductive layer of the transparent signal line L in the display field 000 and a conductive layer of the anode 301. A conductive layer of the data signal line D10 in the display field 000 can be arranged on a side of the first planarization layer 701 facing the base substrate 100. The data signal line D10 in the display field 000 and the VDD current signal line can be arranged in the same layer and made of the same material. A second planarization layer 702 is arranged between a conductive layer of the data signal line D10 and a conductive layer of the transparent signal line L. The auxiliary signal line G20 in the display field 000 can be arranged on a side of the second planarization layer 702 facing the base substrate 100.A third planarization layer 703 is arranged between a conductive layer of the second auxiliary signal line G20 and a conductive layer of the data signal line D10.

[0092] It should be noted that the pixel circuits 200 and the GOA circuits 600 in the present application can be arranged on a side of the third planarization layer 703 facing the base substrate 100. Therefore, a via must be formed in the first planarization layer 701, the second planarization layer 702, and the third planarization layer 703 so that the first pixel circuit 201 is electrically connected to the anode 301 of the corresponding light-emitting device 300 via the via. Furthermore, no via is provided in the planarization layer between the dummy pixel circuit 202 and the light-emitting device 300 in the display field 000, so that the dummy pixel circuit 202 is isolated from the light-emitting device 300 by the planarization layer.Likewise, no via is provided in the planarization layer between the GOA circuit 600 and the light-emitting component 300 in the display field 000, so that the GOA circuit 600 is isolated from the light-emitting component 300 by the planarization layer.

[0093] In one embodiment of the present application, the display field 000 can further comprise an encapsulation layer. The encapsulation layer can be arranged on a side facing away from the base substrate 100 of a plurality of light-emitting components 300. The encapsulation layer can isolate moisture and oxygen from the external environment, so that the moisture and oxygen in the external environment do not attack the light-emitting layer 302 in the light-emitting component 300 and the light-emitting component 300 has a long service life.

[0094] In summary, the display field according to the embodiments of the present disclosure comprises a base substrate, a plurality of pixel circuits, a plurality of light-emitting components, a plurality of data signal lines, and a plurality of redundant signal lines. A redundant signal line may comprise a first line segment connected to a data signal line. The first line segment may function as part of a fan-out line electrically connected to the data signal line. Since the redundant signal line is located in the display area, the part (i.e.,The first section of the fan-out line, which is electrically connected to the data signal line, should be located in the display area, so that the other part of the fan-out line occupies less space in the non-display area than the first section, and the width of the area in which the fan-out line is located is effectively reduced in the non-display area.

[0095] In this way, the screen ratio of a display device equipped with a display field is effectively improved, resulting in excellent display performance. Furthermore, the data signal lines and redundant signal lines can be arranged in the same conductive pattern, and this conductive pattern, encompassing both the data and redundant signal lines, can be evenly distributed across the display area.If part of the first redundant signal lines in the area of ​​a column of dummy pixel circuits acts as part of the fan-out line in the display area, it can be ensured that the conductive layer patterns in the display field are evenly distributed in the display area, provided that the part of the fan-out line can be distributed in the display area, so that the probability of color distortion in the display field is effectively reduced and the display effects of the display field are excellent.

[0096] In one embodiment of the present application, a display device is further provided. The display device can be a product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigation device, and the like. The display device can include a power supply and a display field. The display field can be the display field described above.

[0097] It should be noted that the dimensions of layers and areas in the drawings may be exaggerated for clarity. Furthermore, it should be understood that when an element or layer is described as being "on" another element or layer, it may be located directly on top of the other element, or there may be an intermediate layer. It should also be understood that when an element or layer is described as being "under" another element or layer, it may be located directly beneath the other element, or there may be more than one intermediate layer or element.It should also be understood that when a layer or element is described as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may be more than one intermediate layer or element. The same reference symbols consistently denote identical elements.

[0098] In this application, the terms "first" and "second" are used for descriptive purposes only and cannot be interpreted as indicating or suggesting a relative meaning. The term "a multitude of" refers to two or more unless expressly stated otherwise.

[0099] The embodiments described above are optional embodiments of the present application and are not intended to limit the present application. For the purposes and within the scope of the present application, all variations, equivalent replacements, improvements, and the like fall within the scope of protection of the present application. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 202310974470.7

[0001]

Claims

[1] Display field, characterized by , that the display field has a display area, wherein the display field comprises: a base substrate; a plurality of pixel circuits arranged in an array on one side of the base substrate, wherein the plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of dummy pixel circuits; a plurality of light-emitting components on a side of the plurality of pixe circuits facing away from the base substrate, wherein the plurality of light-emitting components is electrically connected in a one-to-one correspondence to the plurality of first pixe circuits; and a multitude of data signal lines and a multitude of redundant signal lines arranged in the display area, wherein one direction of the data signal lines coincides with one direction of the redundant signal lines; wherein one of the data signal lines is connected to a column of the first pixel circuits, one of the redundant signal lines is arranged in the area of ​​a column of the dummy pixel circuits, and at least a part of the plurality of redundant signal lines is first redundant signal lines, wherein one of the first redundant signal lines comprises a first line section that is connected to one of the data signal lines. [2] Display field according to claim 1, characterized by, that the display field further comprises a plurality of auxiliary signal lines in the display area, wherein one direction of the auxiliary signal lines intersects the direction of the redundant signal lines, wherein one of the auxiliary signal lines is arranged in the area of ​​a series of pixel circuits and at least a part of the plurality of auxiliary signal lines is a first auxiliary signal line, wherein one of the first auxiliary signal lines comprises a second line section, wherein one end of the second line section is electrically connected to one of the data signal lines and the other end of the second line section is electrically connected to an end of the first line section. [3] Display field according to claim 2, characterized by, that one of the first redundant signal lines further comprises a redundant conductor body which is separate from the first conductor section, and that one of the first auxiliary signal lines further comprises an auxiliary conductor body which is separate from the second conductor section, wherein the redundant conductor body is electrically connected to the auxiliary conductor body at a crossing between the redundant conductor body and the auxiliary conductor body. [4] Display field according to claim 3, characterized by, that a portion of the plurality of redundant signal lines is the first redundant signal lines and the other portion of the plurality of redundant signal lines is the second redundant signal lines, wherein the first line section is not arranged in the second redundant signal lines and the second redundant signal line is electrically connected to the auxiliary line body at a crossing between the second redundant signal line and the auxiliary line body; and / or that a portion of the plurality of auxiliary signal lines is the first auxiliary signal lines and the other portion of the plurality of auxiliary signal lines is the second auxiliary signal lines, wherein the second line section is not arranged in the second auxiliary signal lines and the second auxiliary signal line is electrically connected to the redundant line body at a crossing between the second auxiliary signal line and the redundant line body. [5] Display field according to claim 4, characterized by , that in a case where the display field simultaneously includes the second redundant signal lines and the second auxiliary signal lines, the second redundant signal line is electrically connected to the second auxiliary signal line at a crossing between the second redundant signal line and the second auxiliary signal line. [6] Display field according to claim 4, characterized by , that the display field further comprises a first power signal line, wherein the second redundant signal lines are electrically connected to the first power signal line and / or the second auxiliary signal lines are electrically connected to the first power signal line. [7] Display field according to claim 6, characterized by, that the light-emitting device comprises an anode, a light-emitting layer and a cathode layer arranged one above the other, wherein the anode is closer to the base substrate than the cathode layer, wherein the first Pixe circuit is electrically connected to the anode in the corresponding light-emitting device and the cathode layer is electrically connected to the first current signal line. [8] Display field according to one of claims 2 to 7, characterized by , that the display field furthermore has a non-display area that surrounds the display area; that the display field further comprises a plurality of connecting lines in the non-display area which are electrically connected in a one-to-one correspondence to the plurality of data signal lines, wherein a part of the plurality of connecting lines is electrically connected to corresponding data signal lines via the first line section and the second line section, and wherein the other part of the plurality of connecting lines is directly electrically connected to corresponding data signal lines; the multitude of connecting lines are designed in such a way that they can be connected to and linked with a driver assembly. [9] Display board according to any one of claims 2 to 7, characterized bythat the redundant signal lines and the data signal lines are arranged in the same layer and made of the same material, and that the redundant signal lines and the auxiliary signal lines are arranged in different layers. [10] Display field according to any one of claims 1 to 7, characterized by , that the display field further comprises a GOA (Gate Driver On Array) circuit, wherein the light-emitting device comprises an anode, a light-emitting layer and a cathode layer arranged one above the other, the anode being closer to the base substrate than the cathode layer, wherein an orthographic projection of the GOA circuit on the base substrate overlaps with an orthographic projection of the anode on the base substrate. [11] Display field according to claim 10, characterized by, that the display area comprises a first display sub-area, a second display sub-area and a third display sub-area, wherein the second display sub-area is arranged between the first display sub-area and the third display sub-area, wherein the multitude of pixel circuits are arranged in the first display sub-area and in the second display sub-area and are arranged outside the third display sub-area; at least part of the GOA circuit is arranged in the third display sub-area; and wherein the pixel circuits arranged in the first display sub-area comprise the first pixel circuits and the dummy pixel circuits from the plurality of pixel circuits, wherein the pixel circuits arranged in the second display sub-area are the first pixel circuits from the plurality of pixel circuits, wherein a part of the first pixel circuits located in the second display sub-area is electrically connected to the light-emitting components in the second display sub-area, and the other part of the first pixel circuits located in the second display sub-area is electrically connected to the light-emitting components in the third display sub-area. [12] Display field according to claim 11, characterized by , that in the first display sub-area a large number of columns of first pixel circuits and a large number of columns of dummy pixel circuits are arranged offset. [13] Display field according to claim 12, characterized by , that N columns of first pixel circuits are arranged between two adjacent columns of dummy pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6. [14] Display field according to claim 11, characterized by , that the density of light-emitting components in the first display sub-area corresponds to the density of light-emitting components in the second display sub-area. [15] Display field according to claim 11, characterized by , that a plurality of columns of first pixel circuits in the second display sub-area are each electrically connected to anodes of a plurality of columns of light-emitting components in the second display sub-area and in the third display sub-area. [16] Display field according to claim 15, characterized by, that the display field further comprises a plurality of transparent connecting lines in the second display sub-area and in the third display sub-area, wherein anodes of at least some of the light-emitting components in the second display sub-area and in the third display sub-area are electrically connected to corresponding first pixel circuits via the transparent connecting lines. [17] Display field according to claim 16, characterized by , that the display field further comprises a plurality of auxiliary signal lines, a portion of the auxiliary signal lines being arranged in the second display sub-area and the third display sub-area; wherein the transparent connecting line comprises a first transparent line section and a second transparent line section which are connected to each other, wherein a direction of travel of the first transparent line section coincides with a direction of travel of the auxiliary signal line and a direction of travel of the second transparent line section intersects the direction of travel of the auxiliary signal line; wherein an orthographic projection of the first transparent conductor section on the base substrate does not overlap with an orthographic projection of the auxiliary signal line on the base substrate and an orthographic projection of the second transparent conductor section overlaps with the orthographic projection of the auxiliary signal line on the base substrate in at least part of the transparent connecting lines. [18] Display field according to claim 17, characterized by, that the ratio of the overlapping area of ​​an orthographic projection of at least one transparent connecting line on the base substrate and of an orthographic projection of at least one auxiliary signal line on the base substrate to the total area of ​​the orthographic projection of the at least one transparent connecting line on the base substrate is less than or equal to 30%. [19] Display field according to claim 16, characterized by , that an orthographic projection of each of the anodes of at least part of the light-emitting components in the second display sub-area and in the third display sub-area on the base substrate overlaps with orthographic projections of at least two transparent signal lines on the base substrate. [20] Display device, characterized by, that the display device comprises: a power supply and a display field which is electrically connected to the power supply, wherein the display field is a display field according to any one of claims 1 to 19.

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