Intelligent resource planning in multiprocessor environments using predictive task assignment

Abstract

A system for intelligent resource planning in a multiprocessor computing environment, consisting of: a multitude of processing units arranged in a computing machine and configured to perform computing tasks simultaneously; a non-volatile memory that is operationally connected to the multitude of processing units and is configured to store task descriptions, processor state data, and historical execution logs; a task intake unit that is operationally connected to the non-volatile memory and configured to receive task descriptions corresponding to executable workloads, each task description containing characteristics of the workload, indicators of memory access behavior, information about execution dependency, and parameters for time constraints; a processor state monitoring unit that is operationally connected to the multitude of processing units and is configured to collect processor-specific state data during runtime, including utilization level, cache occupancy state, execution throughput behavior, power consumption state, and thermal operating state; a predictive task allocation unit executed by one or more processors and operationally coupled to the non-volatile memory, wherein the predictive task allocation unit is configured to analyze the task descriptions together with the processor-specific state data and historical execution records to generate predicted execution suitability scores corresponding to the assignment of each task to each processing unit prior to task execution; a scheduling control unit executed by one or more processors, which is operationally coupled to the Predictive Task Mapping Unit, wherein the scheduling control unit is configured to assign each received task to a selected processing unit based on the predicted execution suitability values, while suppressing unnecessary task migrations; and a feedback adjustment unit that is operationally coupled with the planning control unit and is configured to monitor the actual execution results of the distributed tasks and update the historical execution records stored in non-volatile memory to refine subsequent predictive task assignment operations.

Description

Technical field of the invention

[0001] The present invention relates generally to computer architecture and operating systems, in particular intelligent scheduling systems for multiprocessor and multicore computing environments. Specifically, the invention relates to a system and an associated physical device that dynamically distributes computing tasks across heterogeneous processing resources. This distribution is achieved by means of predictive task assignment based on previous execution behavior, processor performance characteristics, and system states at runtime. Background of the invention

[0002] Modern computer systems increasingly rely on multiprocessor architectures with multiple central processing units (CPUs), multi-core processors, graphics processing units (GPUs), and specialized accelerators, either integrated into a single computer or distributed across networked hardware structures. While such architectures offer considerable parallel processing capacity, the efficient utilization of these resources remains a persistent technical challenge. Conventional scheduling mechanisms in operating systems typically rely on static priority rules, round-robin allocation, or load balancing heuristics that react to the current processor load. These approaches do not account for the predictable behavior of tasks, such as recurring execution patterns, memory access characteristics, dependencies between tasks, and processor affinity tendencies.

[0003] Existing schedulers are also reaching their limits, as they have only limited insight into processor conflicts, cache interference, thermal constraints, and the effort required for task migration. This leads to frequent task migrations, suboptimal processor allocation, and unpredictable execution latencies, particularly in high-performance computing systems, data centers, embedded real-time systems, and industrial control systems. These inefficiencies result in increased power consumption, reduced throughput, missed real-time deadlines, and accelerated hardware wear.

[0004] Attempts to integrate intelligence into scheduling have so far remained largely software-centric abstractions, lacking a close connection to the physical properties of the processor and machine-level feedback mechanisms. Furthermore, many predictive scheduling methods are based on static profiling or offline training and are therefore unsuitable for dynamic, changing workloads. Consequently, there is a clear technical need for a system that can intelligently and predictively allocate tasks to processing resources in real time, is structurally integrated into a physical machine or computing structure, and can continuously adapt to observed execution behavior.

[0005] Energy- and heat-aware schedulers represent another category of existing solutions. These schedulers attempt to distribute workloads in a way that reduces energy consumption or prevents overheating by throttling processor power or redistributing tasks. While effective at managing specific physical constraints, such approaches often operate independently of performance-oriented scheduling logic. This separation leads to trade-offs where energy savings are achieved at the expense of throughput or determinism. Furthermore, energy-aware schedulers typically react to measured states rather than predicting future states, resulting in delayed responses and temporary exceedances of performance or heat limits.

[0006] In distributed and cloud computing environments, resource planning is often handled by orchestration systems that assign virtual machines or containers to physical hosts. These systems operate with a coarse granularity and rely on aggregated resource metrics such as average CPU utilization or memory usage. The detailed task behavior within individual machines remains largely hidden from the scheduler, leading to inefficient resource utilization and bottlenecks.

[0007] Furthermore, the separation between infrastructure and operating system scheduling creates additional layers of abstraction that obscure important execution details.

[0008] All existing solutions share a common drawback: their predominantly reactive nature. Scheduling decisions are typically based on current or past states, without explicitly predicting how a task will behave on a particular processor in the near future. Therefore, schedulers continuously correct suboptimal decisions through migration, throttling, or priority adjustments, resulting in significant overhead. Furthermore, this lack of predictive capability limits the scheduler's ability to provide deterministic performance guarantees, which are becoming increasingly important in applications such as autonomous machines, industrial automation, and real-time data processing.

[0009] Furthermore, many existing scheduling systems are implemented as pure software abstractions, only loosely coupled to the underlying hardware. This separation limits the scheduler's transparency regarding low-level processor states, such as detailed cache behavior, execution pipeline utilization, or local thermal effects. Without this transparency, scheduling decisions are based on incomplete information, leading to conservative or erroneous task placements. As hardware architectures become increasingly complex, this discrepancy between software scheduling logic and the physical behavior of the machine becomes ever more problematic.

[0010] Given these limitations, existing solutions do not fully exploit the potential of multiprocessor systems. They struggle to balance performance, predictability, and efficiency under dynamic conditions and heterogeneous hardware configurations. The lack of integrated predictive mechanisms capable of anticipating task behavior and processor suitability prior to execution remains a significant technical shortcoming. This gap underscores the need for an intelligent resource planning system that combines predictive task allocation with continuous feedback from the physical machine, enabling proactive and adaptive scheduling decisions that overcome the weaknesses of traditional approaches. Summary of the invention

[0011] The present invention provides a system for intelligent resource planning in multiprocessor systems by means of predictive task assignment. Computing tasks are dynamically assigned to processing units based on their predicted execution suitability and not solely on the basis of current utilization. The system uses a processing unit configured to monitor task execution histories, processor performance states, communication patterns between tasks, and machine-level constraints, and to generate predictive task-to-processor assignments before task distribution.

[0012] In one embodiment, the invention provides a scheduling system implemented in a computer, in which a predictive mapping unit executed by one or more processors calculates the expected execution results for distributing tasks across the available processor resources. Based on these predictions, a scheduling control unit assigns tasks to the selected processors in such a way as to minimize execution latency, migration overhead, conflicts, and energy consumption.

[0013] In another aspect, the invention provides a physical device implemented as a multiprocessor machine or embedded computing structure, comprising dedicated sensor, memory, and control elements to support predictive planning operations at the hardware-software interface level. The device is particularly suitable for high-performance servers, industrial automation machines, robot controllers, and mission-critical computing structures that require deterministic and efficient task execution.

[0014] The present invention aims to provide an intelligent resource planning system for multiprocessor environments that overcomes the limitations of conventional reactive planning mechanisms by proactively predicting suitable processor allocations for computational tasks before their execution. The invention aims to ensure that tasks are mapped to processing units in such a way as to optimize execution efficiency, minimize unnecessary task migrations, and improve the determinism of task capabilities in dynamic and heterogeneous computing environments.

[0015] A further objective of the invention is to provide a scheduling system that continuously learns from the observed execution behavior of tasks and the performance characteristics of the processor, thereby adaptively optimizing scheduling decisions over time. The invention aims to achieve this by storing execution histories and processor state data sets in non-volatile memory and using this data to improve the accuracy of predictive task assignment without requiring offline training or static profiling. This ensures that the system responds to changing workloads and hardware conditions.

[0016] A further objective of the invention is to reduce performance losses due to cache invalidation, memory access latency, and the communication overhead between processors typically associated with task migration in multiprocessor systems. By assigning tasks to processors based on predicted execution suitability and maintaining affinity, the invention aims to preserve cache locality and reduce conflicts over shared resources, thereby improving the overall throughput and stability of the system.

[0017] A further objective of the invention is to provide a scheduling system that is closely linked to the physical properties of the underlying computing machine. The invention aims to incorporate feedback on the processor state, including utilization level, thermal conditions, and performance limitations, into the scheduling decision-making process. This enables the system to make hardware-based scheduling decisions that align performance targets with the physical limits of the machine, thereby reducing the risk of thermal throttling and uneven processor aging.

[0018] A further objective of the invention is to support efficient task planning in heterogeneous processor environments with different processor classes that vary in performance, energy consumption, and execution characteristics. The invention aims to intelligently match task requirements with processor capacities, thereby improving the utilization of specialized processors and avoiding suboptimal task placements that arise from treating all processors equally.

[0019] A further objective of the invention is to provide a scheduling system that can be used in real-time and mission-critical computing structures where predictable execution behavior is essential. By reducing reactive corrections and utilizing predictive task mapping, the invention aims to improve temporal determinism and reduce execution variability. This makes the system suitable for industrial automation machines, embedded control systems, and safety-critical computing devices.

[0020] A further objective of the invention is to provide a self-contained scheduling solution that operates autonomously within a computer without relying on external orchestration or monitoring systems. The invention aims to integrate the predictive scheduling logic into the machine itself, enabling the device to efficiently manage its internal processing resources under varying workload conditions.

[0021] A further objective of the invention is to improve energy efficiency and resource utilization in multiprocessor systems by reducing idle times, avoiding excessive task migration, and distributing workloads according to the efficiency characteristics of the processors. This contributes to lower power consumption and improved operational stability in both embedded systems and large-scale computing environments.

[0022] A further objective of the invention is to provide a technically robust and scalable scheduling architecture that can be implemented on a variety of computing platforms, including servers, industrial machines, robotic systems, and high-performance computers. The invention aims to ensure that the scheduling system can scale with an increasing number of processors and increasing workload complexity without causing unreasonable additional overhead.

[0023] Finally, one objective of the present invention is to create an improved technical basis for intelligent resource planning that can be easily integrated into existing operating systems and machine architectures, while offering measurable improvements in performance, predictability and efficiency compared to prior art planning solutions. BRIEF DESCRIPTION OF THE IMAGE

[0024] These and other features, aspects and advantages of the present invention will be better understood if the following detailed description is read with reference to the accompanying drawing, in which the same symbols represent the same parts: Fig. Figure 1 shows a block diagram of an intelligent resource planning system in a multiprocessor computing environment.

[0025] Furthermore, those skilled in the art will recognize that the elements in the drawing are simplified and not necessarily drawn to scale. For example, the flowcharts illustrate the process by highlighting the main steps to facilitate understanding of the present disclosure. With regard to the construction of the device, one or more components may be represented in the drawing by conventional symbols. The drawing may show only the specific details relevant to understanding the embodiments of the present disclosure, so as not to clutter the drawing with details that are already apparent to those skilled in the art from the description contained herein. Detailed description of the invention

[0026] To facilitate understanding of the principles of the invention, reference is made below to the embodiment shown in the drawing, which is described using specific terms. It is understood, however, that this does not limit the scope of protection of the invention. Rather, modifications and further developments of the depicted system, as well as further applications of the inventive principles shown therein, are conceivable, insofar as they would normally occur to a person skilled in the art in the field of the invention.

[0027] It will be clear to those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not to be understood as a limitation thereof.

[0028] References to “an aspect”, “another aspect”, or similar phrases in this description mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, phrases such as “in one embodiment”, “in another embodiment”, and similar expressions in this description may, but do not necessarily, all refer to the same embodiment.

[0029] The terms "includes," "comprehensive," or similar expressions denote non-exclusive inclusion. Thus, a procedure or method containing a list of steps does not only include those steps but may also include further steps not explicitly listed or inherent in the procedure or method. Likewise, the statement "includes..." for one or more devices, subsystems, elements, structures, or components, without further limitations, does not preclude the existence of other devices, subsystems, elements, structures, or components.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meanings generally known to those skilled in the art in the field to which this invention belongs. The systems, methods, and examples described herein serve only for illustration and are not to be understood as limiting.

[0031] Embodiments of the present disclosure are described in detail below with reference to the attached drawing.

[0032] Fig.Figure 1 shows a block diagram of an intelligent resource planning system in a multiprocessor computing environment. The system 100 comprises: a plurality of processing units (102) arranged in a computer and configured to perform concurrent computational tasks; a non-volatile memory (104) operationally connected to multiple processing units and configured to store task descriptions, processor state data, and historical execution logs; a task intake unit (106) operationally connected to the non-volatile memory and receiving task descriptions corresponding to executable workloads, each task description containing characteristics of the computational load, indicators of memory access behavior, execution dependency information, and parameters for time constraints;a processor state acquisition unit (108) operationally connected to multiple processing units and configured to acquire processor-specific state data during runtime, including utilization level, cache occupancy state, execution throughput behavior, power consumption state, and thermal operating state; a predictive task allocation unit (110) executed by one or more processors and operationally connected to the non-volatile memory, wherein the predictive task allocation unit is configured to analyze the task descriptions together with the processor-specific state data and historical execution logs to generate predicted execution suitability values ​​corresponding to the assignment of each task to each processing unit prior to task execution;A scheduling control unit (112) executed by one or more processors, operationally connected to the predictive task assignment unit, wherein the scheduling control unit is configured to bind each received task to a selected processing unit based on the predicted suitability values ​​for execution, while suppressing unnecessary task migrations; and a feedback adjustment unit (114) operationally connected to the scheduling control unit and configured to monitor the actual execution results of the distributed tasks and update the historical execution records stored in non-volatile memory to refine subsequent predictive task assignment operations.

[0033] In one embodiment, the task assignment prediction unit (110) is configured to evaluate, prior to task assignment, the predicted execution latency, the probability of preserving cache locality, the effects of communication between processors, and the probability of memory conflicts for each candidate task and processing unit pairing.

[0034] In one embodiment, the processor state acquisition unit (108) is configured to continuously sample the operating states of the processor during task execution and to record time-correlated processor behavior profiles that are associated with previously executed tasks.

[0035] In one embodiment, the planning control unit (112) is configured to maintain the processor affinity for tasks that exhibit stable execution behavior by preferentially assigning these tasks to the processing units on which they were previously executed with reduced execution effort.

[0036] In one embodiment, the task assignment prediction unit (110) is configured to generate task-to-processor predictions prior to task assignment, thus reducing task migration correction during execution below a predefined threshold.

[0037] In one embodiment, the feedback adjustment unit (114) is configured to compare predicted execution results with observed execution metrics such as execution time, memory access latency and processor standstill, and to adjust the prediction weighting parameters stored in non-volatile memory accordingly.

[0038] In one embodiment, the plurality of processing units (102) comprises heterogeneous processing units with different computing power, energy efficiency and execution characteristics, wherein the predictive task assignment unit is configured to match the task execution requirements with the corresponding processor performance characteristics.

[0039] In one embodiment, the task acquisition unit (106) is configured to receive task descriptions originating from operating system scheduling requirements, application-level workload generators, or external machine control interfaces.

[0040] In one embodiment, the processor state acquisition unit (108) is additionally configured to acquire information about the cache coherence state and indicators of access conflicts in the shared memory associated with the simultaneous execution of multiple tasks.

[0041] In one embodiment, the scheduling control unit (112) is configured to output processor binding control signals before execution begins, assigning each task to a selected processing unit. This prevents reassignment after dispatch unless an execution anomaly is detected.

[0042] The system is integrated into a computer consisting of multiple processing units connected via shared memory and communication links. The system continuously receives task descriptions from the task intake unit. Each task description represents a computational load to be executed. Upon receipt, the task descriptions are stored in persistent memory and made available to the processing unit, which executes the logic for predicting task assignment. Each task description contains execution-relevant characteristics, including indicators of computational intensity, memory access patterns, dependencies between executions, and execution time constraints derived from previous executions or declared by the task source.

[0043] Simultaneously, the processor state unit works with the processing units to collect processor state data in real time. This data is obtained from hardware counters, firmware interfaces, and execution monitor registers of each processing unit. The collected processor state data includes current utilization, cache occupancy, instruction throughput behavior, memory access latencies, thermal operating margins, and power consumption. The processor state unit timestamps this state data, associates it with the respective processing unit, and stores it in non-volatile memory as part of a continuously evolving processor behavior history.

[0044] The predictive task allocation unit, executed by one or more processors, initiates a predictive analysis cycle as soon as one or more task descriptions are available for scheduling. During this cycle, the unit retrieves the task descriptions, processor-specific state data, and execution history from non-volatile memory. For each task, the unit evaluates the suitability of execution on the available processor units by analyzing correlations between previous task executions and the processor operating states. This evaluation includes estimating the expected execution latency, the probability of maintaining cache locality, the communication overhead between processors, and the impact of memory conflicts that would occur when assigning the task to a particular processor unit.

[0045] The predictive task allocation unit additionally considers processor affinity by identifying processors on which the task was previously executed with low overhead or stable performance. For tasks with recurring or periodic execution patterns, the predictive task allocation unit increases the predicted suitability score for processors that exhibit consistent execution efficiency for the task. Conversely, processors that are under high thermal stress, power constraints, or cache conflicts at the time of analysis receive lower predicted suitability scores for incoming tasks.

[0046] Based on calculated, predicted execution suitability values, the control unit assigns a task to a selected processing unit before execution. This assignment is ensured by processor allocation signals, which prevent unnecessary reassignment or migration of the task after its execution. This pre-allocation mechanism guarantees that the task is executed on the processing unit expected to offer optimal execution conditions. This reduces cache invalidations, memory access latencies, and the synchronization overhead between processors.

[0047] Once tasks are assigned, the feedback adjustment unit monitors the actual execution results using runtime metrics. These metrics include actual execution time, memory access latency, cache error behavior, processor hangs, and deviations from predicted execution characteristics. The feedback adjustment unit compares the observed metrics with the predictions generated by the predictive task allocation unit. Any discrepancies identified are used to update the historical execution data and adjust the weighting parameters stored in non-volatile memory.

[0048] The adaptive update process is incremental and continuous, allowing the system to improve its prediction accuracy without interrupting ongoing task execution. This enables the predictive task assignment technique to evolve over time, adapting to changing workload characteristics, processor aging, and dynamic machine operating conditions. This continuous adaptation allows the system to maintain high planning efficiency even with fluctuating workloads and varying processor availability.

[0049] In heterogeneous processing environments, the predictive task allocation unit takes into account differences in processor performance by incorporating processor-specific performance profiles into the prediction process. Tasks with high throughput are preferentially assigned to processors that exhibit higher execution efficiency under comparable workloads, while tasks with intensive memory access patterns are assigned to processors that demonstrate favorable cache behavior and fewer memory conflicts. This performance-oriented allocation ensures the effective utilization of the diverse processing resources within the computer.

[0050] The control unit coordinates task distribution, taking into account the processor's thermal operating limits, by incorporating thermal state data acquired by the processor state monitoring module. As specific processing units approach predefined thermal thresholds, the predictive task allocation unit reduces the predicted suitability values ​​for these units, thus shifting incoming tasks to cooler processing units. This proactive, temperature-dependent behavior prevents thermal saturation and reduces the likelihood of performance degradation due to thermal throttling.

[0051] The system operates autonomously within the computer throughout its entire lifespan, without relying on external scheduling or orchestration systems. All predictive analytics, task binding, feedback adjustment, and processor state monitoring are performed internally using the processing unit and non-volatile memory. The tight integration of the scheduling system into the physical computer architecture enables proactive, adaptive, and hardware-based task scheduling, significantly improving performance stability, resource utilization, and predictability in multiprocessor environments.

[0052] This detailed workflow directly meets the system requirements described above and provides a complete technical explanation of the predictive task mapping technique and its implementation within the intelligent resource planning system.

[0053] The invention is embodied in a computer device designed as a multiprocessor system, consisting of a robust housing with multiple processing units, a shared memory hierarchy, interconnection buses, and a control unit for scheduling. The device further includes monitoring circuits and firmware interfaces that provide the scheduling system with processor status parameters, thermal conditions, cache utilization, and execution counters.

[0054] Within the device, a processing unit with one or more general-purpose processors is connected to a persistent memory that stores planning data, execution histories, and parameters for predictive task allocation. The processing unit executes predictive task allocation logic that continuously evaluates incoming tasks and available processors to determine the optimal execution placement before task distribution.

[0055] According to the present invention, an intelligent resource planning system is provided for a multiprocessor environment. The system is configured to operate within a physical computer with multiple processing units. It includes a task input interface operationally connected to a processing unit, which receives task descriptors. These descriptors represent executable workloads generated by applications, operating system services, or external computers. Each task descriptor contains execution attributes such as indicators of computational intensity, memory access profiles, time constraints, and identifiers for dependencies between tasks.

[0056] The processor unit is also connected to a processor state monitoring unit, which collects runtime state data from each processor unit in the device. This state data includes processor utilization, cache usage, instruction throughput, thermal headroom, power consumption, and the performance of previously executed tasks. This state data is continuously updated and stored in persistent memory to create a processor behavior history.

[0057] A predictive task assignment unit, executed by the processing unit, analyzes task descriptions along with historical processor behavior to predict the suitability of each task for each available processing unit. The unit evaluates the expected execution time, cache locality preservation, link traffic impact, and migration costs for each potential task-processor pair. Predictions are generated dynamically by adaptively weighting historical execution results and real-time processor state changes.

[0058] Based on predicted execution suitability values, a scheduling control unit (TCU) executed by the processing unit selects a target processing unit before each task is executed. The TCU is configured to generate binding control signals that assign the task to the selected processing unit and initiate task distribution without requiring subsequent correction migration. Furthermore, the TCU maintains task affinity for tasks with stable execution patterns, thereby reducing cache invalidation and communication overhead between processors.

[0059] The system also includes a feedback adjustment unit that is operationally linked to the planning control unit. This feedback adjustment unit monitors the actual execution results of tasks after they have been assigned. The observed execution metrics are compared with the predicted results, and deviations are used to update the prediction parameters stored in memory. In this way, the system continuously improves its prediction accuracy without requiring offline training or manual configuration.

[0060] The system and device of the present invention offer significant technical advantages over conventional scheduling mechanisms. By predictively assigning tasks before execution, the system reduces unnecessary task migrations, improves cache utilization efficiency, increases the determinism of task completion times, and optimizes overall processor utilization. The tight integration of predictive logic with feedback from the physical processor state enables adaptive behavior under dynamic workload conditions and makes the invention particularly suitable for high-performance, real-time critical, and mission-critical computing environments.

[0061] The numerous processing units, non-volatile memory, task acceptance unit, processor state acquisition unit, predictive task assignment unit, planning control unit, and feedback adjustment unit are each implemented as physical hardware components within a physical multiprocessor computer. The processing units consist of semiconductor-based processing components physically mounted on a circuit substrate and electrically interconnected via system links to support the parallel execution of tasks. The non-volatile memory is comprised of physical semiconductor memory elements electrically coupled to the processing units via address, data, and control buses to permanently store task descriptions, processor state data, and execution histories.The task acceptance unit is implemented as a hardware interface circuit comprising input buffers, registers, and control logic to receive task descriptions via physical communication paths and store them in non-volatile memory. The processor state sensing unit comprises hardware monitoring circuits, counters, sensors, and status registers physically connected to each processing unit to directly measure utilization, cache behavior, execution throughput, power consumption, and thermal state during runtime.The units for predictive task assignment, scheduling control, and feedback adjustment are implemented as processor-addressable hardware logic blocks or dedicated control circuits that are instantiated within the processing units and operate via physical registers, comparators, and memory access circuits to analyze stored data, bind tasks to selected processing units, and update historical data sets.

[0062] The drawing and the preceding description illustrate embodiments. Those skilled in the art will recognize that one or more of the described elements can be combined to form a single functional element. Alternatively, certain elements can be divided into several functional elements. Elements of one embodiment can be added to another. For example, the process flows described here can be modified and are not limited to the manner described herein. Furthermore, the actions of a flowchart need not be performed in the sequence shown; nor do all actions necessarily need to be carried out. Actions that do not depend on other actions can be performed in parallel with the other actions. The scope of protection of the embodiments is in no way limited by these specific examples. Numerous variations, whether explicitly stated in the description or not, such as...Differences in structure, dimensions, and materials are possible. The scope of protection of the embodiments is at least as comprehensive as described by the following claims.

[0063] The advantages, other benefits, and problem solutions have been described above with reference to specific embodiments. However, the advantages, benefits, problem solutions, and any components that can effect or enhance an advantage, benefit, or solution are not to be construed as critical, necessary, or essential features or components of the claims. REFERENCES 100 A system for intelligent resource planning in a multiprocessor computing environment. 102 Variety of processing units 104 non-transient memory 106 Task recording unit 108 Processor state monitoring unit 110 units for predictive task assignment 112 Control unit for time planning 114 Feedback adjustment unit

Claims

[1] A system for intelligent resource planning in a multiprocessor computing environment, consisting of: a multitude of processing units arranged in a computing machine and configured to perform computing tasks simultaneously; a non-volatile memory that is operationally connected to the multitude of processing units and is configured to store task descriptions, processor state data, and historical execution logs; a task intake unit that is operationally connected to the non-volatile memory and configured to receive task descriptions corresponding to executable workloads, each task description containing characteristics of the workload, indicators of memory access behavior, information about execution dependency, and parameters for time constraints; a processor state monitoring unit that is operationally connected to the multitude of processing units and is configured to collect processor-specific state data during runtime, including utilization level, cache occupancy state, execution throughput behavior, power consumption state, and thermal operating state; a predictive task allocation unit executed by one or more processors and operationally coupled to the non-volatile memory, wherein the predictive task allocation unit is configured to analyze the task descriptions together with the processor-specific state data and historical execution records to generate predicted execution suitability scores corresponding to the assignment of each task to each processing unit prior to task execution; a scheduling control unit executed by one or more processors, which is operationally coupled to the Predictive Task Mapping Unit, wherein the scheduling control unit is configured to assign each received task to a selected processing unit based on the predicted execution suitability values, while suppressing unnecessary task migrations; and a feedback adjustment unit that is operationally coupled with the planning control unit and is configured to monitor the actual execution results of the distributed tasks and update the historical execution records stored in non-volatile memory to refine subsequent predictive task assignment operations. [2] System according to claim 1, wherein the task assignment prediction unit is configured to evaluate, prior to task assignment, the predicted execution latency, the probability of preserving cache locality, the effects of interprocessor communication, and the probability of memory conflicts for each candidate task and processing unit pairing. [3] System according to claim 1, wherein the processor state acquisition unit is configured to continuously sample the operating states of the processor during task execution and to record time-correlated processor behavior profiles associated with previously executed tasks. [4] System according to claim 1, wherein the planning control unit is configured to maintain the processor affinity for tasks with stable execution behavior by preferentially assigning these tasks to processing units on which these tasks were previously executed with reduced execution effort. [5] System according to claim 1, wherein the task assignment prediction unit is configured to generate task-to-processor predictions prior to task assignment, such that task migration correction during execution is reduced below a predefined threshold. [6] System according to claim 1, wherein the feedback adjustment unit is configured to compare predicted execution results with observed execution metrics such as execution time, memory access latency and processor standstill, and adjusts the prediction weighting parameters stored in non-volatile memory accordingly. [7] System according to claim 1, wherein the plurality of processing units comprises heterogeneous processing units with different computing power, energy efficiency and execution characteristics, and wherein the predictive task assignment unit is configured to match the task execution requirements with the corresponding capabilities of the processor. [8] System according to claim 1, wherein the processor state acquisition unit is further configured to acquire cache coherence state information and indicators of access conflicts in common memory associated with the simultaneous execution of multiple tasks. [9] System according to claim 1, wherein the planning control unit is configured to output processor binding control signals prior to the start of execution, which assign each task to a selected processing unit, thereby preventing reassignment after dispatch unless an execution anomaly is detected.

Images