OPTOELECTRONIC DEVICE

Description

[0001] This patent application claims priority from French patent application FR17 / 56985. Domaine

[0002] The present application relates to an optoelectronic device, in particular a display screen or an image projection device, comprising light-emitting diodes, hereinafter called LEDs, based on semiconductor materials, and their control methods. Exposé de l'art antérieur

[0003] A pixel of an image corresponds to the unit element of the image displayed by the optoelectronic device. When the optoelectronic device is a color image display screen, it generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiation emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the optoelectronic device refers to the assembly formed by the three display sub-pixels used for the display of a pixel of an image.

[0004] Each display sub-pixel may comprise a light source, in particular a light-emitting diode, for example based on semiconductor materials. A known method for manufacturing an optoelectronic device, in particular a display screen or an image projection device, comprising light-emitting diodes, called a "pick and place" method, consists of manufacturing the light-emitting diodes in the form of separate components, and placing each light-emitting diode in a desired position on a support which may comprise conductive tracks for the electrical connection of the light-emitting diodes. US 2009 / 073079 A1 discloses a passive matrix display screen of the prior art.

[0005] A disadvantage of such a method is that it generally requires precise placement of the LEDs on the support. This requires the implementation of alignment processes that become more complex as the dimensions of the LEDs are reduced.

[0006] Another disadvantage of such a method is that an increase in the resolution of the optoelectronic device results in an increase in the number of transfers of light-emitting diodes onto the support and therefore an increase in the manufacturing time of the optoelectronic device which may not be compatible with manufacturing on an industrial scale.

[0007] To create a large LED display made of assembled individual LED components, the LEDs must be assembled with driver circuits that control a certain number of LEDs. The individual units are connected together by wires. This assembly reduces the amount of data that can be transmitted and makes it difficult to display a video stream.

[0008] For micrometer-sized LED displays, later called pLEDs, for formats such as TVs, tablets, and smartphones, which are currently being developed by several manufacturers, an active matrix is ​​required to display a video stream with high resolution. Currently, active matrices for displays are made of thin-film transistors, or TFTs (Thin Film Transistors). TFTs use amorphous or polycrystalline silicon deposits on large glass surfaces and require the use of complex microelectronic processes over large areas.

[0009] The use of so-called smart pixels integrating control electronics with LEDs or pLEDs could make it possible to create active matrices without TFTs. These active matrices could be produced over very large areas because they rely on electronics embedded under the pixel. Furthermore, this electronics would benefit from the performance of silicon-based technology. Large outdoor or indoor screens incorporating this technology could be controlled by active matrix, thereby increasing their brightness and, in addition, could display larger data streams.

[0010] Another advantage of this approach is the ability to create large screens with a very high pixel count. There is no restriction on predefined active TFT matrices or electronics to assemble. Résumé

[0011] Thus, an object of an embodiment is to at least partially overcome the drawbacks of the optoelectronic devices comprising light-emitting diodes described previously.

[0012] Another object of an embodiment is to reduce the number of component transfers onto the support of the optoelectronic device during the manufacture of the optoelectronic device.

[0013] Another object of an embodiment is to reduce precision constraints when placing components on the support of the optoelectronic device.

[0014] Another object of an embodiment is that the optoelectronic devices can be manufactured on an industrial scale and at low cost.

[0015] Another object is that the optoelectronic device comprises an active matrix.

[0016] Another object is that the optoelectronic device allows the display of a video stream.

[0017] Thus, one embodiment provides a method of controlling an optoelectronic device according to claim 1.

[0018] According to one embodiment, the method comprises, after the first phase, a second phase comprising the transmission of data to the electronic circuits connected to said one of the first electrodes and to said one of the second electrodes at the fourth potential by varying the potential of said one of the first electrodes between the first potential and the second potential and by maintaining the potential of said one of the second electrodes at the fourth potential.

[0019] According to one embodiment, the method comprises, during the second phase, transmitting signals of discrete duration and transmitting signals of non-discrete duration.

[0020] According to one embodiment, during the second phase, the electronic circuits connected to said one of the first electrodes and not connected to said one of the second electrodes do not process the transmitted data.

[0021] According to one embodiment, the method comprises turning off the light-emitting diodes of the display pixels connected to said one of the first electrodes and / or to said one of the second electrodes.

[0022] According to one embodiment, each first optoelectronic circuit comprises a first transistor connected in series with the first light-emitting diode, the second phase comprising maintaining said one of the first electrodes at the first potential for a first duration and the first transistor is controlled at a first conduction level which depends on the first duration.

[0023] According to one embodiment, each display pixel comprises at least one second optoelectronic circuit connected to the electronic circuit of said display pixel and comprising at least one second light-emitting diode and a second transistor connected in series with the second light-emitting diode, the second phase comprising maintaining said one of the first electrodes at the first potential for a second duration and the second transistor is controlled at a second conduction level which depends on the third duration.

[0024] According to one embodiment, each display pixel comprises at least one third optoelectronic circuit connected to the electronic circuit of said display pixel and comprising at least one third light-emitting diode and a third transistor connected in series with the third light-emitting diode, the second phase comprising maintaining said one of the first electrodes at the first potential for a third duration and the third transistor is controlled at a third conduction level which depends on the third duration.

[0025] According to one embodiment, the first, second and third durations are successive, said one of the first electrodes being maintained at the second potential between the first duration and the second duration and during the second duration and the third duration.

[0026] An embodiment also provides an optoelectronic device according to claim 10.

[0027] According to one embodiment, the control circuit is adapted, after the first phase, during a second phase, to transmit data to the electronic circuits connected to said one of the first electrodes and to said one of the second electrodes by varying the potential of said one of the first electrodes between the first potential and the second potential and by maintaining the potential of said one of the second electrodes at the fourth potential.

[0028] According to one embodiment, the control circuit is adapted, during the second phase, to transmit signals of discrete duration and signals of non-discrete duration.

[0029] According to one embodiment, during the second phase, the electronic circuits connected to said one of the first electrodes and not connected to said one of the second electrodes are adapted not to process the transmitted data.

[0030] According to one embodiment, the electronic circuits connected to said one of the first electrodes and / or to said one of the second electrodes are adapted to turn off the associated light-emitting diodes.

[0031] According to one embodiment, each first optoelectronic circuit comprises a first transistor connected in series with the first light-emitting diode, the control circuit being adapted, during the second phase, to maintain said one of the first electrodes at the first potential for a first duration, the first optoelectronic circuit being adapted to turn on the first transistor at a first conduction level which depends on the first duration.

[0032] According to one embodiment, each display pixel comprises at least one second optoelectronic circuit connected to the electronic circuit of said display pixel and comprising at least one second light-emitting diode and a second transistor connected in series with the second light-emitting diode, the control circuit being adapted, during the second phase, to maintain said one of the first electrodes at the first potential for a second duration, the second optoelectronic circuit being adapted to turn on the second transistor at a second conduction level which depends on the second duration.

[0033] According to one embodiment, each display pixel comprises at least one third optoelectronic circuit connected to the electronic circuit and comprising at least one third light-emitting diode and a third transistor connected in series with the third light-emitting diode, the control circuit being adapted, during the second phase, to maintain said one of the first electrodes at the first potential for a third duration, the third optoelectronic circuit being adapted to turn on the third transistor at a third conduction level which depends on the third duration.

[0034] According to one embodiment, the first, second and third durations are successive, the control circuit being adapted to maintain said one of the first electrodes at the second potential between the first duration and the second duration and during the second duration and the third duration. Brève description des dessins

[0035] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: THE figures 1 et 2 are respectively a side sectional view and a top view, partial and schematic, of an embodiment of an optoelectronic device; the figure 3 is an equivalent electrical diagram of a display pixel of the optoelectronic device shown in the figures 1 et 2 ; THE figures 4A et 4B are partial, schematic, side sectional views of other embodiments of an optoelectronic device; figure 5 is an equivalent electrical diagram of a display pixel of the optoelectronic device shown in the figure 4B ; there figure 6 is a partial and schematic top view of the optoelectronic device shown in the figures 1 et 2 illustrating an advantage of the manufacturing process of the optoelectronic device; figure 7 is a diagram illustrating the control of the optoelectronic device shown in the figures 1 Or 4 ; THE figures 8A et 8B are partial and schematic top views of other embodiments of an optoelectronic device; figure 9 is a partial, schematic, side sectional view of another embodiment of an optoelectronic device; figures 10 à 12 are partial and schematic top views of other embodiments of optoelectronic devices; figures 13 et 14 are timing diagrams respectively of the potentials applied to the conductive strips connected to a display pixel to be controlled and of the voltage seen between the power supply terminals of the display pixel to be controlled; figure 15 represents an equivalent electrical diagram of an embodiment of a display pixel; the figure 16 represents an equivalent electrical diagram of a part of the display pixel of the figure 15 ; there figure 17 represents a timing diagram of signals during operation of the display pixel of the figure 15 ; THE figures 18 à 21 represent equivalent electrical diagrams of parts of the display pixel of the figure 15 ; there figure 22 represents a timing diagram of signals during operation of the display pixel whose control module is according to the embodiment shown in figure 18 ; there figure 23 represents an equivalent electrical diagram of another embodiment of a display pixel; the figures 24 et 25 represent equivalent electrical diagrams of parts of the display pixel of the figure 23 ; there figure 26 represents a timing diagram of signals during operation of the display pixel of the figure 23 ; THE figures 27A à 27I are partial and schematic side sectional views of structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device shown in the figures 1 et 2 ; and the figures 28A à 28D are partial and schematic side sectional views of structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device shown in the figure 4B . Description détaillée

[0036] The embodiments corresponding to the figures 1-11 And 27A has 28D are not part of the invention as claimed. The invention is defined by the embodiments of the figures 12-26 .

[0037] For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of electronic circuits, the various figures are not drawn to scale. Furthermore, only the elements useful for understanding the present description have been represented and are described. In particular, the structure of a light-emitting diode is well known to those skilled in the art and is not described in detail.

[0038] In the following description, when referring to relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., reference is made to the orientation of the figures or to an optoelectronic device in a normal position of use. Unless otherwise indicated, the terms "substantially", "about", "approximately" and "of the order of" mean "within 10%", preferably within 5%. In addition, the term "active area" of a light-emitting diode refers to the region of the light-emitting diode from which the majority of the electromagnetic radiation provided by the light-emitting diode is emitted. In addition, a "binary signal" refers to a signal that alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example a high state, denoted "1". The high and low states of different binary signals in the same electronic circuit may be different.In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

[0039] THE figures 1 et 2 represent an embodiment of an optoelectronic device 10, for example corresponding to a display screen or an image projection device, comprising display pixels, two display pixels being represented in figure 1 and three display pixels being represented in figure 2 . There figure 1 is a cut of the figure 2 according to line II-II and the figure 2 is a cut of the figure 1 according to line II.

[0040] The device 10 comprises from bottom to top in figure 1 : a support 12 comprising opposite lower and upper faces 14, 16, preferably parallel; a first electrode layer 18 comprising an electrically conductive layer 18 covering the upper face 16; display pixels Pix, also called display pixel circuits hereinafter, resting on the electrode layer 18 and in contact with the electrode layer 18, each display pixel Pix comprising: an electronic circuit 20, called a control circuit hereinafter, having opposite lower and upper faces 22, 24, preferably parallel, the lower face 22 being fixed to the electrode layer 18, possibly by means of a bonding material; optoelectronic circuits 26 fixed to the upper face 24 of the electronic circuit 20, three optoelectronic circuits 26 per display pixel Pix being shown in figure 2 , each optoelectronic circuit 26 comprising at least one light-emitting diode, not shown; an electrically insulating portion 28 covering the optoelectronic circuits 26 and covering the upper face 24 of the control circuit 20 between the optoelectronic circuits 26; electrically conductive elements 30 passing through the insulating portion 28, coming into contact with the optoelectronic circuits 26 and the upper face 24 of the control circuit 20; an electrically insulating layer 32 covering the electrode layer 18 between the display pixels Pix and covering the lateral sides of the electronic circuits 20 and possibly the insulating portions 28;and a second electrode layer 34 comprising an electrically conductive layer at least partially transparent to the radiation emitted by the light-emitting diodes, the conductive layer 34 covering the insulating layer 32 and the insulating portions 28 and being in contact with the conductive elements 30 of each display pixel Pix.;

[0041] An encapsulation layer, not shown, may cover the conductive layer 34.

[0042] When the lower face 22 of the electronic circuit 20 is attached to the electrode layer 18 by a bonding material, the bonding material is preferably electrically conductive. Alternatively, an electrically non-conductive bonding material may be used, for example arranged at the periphery of the lower face 22 of the electronic circuit 20.

[0043] According to one embodiment, each optoelectronic circuit 26 comprises at least one light-emitting diode. In the case where the optoelectronic circuit 26 comprises two or more light-emitting diodes, all the light-emitting diodes of the optoelectronic circuit 26 preferably emit light radiation at substantially the same wavelength.

[0044] Each light-emitting diode may correspond to a so-called two-dimensional light-emitting diode comprising a stack of substantially planar semiconductor layers including the active zone. Each light-emitting diode may comprise at least one three-dimensional light-emitting diode with a radial structure comprising a semiconductor shell covering a three-dimensional semiconductor element, in particular a microwire, a nanowire, a cone, a truncated cone, a pyramid or a truncated pyramid, the shell being formed from a stack of non-planar semiconductor layers including the active zone. Examples of such light-emitting diodes are described in patent applications US2014 / 0077151 and US2016 / 0218240. Each light-emitting diode may comprise at least one three-dimensional light-emitting diode with an axial structure in which the shell is located in the axial extension of the semiconductor element.

[0045] For each display pixel Pix, the optoelectronic circuit 26 can be attached to the control circuit 20 by a "Flip-Chip" type connection. The fusible conductive elements 36, for example solder balls or indium balls, which connect the optoelectronic circuit 26 to the control circuit 20 provide the mechanical connection between the optoelectronic circuit 26 and the control circuit 20 and also provide the electrical connection of the light-emitting diode or light-emitting diodes of the optoelectronic circuit 26 to the control circuit 20. According to another embodiment, each optoelectronic circuit 26 can be attached to the control circuit 20 by direct gluing.

[0046] According to one embodiment, each display pixel Pix comprises at least two types of optoelectronic circuits 26. The optoelectronic circuit 26 of the first type is adapted to emit a first radiation at a first wavelength and the optoelectronic circuit 26 of the second type is adapted to emit a second radiation at a second wavelength. According to one embodiment, each display pixel Pix comprises at least three types of optoelectronic circuits 26, the optoelectronic circuit 26 of the third type being adapted to emit a third radiation at a third wavelength. The first, second and third wavelengths may be different.

[0047] According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0048] According to one embodiment, each display pixel Pix comprises an optoelectronic circuit 26 of a fourth type, the optoelectronic circuit 26 of the fourth type being adapted to emit a fourth radiation at a fourth wavelength. The first, second, third and fourth wavelengths may be different. According to one embodiment, the fourth wavelength corresponds to yellow light and is in the range of 570 nm to 600 nm. According to another embodiment, the fourth radiation corresponds to radiation in the near infrared, in particular at a wavelength between 700 nm and 980 nm, to ultraviolet radiation, or to white light.

[0049] Each optoelectronic circuit 26 may comprise a semiconductor substrate on which the light-emitting diode or light-emitting diodes rests. The semiconductor substrate is, for example, a substrate made of silicon, germanium, silicon carbide, a III-V compound, such as GaN or GaAs, a ZnO substrate, or a sapphire substrate. According to another embodiment, each optoelectronic circuit 26 may not comprise a substrate. A mirror layer may then be arranged on the lower face of the optoelectronic circuit 26 in contact with the light-emitting diode or light-emitting diodes. According to one embodiment, the mirror layer is adapted to reflect at least in part the radiation emitted by the light-emitting diodes.

[0050] Each control circuit 20 may comprise electronic components, not shown, in particular transistors, used for controlling the light-emitting diodes. Each control circuit 26 may comprise a semiconductor substrate in which and / or on which the electronic components are formed. The lower face 22 of the control circuit 20 may then correspond to the rear face of the substrate opposite the front face of the substrate on the side of which the electronic components are formed. The semiconductor substrate is, for example, a silicon substrate, in particular monocrystalline silicon.

[0051] Preferably, the optoelectronic circuits 26 comprise only light-emitting diodes and connection elements for these light-emitting diodes and the control circuits 20 comprise all of the electronic components necessary for controlling the light-emitting diodes of the optoelectronic circuits 26. Alternatively, the optoelectronic circuits 26 may also comprise other electronic components in addition to the light-emitting diodes.

[0052] The optoelectronic device 10 may comprise from 10 to 10 9< display pixels Pix. Each display pixel Pix may occupy, in top view, an area of ​​between 1 µm 2< and 100 mm 2< . The thickness of each display pixel Pix may be between 100 µm and 10 mm. The thickness of each electronic circuit 20 may be between 1 µm and 2000 µm. The thickness of each optoelectronic circuit 26 may be between 0.2 µm and 1000 µm.

[0053] The support 12 may be made of an electrically insulating material, comprising for example a polymer, in particular an epoxy resin, and in particular the FR4 material used for the manufacture of printed circuits, or of a metallic material, for example aluminum. The thickness of the support 12 may be between 100 µm and 10 mm.

[0054] The conductive layer 18 preferably corresponds to a metal layer, for example made of aluminum, silver, copper or zinc. The thickness of the conductive layer 18 may be between 0.5 µm and 1000 µm.

[0055] Each insulating portion 28 may be made of a dielectric material, for example silicon oxide (SiO 2 ), silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4 ), silicon oxynitride (SiO x N y where x may be approximately equal to 1 / 2 and y may be approximately equal to 1, for example Si 2 ON 2 ), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ). The maximum thickness of each insulating portion 28 may be between 0.5 µm and 1000 µm.

[0056] Each conductive element 30 may be made of a material chosen from the group comprising copper, titanium, nickel, gold, tin, aluminum and alloys of at least two of these compounds.

[0057] The insulating layer 32 may be made of a dielectric material, for example silicon oxide (SiO 2 ), silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4 ), silicon oxynitride (SiO x N y where x may be approximately equal to 1 / 2 and y may be approximately equal to 1, for example Si 2 ON 2 ), aluminum oxide (Al 2 O 3 ), or hafnium oxide (HfO 2 ). The thickness of the insulating layer 32 may be between 0.02 µm and 1000 µm. Preferably, the insulating layer 32 is opaque. The insulating layer 32 may correspond to a white resin, a black resin or a transparent resin filled, in particular with titanium particles.

[0058] The conductive layer 34 is adapted to allow the electromagnetic radiation emitted by the light-emitting diodes to pass through. The material forming the conductive layer 34 may be a transparent and conductive material such as indium-tin oxide (or ITO, an acronym for Indium Tin Oxide), zinc oxide doped with aluminum or gallium, or graphene. The minimum thickness of the electrically conductive layer 34 on the display pixels Pix may be between 0.1 µm and 1000 µm.

[0059] The encapsulation layer may be made of an at least partially transparent insulating material. The encapsulation layer may be made of an at least partially transparent inorganic material. For example, the inorganic material is chosen from the group comprising silicon oxides of the type SiO x where x is a real number between 1 and 2 or SiO y N z where y and z are real numbers between 0 and 1 and aluminum oxides, for example Al 2 O 3 . The encapsulation layer may be made of an at least partially transparent organic material. For example, the encapsulation layer is a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate.

[0060] According to one embodiment, in operation, a voltage VE is applied between the electrode layers 34 and 18 to supply the display pixels Pix, in particular the light-emitting diodes of the optoelectronic circuits 26 of the display pixels Pix.

[0061] There figure 3 represents an equivalent electrical diagram of the display pixel Pix shown on the figures 1 et 2 . A first electrode, for example the cathode, of each light-emitting diode LED is connected to the control circuit 20 of the display pixel Pix while the second electrode of each light-emitting diode LED, for example the anode, is connected to the electrode layer 34. The control circuit 20 is connected between the electrode layers 18 and 34 and receives the voltage VE . The circuit 20 controls the light-emitting diodes of the optoelectronic circuits 26.

[0062] There figure 4A is a view analogous to the figure 1 of another embodiment of an optoelectronic device 37 comprising all of the elements of the optoelectronic device 10 with the difference that the insulating layer 32 is not present and that the electrode layer 34 rests on a substrate 38. A method of manufacturing the optoelectronic device 37 comprises the formation of the electrode layer 18 on the support 12, the assembly of the display pixels Pix on the electrode layer 18, the formation of the electrode layer 34 on the substrate 38 and then the hybridization of the display pixels Pix on the electrode layer 34. The support 12 and the substrate 38 may be flexible, which allows the manufacture of a flexible optoelectronic device 37.

[0063] There figure 4B is a view analogous to the figure 1 of another embodiment of an optoelectronic device 40 comprising all the elements of the optoelectronic device 10 with the difference that, for each display pixel Pix, the optoelectronic circuits 26 are integrated in a single optoelectronic circuit 42 covering the upper face 24 of the control circuit 20 of the display pixel Pix and fixed to the upper face 24 of the control circuit 20, for example by the fusible conductive elements 36. Each optoelectronic circuit 42 comprises opposite lower and upper faces 44, 46, preferably parallel, the lower face 44 of the optoelectronic circuit 42 being fixed to the upper face 24 of the control circuit 20.The optoelectronic circuit 42 comprises at least one vertical through-connection 48 or TSV (acronym for Through Silicon Via) formed for example in a portion 47 of the optoelectronic circuit 42, which connects the upper face 46 to the lower face 44 and which is electrically insulated from the rest of the optoelectronic circuit 42. The portion 47 may be made of an electrically insulating material or a semiconductor material. In the latter case, the TSV 48 is surrounded by an electrically insulating layer. The upper face 46 of each optoelectronic circuit 42 is covered by the insulating portion 28. The insulating portion 28 is crossed by an electrically conductive element 30 which is in contact with the TSV 48. According to another embodiment, the power supply of the control circuit 20 is carried out by a means other than the TSV 48.

[0064] According to one embodiment, each TSV 48 may comprise a core of an electrically conductive material, for example polycrystalline silicon, tungsten, copper, aluminum or a refractory metallic material, surrounded by an electrically insulating layer.

[0065] Each optoelectronic circuit 42 comprises at least one first light-emitting diode adapted to emit the first radiation at the first wavelength and a second light-emitting diode adapted to emit the second radiation at the second wavelength. Each optoelectronic circuit 42 may further comprise at least one third light-emitting diode adapted to emit the third radiation at the third wavelength.

[0066] There figure 5 represents an equivalent electrical diagram of the display pixel Pix shown on the figure 3 in the case where each optoelectronic circuit 42 comprises three light-emitting diodes. In this embodiment, the two electrodes of each light-emitting diode LED of the optoelectronic circuit 42 are connected to the control circuit 20 of the display pixel Pix. The control circuit 20 is connected between the electrode layers 18 and 34 and receives the voltage VE . The circuit 20 controls the light-emitting diodes LED of the optoelectronic circuit 26.

[0067] In the present embodiment, the conductive layer 18 is in contact with all the display pixels Pix of the optoelectronic device 10, 40 and the conductive layer 34 is in contact with all the display pixels Pix of the optoelectronic device 10, 40.

[0068] One embodiment of a method for manufacturing the optoelectronic device 10 or 40 comprises manufacturing the display pixels Pix and separately placing each display pixel Pix on the electrode layer 18. According to one embodiment, since the electrode layers 18 and 34 are common to all the display pixels Pix, the connection of the display pixels Pix is ​​simplified and it is not necessary for the placement of each display pixel Pix on the electrode layer 18 to be carried out with high precision. This advantageously makes it possible to implement faster and lower-cost techniques for placing the display pixels Pix on the electrode layer 18. Furthermore, since the light-emitting diodes are pre-assembled on the electronic circuit 20 of the display pixel Pix, the number of transfers to be carried out when mounting the optoelectronic device 10 or 40 is reduced.In the present embodiment, each display pixel Pix may comprise a memory in which an identifier of the pixel is stored. The manufacturing method may comprise a calibration phase in which the position of each display pixel Pix is ​​retrieved based on its identifier. In operation, data may then be transmitted to the pixels based on their identifier.

[0069] There figure 6 represents a schematic top view of the optoelectronic device 10 or 40 illustrating the fact that the display pixels Pix may not be arranged very precisely, for example perfectly aligned in rows and columns, and that some display pixels Pix may be tilted relative to the row and column directions.

[0070] In the embodiments described above, the electrode layer 18 is connected to all of the display pixels Pix and is in the form of an uninterrupted layer extending over most, if not all, of the support 12.

[0071] For each display pixel Pix, the control circuit 20 is adapted to receive control signals and to control, from the received control signals, the light-emitting diodes of the display pixel, in particular the hue, saturation and brightness of the light emitted by the display pixel.

[0072] According to one embodiment, the control signals can be transmitted to the control circuits 20 of the display pixels Pix by modulation of the voltage VE.

[0073] There figure 7 represents very schematically a processing module 49 receiving COM control signals and adapted to supply the optoelectronic device 10 or 40 with a voltage VE for supplying the display pixels Pix which is modulated with the COM control signals. The processing module 49 may correspond to a dedicated circuit or may comprise a processor, for example a microprocessor or a microcontroller, adapted to execute instructions of a computer program stored in a memory.

[0074] The control circuit 20 of each display pixel Pix can extract the COM control signals by demodulating the voltage VE. The control circuit 20 can then determine whether the COM control signals are intended for it. For example, an identifier can be associated with each display pixel Pix and the COM control signals obtained by demodulating the voltage VE can include the identifier of the display pixel to which these control signals are intended.

[0075] Advantageously, active addressing of the display pixels Pix can be achieved. Indeed, each control circuit 20 can control the maintenance of the display properties, in particular the hue, saturation and brightness, of the display pixel until it receives new control signals.

[0076] There figure 8A represents a schematic top view of another embodiment of an optoelectronic device 50 comprising all the elements of the optoelectronic device 10 or 40 in which the electrode layer 18 is divided into parallel electrically conductive strips 52 extending on the support 12, three strips 52 being represented by way of example on the figure 8 . At least one row of display pixels Pix is ​​distributed on each conductive strip. Preferably, several rows of display pixels Pix are distributed on each conductive strip 52, three rows of display pixels Pix being represented per conductive strip 52 as an example on the figure 8 .

[0077] According to another embodiment, the electrode layer 18 and / or the electrode layer 34 may be divided into separate electrode portions. According to another embodiment, the electrode layer 34 may also be divided into parallel and electrically conductive strips. When the electrode layers 18 and 34 are each divided into strips, the strips of the electrode layer 18 preferably have substantially the same dimensions as the strips of the electrode layer 34 and each strip of the electrode layer 34 substantially covers only one of the strips of the electrode layer 18. According to another embodiment, one of the electrodes 18 or 34 may be common to the display pixels Pix while the other electrode 18 or 34 is divided into parallel and electrically conductive strips.

[0078] In the embodiment in which the electrode layers 18, 34 are divided into superimposed strips sandwiching sets of display pixels, different control signals can be transmitted in parallel by modulating the voltage VE differently for each set of display pixels. This allows the control signals for each set of display pixels Pix to be transmitted in parallel. This makes it possible to reduce the modulation frequency of the electromagnetic radiation and / or to increase the transmitted data rate.

[0079] There figure 8B is a partial and schematic top view of another embodiment of an optoelectronic device 55 in which the electrode layer 18 is divided into conductive strips 56 extending in the direction of the rows and in which the electrode layer 34 is divided into conductive strips 58 extending in the direction of the columns, and called column electrodes. At least one display pixel Pix is ​​disposed at the intersection, in top view, between each row electrode 56 and each column electrode 58 and is connected to the row electrode 56 and to the column electrode 58. For example, in figure 8B , three display pixels Pix are provided at the intersection, in top view, between each row electrode 56 and each column electrode 58 and form one pixel of the image to be displayed. When several display pixels Pix are provided for each pixel of the image to be displayed, this allows for redundancy in case one of the display pixels Pix is ​​defective.

[0080] There figure 9 is a view analogous to the figure 1 of another embodiment of an optoelectronic device 60 comprising all of the elements of the optoelectronic device 10 and further comprising a stack of a first layer 62 and a second layer 64 covering the electrode layer 34. The layer 62 is composed of a material whose refractive index is greater than the refractive index of the material composing the layer 64. The layers 62 and 64 are at least partially transparent to the radiation emitted by the display pixels Pix. The layer 64 is for example made of glass, SiO 2 , Al 2 O 3 , HfO 2 , an organic material, for example a polymer, in particular poly(methyl methacrylate) (PMMA). The layer 62 corresponds for example to an air film. The layer 64 forms a waveguide for electromagnetic radiation 66, for example in the visible range or outside the visible range, preferably in a wavelength range between the infrared and ultraviolet range.The optoelectronic device 60 comprises an optoelectronic circuit 68 adapted to emit such radiation 66 into the layer 64. The optoelectronic circuit 68 may be located at the periphery of the layer 64 and emit the radiation 66 into the layer 64 from the lateral edge thereof. The infrared radiation is modulated to carry the control signals described above. According to one embodiment, an optical coupling means 70 is provided between each display pixel Pix and the waveguide 64 so that a fraction 72 of the radiation 66 guided in the waveguide 64 escapes at each display pixel Pix via the coupling means 70. By way of example, the coupling means 70 corresponds to a texturing provided on the layer 64 and / or on the layer 62 opposite each display pixel Pix to ensure the optical coupling between each display pixel Pix and the layer 64.The coupling means 70 corresponds, for example, to a diffraction grating making it possible to return part of the light propagating in the waveguide 64 towards the associated display pixel Pix.

[0081] Each display pixel Pix comprises at least one sensor 74 adapted to detect the radiation emitted by the optoelectronic circuit 68, for example a photodiode or a photoresistor, the sensor providing the control circuit 20 with an electrical signal representative for example of the intensity of the radiation 72 received by the display pixel Pix. The control circuit 20 is connected to the sensor and is adapted to extract the control signals from the measurement signal provided by the sensor.

[0082] According to one embodiment, the same electromagnetic radiation carrying the control signals is transmitted to all the display pixels Pix. According to another embodiment, several waveguides can be provided, each waveguide being associated with a set of display pixels. According to another embodiment, optical break zones can be made in the waveguide to be able to address different groups of pixels.

[0083] There figure 10 is a partial and schematic top view of another embodiment of an optoelectronic device 80 comprising disjoint waveguides 82, or a single waveguide having optical discontinuities, each covering a set of display pixels, not shown. The optoelectronic device 80 further comprises optoelectronic circuits 84 each adapted to emit in the associated waveguide 82 electromagnetic radiation in the non-visible range. This makes it possible to transmit in parallel the control signals for each set of display pixels Pix. This makes it possible to reduce the modulation frequency of the electromagnetic radiation and / or to increase the transmitted data rate.

[0084] There figure 11 is a partial and schematic top view of another embodiment of an optoelectronic device 90 comprising all of the elements of the device 80, each disjoint waveguide 82 covering at least one row of display pixels.

[0085] In the present embodiment, the electrode layer 34 or the electrode layer 18 is divided into conductive strips 92 extending along the column direction. Each conductive strip 92 is connected to the display pixels of at least one pixel column.

[0086] An embodiment of a method for controlling display pixels comprises a phase of selecting a display pixel or a group of display pixels via the electrodes 18, 92 followed by a phase of transmitting data to some of the selected display pixels by one of the waveguides 82. The selection phase can be carried out by bringing the conductive strip 92 connected to the display pixels to be selected to a first potential while the other conductive strips 92 are maintained at a second potential different from the first potential. Only the display pixels that are selected are active and are adapted to process data transmitted by electromagnetic radiation. The other display pixels are inactive and ignore the data that is transmitted by the radiation. The radiation carrying the data is then emitted into the waveguide 82 which covers the display pixels of interest.Only the display pixels that have been selected and are covered by the waveguide 82 will process the data obtained by detecting the radiation transmitted by the waveguide 82.

[0087] According to one embodiment, each conductive strip 92 is connected to the display pixels of a single column of display pixels and each waveguide 82 covers only one row of display pixels. The control method described above then makes it possible to select and transmit data to only a single display pixel.

[0088] There figure 12 is a partial and schematic top view of an embodiment of an optoelectronic device 100 according to the invention in which the electrode layer 18 is divided into conductive strips 102 extending in the direction of the rows, and called row electrodes, each conductive strip 102 being connected to the display pixels Pix of a row of pixels and in which the electrode layer 34 is divided into conductive strips 104 extending in the direction of the columns, and called column electrodes, each conductive strip 104 being connected to the display pixels Pix of a column of pixels.

[0089] As it appears on the figure 12 , the width of each conductive strip 102 is greater than the dimension of the display pixel Pix measured along the column direction and the width of each conductive strip 104 is greater than the dimension of the display pixel Pix measured along the row direction. Therefore, for each row, the display pixels Pix belonging to the row may not be perfectly aligned. Similarly, for each column, the display pixels Pix belonging to the column may not be perfectly aligned.

[0090] An embodiment of a method for controlling a display pixel Pix according to the invention comprises a phase of selecting the display pixel followed by a phase of transmitting data to the display pixel Pix.

[0091] There figure 13 is a timing diagram respectively of the potentials Vpix+ and Vpix- applied respectively to the column and row electrodes connected to a display pixel to be controlled and the figure 14 is a timing diagram of the sig voltage seen between the power supply terminals of the display pixel to be controlled.

[0092] According to the invention, the optoelectronic circuit 100 is adapted to vary the potential of each row electrode between two values ​​V0 and V1, V1 being strictly greater than V0, and to vary the potential of each column electrode between two values ​​V2 and V3, V3 being strictly greater than V2 and V2 being strictly greater than V1. The difference between V3 and V2 can be equal to the difference between V1 and V0.

[0093] According to the invention, the control method comprises a phase S1 of selecting a display pixel to be controlled followed by a phase S2 of transmitting data to the selected display pixel.

[0094] Phase S1 involves bringing the row electrode connected to the display pixel to be driven to V0, leaving the other row electrodes at V1, and bringing the column electrode connected to the display pixel to be driven to V3, leaving the other row electrodes at V2. The display pixel to be driven then sees a voltage equal to V3-V0, while the other display pixels in the same row see a voltage equal to V2-V0, the other display pixels in the same column see a voltage equal to V3-V1, and the other display pixels in the other rows and columns see a voltage equal to V2-V1. All display pixels other than the display pixel to be driven see a voltage lower than V3-V0.

[0095] Phase S2 consists of varying the potential of the column electrode of the display pixel to be driven between V2 and V3 while leaving the row electrode of the display pixel to be driven at V1. As a result, the voltage seen by the display pixel to be driven varies as the potential of the column electrode.

[0096] Each display pixel is adapted to detect whether, in phase S1, the supply voltage applied to it is greater than a threshold. When a display pixel detects that, in phase S1, the supply voltage applied to it is greater than the threshold, it is adapted to process the data which is then transmitted during phase S2. When a display pixel detects that, in phase S1, the supply voltage applied to it is less than the threshold, it does not process the data which is then transmitted to it during phase S2.

[0097] The present embodiment makes it possible to select a display pixel while maintaining the power supply of the other display pixels. The present embodiment further makes it possible to transmit data to a single display pixel of a matrix of display pixels. Advantageously, all the display pixels of the matrix can correspond to identical optoelectronic devices. This simplifies the design of the display pixels and the mounting of the display pixels. The present embodiment further makes it possible to transmit data simultaneously to several display pixels, or even to transmit data simultaneously to all the display pixels. Furthermore, the fact that the potential of one of the electrodes remains constant during the S2 phase advantageously allows the display pixel to have a constant potential reference during the S2 phase, which simplifies the processing of signals by the display pixel.

[0098] The data transmitted during phase S2 can be binary data and / or analog data. The transmitted data can be modulated. This can be frequency modulation, amplitude modulation, phase modulation, or pulse width modulation.

[0099] For example, on the figures 13 et 14 , the S2 phase successively comprises a Scom sub-phase corresponding to the transmission of binary data, an SR phase corresponding to the transmission of a command for a first display sub-pixel, for example the red display sub-pixel, an SG phase corresponding to the transmission of a command for a second display sub-pixel, for example the green display sub-pixel and an SB phase corresponding to the transmission of a command for a third display sub-pixel, for example the blue display sub-pixel. As a variant, the Scom sub-phase may not be present.

[0100] According to one embodiment, each sub-phase SR, SG and SB comprises the transmission of a voltage pulse whose duration is representative of the desired activation duration of the display sub-pixel considered.

[0101] There figure 15 represents an equivalent electrical diagram of an embodiment of the Pix display pixel.

[0102] The display pixel Pix is ​​connected to one of the column electrodes 104 which is at potential Vpix+ and to one of the row electrodes 102 which is at potential Vpix-.

[0103] The display pixel Pix comprises a processing module CM (Signal Processor), a module CR for controlling a first display sub-pixel (Red Pixel), for example the red display sub-pixel, a module CG for controlling a second display sub-pixel (Green Pixel), for example the green display sub-pixel, and a module CB for controlling a third display sub-pixel (Blue Pixel), for example the blue display sub-pixel. The electronic components of the processing module CM are located at the control circuit 20. The electronic components of the modules CR, CG, CB may be located at the control circuit 20 and / or at the optoelectronic circuits 26.

[0104] Each module CM, CR, CG and CB is connected to the column and row electrodes 102, 104 associated with the potentials Vpix+ and Vpix- for their power supply. The control circuit CM receives the potential values ​​Vpix+ and Vpix- and an end signal as input signals and provides three binary signals data, write and clear. According to one embodiment, the modules CR, CG and CB are identical and each module CR, CG and CB includes three inputs write capacitor, write enable and clear pixel and one output write done. Alternatively, the module CB may be different from the modules CR and CG and not include a write done output. The write capacitor inputs of each module CR, CG and CB each receive the data signal. The clear pixel inputs of each module CR, CG and CB each receive the clear signal. The input write enable of the module CR receives the write signal.The write enable input of the CG module is connected to the write done output of the CR module and the write enable input of the CB module is connected to the write done output of the CG module. In the embodiment illustrated in . figure 15 , the write done output of the CB module provides the end signal received by the CM module.

[0105] There figure 16 represents an equivalent electrical diagram of an embodiment of the CR module, the CG and CB modules possibly being identical.

[0106] According to one embodiment, the CR module comprises a light-emitting diode LED whose anode is connected to the electrode at potential Vpix+ and whose cathode is connected to a control terminal among the drain or the source of a MOS transistor T1 and whose other control terminal is connected to the electrode at potential Vpix-. The CR module further comprises a capacitor C1 whose one electrode is connected to the gate of the transistor T1 and whose other electrode is connected to the electrode at potential Vpix-. The CR module further comprises a MOS transistor T2 whose one control terminal among the drain or the source is connected to the gate of the transistor T1 and whose other control terminal is connected to the electrode at potential Vpix-. The gate of the transistor T2 is connected to the clear pixel input. The CR module further comprises a three-input AND logic gate AND1, two inputs of which correspond to the write enable and write capacitor inputs of the CR module.The AND1 logic gate provides a control enable signal to a current source CS, one terminal of which is connected to the electrode at potential Vpix+ and the other terminal of which is connected to the gate of transistor T1. The CR module also includes an RS flip-flop RS1, the S input of which, sensitive to falling edges, receives the enable signal, the R input of which is connected to the clear pixel input of the CR module and the Q output of which is connected to the third input of the AND1 logic gate. The Q output of the RS1 flip-flop is connected to the write done output of the CR module. In operation, the intensity of the current flowing through the light-emitting diode LED depends on the conduction of transistor T1, which is set by the voltage across capacitor C1. The higher the voltage across capacitor C1, the more transistor T1 is on.

[0107] There figure 17 represents a timing diagram of signals during a control cycle of the display pixel of the figure 15 . We call t0, t1, t2, t3, t4, t5, t6 and t7 successive instants. The write enable output of the CR module provides the Red Done signal. The write enable output of the CG module provides the Green Done signal. The write enable output of the CB module provides the Blue Done signal.

[0108] The Red Cap, Green Cap and Blue Cap signals correspond to the voltages across capacitors C1 of modules CR, CG and CB respectively. The sig signal corresponds to the difference between potentials Vpix+ and Vpix-. The sig signal can take three discrete values ​​"0", "1" and "2".

[0109] In the present embodiment, the data signal is equal to the sig signal outside the selection phase and the write signal is set to "1" during the display subpixel control phases.

[0110] At time t0, the Red Done, Green Done, and Blue Done signals are "1," the sig signal is "0," and the clear signal is "0." At time t1, the sig signal changes from "0" to "2." The CM module detects that the display pixel is selected and sets the clear signal to "1." At time t2, the sig signal changes to "0." The CM module then sets the write signal to "1" and the clear signal to "0." This initializes the RS1 flip-flops of the CR, CG, and CB modules, sets the Red Done, Green Done, and Blue Done signals to "0," and empties the C1 capacitors of the CR, CG, and CB modules, setting the Red Cap, Green Cap, and Blue Cap voltages to 0. At time t3, the drive phase of the red display subpixel begins. In the present embodiment, the red display subpixel is activated, and the sig signal changes to "1." The data signal is equal to the sig signal so that the capacitor C1 of the CR module is charged by the current source CS until time t4 at which the sig and data signals go to "0".The Red Done signal then changes to "1". At time t5, the green display sub-pixel control phase begins. In the present embodiment, the green display sub-pixel is not activated and the sig signal changes to "1" for a very short time. The capacitor C1 of the CG module is then substantially not charged and the Green Done signal then changes to "1". At time t6, the blue display sub-pixel control phase begins. In the present embodiment, the blue display sub-pixel is activated and the sig signal changes to "1". The data signal is equal to the sig signal so that the capacitor C1 of the CR module is charged by the current source CS until time t7 at which time the sig and data signals change to "0". The Blue Done signal then changes to "1".

[0111] There figure 18 represents an equivalent electrical diagram of another embodiment of the CM module adapted to the case where the end signal is supplied by the write output of the CG module, the CR, CG modules corresponding for example to the electrical diagram represented on the figure 20 described below and the CB module corresponding for example to the electrical diagram shown on the figure 21 described below. In the present embodiment, during the transmission phase S2, the data signal is equal to the sig signal delayed by a given duration ΔT and the write signal is equal to the sig signal.

[0112] The CM module comprises a start detector block comprising an s+ input connected to the electrode at potential Vpix+ and an s- input connected to the electrode at potential Vpix- and providing a binary start signal. The start detector block is adapted to detect that the sig signal, which corresponds to the voltage between the s+ and s- inputs, changes to "2" and is adapted to set the start signal to "1" when the sig signal changes back to "0".

[0113] The CM module includes a data extractor block comprising an s+ input connected to the electrode at Vpix+ potential, an s- input connected to the electrode at Vpix- potential and an enable input receiving the start signal. The block provides the clear signal and the raw_data signal which is extracted from the sig signal, and which corresponds for example to a binary version of the sig signal outside the selection phase.

[0114] The CM module includes a zero detector block receiving the raw_data signal and providing the write signal equal to the raw_data signal and providing the data signal which is equal to the raw_data signal whose duration of each pulse at "1" is reduced by the duration ΔT, the start of each pulse being delayed by the duration ΔT and the end of each pulse not being modified so that if the pulse of the raw_data signal is less than the duration ΔT, the data signal does not include a corresponding pulse.

[0115] There figure 19 represents an electrical diagram of a more detailed embodiment of the CM module shown in figure 18 .

[0116] The CM module comprises a first voltage divider bridge comprising two resistors R1 and R2 connected in series between the electrode at potential Vpix+ and the electrode at potential Vpix-. The midpoint of the first divider bridge supplies a succession of two inverters INV1 and INV2 in series, the second inverter INV2 providing the start signal. The CM module comprises an RS flip-flop RS2 whose input S receives the start signal and whose input R, sensitive to falling edges, receives an end signal. The end signal is provided by the write done output of the CG module as described in figure 20 The CM module includes a NOR1 NOR logic gate whose first input receives the start signal, whose second input is connected to the Q output of the RS2 flip-flop and which provides the enable signal.

[0117] The CM module includes a second voltage divider bridge comprising two resistors R3 and R4 connected in series between the electrode at potential Vpix+ and the electrode at potential Vpix-. The CM module includes three MOS transistors T3, T4 and T5 in series between the electrode at potential Vpix+ and the electrode at potential Vpix-. Transistor T3 is P-channel and transistors T4 and T5 are N-channel. The gates of transistors T3 and T4 receive the enable signal. The midpoint of the second divider bridge supplies the gate of transistor T5.

[0118] The source of transistor T3 powers an inverter INV3 which provides the write signal. The CM module includes a two-input AND logic gate AND2 whose first input receives the write signal. The CM module includes a resistor R5 connected between the output of inverter INV3 and the second input of the AND2 gate. The CM module includes a capacitor C2 whose one electrode is connected to the second input of the AND2 gate and whose other electrode is connected to the electrode at potential Vpix-. The output of the AND2 gate provides the data signal.

[0119] There figure 20 represents an equivalent electrical diagram of another embodiment of the CR module, the CG module possibly being identical. The CR module includes all the elements of the module represented in figure 16 with the difference that the S input of the RS1 flip-flop is connected to the write enable input of the CR module and that it includes a two-input AND logic gate AND3 whose first input receives the Q signal, whose second input is connected to the write enable input and whose output is connected to the write done output.

[0120] There figure 21 represents an equivalent electrical diagram of another embodiment of the CB module. The CB module comprises all the elements of the module represented in figure 16 with the difference that the RS1 flip-flop is not present and the three-input AND1 logic gate is replaced by a two-input AND4 logic gate, the first input of which is connected to the write capacitor input of the CB module and the second input of which is connected to the write enable input of the CB module and providing the enable signal.

[0121] There figure 22 represents a timing diagram of signals during a control cycle of the display pixel of the figure 18 . We call t'0, t'1, t'2, t'3, t'4, t'5, t'6, t'7, t'8 and t'9 successive instants. The Red write enable, Green write enable and Blue write enable signals correspond to the signals received respectively by the write enable inputs of the CR, CG and CB modules.

[0122] The signals evolve at times t'0, t'1, t'2 in the same way as previously described for signals t0, t1 and t2. At time t'3, the control phase of the red display sub-pixel begins. In the present embodiment, the red display sub-pixel is activated and the sig signal changes to "1". The data signal is equal to the sig signal delayed by a duration ΔT so that the capacitor C1 of the CR module is charged by the current source CS from time t'4 until time t'5 at which time the sig, data and Red write enable signals change to "0". The write done signal of the CR module then becomes equal to the Red write enable signal. At time t'6, the control phase of the green display sub-pixel begins. In the present embodiment, the green display sub-pixel is not activated and the sig signal changes to "1" for a duration less than ΔT. The write and Green write enable signals also go to "1" during this very short duration.However, the data signal remains at "0" so that the capacitor C of the CG module is not charged. The write done signal of the CR module then becomes equal to the Green write enable signal. At time t'7, the control phase of the blue display sub-pixel begins. In the present embodiment, the blue display sub-pixel is activated and the sig signal goes to "1". The data signal is equal to the sig signal delayed by a duration ΔT so that the capacitor C of the CB module is charged by the current source CS from time t'8 until time t'9 at which time the sig, data, Red write enable, Green write enable and Blue write enable signals go to "0".

[0123] According to one embodiment, the display pixel can be realized with less than 150 MOS transistors, 5 resistors and 4 capacitors. It can thus occupy a reduced surface area.

[0124] There figure 23 represents an electrical diagram of another embodiment of the Pix display pixel.

[0125] The display pixel Pix is ​​connected to one of the column electrodes 102 which is at potential Vpix+ and to one of the row electrodes 104 which is at potential Vpix-.

[0126] The display pixel Pix comprises a level detection module M1, a rising front detector module M2 and a ring counter M3 and the display subpixel control modules CR, CG and CB. The electronic components of the modules M1, M2 and M3 are located at the control circuit 20. The electronic components of the modules CR, CG, CB may be located at the control circuit 20 and / or at the optoelectronic circuits 26.

[0127] Each module M1, M2, M3, CR, CG and CB is connected to the associated column and row electrodes 102, 104 to the potentials Vpix+ and Vpix- for their power supply.

[0128] Module M1 receives the potential values ​​Vpix+ and Vpix- as input signals at V+ and V- inputs respectively and a binary Reset signal and provides a binary Detect enable signal and a binary Clear signal. Module M2 receives the potential values ​​Vpix+ and Vpix- as input signals at V+ and V- inputs respectively and the binary Detect enable signal at an Enable input and provides a binary Clock signal. Module M3 receives the binary Clock signal and provides three binary signals b0, b1 and b2. The falling edge of b2 resets module M1.

[0129] Each CR, CG, and CB module includes a Cap reset input and a Prog input. The Cap reset input of each CR, CG, and CB module receives the Detect enable signal. The Prog input of the CR module receives the b0 signal, the Prog input of the CG module receives the b1 signal, and the Prog input of the CB module receives the b2 signal.

[0130] In the present embodiment, the module M1 is adapted to detect that the display pixel is selected by an increase in the signal sig. When a selection has been detected, the module M2 detects the rising edges of the signal sig. The capacitors of the modules CR, CG and CB are charged sequentially, the transition from one module to another being triggered by a falling edge of the signal sig. At the beginning of each sequence, the capacitors of the modules CR, CG and CB are discharged.

[0131] There figure 24 represents an embodiment of the M3 module. The M3 module comprises a succession of four D-type flip-flops with asynchronous / S and / R inputs D1, D2, D3 and D4. The ck input of each flip-flop D1, D2 and D3 receives the Clock signal. The Q output of flip-flop D1 is connected to the D input of flip-flop D2, the Q output of flip-flop D2 is connected to the D input of flip-flop D3 and the Q output of flip-flop D3 is connected to the D input of flip-flop D4. The output of flip-flop D1 is at "1" when the counter is initialized, while the outputs of the other flip-flops are at logic state "0". Bit b0 corresponds to the signal provided by the Q output of flip-flop D2, bit b1 corresponds to the signal provided by the Q output of flip-flop D3 and bit b2 corresponds to the signal provided by the Q output of flip-flop D4. The Clear signal from module M1 is supplied to inverter INV9 and feeds the / S input of flip-flop D1 as well as the / R inputs of flip-flops D2, D3 and D4.

[0132] There figure 25 represents an embodiment of the CR module. The CG and CB modules may have the same structure. The CR module has the same structure as the CR module shown in figure 16 with the difference that the logic gate AND1 and the flip-flop RS1 are not present, that the current source CS is controlled by the signal received at the Prog input of the CR module and that the gate of the transistor T2 is controlled by the signal received at the Cap_reset input of the CR module.

[0133] There figure 26 represents a timing diagram of signals during a control cycle of the display pixel of the figure 23 . We call t"0, t"1, t"2, t"3, t"4, t"5, t"6, t"7, t"8, t"9, t"10, t"11 and t"12 successive instants.

[0134] At time t"0, the signals sig, Cap_reset, detect enable, up, b0, b1 and b2 are at "0". At time t"1, the signal sig changes from "0" to "2". The module M1 detects that the display pixel is selected and sets the signal Clear and the signal detect enable to "1". At time t"2, the signal sig changes to "1" and the module M1 changes the signal Clear to "0". At time t"3, the SR phase of driving the red display sub-pixel begins. In the present embodiment, the red display sub-pixel is activated and the signal sig changes to "2". The clock signal is set to "1" from time t"3 to time t"4. The signal b0 is set to "1" at time t"3. At time t"5, the signal sig changes to "1". At time t"6, the signal sig changes to "2", the SG phase of driving the green display sub-pixel begins while the phase of driving the red sub-pixel is completed. In the present embodiment, the green display sub-pixel is activated.The clock signal is set to "1" from time t"6 to time t"7. The signal b1 is set to "1" at time t"6. The signal b0 is set to "0" at time t"6. At time t"8, the signal sig changes to "2", the SB phase of driving the blue display sub-pixel begins. In the present embodiment, the blue display sub-pixel is activated. The clock signal is set to "1" from time t"8 to time t"9. The signal b2 is set to "1" at time t"8. The signal b1 is set to "0" at time t"8. At time t"10, the signal sig changes to "1". At time t"11, the sig signal is set to "2". The end of the transaction is signaled. At time t"11, the clock signal is set to "1" and the b2 signal is set to "0", the SB phase of control of the blue sub-pixel ends. At time t"12, the sig signal goes to "1" then to "0".

[0135] According to one embodiment, the display pixel can be realized with less than 150 MOS transistors, 3 resistors and 4 capacitors. It can thus occupy a reduced surface area.

[0136] In order to optimize the data transfer conditions, all embodiments could integrate a function to turn off the pixels of the addressed row or column for the duration of the communication, which will limit the load to be driven during data transfer. Adding such a functionality could be done by reducing the potential difference Vpix+ - Vpix-.

[0137] THE figures 27A à 27H are partial and schematic sectional views of structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device 10 shown in the figures 1 et 2 , which is not part of the invention as claimed.

[0138] There figure 27A represents the structure obtained after the manufacture of an electronic circuit 110 comprising several copies of the desired control circuit 20, four copies of the control circuit 20 being represented as an example in figure 27A The method of manufacturing the electronic circuit 110 may comprise conventional steps of a method of manufacturing an integrated circuit.

[0139] There figure 27B represents the structure obtained after fixing the optoelectronic circuits 26 on the electronic circuit 110. The methods of assembling the optoelectronic circuits 26 on the electronic circuit 110 may include soldering operations.

[0140] There figure 27C represents the structure obtained after the deposition of an electrically insulating layer 112 covering the optoelectronic circuits 26 and the electronic circuit 110 between the optoelectronic circuits 26. The insulating layer 112 is of the same material as the insulating portions 28 described previously. The insulating layer 112 may be SiO 2 , SiN, Al 2 O 3 , ZrO 2 , HfO 2 or any other dielectric material deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or sputtering.

[0141] There figure 27D represents the structure obtained after the formation of the conductive elements 30 in the insulating layer 112. The conductive elements 30 can be formed by etching openings in the insulating layer 112 stopping on the optoelectronic circuits 26 and / or the control circuits 20, by depositing a conductive layer on the entire structure obtained and by removing the part of the conductive layer outside the openings.

[0142] There figure 27E represents the structure obtained after cutting the electronic circuit 110 and the insulating layer 112 to delimit the display pixels Pix.

[0143] There figure 27F represents the structure obtained after having fixed the display pixels Pix to the electrode layer 18 which was previously deposited on the support 12. By way of example, each display pixel Pix can be fixed to the electrode layer 18 by molecular bonding or by means of a bonding material, in particular an electrically conductive epoxy glue.

[0144] There figure 27G represents the structure obtained after forming the insulating layer 32 on the display pixels Pix and on the electrode layer 18 between the display pixels Pix. The insulating layer 32 may be SiO 2 , SiN, Al 2 O 3 , ZrO 2 , HfO 2 or any other dielectric material.

[0145] There figure 27H represents the structure obtained after the removal of the insulating layer 32 at the top of each display pixel Pix. According to one embodiment, the removal can be carried out by chemical mechanical polishing or CMP (English acronym for Chemical Mechanical Planarization) with stopping on the insulating portions 28. According to another embodiment, this can be obtained by chemical etching of the insulating layer 32. According to another embodiment, the removal can be carried out by a so-called lift-off method comprising the deposition of a sacrificial layer at the top of each display pixel Pix before the deposition of the insulating layer 32, and, after the deposition of the insulating layer 32, the removal of the sacrificial layer and of the part of the insulating layer 32 covering the sacrificial layer.

[0146] There figure 27I represents the structure obtained after the formation of the electrode layer 34. The electrode layer 34 may be TCO deposited by CVD, PECVD, ALD, sputtering or evaporation.

[0147] THE figures 28A à 28D are partial and schematic sectional views of structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device shown in the figure 4B , which is not part of the invention as claimed.

[0148] There figure 28A represents the structure obtained after the formation of an optoelectronic circuit 90 comprising several copies of the optoelectronic circuit 42, three copies of the optoelectronic circuit 42 being represented as an example in figure 27A . For example, in figure 28A , each optoelectronic circuit 42 is shown comprising two optoelectronic circuits 26 separated by the portion 47.

[0149] There figure 28B represents the structure obtained after the formation of the TSVs 48 passing through the optoelectronic circuits 64. Each TSV 48 can be formed by etching an opening passing through the optoelectronic circuit 90. This opening can have a circular or rectangular cross-section. The etching can be a deep reactive ion etching (DRIE). An insulating layer is then deposited on the walls of the opening. The insulating layer is, for example, produced by conformal deposition by PECVD or by conformal deposition of an insulating polymer. The insulating layer has a thickness of between 10 nm and 5000 nm, for example approximately 3 µm. The filling of the TSV can then be carried out by electrolytic deposition of copper.

[0150] There figure 28C represents the structure obtained after the deposition of an insulating layer 92 on the optoelectronic circuit 90. The insulating layer 92 is of the same material as the insulating portions 28 described previously. The insulating layer 92 can be deposited by CVD, PECVD, ALD or cathode sputtering.

[0151] There figure 28D represents the structure obtained after the formation of the conductive elements 30 in the insulating layer 92.

[0152] The subsequent steps of the process may be the same as those described previously in relation to the figures 27E à 27I .

[0153] Various embodiments with various variations have been described above. It will be noted that those skilled in the art will be able to combine various elements of these various embodiments and variations without demonstrating inventive step. For example, the electrical diagram shown in the figure 3 can be implemented with the structure of the device 40 shown in figure 4B and the electrical diagram shown on the figure 5 can be implemented with the structure of the device 10 shown in the figures 1 et 2 .

Claims

1. A method of controlling an optoelectronic device (10; 40; 50; 60; 70) comprising display pixels (Pix) arranged in rows and in columns, each display pixel comprising an electronic circuit (20; CM) and at least one first optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit and comprising at least one first light-emitting diode (LED), the optoelectronic device further comprising first electrodes (102) extending along the rows, each first electrode being connected to the electronic circuits of display pixels of at least one of the rows, second electrodes (104) extending along the columns, each second electrode being connected to the electronic circuits of display pixels of at least one of the columns, and a circuit for controlling the first and second electrodes, the method being characterized in that it comprises, in a first phase, activating the electronic circuits connected to one of the first electrodes and to one of the second electrodes by the following steps, carried out simultaneously: taking one of the first electrodes to a first potential (V1), the other first electrodes being maintained at a second potential (V0) smaller than the first potential; and taking one of the second electrodes to a third potential (V2) smaller than the second potential, the other second electrodes being maintained at a fourth potential (V3) greater than the third potential and smaller than the second potential.

2. The control method of claim 1, comprising, after the first phase, a second phase comprising transmitting data to the electronic circuits (20; CM) connected to said one of the first electrodes (102) and to said one of the second electrodes (104) by varying the potential of said one of the first electrodes between the first potential and the second potential and by maintaining the potential of said one of the second electrodes at the fourth potential.

3. The control method of claim 2, comprising, during the second phase, transmitting signals having a discrete duration and transmitting signals having a non-discrete duration.

4. The control method of claim 2 or 3, wherein, during the second phase, the electronic circuits (20; CM) coupled to said one of the first electrodes (102) and which are not coupled to said one of the second electrodes (104) do not process the transmitted data.

5. The control method of any of claims 2 to 4, comprising turning off the light-emitting diodes (LED) of the display pixels (Pix) coupled to said one of the first electrodes (102) and / or to said one of the second electrodes (104).

6. The control method of any of claims 1 to 5, wherein each first optoelectronic circuit (CR, CG, CB) comprises a first transistor (T1) series-assembled with the first light-emitting diode (LED), the second phase comprising maintaining said one of the first electrodes (102) at the first potential for a first time period and wherein the first transistor is controlled at a first conduction level which depends on the first time period.

7. The control method of claim 6, wherein each display pixel comprises at least one second optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit (20; CM) of said display pixel and comprising at least a second light-emitting diode (LED) and a second transistor (T1) series-assembled with the second light-emitting diode (LED), the second phase comprising maintaining said one of the first electrodes (102) at the first potential for a first time period and wherein the second transistor is controlled at a second conduction level which depends on the third time period.

8. The control method of claim 7, wherein each display pixel (Pix) comprises at least one third optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit of said display pixel and comprising at least a third light-emitting diode (LED) and a third transistor (T1) series-assembled with the third light-emitting diode (LED), the second phase comprising maintaining said one of the first electrodes (102) at the first potential for a third time period and wherein the third transistor is controlled at a third conduction level which depends on the third time period.

9. The control method of claim 8, wherein the first, second, and third time periods are successive, said one of the first electrodes (102) being maintained at the second potential between the first time period and the second time period and for the second time period and the third time period.

10. An optoelectronic device (10; 40; 50; 60; 70) comprising display pixels (Pix) arranged in rows and in columns, each display pixel comprising an electronic circuit (20) and at least one first optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit and comprising at least one first light-emitting diode (LED), the optoelectronic device further comprising first electrodes (102) extending along the rows, each first electrode being connected to the electronic circuits of display pixels of at least one of the rows, second electrodes (104) extending along the columns, each second column being connected to the electronic circuits of display pixels of at least one of the columns, and a circuit for controlling the first and second electrodes, the optoelectronic device being characterized in that said control circuit is configured, during a first, to simultaneously: take one of the first electrodes to a first potential, the other first electrodes being maintained at a second potential smaller than the first potential; and take one of the second electrodes to a third potential smaller than the second potential, the other second electrodes being maintained at a fourth potential greater than the third potential and smaller than the second potential, which results in the activation of the electronic circuits connected to said one of the first electrodes and to said one of the second electrodes.

11. The device of claim 10, wherein the control circuit is capable, after the first phase, during a second phase, of transmitting data to the electronic circuits (20; CM) connected to said one of the first electrodes (102) and to said one of the second electrodes (104) by varying the potential of said one of the first electrodes between the first potential and the second potential and by maintaining the potential of said one of the second electrodes at the fourth potential.

12. The device of claim 11, wherein the control circuit is capable, during the second phase, of transmitting signals having a discrete duration and signals having a non-discrete duration.

13. The device of claim 11 or 12, wherein, during the second phase, the electronic circuits (20; CM) coupled to said one of the first electrodes (102) and which are not coupled to said one of the second electrodes (104) are capable of not processing the transmitted data.

14. The device of any of claims 11 to 13, wherein the electronic circuits (20; CM) coupled to said one of the first electrodes (102) and / or to said one of the second electrodes (104) are capable of turning off the associated light-emitting diodes (LED).

15. The device of any of claims 11 or 14, wherein each first optoelectronic circuit (CR, CG, CB) comprises a first transistor (T1) series-assembled with the first light-emitting diode (LED), the control circuit being capable, during the first phase, of maintaining said one of the first electrodes (102) at the first potential for a first time period, the first optoelectronic circuit being capable of turning on the first transistor at a first conduction level which depends on the first time period.

16. The device of claim 15, wherein each display pixel (Pix) comprises at least one second optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit (20; CM) of said display pixel and comprising at least a second light-emitting diode (LED) and a second transistor (T1) series-assembled with the second light-emitting diode (LED), the control circuit being capable, during the second phase, of maintaining said one of the first electrodes at the first potential for a second time period, the second optoelectronic circuit being capable of turning on the second transistor at a second conduction level which depends on the second time period.

17. The device of claim 16, wherein each display pixel comprises at least one third optoelectronic circuit (26; 42; CR, CG, CB) coupled to the electronic circuit and comprising at least a third light-emitting diode (LED) and a third transistor (T1) series-assembled with the third light-emitting diode (LED), the control circuit being capable, during the second phase, of maintaining said one of the first electrodes (102) at the first potential for a third time period, the third optoelectronic circuit being capable of turning on the third transistor at a third conduction level which depends on the third time period.

18. The device of claim 17, wherein the first, second, and third time periods are successive, the control circuit being capable of maintaining said one of the first electrodes (102) at the second potential between the first time period and the second time period and for the second time period and the third time period.