COMPUTER SYSTEM AND METHOD FOR PERFORMING RANDOM ACCESS TO A BIT IN A MEMORY

Description

[0001] Some embodiments and implementation methods relate to the random reading and writing of a bit in a data memory of a computer system.

[0002] A computer system may include a data memory configured to store an array of bytes and a central processing unit configured to read and / or write to that data memory in order to read or write words in said array of bytes.

[0003] The central processing unit is usually configured to access data memory for reading and / or writing in order to read 8-bit, 16-bit, or 32-bit words.

[0004] There are certain applications that require the random reading and / or writing of a bit from a byte array stored in a computer system's data memory. Random reading and / or writing refers to operations that occur at unpredictable times. Read and / or write accesses can be performed to read and / or write each bit of the byte array. For example, a well-known application that requires the random reading or writing of a bit from a data memory is the encoding and decoding of an audio signal.

[0005] In these applications, 8-bit, 16-bit, or 32-bit memory accesses do not allow direct reading or writing of a bit into data memory.

[0006] To access a single bit in the data memory byte array, it is common practice to access the byte of the byte array containing the bit to be accessed and then use a mask associated with the position of the bit to be accessed within that byte to select the bit. This bit access is performed in software by the central processing unit.

[0007] Such a method requires multiple tests and updates to access a single bit. Specifically, the mask must be updated for each bit to be accessed. These software-based tests and updates can require several CPU cycles. Therefore, such bit access is relatively time-consuming. Furthermore, such bit access consumes a significant amount of energy due to the numerous CPU cycles required. However, for certain applications, particularly Bluetooth Low Energy (BLE), it is crucial to minimize energy consumption and the number of calculations required to perform a given task.

[0008] US 2013 / 326201 A1 discloses an apparatus and method for processing bit streams using dedicated "bit-oriented" instructions in a processor.

[0009] Therefore, there is a need to propose a solution that allows simpler and faster access to a bit in a byte array.

[0010] In one respect, a computer system is proposed comprising: a data memory configured to store a byte array, and a program memory configured to store a computer program, a digital signal processor configured to execute a computer program comprising instructions for accessing a bit in said byte array, said digital signal processor being configured to access each byte of said byte array, a dedicated circuit - in particular integrated in the digital signal processor - configured to read and / or write a bit of a byte of said byte array using: a bit position pointer pointing to the bit to be accessed in the byte array, and said byte comprising the bit to be accessed.

[0011] Such a computer system simply uses a bit position pointer, and not a byte position pointer taken in combination with a mask.

[0012] Such a computer system is configured to access a bit in memory randomly using a dedicated circuit to execute certain instructions. This dedicated circuit occupies little space in the computer system and significantly improves the time required to access a bit in memory.

[0013] Such a computer system is configured to access a bit in memory simply and quickly at random. Indeed, such a dedicated circuit requires few execution cycles of the digital signal processing unit to access a bit in memory randomly.

[0014] Such a dedicated circuit also makes it possible to reduce the energy consumption for accessing a bit in memory randomly, because such access is carried out by performing few operations and in few cycles.

[0015] In an advantageous embodiment, the dedicated circuit includes a first block configured to calculate a byte shift value according to the value of the bit position pointer.

[0016] Advantageously, the first block of the dedicated circuit includes: an "AND" type logic gate configured to perform an "AND" type logic operation between the bit position pointer value and the hexadecimal value 0x7 to obtain an index value, a comparator circuit configured to calculate the byte offset value by comparing the index value to 0, the byte offset value being -1 when the index value is 0 and 0 otherwise.

[0017] In an advantageous embodiment, the dedicated circuit includes a second block configured to determine the value of a bit to be read from the bit position pointer and a byte comprising said bit to be read.

[0018] Advantageously, the second block of the dedicated circuit includes: an adder circuit configured to increment the bit position pointer value by 1, a first AND logic gate configured to perform an AND logic operation between the incremented bit position pointer value and a hexadecimal value of 0x7, a subtractor circuit configured to calculate a shift value by subtracting a value of 7 from the output value of the first AND logic gate, a shift circuit configured to shift the value of the byte containing the bit to be accessed to the right by a number of bits corresponding to the shift value, a second AND logic gate configured to perform an AND logic operation between a value of 1 and the shifted byte value to obtain the value of the bit to be read.

[0019] The dedicated circuit uses two blocks to read a bit from the byte array. Specifically, all the tests for reading a bit are performed by the dedicated circuit, not by a central processing unit of the computer system. This results in faster random read access to a bit from the data memory's byte array.

[0020] In an advantageous embodiment, the computer program includes instructions which, when implemented by the digital signal processing unit, cause it to make at least one call to a function to read a bit from the byte array, each call to this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: a calculation of a byte shift value by said first block, then an update of the byte pointer by said byte shift value, then a determination of the value of the bit to be read by said second block of the dedicated circuit.

[0021] To program such a bit read from the byte array of said data memory, it is possible to use intrinsic functions that allow the use of the dedicated circuit. An intrinsic function is integrated into a compiler. This simplifies the programming of such a random access to a bit in the data memory.

[0022] Advantageously, the dedicated circuit includes a third block configured to write the value of a bit in place of a bit pointed to by the bit position pointer in a byte to be written over.

[0023] In an advantageous embodiment, the third block of the dedicated circuit comprises: an adder circuit configured to increment the bit position pointer value by 1, a first AND logic gate configured to perform an AND logic operation between the incremented bit position pointer value and a hexadecimal value of 0x7, a subtractor circuit configured to calculate a shift value by subtracting a value of 7 from the output value of the first AND logic gate, a shift circuit configured to shift the value 1 left by a number of bits corresponding to said shift value to create a mask, an inverter logic gate configured to create a complementary mask from said mask obtained at the output of the shift circuit, a second AND logic circuit configured to apply the complementary mask to the byte to be written to in order to obtain a first byte B0,A logic OR circuit configured to apply the mask to the byte to be written to in order to obtain a second byte. A selection circuit configured to generate a byte corresponding to the first byte if the value of the bit to be written is equal to 1, or corresponding to the second byte otherwise.

[0024] Preferably, the computer program includes instructions which, when implemented by the digital signal processing unit, cause it to make at least one call to a function to write a bit to the byte array, each call to this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: a calculation of a byte shift value by said first block, then an update of the byte pointer by said byte shift value, then a writing of the bit to be written by said third block of the dedicated circuit.

[0025] To program such a writing of a bit in the byte array of said data memory, it is also possible to use intrinsic functions which allow the use of said dedicated circuit.

[0026] Preferably, the computer program includes instructions which, when implemented by the digital signal processing unit, cause the unit to initialize the bit position pointer to point to the position of the last bit in the byte array, and to decrement said bit position pointer on each read and / or write access.

[0027] According to another aspect, a method is proposed, implemented by a computer system, for reading and / or writing to a bit of a byte stored in a byte array in a data memory of said computer system, the method comprising an implementation of instructions from the computer program by a digital signal processing unit of the computer system resulting in: access to said byte stored in data memory by the digital signal processing processor, an implementation of a dedicated circuit of the computer system - notably integrated in the digital signal processing processor - to access in read and / or write said bit of the byte accessed by the digital signal processing processor using: a bit position pointer pointing to the bit to be accessed in the byte array, and said byte including the bit to be accessed.

[0028] In an advantageous implementation mode, the method includes an implementation of a first block of the dedicated circuit to calculate a byte shift value according to the value of the bit position pointer.

[0029] Advantageously, implementing the first block of the dedicated circuit results in: an implementation of an "AND" type logic gate from the first block to perform an "AND" type logic operation between the bit position pointer value and the hexadecimal value 0x7 to obtain an index value, an implementation of a comparator circuit from the first block to calculate the byte shift value by comparing the index value to 0, the byte shift value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise.

[0030] In an advantageous embodiment, the method further includes an implementation of a second block of the dedicated circuit to determine the value of a bit to be read from the bit position pointer and a byte comprising said bit to be read.

[0031] Advantageously, implementing the second block of the dedicated circuit results in: an implementation of an adder circuit of the second block to increase the value of the bit position pointer by 1, an implementation of a first logic gate of type "AND" of the second block to perform a logic operation of type "AND" between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, an implementation of a subtractor circuit of the second block to calculate a shift value by subtracting a value equal to 7 from the output value of the first logic gate of type "AND", an implementation of a shift circuit of the second block to shift right the value of the byte containing said bit to be accessed by a number of bits corresponding to said shift value, an implementation of a second logic gate of type "AND" of the second block to perform a logic operation of type "AND" between a value equal to 1 and the value of the shifted byte so as to obtain the value of the bit to be read.

[0032] In an advantageous implementation, the method includes an implementation of computer program instructions by the digital signal processing unit resulting in at least one call to a function to read a bit from the byte array, each call to this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: a calculation of a byte shift value by said first block, then an update of the byte pointer by said byte shift value, then a determination of the value of the bit to be read by said second block of the dedicated circuit.

[0033] Advantageously, the method further includes an implementation of a third block of the dedicated circuit to write the value of a bit in place of a bit pointed to by the bit position pointer in a byte to be written to.

[0034] In an advantageous implementation mode, the implementation of the third block of the dedicated circuit results in: an implementation of an adder circuit from the third block to increment the bit position pointer value by 1, an implementation of a first AND logic gate from the third block to perform an AND logic operation between the incremented bit position pointer value and a hexadecimal value of 0x7, an implementation of a subtractor circuit from the third block to calculate a shift value by subtracting a value of 7 from the output value of the first AND logic gate, an implementation of a shift circuit from the third block to shift the value 1 left by a number of bits corresponding to said shift value to create a mask, an implementation of an inverter logic gate from the third block to create a complementary mask from said mask obtained by implementing the shift circuit,An implementation of a second AND logic circuit from the third block to apply the complementary mask to the byte to be written to in order to obtain the first byte; an implementation of an OR logic circuit from the third block to apply the mask to the byte to be written to in order to obtain the second byte; and an implementation of a selection circuit to generate a BTE_OUT byte corresponding to the first byte if the value of the bit to be written is equal to 0, or corresponding to the second byte otherwise.

[0035] Preferably, including an implementation of computer program instructions by the digital signal processing unit resulting in at least one call to a function to write a bit into the byte array, each call to this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: a calculation of a byte shift value by said first block, then an update of the byte pointer by said byte shift value, then a writing of the bit to be written by said third block of the dedicated circuit.

[0036] Advantageously, the method includes an implementation of computer program instructions by the digital signal processing processor resulting in an initialization of the bit position pointer to point to the position of the last bit in the byte array, and a decrement of said bit position pointer at each read and / or write access.

[0037] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which: [ Fig 1 ] ] Fig 2 ] ] Fig 3 ] ] Fig 4 ] ] Fig 5 ] ] Fig 6 ] illustrate methods of embodiment and implementation of the invention.

[0038] There figure 1 This illustrates one embodiment of a computer system (SYS). The SYS computer system comprises a central processing unit (CPU) and a main memory (MMEM). The computer system also includes a digital signal processor (DSP) with a data memory (MEM), a program memory (MEMP), and a hardware control circuit (HWC) dedicated to reading and / or writing to a single bit within a byte. This HWC is integrated into an arithmetic and logic unit (ALU) of the DSP.The digital signal processor (DSP) also contains a control unit (CU), an address generation unit (AGU), and a register file. The SYS computer system can be a system-on-a-chip.

[0039] The data memory (MEM) is configured to store a BTAB byte array. The DSP can access the MEM for reading or writing. Each DSP access to the memory is performed for words with a minimum size of one byte. Thus, the DSP can access every byte of the BTAB byte array in the MEM. The DSP can place the loaded bytes into its registers, which act as buffers between the data memory (MEM) and the DSP's ALU (Automatic Logging Unit). However, the DSP cannot directly read or write a bit to the BTAB byte array.

[0040] The data in the BTAB byte array can correspond to compressed data from an audio data stream. Specifically, the audio data stream comprises a series of audio samples. These samples can be compressed to reduce their size. For example, the samples can be independently compressed using one, two, three, or four bits. Each bit in the audio data stream can have its own meaning. The value of each bit in the data stream can influence the action taken in the decompression process, for example. This is why it is important to be able to access a bit of the compressed audio data stream. Therefore, it is important to be able to access each bit of the byte array stored in memory.

[0041] The digital signal processor (DSP) is configured to execute a computer program (PRG) containing instructions that, when implemented in the DSP, cause it to perform a read and / or write access to a bit of a byte in the byte array stored in memory. This computer program (PRG) can be stored in the SYS computer system's program memory (MEMP).

[0042] The digital signal processor (DSP) can allocate a first register, R1, to store a byte (BTE_IN) read from the byte array (BTAB) stored in memory (MEM). The DSP can also allocate a second register, R2, to store a bit pointer (BITP) indicating the position of the bit to be accessed in the byte array (BTAB). The DSP can also allocate a third register, R3, to store an offset (OFFST) value. Finally, the DSP can allocate a fourth register, R4, to store the value of the bit to be accessed (BIT_OUT). To write a bit, the DSP uses register R4 to store the bit (BIT_IN) to be written to the byte (BTE_IN) contained in register R1. It then reuses register R1 to store the resulting byte (BTE_OUT) with the bit written to the output.

[0043] The HWC circuit can notably be obtained from an "RTL" code (from the English "Register Transfer Level")

[0044] The dedicated HWC circuit includes a first NXTBBW block configured to determine the next value of the OFFST byte shift. Such a first NXTBBW block is illustrated in the figure 2 .

[0045] In particular, the first NXTBBW block is configured to receive as input the value of the bit position pointer BITP stored in the second register R2.

[0046] This first NXTBBW block includes an AND1 logic gate of type "AND". The AND1 logic gate is configured to receive as input the value of the bit position pointer BITP along with a value mask of '0x7' (in hexadecimal). The "AND" logic gate is configured to apply the value mask '0x7' to the value of the bit position pointer BITP. The "AND" logic gate thus allows the system to determine, based on the three least significant bits of the bit position pointer BITP, whether or not to pre-adjust the byte pointer via the byte offset OFFST.

[0047] The AND1 logic gate is configured to output an index value INDX. Specifically, the INDX index value for a byte is between 0 and 7. Thus, the index value INDX can be determined by looking at the three least significant bits of the bit position pointer.

[0048] The first NXTBBW block also includes a CMPC comparator circuit that takes the index value INDX as input. The CMPC comparator circuit checks if the index value is 0. If the index value is 0, it means that only one bit of the byte remains to be read because the others have already been read. In this case, the byte shift value must be modified to process the next byte in the byte array after reading the last bit of the current byte.

[0049] In particular, the CMPC comparison circuit also takes as input two parameters with values ​​of '-1' and '0'.

[0050] Thus, the CMPC comparison circuit is configured to compare the index value INDX to '0' and to generate the next byte offset value based on the result of this comparison. Specifically, the CMPC comparison circuit is configured to generate a next byte offset value OFFST of '-1' when the index value is '0', and '0' when the index value is not '0'. This next byte offset value OFFST is then stored in the third register, R3.

[0051] The first NXTBBW block is then configured to determine the OFFST byte shift value in a single cycle in the DSP digital signal processing processor.

[0052] The dedicated HWC circuit includes a second READBIT block configured to determine the BIT_OUT value of a given bit in a BTE_IN byte. Such a second READBIT block is illustrated in the figure 3 The second READBIT block is configured to receive as input the BITP value of the bit position pointer stored in the second register R2 as well as the BTE_IN byte stored in the first register R1.

[0053] The second READBIT block includes an adder circuit ADD1 configured to receive as input the value of the bit position pointer BITP as well as a value equal to '1'. The adder circuit ADD1 is thus configured to add '1' to the value of the bit position pointer BITP.

[0054] The second READBIT block also includes a first AND2 logic gate of type "AND" configured to receive as input the value of the bit position pointer BITP augmented by '1' and a value mask of '0x7' in hexadecimal.

[0055] The second READBIT block also includes a subtractor circuit SUB1 configured to receive as input a value equal to '7' and the value generated at the output of the AND2 logic gate. This subtractor circuit SUB1 is configured to generate a value SL corresponding to the difference between the value '7' and the value generated at the output of the AND2 logic gate.

[0056] The SL value is therefore calculated by the following formula: SL = 7 - (BITP + 1)&0x7.

[0057] The second READBIT block also includes a shift register SFT1 configured to receive the BTE_IN byte stored in the first register R1 and to shift this BTE_IN byte to the right by a number of bits corresponding to the SL value.

[0058] The second READBIT block also includes a second AND3 logic gate configured to receive as input a value of '1' and the shifted byte generated as output from the shift register SFT1. This AND3 logic gate thus generates as output the BIT_OUT value of the lowest bit of the shifted byte. This value corresponds to the value of the bit in the BTE_IN byte stored in the first register located at the position pointed to by the bit position pointer BITP. This BIT_OUT value of the bit in the BTE_IN byte is then stored in the fourth register R4.

[0059] Thus, the second READBIT block determines the BIT_OUT value of the bit in the BTE_IN byte stored in the first register R1, located at the position pointed to by the bit position pointer BITP. Specifically, the second READBIT block is configured to determine the BIT_OUT value in a single cycle of the digital signal processing (DSP) processor.

[0060] The third WRITEBIT block is configured to write a bit BIT_IN at a position BITP into a byte BTE_IN stored in the first register R1. Such a third WRITEBIT block is illustrated in the figure 5 .

[0061] The third WRITEBIT block is configured to receive as input the value of the BIT_IN bit stored in the fourth register R4, the BITP value of the bit position pointer stored in the second register R2, and the BTE_IN byte stored in the first register R1.

[0062] The third WRITEBIT block includes an ADD1 adder circuit configured to receive as input the value of the BITP bit position pointer as well as a value equal to '1'. The ADD1 adder circuit is thus configured to add '1' to the value of the BITP bit position pointer.

[0063] The third WRITEBIT block also includes a first AND2 logic gate of type "AND" configured to receive as input the value of the bit position pointer BITP augmented by '1' and a value mask of '0x7' in hexadecimal.

[0064] The third WRITEBIT block also includes a SUB1 subtractor circuit configured to receive an input value of '7' and the output value of the AND2 logic gate. This SUB1 subtractor circuit is configured to generate an SL value corresponding to the difference between the value '7' and the output value of the AND2 logic gate.

[0065] The SL value is therefore calculated by the following formula: SL = 7 - (BITP + 1)&0x7.

[0066] The third WRITEBIT block also includes an SFT2 shift register configured to calculate an MSK mask. This MSK mask is used to insert the input bit BIT_IN into the byte BTE_IN. Specifically, the SFT2 shift register is configured to shift the value 1 to the left by a number of bits corresponding to the SL value to obtain the MSK mask.

[0067] The third WRITEBIT block further includes an inverter gate NOT1 configured to invert the MSK mask in order to obtain a complementary INVMSK mask.

[0068] The third WRITEBIT block also includes a second AND4 logic gate of type "AND" configured to apply the INVMSK complementary mask to the BTE_IN byte. This AND4 logic gate thus generates a first B0 byte as output.

[0069] The third WRITEBIT block also includes an OR1 logic gate configured to perform an OR operation between the MSK mask and the BTE_IN byte. This OR1 gate then generates a second B1 byte as output.

[0070] The third WRITEBIT block also includes a selection circuit, MUX1, configured to receive bytes B0 and B1 and to generate a BTE_OUT byte corresponding to either byte B0 or ​​byte B1, depending on the value of the BIT_IN bit. Specifically, if the value of the BIT_IN bit is 0, then the BTE_OUT byte corresponds to byte B0. Otherwise, the BTE_OUT byte corresponds to byte B1. The MUX1 selection circuit can, in particular, be a multiplexer.

[0071] The BTE_OUT byte obtained at the output of the MUX1 selection circuit corresponds to the BTE_IN byte in which the bit pointed to by the bit position pointer BITP has been modified by the value of the bit BIT_IN.

[0072] Thus, the third WRITEBIT block writes the value of the BIT_IN bit into the BTE_IN byte at the position pointed to by the BITP bit position pointer. Specifically, the third WRITEBIT block is configured to write this bit into the BTE_IN byte in a single cycle of the DSP digital signal processor. The resulting BTE_OUT byte, containing this written bit, is stored in register R1 at the output.

[0073] The third WRITEBIT block can share the ADD1, AND2, and SUB1 circuits with the second READBIT block. Alternatively, the ADD1, AND2, and SUB1 circuits of the second READBIT block and the third WRITEBIT block can be separate.

[0074] As previously discussed, the digital signal processor (DSP) is configured to execute a computer program containing instructions that, when the program is executed, cause the DSP to perform a read and / or write access to a bit of a byte in the byte array stored in memory. Specifically, the execution of these instructions causes the DSP to execute either an RD_BIT_NW function or a WRT_BIT_NW function.

[0075] The RD_BIT_NW function is configured to randomly read a bit from a byte array stored in MEM memory. This RD_BIT_NW function is called several times to read all the bits of the BTAB byte array.

[0076] In particular, the PRG computer program is configured to implement the read access procedure for a bit stored in the BTAB byte array illustrated in the figure 4 .

[0077] Specifically, the PRG computer program includes instructions for performing an initialization step 40. This step 40 initializes the bit position pointer BITP to a length equal to one less than the bit sequence in the BTAB byte array. This step 40 also initializes the byte pointer to the address of the last byte in the BTAB byte array stored in MEM memory.

[0078] The RD_BIT_NW function can then be called multiple times to read the different bits of the BTAB byte array. Calling the RD_BIT_NW function performs steps 41, 42, 43, 44, and 45, described below. Therefore, each time the RD_BIT_NW function is called, these steps 41, 42, 43, 44, and 45 are executed.

[0079] Specifically, the RD_BIT_NW function is configured to precalculate the next byte shift value. To do this, in step 41, the RD_BIT_NW function uses the NXTBBW instruction implemented by the first NXTBBW block of the dedicated circuit. Precalculating the next byte shift value allows the system to determine the next byte to be used for the next read access in a subsequent implementation of the RD_BIT_NW function. The NXTBBW instruction allows the calculation of the next byte shift value to be performed before reading the bit from the current byte. This reduces the execution time of the RD_BIT_NW function by decreasing the number of execution cycles of the digital signal processor (DSP).

[0080] The said RD_BIT_NW function is then configured to decrement the bit position pointer, in step 42. Thus the decremented bit position pointer points to the position of the next bit in the BTAB byte array.

[0081] The said RD_BIT_NW function is then configured to read the current byte pointed to by the byte pointer in the byte array, in step 43.

[0082] The said RD_BIT_NW function is then configured to update the byte pointer by adding the byte offset value to the byte pointer, in step 44.

[0083] The said RD_BIT_NW function is then configured to read and then return the current bit, in step 45. To do this, the RD_BIT_NW function uses the READBIT instruction implemented by the second READBIT block of said dedicated circuit.

[0084] In a "multi-issue" or "multi-threaded" processor, that is, one which can execute several instructions in parallel taking into account the data dependencies between them, these steps 41, 42, 43, 44 and 45 can be executed either sequentially or in parallel.

[0085] The RD_BIT_NW function uses only the bit position pointer instead of a byte pointer and mask to read a bit from a byte array. Therefore, the RD_BIT_NW function uses only one variable instead of two. From the bit position pointer, using the first NXTBBW block of the dedicated circuit, it is possible to determine an index value for the bit to be read in the current byte of the byte array and to calculate the offset value for the byte containing the next bit to be read. The first NXTBBW block and the second READBIT block of the HWC dedicated circuit are configured to perform all the calculations and tests to extract the bit to be read from a byte in a byte array. This allows the bit to be read much faster. For example, using the dedicated circuit makes it twice as fast as a software-only read access using a byte pointer and mask.

[0086] The RD_BIT_NW function can be used in any application requiring random read access to a bit in a byte array in memory. Specifically, the RD_BIT_NW function can be used in any audio encoder-decoder that requires random read access to a bit in a byte array in memory. More particularly, the RD_BIT_NW function can be implemented in the LC3 (Low Complexity Communication Codec) audio encoder-decoder. For example, the RD_BIT_NW function can be implemented during the decoding of an audio data stream.

[0087] The computer program may also include instructions that, when the program is executed by the digital signal processor (DSP), cause the DSP to execute a WRT_BIT_NW function. This WRT_BIT_NW function allows random write access to a bit in a byte array stored in memory.

[0088] The WRT_BIT_NW function is configured to randomly access and write to a bit in a byte array stored in MEM memory. This WRT_BIT_NW function is called several times to write to all the bits in the BTAB byte array.

[0089] In particular, the PRG computer program is configured to implement the one-bit write access procedure in the BTAB byte array illustrated in the figure 6 .

[0090] Specifically, the PRG computer program includes instructions for performing an initialization step 60. This step 60 initializes the bit position pointer BITP to a length equal to one less than the bit sequence in the BTAB byte array. This step 60 also initializes the byte pointer to the address of the last byte in the BTAB byte array stored in MEM memory.

[0091] The WRT_BIT_NW function can then be called multiple times to write to the different bits of the BTAB byte array. Calling the WRT_BIT_NW function performs steps 61, 62, 63, 64, and 65, described below. Therefore, each time the WRT_BIT_NW function is called, these steps 61, 62, 63, 64, and 65 are executed.

[0092] Specifically, the WRT_BIT_NW function is configured to precalculate the next byte shift value. To do this, in step 61, the WRT_BIT_NW function uses the NXTBBW instruction implemented by the first NXTBBW block of the dedicated circuit. Precalculating the next byte shift value allows the function to know the next byte to be used for the next write access performed for a subsequent implementation of the WRT_BIT_NW function. The NXTBBW instruction allows the calculation of the next byte shift value to be anticipated before writing the bit to the current byte. This reduces the execution time of the WRT_BIT_NW function by reducing the number of execution cycles of the digital signal processor (DSP).

[0093] The said WRT_BIT_NW function is then configured to decrement the bit position pointer, in step 62. Thus the decremented bit position pointer points to the position of the next bit in the BTAB byte array.

[0094] The said WRT_BIT_NW function is then configured to read the current byte pointed to by the byte pointer in the byte array, at step 63.

[0095] The said WRT_BIT_NW function is then configured to update the byte pointer by adding the byte offset value to the byte pointer, in step 64.

[0096] The said WRT_BIT_NW function is then configured to write a BIT_IN bit into the current bit, at step 65. To do this, the WRT_BIT_NW function uses the WRITEBIT instruction implemented by the third WRITEBIT block of said dedicated circuit.

[0097] In a "multi-issue" or "multi-threaded" processor, these steps 61, 62, 63, 64 and 65 can be executed either sequentially or in parallel.

[0098] The WRT_BIT_NW function uses only the bit position pointer instead of a byte pointer and mask to write a bit to a byte array. Therefore, WRT_BIT_NW uses only one variable instead of two. From the bit position pointer, using the first NXTBBW block of the dedicated circuit, it is possible to determine an index value for the bit to be written to in the current byte of the byte array and to calculate the offset value for the byte containing the next bit to be written to. The first NXTBBW block and the third WRITEBIT block of the HWC dedicated circuit are configured to perform all the calculations and tests for writing to a bit in a byte array. This allows for faster bit writing. For example, using the dedicated circuit makes write access twice as fast as a software-only write access using a byte pointer and mask.

[0099] The WRT_BIT_NW function can be used in any application requiring random write access to a bit in a byte array in memory. In particular, the WRT_BIT_NW function can be used in any audio encoder-decoder requiring random read access to a bit in a byte array in memory. Specifically, the WRT_BIT_NW function can be implemented in the LC3 (Low Complexity Communication Codec) audio encoder-decoder.

[0100] Furthermore, the dedicated HWC circuit in the SYS computer system has the advantage of being inexpensive and occupying little space within the system. Using such a dedicated circuit has no impact on the maximum frequency of the digital signal processing unit. It also reduces the energy consumption required to read a bit from a byte array in memory.

Claims

1. A computer system comprising: - a data memory (MEM) configured to store a byte array (BTAB), and a program memory (MEMP) configured to store a computer program (PRG), - a digital signal processor (DSP) configured to execute a computer program (PRG) comprising instructions allowing accessing a bit in said byte array (BTAB), said digital signal processor (DSP) being configured to access each byte of said byte array, - a dedicated circuit (HWC) configured to read and / or write access a bit of a byte of said byte array using: • a bit position pointer (BITP) pointing towards the bit to be accessed in the byte array, and • said byte (BTE_IN) comprising the bit to be accessed, wherein the dedicated circuit (HWC) comprises: - a first block (NXTBBW) configured to calculate a byte shift value according to the value of the bit position pointer, and - a second block (READBIT) configured to determine the value of a bit to be read based on the bit position pointer (BITP) and a byte (BTE_IN) comprising said bit to be read, and wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor, cause the latter to perform at least one call of a function (RD_BIT_NW) to read a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a determination of the value of the bit to be read by said second block (READBIT) of the dedicated circuit (HWC).

2. The system according to claim 1, wherein the first block (NXTBBW) of the dedicated circuit (HWC) comprises: - an "AND" type logic gate (AND1) configured to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX), - a comparison circuit (COMPC) configured to calculate the byte shift value by comparing the index value (INDX) with 0, the byte shift value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise.

3. The system according to any one of claims 1 or 2, wherein the second block (READBIT) of the dedicated circuit (HWC) comprises: - an adder circuit (ADD1) configured to increase the value of the bit position pointer by 1, - an "AND" type first logic gate (AND2) configured to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - a shift circuit (SFT1) configured to shift to the right the value of the byte comprising said bit to be accessed by a number of bits corresponding to said shift value (SL), - an "AND" type second logic gate (AND3) configured to perform an "AND" type logic operation between a value equal to 1 and the shifted value of the byte so as to obtain the value (BIT_OUT) of the bit to be read.

4. The system according to one of claims 1 to 3, wherein the dedicated circuit (HWC) comprises a third block (WRITEBIT) configured to write the value of a bit instead of a bit pointed to by the bit position pointer (BITP) in a byte (BTE_IN) on which to write.

5. The system according to claim 4, wherein the third block (WRITEBIT) of the dedicated circuit (HWC) comprises: - an adder circuit (ADD1) configured to increase the value of the bit position pointer by 1, - an "AND" type first logic gate (AND2) configured to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - a shift circuit (SFT2) configured to shift to the left the value 1 by a number of bits corresponding to said shift value (SL) to create a mask (MSK), - an inverter logic gate (NOT1) configured to create a complementary mask (INVMSK) based on said mask (MSK) obtained at the output of the shift circuit (SFT2), - an "AND" type second logic circuit (AND4) configured to apply the complementary mask (INVMSK) on the byte (BTE_IN) on which to write to obtain a first byte (B0), - an "OR" type logic circuit (OR1) configured to apply the mask (MSK) on the byte (BTE_IN) on which to write to obtain a second byte (B1), - a selection circuit (MUX1) configured to generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0 or corresponding to the second byte (B1) otherwise.

6. The system according to any one of claims 4 or 5, wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor, cause the latter to perform at least one call of a function (WRT_BIT_NW) to write a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a writing of the bit to be written by said third block (WRITEBIT) of the dedicated circuit (HWC).

7. The system according to one of claims 1 to 6, wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor (DSP), cause the latter to initiate the bit position pointer so that it points towards the position of the last bit of the byte array (BTAB), and to decrement said bit position pointer (BITP) at each read and / or write access.

8. A method, implemented by a computer system (SYS), for read and / or write accessing a bit of a byte stored in a byte array (BTAB) in a data memory (MEM) of said computer system, the method comprising implementing instructions of the computer program (PRG) stored in a program memory (MEMP) by a digital signal processor (DSP) of the computer system (SYS) resulting in: - an access to said byte stored in the data memory (MEM) by the digital signal processor (DSP), - an implementation of a dedicated circuit (HWC) of the computer system (SYS) to read and / or write access said bit of the byte accessed by the digital signal processor (DSP) using: • a bit position pointer (BITP) pointing towards the bit to be accessed in the byte array, and • said byte (BTE_IN) comprising the bit to be accessed, the method further comprising: - implementing a first block (NXTBBW) of the dedicated circuit (HWC) to calculate a byte shift value (OFFST) according to the value of the bit position pointer (BITP), - implementing a second block (READBIT) of the dedicated circuit (HWC) to determine the value of a bit to be read based on the bit position pointer (BITP) and a byte (BTE_IN) comprising said bit to be read, and wherein the method further comprises implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in at least one call of a function (RD_BIT_NW) to read a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a determination of the value of the bit to be read by said second block (READBIT) of the dedicated circuit (HWC).

9. The method according to claim 8, wherein the implementation of the first block (NXTBBW) of the dedicated circuit (HWC) results in: - an implementation of an "AND" type logic gate (AND1) of the first block (NXTBBW) to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX), - an implementation of a comparison circuit (COMPC) of the first block (NXTBBW) to calculate the byte shift value by comparing the index value (INDX) with 0, the byte shift value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise.

10. The method according to one of claims 8 or 9, wherein the implementation of the second block (READBIT) of the dedicated circuit (HWC) results in: - an implementation of an adder circuit (ADD1) of the second block (READBIT) to increase the value of the bit position pointer by 1, - an implementation of an "AND" type first logic gate (AND2) of the second block (READBIT) to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - an implementation of a subtractor circuit (SUB1) of the second block (READBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - an implementation of a shift circuit (SFT1) of the second block (READBIT) to shift to the right the value of the byte comprising said bit to be accessed by a number of bits corresponding to said shift value (SL), - an implementation of an "AND" type second logic gate (AND3) of the second block (READBIT) to perform an "AND" type logic operation between a value equal to 1 and the shifted value of the byte so as to obtain the value (BIT_OUT) of the bit to be read.

11. The method according to one of claims 8 to 10, further comprising implementing a third block (WRITEBIT) of the dedicated circuit (HWC) to write the value of a bit instead of a bit pointed to by the bit position pointer (BITP) in a byte (BTE_IN) on which to write.

12. The method according to claim 11, wherein the implementation of the third block (WRITEBIT) of the dedicated circuit (HWC) results in: - an implementation of an adder circuit (ADD1) of the third block (WRITEBIT) to increase the value of the bit position pointer by 1, - an implementation of an "AND" type first logic gate (AND2) of the third block (WRITEBIT) to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - an implementation of a subtractor circuit (SUB1) of the third block (WRITEBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - an implementation of a shift circuit (SFT2) of the third block (WRITEBIT) to shift to the left the value 1 by a number of bits corresponding to said shift value (SL) to create a mask (MSK), - an implementation of an inverter logic gate (NOT1) of the third block (WRITEBIT) to create a complementary mask (INVMSK) based on said mask (MSK) obtained by implementation of the shift circuit (SFT2), - an implementation of an "AND" type second logic circuit (AND4) of the third block (WRITEBIT) to apply the complementary mask (INVMSK) on the byte (BTE_IN) on which to write to obtain a first byte (B0), - an implementation of an "OR" type logic circuit (OR1) of the third block (WRITEBIT) to apply the mask (MSK) on the byte (BTE_IN) on which to write to obtain a second byte (B1). - an implementation of a selection circuit (MUX1) to generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0 or corresponding to the second byte (B1) otherwise.

13. The method according to any one of claims 11 or 12, comprising implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in at least one call of a function (WRT_BIT_NW) to write a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a writing of the bit to be written by said third block (WRITEBIT) of the dedicated circuit (HWC).

14. The method according to one of claims 8 to 13, comprising implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in an initiation of the bit position pointer so that it points towards the position of the last bit of the byte array (BTAB), and in a decremention of said bit position pointer (BITP) at each read and / or write access.