Light emitting diode display pixel

Abstract

The present disclosure relates to a display pixel (12i,j) comprising at least one light-emitting diode (LED), a driver (40) for driving the LED and first, second, third, and fourth conductive pads (36). The driver is powered by a first supply voltage (Vdd) received between the first and second pads. The LED is powered by a first binary signal (Vcci, Veei), received between the third and second pads, and alternating between a second supply voltage (Vcc), strictly higher than the first voltage, and a third voltage, strictly lower than the first voltage. The driver (40) is configured to determine a digital signal (R, G, B) from the values of a second binary signal (Dataj) on the fourth pad, received during each of first pulses of the first binary signal at the third voltage, and to control the LED on the basis of the digital signal.

Description

[0001] This patent application claims priority from French patent application FR21 / 03309 which will be considered as an integral part of this description. Domaine technique

[0002] The present application relates to a display screen whose display pixels comprise light-emitting diodes. Technique antérieure

[0003] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises for the display of each pixel of the image at least three components, also called display sub-pixels, which each emit light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiation emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the display screen is called the assembly formed by the three display sub-pixels used for the display of a pixel of an image. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0004] Display pixels can be distributed in a matrix fashion, with each display pixel located at the intersection of a row (or line) and a column of the matrix. Typically, each row of display pixels is selected in succession, and the display pixels in the selected row are programmed to display the desired image pixels.

[0005] An active matrix is ​​a screen driver architecture that keeps all pixel lines active for the entire duration of an image, unlike so-called passive matrices where each line is only active for a time T=Tframe / N (where Tframe is the duration of the image and N is the number of lines on the screen). This allows the brightness of the display screen to be increased. In addition, it is possible to send low levels of voltage or current to the matrix control lines, which allows larger data streams to be displayed.

[0006] In the context of a screen based on micrometric light-emitting diodes formed on electronic circuits, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel due to the high intrinsic brightness of the light-emitting diodes. One of the solutions used is therefore to deposit these unitary light-emitting diodes on a support (also called a panel) containing the control electronics. Another solution consists of using display pixels comprising light-emitting diodes and a circuit for controlling the light-emitting diodes. These are then referred to as smart pixels. This makes it possible in particular to simplify the production of an active matrix, since the control electronics for the light-emitting diodes of the display pixel are essentially embedded on the display pixel. Document WO 2018 / 185433 describes an example of a smart pixel.

[0007] For a smart pixel, it is generally the number of conductive pads of the smart pixel, used for the electrical connection of the smart pixel to the support, which imposes the dimensions of the smart pixel, in particular due to the minimum size of these pads and the minimum space that must be provided between these pads. To limit the number of conductive pads, it is known to provide a single supply voltage to the display pixels, and each display pixel internally generates one or more reduced supply voltages in particular for the polarization of components of the control electronics.

[0008] The static power consumption of a display pixel corresponds to the electrical power consumed by the display pixel when it is not emitting light. It can consist of component leakage currents or currents required for the internal operation of the display pixel's drive circuit. In the case of smart pixels, a significant portion of the static power consumption comes from the generation of supply voltages internal to the smart pixel.

[0009] One could consider providing an additional conductive pad on each smart pixel to provide the smart pixel with the reduced supply voltage so that it is not generated within the smart pixel. However, this may result in an increase in the dimensions of the smart pixel, which is not desirable.

[0010] The trend is towards increasing the number of display pixels on the display screen. The static consumption of display pixels can then become a critical factor. Indeed, for a so-called 4K display screen with a resolution of 2160 by 3840 display pixels, the static consumption of the display screen can be higher than 150 W.

[0011] There is a need to reduce the static consumption of the display screen. Résumé de l'invention

[0012] An object of an embodiment is to provide a light-emitting diode display screen that overcomes all or part of the disadvantages of existing light-emitting diode display screens.

[0013] Another object of an embodiment is that the display pixels have dimensions less than 200 µm, which limits the number of interconnections between the display pixel and the support of the display pixels.

[0014] An embodiment provides a display pixel for a display screen, comprising at least one light-emitting diode, a circuit for driving the light-emitting diode and first, second, third, and fourth electrically conductive pads, the driving circuit being at least partly powered by a first supply voltage received between the first and second electrically conductive pads, the light-emitting diode being powered by a first binary signal received between the third and second electrically conductive pads, the first binary signal alternating between a second supply voltage, strictly higher than the first supply voltage, and a third voltage, strictly lower than the first supply voltage,the driving circuit being configured to determine a digital signal from the values ​​of a second binary signal on the fourth electrically conductive pad received during each of the first pulses of the first binary signal at the third voltage and to control the light-emitting diode from the digital signal.,

[0015] According to one embodiment, the driving circuit is configured to control the light-emitting diode by pulse width modulation from the digital signal.

[0016] According to one embodiment, the display pixel comprises only the first, second, third, and fourth electrically conductive pads.

[0017] According to one embodiment, the driving circuit is configured to turn on or off the light-emitting diode at the rate of second pulses of the first binary signal at the third voltage.

[0018] According to one embodiment, the driving circuit is configured to determine a clock signal and a third binary signal from the second binary signal.

[0019] According to one embodiment, the control circuit comprises a circuit for storing binary data determined during each first pulse from the third binary signal.

[0020] According to one embodiment, the second binary signal is intended to comprise a mixture of third pulses having the same duration and fourth pulses having the same duration greater than the duration of each third pulse, the control circuit being configured to provide the clock signal at the same rate as the third and fourth pulses and the third binary signal equal to a first state or to a second state according to the succession of the third and fourth pulses.

[0021] An embodiment also provides a display screen comprising a matrix of display pixels as defined previously, the display screen further comprising circuits for supplying, for each display pixel, the first supply voltage between the first and second electrically conductive pads, the first binary signal between the third and second electrically conductive pads, and the second binary signal on the fourth electrically conductive pad.

[0022] According to one embodiment, the supply circuits are configured to maintain the first electrically conductive pad at a substantially constant first potential, the second electrically conductive pad at a substantially constant second potential, and the third electrically conductive pad at a third potential which alternates between first and second values, either the first value is strictly greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is strictly less than the second potential.

[0023] According to one embodiment, the supply circuitry is configured to supply the third voltage equal to the zero voltage.

[0024] According to one embodiment, the supply circuits are configured to supply the second binary signal alternating between two potentials, the difference in absolute value between the two potentials being strictly less than the second supply voltage.

[0025] According to one embodiment, the supply circuits are configured to supply the first binary signal comprising, for the display of an image, the first pulse at the third voltage of a first duration and a succession of second pulses, each second pulse having a second duration less than the first duration.

[0026] According to one embodiment, the durations between two pairs of successive second pulses increase or decrease. Brève description des dessins

[0027] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 represents, in a partial and schematic manner, a known example of a display screen; the figure 2 is a very schematic sectional view of a known example of a display pixel; the figure 3 is a bottom view of the display pixel of the figure 2 ; there figure 4 represents a known example of a block diagram of the display pixel of the figure 2 ; there figure 5 represents known examples of timing diagrams of signals of the display pixel of the figure 4 ; there figure 6 represents, in a partial and schematic manner, an embodiment according to the invention of a display screen; the figure 7 represents a block diagram of an embodiment according to the invention of a display pixel of the display screen of the figure 6 ; there figure 8 represents timing diagrams of signals from the display pixel of the figure 7 ; there figure 9 represents a block diagram of another embodiment according to the invention of a display pixel of the display screen of the figure 6 ; and the figure 10 represents timing diagrams of signals from the display pixel of the figure 9 . Description des modes de réalisation

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures or to a display screen in a normal position of use.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be linked through one or more other elements. In addition, a "binary signal" is a signal that alternates between a first constant state, for example a low state, noted "0", and a second constant state, for example a high state, noted "1". The high and low states of different binary signals in the same electronic circuit may be different. In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.Furthermore, in the remainder of the description, the source and drain of the MOS transistor are referred to as the "power terminals" of an insulated gate field effect transistor, or MOS transistor.

[0031] Furthermore, unless otherwise indicated, when we speak of a voltage at a conductive pad, we consider the difference between the potential at said conductive pad and a reference potential, for example ground, taken equal to 0 V.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially constant" means varying by less than 10% over time compared to a reference value.

[0033] There figure 1 represents, in a partial and schematic manner, a known example of a display screen 10. The display screen 10 comprises display pixels 12 i,j for example arranged in M ​​rows and in N columns, M being an integer varying from 1 to 8000 and N being an integer varying from 1 to 16000, i being an integer varying from 1 to M and j being an integer varying from 1 to N. By way of example, in figure 1 , M and N are equal to 6. Each display pixel 12 i,j is connected to a source of a low reference potential Gnd, for example ground, via an electrode 14 i and to a source of a high reference potential Vcc via an electrode 16 j . As an example, the electrodes 14 i are shown aligned according to the rows in figure 1 and the 16 j electrodes are shown aligned along the columns in figure 1 , the reverse arrangement being possible. The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology used to manufacture the light-emitting diodes. For example, the supply voltage can be in the order of 4 V to 5 V.

[0034] For each row, the display pixels 12 i,j of the row are connected to a row electrode 18 i . For each column, the display pixels 12 i,j of the column are connected to a column electrode 20 j . The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18 i and adapted to provide a selection and timing signal Com i on each row electrode 18 i . The display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20 j and adapted to provide a data signal Data j on each column electrode 20 j . The selection circuit 22 and the control circuit 24 are controlled by a circuit 26, comprising for example a microprocessor.

[0035] There figure 2 is a very schematic cross-sectional view of a known example of the 12 i,j display pixel and the figure 3 is a bottom view of the display pixel 12 i,j . Each display pixel 12 i,j comprises a control circuit 30 covered by a display circuit 32. The display circuit 32 comprises at least one light-emitting diode LED, preferably at least three light-emitting diodes LED. The display pixel comprises a lower face 34 and an upper face 35 opposite the lower face 34, the faces 34 and 35 preferably being planar and parallel. The control circuit 30 further comprises conductive pads 36, not shown in the figure 2 , on the lower face 34. The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin-film transistors, also called TFT transistors (English acronym for Thin-Film Transistor). Preferably, the display circuit 32 comprises only the LED light-emitting diodes, and the conductive elements of these LED light-emitting diodes and the control circuit 30 comprises all of the electronic components necessary for controlling the LED light-emitting diodes of the display circuit 32. Alternatively, the display circuit 32 may also comprise other electronic components in addition to the LED light-emitting diodes.LEDs can be 2D LEDs, also called planar LEDs, comprising a stack of planar layers, or 3D LEDs each comprising a three-dimensional semiconductor element covered with an active area. On the . figure 2 , the light-emitting diodes are shown connected with a common anode. However, it may be desirable to arrange the light-emitting diodes LED in another configuration. For example, the light-emitting diodes can be connected with a common cathode, or they can be connected independently of each other.

[0036] According to one embodiment, the display pixel 12 i,j comprises three display sub-pixels emitting light at first, second, and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0037] Each conductive pad 36 is intended to be connected to one of the electrodes 14 i , 16 j , 18 i , 20 j shown schematically in figure 2 . A first conductive pad 36 is connected to the source of the low reference potential Gnd. A second conductive pad is connected to the source of the high reference potential Vcc. A third conductive pad 36 is connected to the row electrode 18 i and receives the selection and timing signal Com i . A fourth conductive pad 36 is connected to the column electrode 20 j and receives the data signal Data j . The dimensions of the conductive pads 36 and the arrangement of the conductive pads 36 on the face 34 are notably imposed by the design rules of the display pixel 12 i,j and by the method of assembling the display pixels 12 i,j in the display screen 10.

[0038] There figure 4 represents a known example of a block diagram of a display pixel 12 i,j of the display screen 10. In figure 4 , the supply voltage used to power the electronic components of the block is indicated above each block.

[0039] According to one example, the display pixel 12 i,j comprises at least three light-emitting diodes, a single light-emitting diode LED being shown in figure 4 . Each light-emitting diode LED is connected in series to a controllable current source CS, comprising for example a MOS transistor. In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED is for example connected to the conductive pad 36 receiving the high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS being connected to the conductive pad 36 receiving the low reference potential Gnd.

[0040] The display pixel 12 i,j further comprises a circuit 40 for driving the controllable current source CS. The driving circuit 40 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage, less than 4 V, for example of the order of 1 V or 1.8 V, to power the electronic components of the driving circuit 40, this reduced supply voltage corresponding, for example, to the voltage likely to be applied between the power terminals of the MOS transistors. For this purpose, the display pixel 12 i,j comprises a circuit 42 (Vdd Generation) for supplying, from the supply voltage Vcc, a reduced supply voltage Vdd used in particular for powering the driving circuit 40. The circuit 42 comprises for example a voltage divider.

[0041] According to one embodiment, the selection and timing signal Com i , received at one of the conductive pads 36 of each display pixel 12 i,j , is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, for example approximately 1 V, strictly lower than the reduced supply voltage Vdd. The data signal Data j is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, for example approximately 1 V, strictly lower than the reduced supply voltage Vdd.

[0042] The driving circuit 40 comprises a circuit 44 (Clk & data separation) connected to the conductive pad 36 receiving the data signal Data j and providing, from the data signal Data j , a clock signal Clk and data Data. The driving circuit 40 comprises a circuit 46 (Mode selection) receiving the signals Clk and Data, connected to the conductive pad 36 receiving the selection and timing signal Com i , and configured to provide the signals Clk and Data to a storage circuit 48 (Color Data registers) or to provide a PWM signal to a circuit 50 (LED driver) for controlling the controllable current source CS associated with each light-emitting diode LED. The storage circuit 48 is configured to store color signals R, G, B representative of the image pixel to be displayed.The circuit 50 is adapted to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green, and I_blue, obtained from the color signals R, G, B, and the PWM signal.

[0043] As will be described later, to limit the number of conductive pads 36 per display pixel 12 i,j , the data signals Data j allow both the determination, by each display pixel 12 i,j , of a clock signal and color signals R, G, B representative of the desired light intensities for the radiation at the first, second, and third wavelengths.

[0044] There figure 5 represents a timing diagram of signals received by the display pixels 12 i,j having the structure shown in figure 4 when displaying an image on the display screen 10.

[0045] The potentials Vcc and Gnd are substantially constant. The image pixels of a new image to be displayed are displayed successively from the row of rank 1 to the row of rank M. The duration of the frame T is the duration separating two successive selections of the same row of the display screen 10. Timing diagrams of the signals Com 1 and Data 1 will be detailed for the row of rank 1, knowing that the timing diagrams of the signals Com i are similar to the timing diagram of the signal Com 1 although shifted in time. The display of a new image pixel by a display pixel 12 i,j , j varying from 1 to N, of the row of rank 1 comprises a first phase P1 followed by a second phase P2. During the phase P1, data signals Data j are transmitted to each display pixel 12 1,j of the row of rank 1, only the signal Data 1 being represented in figure 5 . During the second phase P2, the light-emitting diodes of each display pixel 12 1,j are controlled from the color signals R, G, B, determined from the data signals Data j .

[0046] During the first phase P1, the selection and timing signal Com 1 is set to state "1". Setting the signal Com 1 to state "1" for a long duration is detected by the circuit 46 of each display pixel 12 1,j of the row of rank 1 and thus allows the selection of the display pixels 12 1,j of this row, the display pixels of the other rows not being selected. During the first phase P1, the data signals Data j are transmitted on the column electrodes 20 j . For each display pixel 12 i,j , the circuit 44 determines the clock signal Clk and the data Data from the pulses of the data signal Data j . For example, each pulse of the data signal Data j can have a first duration or a second duration, strictly greater than the first duration.The signal Clk may correspond to a sequence of pulses of the same durations whose rising edges coincide, apart from a possible constant offset, with the rising edges of the pulses of the data signal Data j. The data Data may correspond to a binary signal in state "0" when the pulse of the signal Data j has the first duration, and in state "1" when the pulse of the signal Data j has the second duration. The circuit 46, selected by the signal Com 1 in state "1", provides, at the rate of the clock signal Clk, the data Data which are stored in the circuit 50 in the form of digital signals R, G, B whose bits are given by the successive values ​​of the signal Data. The end of the first period P1 for a row corresponds to the start of the first period P1 for the following row.

[0047] According to one embodiment, the light-emitting diodes of the display pixel 12 1,j are controlled by pulse width modulation or PWM control (English acronym for Pulse Width Modulation). For this purpose, during the second phase P2, the selection and timing signal Com 1 presents the repetition of a succession of pulses in state "1" which are transmitted by the circuit 46 of each display pixel 12 1,j of the row of rank 1 to the circuit 50 (PWM signal) to clock the operation of the circuit 50 for the control of the light-emitting diodes LED by pulse width modulation. The number of pulses in the succession corresponds to the number of bits of each digital signal R, G, and B.For example, when the current source CS corresponds to a MOS transistor, this transistor is turned on or off, at the rate of the PWM pulses, according to the value "0" or "1" of each bit of the color signal R, G, or B starting with the most significant bit, the transistor being kept on or off until the next pulse of the signal Com 1. The duration between two successive pulses of the signal Com 1 is divided by two each time, so that the total duration during which the light-emitting diode is lit depends on the value of the color signal R, G, or B. The succession of pulses of the signal Com 1 is repeated until the next first phase P1 of the row of rank 1, a single repetition being illustrated as an example in . figure 5 .

[0048] The static consumption of the display pixel 12 i,j is largely due to the electronic components other than the MOS transistors of the driving circuit 40, in particular the circuit 42 for supplying the reduced supply voltage Vdd. The current trend is to increase the number of display pixels 12 i,j of the display screen 10. The static consumption of the display pixels can then become a critical factor. Indeed, for a display screen 10 called 4K, having a resolution of 2160 by 3840 display pixels, the static consumption of the display screen 10 can be greater than 150 W.

[0049] It could be considered to provide an additional conductive pad 36, on each display pixel 12 i,j , in addition to those represented in figure 3 , to provide the display pixel 12 i,j with an additional high reference potential Vdd, so that the reduced supply voltage Vdd is not produced within the display pixel 12 i,j . However, it may not be possible to add an additional conductive pad 36 without increasing the lateral dimensions of the display pixel 12 i,j , which may not be desirable.

[0050] According to an embodiment according to the invention, one of the conductive pads 36 is used to receive the high supply voltage Vcc and another conductive pad 36 is used to receive the reduced supply voltage Vdd without modifying the total number of conductive pads 36. As a result, the generation of the reduced supply voltage is no longer carried out within each display pixel 12 i,j and the static consumption of the display screen is reduced. Furthermore, the lateral dimensions of the display pixels 12 i,j may not be modified. However, to operate with the same number of conductive pads 36, the structure of the driving circuit 40 of the display pixel 12 i,j is modified and some of the signals supplied to the display pixels 12 i,j are modified.

[0051] There figure 6 represents, in a partial and schematic manner, an embodiment of a display screen 60. The display screen 60 comprises all of the elements of the display screen 10 of the figure 1 , with the difference that the electrodes 16 j , j varying from 1 to N, provide the reduced supply voltage Vdd and that the row electrodes 18 i , i varying from 1 to M, provide the high supply voltage Vcc i which contains a part of the timing signal. The column electrodes 20 j provide the data signals Data j and the electrodes 14 i provide the low reference potential as for the display screen 10.

[0052] There figure 7 represents an example of a block diagram of a display pixel 12 i,j of the display screen 60. The display pixel 12 i,j of the display screen 60 has the same structure as the display pixel 12 i,j of the display screen 10 shown in figure 4 , with the difference that it does not include the circuit 42 for supplying the reduced supply voltage Vdd and that it further includes a circuit 62 (Vcc pulse detection) for detecting pulses of the signal Vcc i which provides the selection and timing signal Com i to the selection circuit 46. The reduced supply voltage Vdd is directly supplied by one of the conductive pads 36.

[0053] There figure 8 represents a timing diagram of signals received by the display pixels 12 i,j having the structure shown in figure 7 when displaying an image on the display screen 60.

[0054] The potentials Vdd and Gnd are substantially constant. Each signal Vcc i , i varying from 1 to M, is a binary signal which varies between a state "1" in which the signal Vcci is equal to the high supply voltage Vcc described previously, for example of the order of 4 V to 5 V, and a state "0", in which the signal Vcc i is substantially equal to the low reference potential GND. Each signal Vcc i has a first phase P1 followed by a second phase P2. During phase P1, data signals Data j are transmitted to each display pixel 12 i,j of the row of rank i, only the signal Data 1 being represented in figure 8 . During the second phase P2, the light-emitting diodes of each display pixel 12 i,j are controlled from the color signals R, G, B, determined from the data signals Data j .

[0055] The signal Com i , supplied by the circuit 62 of each display pixel 12 i,j , therefore varies between states "0" and "1" in a complementary manner to the signal Vcc i , the state "0" corresponding for example to the low reference potential GND and the state "1" corresponding to a low voltage, for example approximately 1 V, equal for example to the reduced supply voltage Vdd. The operation of the rest of the control circuit 40 is therefore identical to what was described previously in relation to the figure 5 . In particular, during the first phase P1, the signal Vcc i is set to the state "0". The setting to the state "0" of the signal Vcc i for a long duration is detected by the circuits 62 and 46 of each display pixel 12 i,j of the row of rank i and thus allows the selection of the display pixels 12 i,j of this row, the display pixels of the other rows not being selected. During the first phase P1, the data signals Data j are transmitted on the column electrodes 20 j . For each display pixel 12 i,j , the circuit 44 determines the clock signal Clk and the data Data from the pulses of the data signal Data j , for example as described previously. Circuit 46, selected by the signal Com i at state "1", provides, at the rate of the clock signal Clk, the data Data which are stored in circuit 50 in the form of digital signals R, G, B whose bits are given by the successive values ​​of the signal Data.

[0056] During the second phase P2, the signal Vcc i presents the repetition of a succession of pulses in state "0" which are converted by the circuit 62 of each display pixel 12 i,j of the row of rank i into pulses in state "1" of the signal Com i. These pulses are transmitted by the circuit 46 of each display pixel 12 i,j of the row of rank i to the circuit 50 (PWM signal) to regulate the operation of the circuit 50 for controlling the light-emitting diodes LED by pulse width modulation, for example as described previously.

[0057] Advantageously, the durations of the pulses in the "0" state of each signal Vcc i during the phases P1 and P2 are less than at least 75% of the duration of the frame T, preferably at least 80%, more preferably at least 85% of the duration of the frame T. The signal Vcc i is therefore most of the time equal to the high supply voltage Vcc, and the power supply of the light-emitting diodes LED is not substantially disturbed by the pulses of the signal Vcc i. This would not have been the case if the high supply voltage had been transported by the data signals Data j which themselves vary substantially continuously between the high and low states.

[0058] In the embodiment described above in relation to the figure 7 , LEDs are in a common anode configuration. However, it may be desirable to arrange the LEDs in a common cathode configuration.

[0059] There figure 9 represents an exemplary block diagram of a display pixel 12 i,j of the display screen 60 in which the light-emitting diodes LED of the display pixel 12 i,j are in a common-cathode configuration. The display pixel 12 i,j shown in figure 9 has the same structure as the display pixel 12 i,j shown in figure 7 , with the difference that the signal Vcc i is replaced by a signal Vee i , that the cathode of the light-emitting diode LED is for example connected to the conductive pad 36 receiving the signal Vee i , that the anode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS being connected to the conductive pad 36 receiving the reduced supply voltage Vdd.

[0060] There figure 10 represents a timing diagram of signals received by the display pixels 12 i,j having the structure shown in figure 9 when displaying an image on the display screen 60. Each signal Vee i , i varying from 1 to M, is a binary signal which varies between a state "1" in which the signal Vee i is equal to the reduced supply voltage Vdd described previously, for example of the order of 1 V or 1.8 V, and a state "0", in which the signal Vee i is at a reference potential strictly lower than the reference potential GND, for example at a negative potential, in particular of the order of -2.2 V or -3 V, so that the difference between the potentials Vdd and Vee is equal to the high supply voltage Vcc described previously. According to one embodiment, the signal Vee i evolves like the signal Com i described previously. In the present embodiment, the circuit 62 is not present insofar as, as the signal Vee i evolves like the signal Com i , it can be used directly by the circuit 46.However, since the dynamics of the signal Vee i are different from those of the signal Com i , it may be desirable to provide that the circuit 62 is adapted to provide the signal Com i from the signal Vee i .

[0061] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the PWM modulation could be generated internally in the control circuit 30 of the display pixel 12 i,j in order to avoid using the signal Com i to generate it. Other embodiments could also not use PWM modulation but linear driving of the light-emitting diode LED. Other embodiments could also use other electro-optical components such as organic light-emitting diodes.

[0062] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, with regard to the second embodiment described in figure 9 , it may be advantageous to use SOI (Silicon on insulator) type structures to facilitate the management of negative voltages.

Claims

1. Display pixel (12i,j) for a display screen (60), comprising at least one light-emitting diode (LED), a circuit (40) for driving said at least one light-emitting diode, and first, second, third, and fourth electrically-conductive pads (36), the driver circuit being at least partly powered with a first power supply voltage (Vdd) received between the first and second electrically-conductive pads, characterized in that said at least one light-emitting diode is powered with a first binary signal (Vcci, Veei) received between the third and second electrically-conductive pads, the first binary signal alternates between a second power supply voltage (Vcc), greater than the first power supply voltage, and a third voltage, smaller than the first power supply voltage, the driver circuit (40) is configured to determine a digital signal (R, G, B) based on the values of a second binary signal (Dataj) on the fourth electrically-conductive pad received during each of first pulses of the first binary signal at the third voltage and to control said at least one light-emitting diode from the digital signal.

2. Display pixel according to claim 1, wherein the driver circuit (40) is configured to control said at least one light-emitting diode (LED) by pulse-width modulation from the digital signal (R, G, B).

3. Display pixel according to claim 1 or 2, not comprising any other electrically-conductive pads than the first, second, third, and fourth electrically-conductive pads (36).

4. Display pixel according to any of claims 1 to 3, wherein the driver circuit (40) is configured to turn on or turn off said at least one light-emitting diode (LED) at the rate of second pulses of the first binary signal (Vcci, Veei) at the third voltage.

5. Display pixel according to any of claims 1 to 4, wherein the driver circuit (40) is configured to determine a clock signal (Clk) and a third binary signal (Data) based on the second binary signal (Dataj).

6. Display pixel according to claim 5, wherein the driver circuit (40) comprises a circuit (50) for storing binary data determined at each first pulse based on the third binary signal.

7. Display pixel according to claim 5 or 6, wherein the second binary signal (Dataj) is intended to comprise a mixture of third pulses having the same duration and of fourth pulses having the same duration longer than the duration of each third pulse, the driver circuit (40) being configured to deliver the clock signal (Clk) at the same rate as the third and fourth pulses and the third binary signal (Data) equal to a first state or to a second state according to the succession of the third and fourth pulses.

8. Display screen (60) comprising an array of display pixels (12i,j) according to any of claims 1 to 7, the display screen further comprising circuits (22, 24) for delivering, for each display pixel, the first power supply voltage (Vdd) between the first and second electrically-conductive pads, the first binary signal (Vcci, Veei) between the third and second electrically-conductive pads, and the second binary signal (Dataj) on the fourth electrically-conductive pad.

9. Display screen according to claim 8, wherein the delivery circuits (22, 24) are configured to maintain the first electrically-conductive pad (36) at a substantially constant first potential (Vdd), the second electrically-conductive pad at a second substantially constant potential (GND), and the third electrically-conductive pad at a third potential which alternates between first and second values, either the first value is greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is smaller than the second potential.

10. Display screen according to claim 8 or 9, wherein the delivery circuits (22, 24) are configured to deliver the third voltage equal to the zero voltage.

11. Display screen according to any of claims 8 to 10, wherein the delivery circuits (22, 24) are configured to deliver the second binary signal (Dataj) alternating between two potentials, the difference in absolute value between the two potentials being smaller than the second power supply voltage (Vdd).

12. Display screen according to any of claims 8 to 11, wherein the delivery circuits (22, 24) are configured to deliver the first binary signal (Vcci, Veei) comprising, for the display of an image, the first pulse at the third voltage of a first duration and a succession of second pulses, each second pulse having a second duration shorter than the first duration.

13. Display screen according to claim 12, wherein the durations between two pairs of second successive pulses increase or decrease.

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