An optical receiver apparatus

Abstract

An optical receiver apparatus has a photodiode or a link to an external photodiode, a TIA, and an analog to digital converter to provide a digital output. A constant delay filter, CDF (3), receives a digital representation of a received optical signal and provides a digital output, whereby the apparatus is robust to electromagnetic interference. The CDF provides a finite delay time that receives a digital input signal and outputs a digital signal to said digital output delayed by said finite delay time and filters any pulses of duration shorter than said finite delay time. The receiver apparatus may also have an input emulation circuit for testing, and / or a means to adjust the bandwidth of the TI.

Description

[0001] “An Optical Receiver Apparatus”

[0002] INTRODUCTION

[0003] Field of the Invention

[0004] The invention relates to an optical receiver circuit for optical to electronic digital communications, particularly aimed at industrial applications.

[0005] Prior Art Discussion

[0006] Optical receivers are typically designed for communications systems that use fiber optic or waveguide mediums. Many industrial applications use plastic optic fiber (POF) as a medium. The receiving element is usually a photodiode. A transimpedance amplifier (TIA) converts the current generated by the photodiode into an analog voltage signal. A typical TIA consists of an amplifier with shunt feedback. The feedback network may consist of a resistor in parallel with a capacitor. A limiting amplifier or comparator usually follows the TIA to convert the signal into an analog representation of a digital signal. A decision threshold circuit is typically used to detect the signal level and adjust the limiting amplifier or comparator to give a digital output which transitions at the 50% optical input threshold. The decision threshold circuit often employs a peak detector or an integrator. There is typically a driver circuit after the limiting amplifier or comparator to transmit the digital output to another circuit, usually using a standard protocol such as transistortransistor logic (TTL) levels for single-ended transmission, or one of several well-known differential signalling protocols (LVDS, LVPECL, CML etc.). The driver circuit is generally implicit in optical receivers without elaboration.

[0007] Industrial optical receivers may operate over a wide dynamic range of input light, for example from -30dBm to +2dBm. Automatic gain control (AGC) circuits are typically used to adjust the transimpedance gain to prevent overload over the wide dynamic range. The AGC circuit typically affects control over the transimpedance gain by adjusting the TIA feedback network. The TIA feedback network may employ variable resistors and capacitors that can vary the gain and frequency compensation depending on a control signal from the AGC. A typical variable resistor circuit is a transistor whose gate or base voltage is adjusted by the AGC. It is common practice to limit the receiver bandwidth to be sufficient for the application to filter frequencies that are not of interest. This reduces the total integrated noise but must be balanced to not introduce excessive inter-symbol interference (ISI), as described in [1] page 65. One advantage to optical fiber as a transmission medium is its inherent robustness to electromagnetic interference (EMI). However, the integrated circuit of the optical receiver may be exposed to EMI and may have erroneous outputs due to EMI. Industrial receivers should be robust to EMI.

[0008] Many electronics circuits that process digital signals subject to interference employ filters, such as “glitch” filters in [2], Glitch filters such as described in [2] use a technique of creating a voltage ramp which is input into a decision threshold circuit that has a trip dependency on the transistor threshold voltage (Vth). The Vth of a transistor is notoriously variable, subject to much part-to- part mismatch and variation due to its dependency on temperature, doping concentrations, operating conditions (back-gate effects) etc. A dependency on Vth will lead to pulse-width- distortion (PWD), especially as such a parameter varies significantly with temperature and suffers notable process and mismatch effects. The invention described in [3] incorporates a comparator and reference voltage. Mismatch in components in [3] leads to PWD.

[0009] Propagation delay is a fundamental property of optical communications. An optical receiver introduces a finite propagation delay. This propagation delay may vary and is affected by many variables including process variation, device mismatch, optical power, power supply variation, and ambient conditions. The circuit of [4] addresses circuit delay compensation. An ideal optical receiver does not have any part-to-part variation in propagation delay. Some modem industrial optical receivers, such as [5] include maximum skew as a specification.

[0010] Testing of optical receivers for their basic performance metrics of PWD or propagation delay is typically a challenge. Providing an optical input to an optical receiver for testing can be expensive, or simply not practical for mass production. A standard means of measuring propagation delay involves using a high-speed digital oscilloscope, an expensive piece of equipment, as described in [6] . A technique known as pulse-reflection oscillation (PRO) as well as a technique known as timetransit oscillation (TTO) are employed in laboratory conditions to measure propagation delay in optical fibers, as described in [7],

[0011] It is standard practice to test ICs by probing them while they are still on a silicon wafer and noting the failing ICs to avoid further processing of them. This is a standard cost-saving alternative to performing tests on the ICs when they have been packaged. Many fabless IC businesses outsource the IC probing. Third-party probe facilities do not typically have the means of providing an optical signal input to integrated circuits on a wafer, and do not have any special test equipment for complex testing.

[0012] The circuit of [8] emulates a photodiode input to a TIA circuit. An approach by [9] provides a photodiode emulator circuit to provide a current input to a device-under-test (DUT).

[0013] The invention is directed towards achieving any one or more of the following objectives: an industrial optical receiver demands high EMI robustness, low propagation delay variation from part-to-part, and a low-cost means of testing optical receivers, for economical mass production, ideally without needing specialized equipment, and ideally with a means to measure key specifications such as propagation delay and pulse-width distortion.

[0014] The first technical problem, EMI, provides a challenge to industrial optical receiver design. There are many sources of EMI, but one common source is EMI generated by high-energy switching events. The EMI generated by these events may interfere with optical receivers causing erroneous outputs. The characteristic high-frequency short burst EMI induced erroneous output is depicted in Fig. 1. The photodiodes in such receivers are connected to highly sensitive inputs and as such are susceptible to EMI. EMI on the input to the optical receiver that appears to the receiver as a characteristic optical pulse will be difficult to differentiate from a real optical pulse.

[0015] Industrial optical receivers must be robust to EMI. The undesirable effect of EMI is typically incorrect data output. Depending on the characteristics of the EMI and the receiver the typical result of the EMI may take the form of brief output glitches or short duration oscillations. In less typical cases long duration false outputs may occur, or even receiver failure. In some applications, false outputs can cause destructive failure of the circuit by, for example, causing a short circuit of switching elements.

[0016] Reducing bandwidth in the front end (RC filter, active filter, bandwidth limiting TIA etc,) is a typical strategy to reduce circuit noise. A known trade-off for electrical circuits is that propagation delay increases as bandwidth reduces. This is exemplified by the well-known first order system relationship between bandwidth and time-constant: f3dB=l / 27tT ; f3dB = bandwidth, T = Time Constant Increasing propagation delay is typically undesirable for several possible reasons: a receiver IC may have an application that demands a particular maximum propagation delay specification, limiting the maximum allowable propagation delay; some applications may require short propagation delays; increased propagation delay is undesired because many applications require low skew, and increased propagation delay generally leads to more skew.

[0017] This leads us to the second technical problem, propagation delay skew. Skew does not have an industry standard definition. Generally, it is described as the maximum possible variation in propagation delay in optical receivers operating at the same conditions. There is no standard to define any allowable variation in conditions, but in practice such variations must occur. While two receivers are ostensibly operated with the same optical input power, in practice no two transmitters have identical optical power outputs, coupling efficiencies may vary from part-to-part due to lens misalignment, or poorly polished POF, or any number of other possible differences. The end result is there can be large variations in received optical power between two IC’s. Greater than 3dBs of variation in what are intended to be identical optical links would be unsurprising.

[0018] Some optical receiver applications benefit greatly from tightly controlled propagation delay variation, i.e., low skew. Many industrial power conversion applications, such as wind turbines and power transmission, use optical fibers to provide electrical isolation between low voltage control circuitry and high voltage power conversion circuitry. These applications employ circuits that are very sensitive to propagation delay variation. For example, shown in Fig. 2 is a simplified H-bridge circuit. In such a circuit the timing of the opening and closing of switches is essential to both protect the circuit and to optimize power conversion efficiency. In these circuits the switching speeds in the state-of-the-art are often less than 100 Kilobits per second (Kbps). Although the tendency of this technology is to increase switching speeds, these speeds are relatively low in terms of state-of-the-art capability of optical receiver designs. Variation in propagation delay in the optical receiver in this application has a direct impact on performance, whereas absolute propagation delay has little impact. For example, if four optical receivers are employed to control four switches as in Fig. 2, then ideally, they would all have identical propagation delays. Break- before-make switch control in such a H-bridge is standard and essential to avoid causing short- circuit currents which can destroy the circuit. There is significant power-loss (usually in the form of heat) during the break time, which itself can limit the switching frequency and conversion efficiency, so limiting this break time is important for power-conversion efficiency. Large skew between receivers will necessitate a long and inefficient ‘break’ time to prevent any possibility of a short-circuit. In this example the absolute value of the propagation delay will not impact on power conversion efficiency. Only the propagation delay skew will impact the power conversion efficiency.

[0019] As power conversion technologies improve, the tendency is towards faster switching speeds, but this may be limited by propagation delay skew. This refers to both the turn-on and turn-off times of a switch as well as the absolute data-rate. Technologies such as high voltage insulated gate bipolar transistor (IGBT) allow for very short turn-on times. The effect of faster switching is to increase the EMI generated by the switching action. This has increased the demands these technologies place on optical receivers for EMI robustness.

[0020] The propagation delay is affected by many parameters that may cause the propagation delay to vary. These include process variations, device mismatch, optical power, etc. A common approach to IC design is to ensure that the worst-case variation of these parameters still results in a maximum propagation delay that meets requirements.

[0021] The third technical problem to address, the electrical testing and measurement of propagation delay for mass production presents a significant challenge. There is presently no industrial standard that defines the conditions in which propagation skew would be measured. One approach is to define skew in an optical receiver as the part-to-part variation in a limited set of conditions, for example, limiting environmental variations such as ambient temperature and humidity, and defining limited variations in the optical receiver power supply voltage and received optical power.

[0022] In the IC industry it is common to have a performance specification that is not physically tested in every IC but is characterized on a subset of representative IC’s chosen from a range of wafers. This is often because the particular test required is either not possible or not practical to carry out on every IC, but it would usually otherwise be the preference to test this performance specification if it were possible. This type of specification is typically said to be guaranteed by design and thoroughly characterized to guarantee conformity to the specification. However, variation limits on this type of performance specification must be wide enough to guarantee all parts meet the specification. Because outlier parts cannot be identified individually, the datasheet limits must be chosen conservatively to guarantee even outlier parts fall within the spec limits. This this leads to wider specification limits than if all parts could be tested and outliers removed. A strategy to allow tighter specification limits is to ensure that all parts undergo testing for the specification. Tight specifications may be defined and parts that fail to perform within these limits may be binned. This allows tighter performance specification for the product. In the absence of a means of mass testing propagation delay in every IC, the more conservative (wider) datasheet limits must be chosen, increasing skew.

[0023] It can be difficult and expensive to measure the propagation delay in a receiver, and it is particularly burdensome to carry out such a measurement as a part of standard testing of all optical receiver ICs. The propagation delay in a receiver may be defined as the time between the optical signal reaching 50% of its output high value and the electrical measure of the digital output of the receiver reaching 50% of its supply voltage. Measuring this is most typically done with a high- performance oscilloscope and requires an optical test input signal. Doing this highly accurately in high-speed receivers typically requires expensive test equipment which might include a high- performance oscilloscope to carry out automatic measurement of the propagation delay, as well as a means of inputting an optical signal in a wafer probe or test environment. Testing propagation delay in high-volume production is very challenging. In the increasingly common fabless IC industry, the probe testing of IC wafers is often carried out by dedicated third-party companies that do not provide the option of optical testing. This is problematic for optical receiver ICs.

[0024] References

[0025] [1] Title: Design of Integrated Circuits for Optical Communications, Second Edition

[0026] Author: Behzad Razavi

[0027] ISBN: 978-1-118-33694-6

[0028] [2] Title: Digital Input Buffer with Glitch Suppression

[0029] Patent: US7397292B1

[0030] Inventors: Potanin

[0031] [3] Title: Chattering Eliminating Apparatus Including Oscillation Circuit...

[0032] Patent: US6873216B2

[0033] Inventors: Seya

[0034] [4] Title: Delay Circuit Compensation for Variations in Delay Time

[0035] Patent: US5719514

[0036] Inventors: Sato

[0037] [5] Title: AFBR-2531CZ Data Sheet

[0038] Manufacturer: Broadcom [6] Title: DR Larson, NG Paulter Jr 2007 - A measurement of propagation delay

[0039] Publication: Institute of Physics Publishing

[0040] DOI: 10.1088 / 0026-1394 / 44 / 1 / 009

[0041] [7] Title: WC Liu, MH Lu 2004 - The measurement of propagation delay in multimode optical fibre with pulse-reflection-oscillation method.

[0042] Publication: Optics & Laser Technology 36 (2004) 81-84

[0043] DOI: 10.1016 / S0030-3992(03)00138-5

[0044] [8] Title: Photodiode Emulator Circuit for Transimpedance Amplifier Testing

[0045] Patent: US10481246B2

[0046] Inventors: Aksin et al.

[0047] [9] Title: Electrically Testing an Optical Receiver

[0048] Patent: US9960844B1

[0049] Inventors: Raj et al.

[0050] SUMMARY OF THE INVENTION

[0051] We describe in various embodiments an optical receiver apparatus comprising an optical receiver comprising a TIA, and an analog to digital converter to provide a digital output.

[0052] In some embodiments, the apparatus further comprises a constant delay filter, CDF, for receiving a digital representation of a received optical signal and providing a digital output, wherein the constant delay filter receives a digital input signal and outputs a digital signal to said digital output delayed by a delay time and prevents any pulses of duration shorter than said delay time being sent to the output.

[0053] In some embodiments, the CDF comprises a differential voltage ramp generator with differential voltage outputs connected to at least one comparator.

[0054] In some embodiments, the differential voltage ramp generator further comprises a first charging element to a positive supply, a second charging element to a negative supply, and wherein a first output is connected to the first charging element through a first switch and connected to the second charging element through a second switch, and wherein a second output is connected to the first charging element through a third switch and connected to the second charging element through a fourth switch, and further consisting of a switch control circuit to open and close said switches to generate the differential voltage outputs whose polarity depends on the digital input.

[0055] In some embodiments, the first output of the differential voltage ramp generator is connected to a first capacitor and the second output of the differential voltage ramp generator is connected to a second capacitor.

[0056] In some embodiments, a capacitor connects between the outputs of the differential voltage ramp generator.

[0057] In some embodiments, the differential voltage ramp generator has two charging states which are selected by the polarity of the digital input, wherein in a first charging state the first and fourth switches are closed while the second and third switches are open, and in a second charging state the first and fourth switches are open while the second and third switches are closed.

[0058] In some embodiments, the switch control circuit is configured to implement a break-before-make control over the switches.

[0059] In some embodiments, the CDF is configured to reset its voltage ramp once the comparator has detected that the differential ramp voltage has reached a target differential voltage, so that it is ready to start the next ramp as quickly as possible.

[0060] In some embodiments, the differential voltage ramp generator comprises two linear voltage ramp generation circuits of opposite polarity.

[0061] In some embodiments, the apparatus further comprises a dual-differential amplifier, which takes two pairs of differential signals as input, applies the same gain to them and sums them to provide a single differential pair output to a comparator, and a circuit which provides reference differential voltages whose polarity is selected by the comparator output, and provides one differential input to the dual differential amplifier DDA and provides a means of adjusting the delay time, as well as acting as a hysteresis voltage to the comparator, and wherein the other differential input to the DDA is provided by the differential voltage ramp generator In some embodiments, the differential voltage ramp generator comprising two single-ended voltage ramp generators, and each single-ended voltage ramp generator comprises a charging element and a discharging element (and charging capacitors, in which one or more of the charging / discharging elements or the capacitors are trimmable.

[0062] In some embodiments, the capacitors are trimmable so as to adjust the delay time. In some embodiments, the charging elements are trimmable so as to adjust the delay time. In some embodiments, the charging and discharging elements in the voltage ramp generator are resistors or current sources.

[0063] In some embodiments, the apparatus further comprises a means of trimming or adjusting a propagation delay of signals through the optical receiver apparatus.

[0064] In some embodiments, the apparatus further comprises a CDF and a trimming or adjusting circuit to adjust said delay time of the CDF.

[0065] In some embodiments, the apparatus further comprises a digital filter and a trimming or adjusting circuit to adjust said the propagation delay of the digital filter.

[0066] In some embodiments, the apparatus further comprises an adjustable capacitance to adjust the propagation delay of the apparatus by adjusting the input capacitance seen by the receiver at the photodiode.

[0067] In some embodiments, the apparatus comprises an adjustable capacitance to adjust the propagation delay of the apparatus by adjusting the input capacitance seen by the receiver at the photodiode, in which trimming the area of the photodiode may be adjusted by connecting or disconnecting parallel photodiodes, thus altering the input capacitance and affecting the propagation delay.

[0068] In some embodiments, the TIA has a trimmable or adjustable bandwidth.

[0069] In some embodiments, the apparatus comprises a feedback network to adjust the transimpedance bandwidth of the TIA.

[0070] In some embodiments, the apparatus comprises an adjustable capacitor connected in the TIA feedback network to adjust the bandwidth of the TIA. In some embodiments, the apparatus comprises a circuit configured to adjusting a transimpedance bandwidth of the TIA by adjusting a feedback network comprising an RC combination across the TIA , which receives inputs from a trim memory.

[0071] In some embodiments, the apparatus is configured to adjust bandwidth of the TIA by a trimmable an analog filter at the output of the TIA, and preferably said filter comprises a low-pass RC filter with trimmable components.

[0072] In some embodiments, the TIA comprises a trimmable resistor connected between a TIA output and a TIA input.

[0073] In some embodiments, the apparatus comprises an integrated photodiode, wherein area of said photodiode is adjustable.

[0074] In some embodiments, the apparatus further comprises an optical input emulation circuit that can be connected to the TIA via a test mode switch, wherein said optical input emulation circuit comprises at least a current source that can be modulated on and off.

[0075] In some embodiments, said optical input emulation circuit further includes a load network to emulate a photodiode load.

[0076] In some embodiments, the digital output is coupled to the optical input emulation circuit so as to set the receiver digital output to oscillate.

[0077] In some embodiments, the optical input emulation circuit comprises an adjustable current source and a switch.

[0078] In some embodiments, the optical input emulation circuit comprises an adjustable current source, a switch, and a load network.

[0079] In some embodiments, the optical input emulation circuit comprises an adjustable current source and a switch and a load network comprising a load capacitance to emulate the photodiode capacitance load, a load resistor to emulate photodiode leakage, and a series resistor to emulate photodiode output impedance.

[0080] In some embodiments, the optical input emulation circuit comprises a digital control input to modulate test current on and off, in which the input signal to this digital control input can be configured to come from external to the optical receiver apparatus or from an internal source within the optical receiver apparatus.

[0081] In some embodiments, the apparatus further comprises a circuit configured to electrically test the propagation delay, and the output digital signal is arranged to be coupled to the input signal on the digital control input on the optical input emulation circuit, with the polarity such that the optical receiver apparatus oscillates.

[0082] In some embodiments, the receiver apparatus comprises an external delay circuit between the output digital signal and the optical input emulation circuit input, configured to add a known constant propagation delay to the oscillating signal.

[0083] In some embodiments, the apparatus comprises a PD emulator connected to the optical receiver via a switch, a test mode enable switch to allow coupling an on / off signal to the switch, a test mode select switch to select between internal signal input to the switch or external input to the switch, and an internal feedback logic inverter to couple the correct polarity to cause oscillation when the internal test mode is selected and the test mode is enabled.

[0084] DETAILED DESCRIPTION OF THE INVENTION of the

[0085] The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings, in which:

[0086] Fig. 1 is a plot showing prior art EMI output,

[0087] Fig. 2 is a diagram of a typical prior art H-Bridge,

[0088] Fig. 3 is a diagram showing a prior art self-induced EMI switching arrangement, as described below in the description,

[0089] Figs. 4 to 20 show aspects of an optical receiver apparatus with a constant delay filter (“CDF”) as follows: Fig. 4 is a high-level block diagram of a receiver with a constant delay filter (“CDF”) located after the analog-to-digital conversion circuitry (comparator) and receiving a digital input,

[0090] Fig. 5 shows the CDF standard operation with fixed delays,

[0091] Fig. 6 is a set of plots showing EMI filtering due to the CDF,

[0092] Fig. 7 is a plot showing typical prior art propagation delay vs. optical power in the presence of an automatic gain control circuit that reduces TIA transimpedance gain and increases TIA bandwidth with increasing optical power,

[0093] Fig. 8 is a block diagram of the CDF with a differential voltage ramp generator and a comparator,

[0094] Fig. 9 is a more detailed CDF block diagram with two ramp capacitors (CO, Cl), resistive current sources (RO, Rl), ideal switches (SO, SI, S2, S3), and a switch control circuit to control switch opening and closing timings,

[0095] Fig. 10 shows CDF RC voltage ramp curves,

[0096] Fig. 11 shows a CDF embodiment with current mirror sources (10, II),

[0097] Fig. 12 shows a differential cap embodiment of the CDF, and a simplified switch control circuit,

[0098] Fig. 13 is a diagram showing CDF with reset,

[0099] Fig. 14 is a set of plots showing CDF RC voltage ramp waveforms with reset,

[0100] Fig. 15 is an embodiment with CDF and a pulsed reset,

[0101] Fig. 16 is a set of plots showing CDF linear voltage ramp waveforms with pulsed reset,

[0102] Fig. 17 is a set of plots showing CDF linear voltage ramp waveforms in the presence of EMI and with reset,

[0103] Fig. 18 is an embodiment with a switch implementation using MOS devices, Fig. 19 is an embodiment of the CDF with dual single-ended ramp generators, Fig. 20 is an embodiment with a CDF and a dual-differential amplifier and a reference voltage generator,

[0104] Fig. 21 to 27 are illustrations showing aspects of a trimmable (adjustable) propagation delay, as follows:

[0105] Fig. 21 shows a trimmable TIA feedback network,

[0106] Fig. 22 shows an adjustable analog low-pass filter,

[0107] Fig. 23 shows a trimmable photodiode area,

[0108] Fig. 24 shows a trimmable capacitor at a TIA inputFig. 25 shows a receiver incorporating an adjustable CDF to trim the propagation delay, and Fig. 26 shows a receiver incorporation an adjustable digital filter,

[0109] Fig. 27 shows an optical receiver with a PD emulator,

[0110] Fig. 28 shows an optical receiver with a PD and an optical input emulator and configured to oscillate using connections which are external,

[0111] Fig. 29 shows an optical receiver configured to oscillate incorporating a delay in the feedback path,

[0112] Fig. 30 shows an oscillating test mode which is integrated and uses PD emulation circuitry, Fig. 31 shows a TIA trim and test mode circuit.

[0113] Fig. 32 shows an oscillating test mode circuit with a fuse memory,

[0114] Fig. 33 shows an embodiment that incorporates an optical emulation circuit with a testmode option to enter an oscillating mode, incorporating a CDF and incorporating propagation delay trim,

[0115] Fig. 34 shows a circuit with CDF and trim, and

[0116] Fig. 35 shows an embodiment with an oscillating setup with an external connection from Vo to Din.

[0117] Detailed Description of the Embodiments

[0118] In applications that need low propagation delay skew, increasing propagation delay is normally avoided as state-of-the-art receivers intended for low skew are generally designed with low propagation delays to minimize skew, but, essentially, such receivers are still required to be EMI robust. The present invention provides a filtering technique that improves EMI robustness, albeit with a small cost of introducing a propagation delay to the circuit.

[0119] In power converter applications the characteristic EMI is one that the application circuit generates itself; the switching event generates the EMI, as shown in Fig. 3. There are two characteristics of this EMI event that are noteworthy in relation to the present invention. Firstly, the EMI tends to have most of its power in high frequencies. Secondly, the EMI event occurs after the receiver has propagated a valid control signal to its output. The effect of such EMI on the digital output of an optical receiver is typically several short duration glitches, as shown in Fig. 1.

[0120] CONSTANT DELAY FILTER

[0121] In the invention a constant delay filter (CDF) is employed in some embodiments, and Fig. 4 shows a receiver apparatus 1 comprising an optical receiver 2 followed by a CDF 3 which provides the output voltage Vo. An ideal CDF receives a digital input and outputs a digital output delayed by a finite filter time. An ideal CDF is characterized in that it applies identical propagation delays to both rising edge and falling edge inputs, and it filters any signals of duration less than its delay time. That is, it removes any input pulses of shorter duration than the delay and prevents these pulses from being output. An ideal CDF is further characterized in that the delay time of the filter is time invariant, that is the delay time does not vary depending on the period between input edges, provided that period is greater than the delay time of the filter. The filter delay time of the CDF therefore is invariant (constant delay) to the input data rate, again, provided that the time between input data edges is greater than the filter time. In other words, an ideal CDF introduces no pulsewidth distortion (PWD) to the signal. This is typically not the case in the known prior-art circuits.

[0122] In the device of Fig. 4 the CDF introduces an extra fixed propagation delay to the optical receiver, as shown in Fig. 5. Increased propagation delay is typically undesirable in an optical receiver, but in the present invention the benefits of the delay to filter EMI outweigh any drawbacks. The function of the constant delay filter is to filter any EMI events with a duration less than the constant delay, as shown in Fig. 6. The EMI event shown at DIN (Original Output) in Fig. 6 does not affect the output signal VO (Output after CDF). In the case where the EMI event is self-induced due to a controlled switching event, such as shown in Fig. 3 , then the erroneous outputs induced by the EMI event are filtered effectively by the CDF.

[0123] The constant delay filter preferably does not introduce any PWD in normal operation. The maximum allowable PWD requirement for a CDF can be less than a nanosecond. Prior art CDF (or glitch filter) architectures when examined in detail will introduce PWD because they do not delay both rising and falling edges equally. Some CDF architectures depend on undesired complex oscillator circuits.

[0124] In one embodiment of the invention an integrated optical receiver circuit outputs a digital output signal to a constant delay filter circuit which provides a filtered digital output, as shown in Fig. 6. The CDF applies a fixed delay to both rising and falling edge. Input pulses to the CDF shorter than the fixed delay are filtered. As EMI pulses are generally of short duration this is an effective EMI filter. Moreover, the use of a CDF facilitates a change in design philosophy to improve skew. As shown in Fig. 7, the propagation delay through an optical receiver with AGC generally experiences significant variation over optical input power. Optical receivers operating with small variations in optical input power can have significant propagation delay skew. A strategy of increasing the TIA bandwidth will reduce the absolute propagation delay variation through the TIA due to the AGC. However, increasing the TIA bandwidth may compromise EMI performance. The introduction of the CDF facilitates the strategy of using a high-bandwidth optical receiver architecture with little variation over received optical powers. The CDF provides an effective EMI filter and does not introduce any propagation delay variation over optical received power. Preferably the propagation delay of the constant delay filter is trimmable.

[0125] The present invention uses in some preferred embodiments a constant delay filter that is based on generating a differential voltage ramp whose output connects to a comparator, as shown in Fig. 8 . In this example a CDF 10 comprises a differential ramp generator 11 receiving Din and linked at its output to a comparator 12 which provides DOUT. The delay time of the CDF is set by choosing the speed of the charging of the ramp and the level of comparator hysteresis. Any input that is shorter than the delay time at the input during the ramping process will be rejected.

[0126] The differential nature of the ramp 11 cancels any non-linearities or mismatches of the circuit and component, ensuring equal propagation delays for rising and falling input edges.

[0127] Non-linearities in circuit components are common. For example, it is usually cheaper in MOS processes to use MOS based capacitors as they do not require extra expensive masking steps such as for metal-insulator-metal capacitors or poly-poly capacitors which both require extra expensive process layers compared to a simple MOS process. MOS capacitors exhibit strongly non-linear capacitance with respect to the differential voltage. This introduces non-linear effects to a typical current-capacitor ramp circuit. The differential ramp may be a linear voltage ramp with respect to time, such as is generated through a constant current charging a capacitor. The ramp may also be non-linear, for example an R-C curve as generated through a resistor connection charging a capacitor.

[0128] One preferred method of generating the differential ramp voltage is shown in Fig. 9. As shown, the differential ramp generator 11 comprises a switch control circuit 21 receiving DIN and controlling a H-bridge of switches SO, SI, S2, and S3 which provides RAMP_P and RAMP_ M signals to the comparator 12, with these links having charging capacitors CO and Cl connected to RAMP P and RAMP M respectively. CO and Cl are shown connected to ground but can connect to any AC ground or virtual ground such as the negative supply voltage (VSS) or the positive supply voltage (VDD). One side of the switches SO and SI is shared and connected to the positive supply voltage (VDD) through resistor RO. The other switch connections of SO and SI are connected to the nodes RAMP_M and RAMP_P respectively. Similarly switches S2 and S3 share a connection through R1 to the negative supply voltage (VSS) while the other connection of S2 an S3 connects to RAMP_M and RAMP_P respectively. The physical connections between the switch control circuit 21 and the switches SO, SI, S2, S4 are not shown for clarity, but are implicit. The capacitors CO and Cl are charged or discharged through resistors RO or R1 by the opening or closing of switches SO, SI, S2 and S3 in a standard H-B ridge manner, creating a differential voltage ramp with a characteristic R-C curve. As the voltage ramp is differential the PWD is robust to mismatch of components.

[0129] As shown in Fig. 10 , there are two charging states, which are selected by the polarity of the digital input at DIN. In the first charging state switches SO and S3 are closed while SI and S2 are open. In the second charging stage, the reverse of this, switches SI and S2 are closed while switches SO and S3 are open. The switch control circuit controls the charging states depending on the input signal on DIN. The switch control circuit may implement a break-before-make control over the switches. The first output of the ramp voltage may be generated by charging a first capacitor, which starts from a negative supply voltage (VSS), by connecting the capacitor to a first resistor tied to the positive supply voltage (VDD). The second output of the ramp voltage is similarly generated by charging (or discharging given the inverted polarity) a second capacitor, which starts from a positive supply voltage, by connecting the capacitor to a second resistor tied to the negative supply voltage. The characteristic ramp generated using charging resistors and capacitors is the well-known RC curve with an RC time constant, as shown in Fig. 10. If the comparator detects the differential crossing point of such a curve the characteristic delay of such a circuit is set by the resistor and capacitor values and is independent of supply voltages. This is advantageous as it retains a propagation delay that is robust to supply voltage variation.

[0130] As shown in Fig. 11 the charging resistors RO, R1 may be replaced with current sources 10, Il to create a linear differential voltage ramp. Current sources may be advantageous as they usually require less IC area than large resistor values. The embodiment of Fig. 11 comprises a digital input (DIN), a differential voltage ramp generator circuit with differential voltage output terminals (RAMP_P, RAMP_M), and a comparator with a digital output (DOUT). The differential voltage ramp generator circuit further comprises capacitors CO, Cl, connected between the voltage ramp generator output terminals (RAMP P, RAMP M) and an AC ground, a first current source (10) which is coupled to a positive power supply rail (VDD) and a second current source (II) which is coupled to a negative supply rail (VSS). The current sources are connected to the capacitors through a network of switches (SO, SI, S2, S3) such that there are two logical connection states, a first state and a second state. In the first state when the digital input (DIN) is a logic one the first current source (10) is connected to the positive output terminal of the voltage ramp generator (RAMP P) and the second current source (II) is connected to the negative output terminal of the voltage ramp generator (RAMP P), and the comparator output (DOUT) is also a logic one. In the second state when the digital input (DIN) is a logic zero, the current sources connect to the opposite output terminals, that is, the first current source (10) connects to the negative output of the voltage ramp generator (RAMP_M) and the second current source (II) connects to the positive output of the voltage ramp generator (RAMP_P), and the comparator digital output (DOUT) is a logic zero. The comparator digital output changes state when voltage ramp generator differential voltage changes polarity. When the digital input logic transitions from one state to another the current sources supply current to the capacitor such that a differential voltage ramp is generated and thus generates a known filter delay between a change in DIN to the differential voltage RAMP P- RAMP_M reaching zero. The voltage ramp (RAMP_P - RAMP_M) is linear and governed by the well-known formula:

[0131] V = I.t / C where V= Differential Ramp Voltage, I = Sum of magnitudes of 10 and II, t=time, C = CO in Farads,

[0132] The starting voltage of the differential voltage ramp is the potential difference between the supply rails (VDD-VSS). As the comparator will trip when V = 0 the filter delay can be calculated using the formula:

[0133] Filter Delay = V.C / I

[0134] ; where V= VDD-VSS, I = Sum of magnitudes of 10 and II, C = CO in Farads

[0135] Because the starting voltage is either VDD-VSS or VSS-VDD the magnitude is always the same. Therefore, positive and negative ramps will have equal delay irrespective of the values of 10 and II. In practice, it is preferred that they are chosen to be of similar magnitude so that the commonmode voltage at which RAMP_P and RAMP_M are equal is adequate for the comparator input bias.

[0136] The comparator may if desired incorporate hysteresis, which will change the trip voltage accordingly. Many elements of the embodiment may be designed to be trimmable to allow trimming of the propagation delay, such as the magnitude of the current mirrors, the value of the capacitor CO, or the hysteresis voltage in the comparator. The control on the switches SO, SI, S2 and S3 is preferably implemented with a break-before-make topology to prevent any short-circuit currents. In alternative embodiments the ramp voltage may be developed across a single capacitor that is connected across the differential ramp outputs, as shown in Fig. 12, capacitor CD. This shows a receiver apparatus 30 with a differential ramp generator 31 which also has a H-bridge with switches SO to S3, and also has a current source 10 linked to VDD and a current source II linked to VSS, the current sources (10, II) replacing the charging capacitors. Using current sources to charge the capacitors instead of using resistors will result in linear ramp voltages. Fig. 12 also shows a very simply switch control mechanism, whereby DIN connects to a switch SO which is OPEN when the input is low, and DIN also connects to S2 which is CLOSED when the input is low. DIN passes through a logic inverter and connects to a switch SI which is OPEN when the input is low and connects to a switch S3 which is CLOSED when the input is low. This is a very simple H-bridge control for exemplary purposes. Preferably break-before-make timing circuitry is used to avoid any short-circuit currents.

[0137] Fig. 13 depicts a preferred embodiment with a reset function. Once the comparator has detected that the differential ramp voltage has reached its target differential voltage the CDF should reset its voltage ramp so that it is ready to start the next ramp from the same voltage as quickly as possible. This enhancement brings the nodes RAMP_P and RAMP_M quickly to their final voltages to ready the CDF to receive another input pulse without causing PWD. One possible means of providing this reset is depicted in Fig. 13. In this case a differential ramp generator 41 comprises a switch control circuit 42, a feedback XOR gate 43, a H-bridge SO to S3, charging resistors RO and R1 and outputs RAMP P and RAMP_M with capacitors CO and Cl respectively.

[0138] The generated waveforms are shown in Fig. 14 . When the digital input and digital output are the same polarity, the charging elements (RO, Rl, 10, 11) are bypassed by closing reset switches (S4, S5) across them. When the digital input DIN to the CDF 12 and the output from the CDF comparator 12 are of different polarities the discharge switches are open and do not affect the charging of the voltage ramps.

[0139] An alternative means of providing this reset is depicted in Fig. 15 in a CDF 51 of an apparatus 50. In this diagram like parts are given the same reference numerals, and in this case, there are switches S4 and S5 across the current sources 10 and II respectively. A pulse generator circuit can generate a short pulse when the comparator output polarity changes. This pulse can be used to close the discharge switches in the ramp generator for a short period. As shown in Fig. 15, a further enhancement to the CDF circuit includes a reset circuit, comprising a reset pulse generator with an input from the comparator output (DOUT) and providing an output to close switches S4 and S5 across the charging current sources (10, II, RO, Rl). The reset pulse generator outputs a short digital pulse in response to a digital edge at its input. This form of reset generator is advantageous in the presence of EMI events.

[0140] Fig. 16 depicts the input, output, and voltage ramp waveforms for the receiver of Fig. 15 in normal operation.

[0141] Fig. 17 is a set of plots of the operation of Fig. 15 in the presence of EMI events, showing EMI rejection affecting propagation delay. In more detail this depicts the duration of the EMI event increasing the propagation delay by an amount equal to twice the duration of the EMI event.

[0142] The embodiment Fig. 18 depicts a CDF with a simplified implementation of the switches (SO, SI, S2, S3) using MOS transistors (MO, Ml, M2, M3) as switches. Preferably t-gate MOS switches are used. CO and Cl are preferably identical. CO and Cl advantageously define the common-mode voltages of the differential voltage ramp output independent of the switch impedance and with little impact from parasitic capacitive switching transients from switches MO, Ml, M2 and M3.

[0143] An embodiment of a CDF for an optical receiver apparatus, 200, is shown in Fig. 19 . The apparatus 200 comprises a dual-differential amplifier 201, which takes two pairs of differential signals as input, applies the same gain to them and sums them to provide a single differential pair output to a comparator 202. A circuit 203 provides reference differential voltages REF_P, REF_M, whose polarity is selected by the comparator 202 output, and provides one differential input to the dual differential amplifier (DDA) 201 and provides a means of adjusting the delay time, as well as acting as a hysteresis voltage to the comparator. The other differential input to the DDA is provided by the differential voltage ramp generator 204 comprising two single-ended voltage ramp generators 205, 206. Each single-ended voltage ramp generator comprises a charging element (IT2, IT4) and a discharging element (IT3, IT5) which may be current sources or resistors, and charging capacitors (CT3, CT4). One or more of the charging / discharging elements (IT2, IT3, IT4, IT5), or the capacitors (CT3, CT4) may be trimmable. This may advantageously allow a trim that deliberately unbalances the ramp times of the voltages RAMP_P and RAMP_M, and deliberately introduces a PWD which may be used to compensate for PWD in the input signal, thus cancelling the overall PWD of a receiver.

[0144] Fig. 20 shows another CDF, 210, having a DDA 211, a comparator 212 at the output of the DDA 211, a reference difference voltage circuit 213, and a differential ramp generator 214. The reference difference voltage circuit consists of a current source (16) that inputs a current into a reference resistor (R2) and a common mode setting resistor (R3). The difference voltage created by the IR combination of R2 and 16 is input to the DDA and sets the comparator trip voltage for the input differential ramp (RAMP_P, RAMP_M). This advantageously allows a method of trim of the propagation delay by trimming either the value of R2 or of 16.

[0145] SKEW / PROPAGATION DELAY TRIM

[0146] The present invention provides a receiver with improved skew performance. Skew is a specification that does not presently have an industrial standard definition, nor is it an easy thing to measure. Mass production measurement of propagation delay is difficult, and a typical approach has been to accept a significant amount of skew as inherent in optical receivers. The embodiments depicted generally show a single-ended circuit for simplicity but may be fully differential circuits. For example, two single ended TIAs may be combined to form a differential TIA where one TIA serves as reference. Alternatively, a fully differential amplifier may have two photodiodes at its inputs, where one photodiode serves as a “dark” reference. Differential circuitry following the TIAs may be employed rather than the single ended circuitry which is depicted for simplicity. It is also worth noting that wherever transistors are used, it is usually trivial to interchange MOS or bipolar transistor technologies.

[0147] The propagation delay of an optical receiver may be trimmed by adjusting the transimpedance bandwidth of the TIA, in particular by adjusting the feedback network, as shown in Fig. 21 . This diagram shows a trimmable TIA feedback network 60, in which a TIA has a PD 62 at its input, and there is an RC combination 63 across the Amplifier 61, which receives inputs from a trim memory 64. The output of the TIA is linked with a circuit 65 for gain, decision threshold, and digital output control. The bandwidth of the TIA can be adjusted by trimming either the capacitor or the resistor in the feedback network 63, or both. The trim memory is typically a one-time- programmable memory that is adjusted during the testing phase of the IC, preferable during wafer probe testing. Alternative trim methods include resistor laser trim, polysilicon fuse memory, or flash memory.

[0148] In one embodiment of the invention an optical receiver includes a TIA with an adjustable feedback resistor. There may additionally be an automatic gain control circuit. The propagation delay of the optical receiver can be trimmed through a trimmable resistor element in the shunt feedback of the TIA. This has the benefit of reducing part-to-part variation in the TIA transimpedance bandwidth. Fig. 7 shows a typical relationship between propagation delay and optical power in an optical receiver with automatic gain control (AGC). For relatively low power there is no effect from the AGC, and small reductions in propagation delay may be seen due to increased drive strength from the analog induced signal, although ideally the propagation delay would not vary due to received optical power before the AGC affects the bandwidth. Once the AGC begins to reduce the shunt feedback impedance the transimpedance bandwidth increases. The resulting variation in propagation delay that typically results is depicted in Fig. 7 . If optical receivers have part-to-part variation in their transimpedance bandwidth, then that will affect this characteristic propagation delay variation over the range of optical received power. Optical receivers with trimmed TIA shunt feedback impedance can then have better matched propagation delay over a range of optical powers in the presence of automatic gain control.

[0149] In some embodiments of the invention an optical receiver includes a trimmable capacitor connected so as the affect the transimpedance bandwidth of the TIA. Preferable the TIA features an AGC circuit. Fig. 7 shows an example variation of propagation delay with received input optical power. Trimming the transimpedance bandwidth of the TIA using capacitors may be advantageous in the presence of automatic gain control. The capacitor may be trimmed in the presence of an input signal of sufficient magnitude to necessitate operation of the AGC. The AGC may be configured to adjust the transimpedance gain so as to output a target voltage when operational. This necessitates that for a given signal there must be a definite transimpedance value. If parts are trimmed using an adjustable capacitor with the same input signal magnitude applied to the TIA, then the propagation delay versus input optical power curves can be made closely match.

[0150] In one embodiment of the invention an optical receiver includes a TIA with an adjustable feedback capacitor connected in parallel with a negative feedback resistor between the TIA input and output. The capacitor value may be trimmed by adding or subtracting capacitors in parallel using switches. Trimming the capacitor adjusts the transimpedance bandwidth of the TIA in the optical receiver.

[0151] In one embodiment of the invention an optical receiver includes a TIA with an adjustable feedback capacitor connected between the TIA input and an AC ground, such as the positive or negative voltage supplies. The capacitor value may be trimmed by adding or subtracting capacitors in parallel using switches. Trimming the capacitor adjusts the transimpedance bandwidth of the TIA in the optical receiver.

[0152] In one embodiment of the invention an optical receiver includes a TIA with a combination of an adjustable feedback resistor and an adjustable capacitor connected to the TIA input. Alternatively, as shown in Fig. 22, the bandwidth of the signal from the TIA 63 can be adjusted by employing a trimmable analog filter between the output of the TIA 63 and the decision circuitry 65. For example, a simple low-pass RC filter 67 with trimmable components may be employed to filter the analog signal. An active filter may also be employed to act as a low-pass filter. A low pass filter provides a means of filtering EMI, therefore adjusting the filter to trim the propagation delay to a target value improves EMI robustness at the same time as minimizing propagation delay skew.

[0153] The propagation delay of an optical receiver may be trimmed by adjusting the input capacitance seen by the receiver at the photodiode, that is, trimming the area of the photodiode may be adjusted by connecting or disconnecting extra parallel photodiodes, thus altering the input capacitance and affecting the propagation delay. Fig. 23 depicts a receiver with differential photodiodes 73, 75, with trimmable photodiode area. Both photodiodes would be trimmed with the same trim code. Only one of the photodiodes would be configured to receive an optical input signal, the active PD, while the other would not receive an optical input signal, through for example, an opaque covering such as metal over the dark (or non-active) photodiode, or by placing in a location that does not receive an optical signal. A receiver apparatus 70 has a trim memory linked by switches 72 to an active PD with trimmable area 73 and linked by switches 74 to a non-active PD with trimmable area 75. The photodiodes 73 and 75 are linked to the input of the optical receiver 76 which provides the output Vo. Trimming the photodiode area to adjust the TIA bandwidth, and therefore the propagation delay, has the beneficial effect of increasing light received when the bandwidth is slowed down, thus optimizing receiver sensitivity for a given propagation delay target. A low bandwidth photodiode provides a means of filtering EMI, therefore adjusting the photodiode area to trim the propagation delay to a target value improves EMI robustness at the same time as minimizing propagation delay skew.

[0154] A capacitance connected in parallel with the input photodiode may be trimmed by connecting or disconnecting capacitive elements to alter the input capacitance of the optical receiver and thus alter the propagation delay of the receiver, as shown in Fig. 24 . Fig. 24depicts an input PD 83 coupled to a TIA 81. The PD 83 has a trimmable capacitance 84 across it. This trim method has the benefit of requiring less on-chip area than other means of affecting the input capacitance.

[0155] CDF AND PROP DELAY TRIM

[0156] Fig. 25 shows a block diagram of a receiver in which the propagation delay may be affected through the incorporation of a constant delay filter 86 with an adjustable propagation delay time. Fig. 25 depicts an input PD 83 coupled to a TIA 81, the output of the TIA is linked with a circuit 65 for gain, decision threshold, and digital output control which links to a trimmable CDF block 86. This is advantageous in that this embodiment incorporates propagation delay trim to improve skew performance as well as availing of the EMI filtering advantages of the CDF. It is also advantageous that the CDF provides a constant delay that is ideal for low skew.

[0157] Fig. 26 is an embodiment of a receiver 88 where the gain, decision threshold, and digital output control circuit 65 links to a trimmable digital filter 89. The receiver propagation delay can be changed through the introduction of the adjustable digital filter 87. This has the disadvantage of requiring extra digital circuitry but has the advantage of availing of various advantages of digital filters, such as precision of the filter.

[0158] OPTICAL INPUT EMULATION CIRCUIT)

[0159] The present invention provides a means of emulating optical testing of the integrated circuit without the need for an optical input. In the case of a receiver that does not integrate the photodiode the present invention may also emulate the presence of the photodiode load. Secondly, the present invention provides a test configuration that allows for electrical testing of propagation delay, and PWD.

[0160] To emulate optical testing, an optical input emulation circuit is used to provide a test mode whereby an on-chip circuitry to provide a test function. It consists of an adjustable current source, such as a current output digital-to-analog converter (IDAC), and a switch. In the case of an integrated receiver with an integrated photodiode on the same substrate a further load to emulate the photodiode is not necessary. Alternatively, in the case of an integrated receiver that does not incorporate the photodiode the optical input emulation circuit may include a load network, such as a load capacitance to emulate the photodiode capacitance load, a load resistor to emulate photodiode leakage, and a series resistor to emulate photodiode output impedance. When using a testmode with a photodiode load network emulating a photodiode load, the load is connected to the input of the TIA via a testmode switch. The photodiode optical current emulation circuit is then modulated on and off using a different testmode switch while the load network remains connected to the input of the TIA.

[0161] Referring to Fig. 27 a receiver apparatus 90 has an optical receiver 91 at the input of which there is an optical input emulation circuit 92 with a digital controller. The optical input emulation circuit is fully integrated on a substrate with the optical receiver circuit 91. It is disconnected by the controller 93 from the optical receiver during normal operation. The chip can be configured to enter a test mode wherein it connects the optical input emulation circuit to the input of the optical receiver via a switch, as shown in Fig. 27 . The purpose of the optical emulation circuit is to input a current signal to the TIA that emulates optically induced current from a photodiode to perform tests without requiring an optical input to the IC. The optical emulation circuit may additionally emulate the load presented by a photodiode, if required. The optical input emulation circuit has a digital control input to modulate the test current on and off. The input signal to this digital control input can be configured to come from external to the IC or from an internal source within the IC. Fig. 27 does not explicitly depict a photodiode, but there may be a photodiode present integrated into the optical receiver, in which case the optical input emulation circuit need only emulate a photodiode input current, or alternatively the IC may be intended to connect to an external discrete photodiode, in which case the optical input emulation circuit may additionally emulate the load circuit of an external photodiode.

[0162] To electrically test the propagation delay, the IC can be configured via a test mode to couple the output digital signal to be the input signal on the digital control input on the optical input emulation circuit, with the polarity such that the receiver IC oscillates, as shown in Fig. 28. This diagram shows a receiver apparatus 100 having an optical receiver 101 connected via a switch 102 to a PD emulator comprising a current source 103. The optical receiver 101 also includes an integrated photodiode 104 at its input. The connection between the receiver output and the optical emulation circuit test mode input is made externally in Fig. 28.

[0163] The propagation delay of the signal from the optical emulation circuit input to the receiver IC output will determine the period of oscillation on the output signal. In the case where both rising edge inputs and falling edge inputs experience the same propagation delay, the duty cycle of the oscillation will be 50%. In the case where the propagation delays experienced by rising and falling edge inputs is different the duty cycle will not be 50% and will be indicative of pulse-width- distortion.

[0164] Measurement of an oscillator frequency and duty cycle is standard test procedure and is commonly carried out in a wafer-probe or test environment. Highly accurate measurements are possible with standard test equipment that would be commonly available to third-party wafer probe testing services. Thus, the problem of how to measure propagation delay and pulse-width-distortion in a test environment without requiring an optical input or expensive specialized test equipment is solved. The propagation delay of the optical receiver can therefore be economically and accurately measured in mass production of an optical receiver IC, providing the practical means by which propagation delay trim can be carried out.

[0165] Fig. 29, shows an embodiment similar to Fig. 28 with the addition of an external delay circuit. The purpose of the delay circuit is to add a known constant propagation delay to the oscillating signal. This known delay can simply be subtracted from the propagation delay calculated through measurement of the oscillation frequency. This is advantageous in the case of a receiver where some analog elements, such as the TIA, or peak-detector, or automatic-gain-control have not had time to come to a settled value. For example, if the propagation delay after the TIA is very small then the input signal to the TIA, when in oscillation mode, may change polarity before the TIA has reached its final value as it is limited by its bandwidth. This is problematic, as the propagation delay in this case will not reflect the real operating case where input signal is of sufficiently long duration to allow the TIA to settle, and consequently allow the decision circuitry to accurately determine the signal strength, and therefore the 50% crossing value, and also apply the correct automatic gain setting. This additional delay time therefore allows the analog circuitry to settle before the change in polarity of the input signal pulse arrives. The resulting propagation delay of the receiver will therefore better match that expected in real operating conditions. The external delay element may therefore improve accuracy of propagation delay measurements. It is also possible to introduce this delay to be internal to the IC. This may be advantageous as it results in less external test circuitry.

[0166] Optionally the test mode could be configurable such that the coupling of the receiver output signal to the optical emulation circuit input is made internally, as shown in Fig. 30.

[0167] Fig. 30 shows an apparatus 110 with an optical receiver 101, a PD emulator 103 connected to an optical receiver 101 via a switch 102, a test mode enable switch 105 to allow coupling an on / off signal to the switch 102, a test mode select switch 106 to select between internal signal input to the switch 102 or external input to the switch 102, and an internal feedback logic inverter 107 to couple the correct polarity to cause oscillation when the internal test mode is selected and the test mode is enabled. Coupling Vo internally advantageously requires fewer external connections in the test environment. The test mode select switch 102 may be configured to provide the input from external to the IC, and thus the connections required to set the receiver to oscillate may alternatively be made external to the apparatus. The oscillation signal will be output by the IC driver and measurable on the IC output pin. Fig. 30 additionally depicts the switchable current source in the PD emulator circuit 103 as being adjustable. The adjustable current source allows emulation of a range of input optical powers allowing measurement of propagation delay over a range of optical power, providing a means of making a precise measurement of propagation delay skew over a range of optical powers.

[0168] Moreover, since the switchable current source in the optical input emulation circuit is adjustable the part may be trimmed to be particularly low skew at a desired optical power that may be appropriate to the receiver application.

[0169] Fig. 30 additionally depicts a voltage buffer with an input from the oscillating output signal and with an output into a low pass RC fdter incorporating a resistor load RL and a capacitor load CL and generating a voltage VI. The DC component of the voltage VI is proportional to the duty cycle of the square wave output in the oscillating mode. For example, with a 50% duty cycle this voltage is 50% of the supply voltage. The duty cycle of the output oscillating signal is indicative of the PWD of the receiver, with 50% duty cycle indicating zero PWD. Deviations from the 50% duty cycle indicate PWD. A measure of the duty cycle and the oscillation period allow calculation of the PWD. This voltage V 1 may be measured in test as a convenient means to measure the PWD.

[0170] COMBINED FEATURES

[0171] Embodiments of the invention may have one or any desired combination of features selected from CDF circuits, propagation delay trim, and optical input emulation. The description above focuses on receiver apparatus with one of these aspects, however the following describes apparatus with some preferred combinations.

[0172] OPTICAL INPUT EMULATION AND PROP DELAY TRIM

[0173] The optical input emulation circuitry configured to oscillate can be combined with a method to trim the propagation skew to provide a means of measuring the propagation delay before trimming it to a target so as to reduce propagation delay skew. Fig. 31 shows the optical input emulation test mode circuit combined with a propagation delay trim that alters the feedback network (resistor or capacitor) in the TIA. In particular, this diagram shows an apparatus 120 with gain, decision and digital output circuits 121 fed by a TIA 122. There is an RC combination 123 in parallel with the amplifier and this is linked with a trim memory 124. Also, there is a PD / optical input emulator combination 125 at the input to the TIA 122. Fig. 32 shows an optical receiver apparatus 130 which can be configured by a test mode switch 135 to provide an oscillating mode of operation, with an optical receiver 131, a photodiode 134, an optical input emulator 132, and a fuse memory 133. The polarity of the photodiode is such that the cathode connects to a positive voltage (VDD) and the anode connects to the optical receiver input. The output polarity of the receiver in Fig. 32 is shown with an output polarity at Vo inverted with respect to the input signal. The optical receiver can be programmed through the fuse memory to adjust its propagation delay.

[0174] CDF, OPTICAL INPUT EMULATION, and PROP DELAY TRIM

[0175] Fig. 33 shows an optical receiver apparatus with an optical input emulation circuit 153 coupled to the input of an optical receiver circuit 151 which outputs to a trimmable CDS 152. The constant delay filter can effectively filter the characteristic EMI in power converter applications. A CDF with a trimmable delay time makes it an effective method of implementing a propagation delay to reduce skew. Carrying out the trim using the optical input emulator test mode circuit configured to oscillate the receiver allows a practical means of carrying out mass-production trim and testing of optical receivers. The apparatus 150 has the various advantages of these components as described above in a synergistic manner. In particular the EMI filtering capability of the CDF is incorporated, as well as taking advantage of the CDF circuit to provide a convenient means of applying a propagation delay trim.

[0176] Advantageously, the CDF architecture previously described, can be easily modified to provide several means with which to trim the filter delay time, as shown in Fig. 34. Fig. 34, consists of a constant delay filter 140 similar to as described in other embodiments with the enhancement of several adjustable components to allow implementation of a trimmable delay. It has a differential voltage ramp generator 141 linked with the input of a comparator 142. The generator 141 has a Elbridge 143 (SO, SI, S2, S3, CTO, CT1), a switch control circuit 144, and a reset pulse generator 145 and reset switches (S4, S5) as described for ramp generators of other embodiments. Shown are trimmable charging elements RTO and RT1, which may be either adjustable resistors or adjustable current sources. CTO and CT1 are trimmable capacitors that may have their capacitance adjusted, for example by connecting or disconnecting parallel capacitors using switches. The comparator 142 may have adjustable hysteresis, which may increase or decrease the trip voltage thus altering the propagation delay. The propagation delay may be trimmed during testing by adjusting one or more of the outlined adjustable elements. Trimming the CDF allows a means of maximizing the EMI robustness at the same time as minimizing the propagation delay skew. For example, an optical receiver may have a datasheet maximum propagation delay specification of 100ns. Not including the CDF, the receiver front-end may have, for example, a propagation delay of between 40ns and 70ns. This is a skew of 30ns. This variation is mostly due to variation in IC process corners and part-to-part variation. A CDF is included before the optical receiver digital output. The CDF can have a trimmable delay between 30ns and 60ns. Parts with a 40ns propagation delay in the front-end can be combined with a CDF trimmed to 60ns to give a 100ns total propagation delay. Parts with a 70ns front-end propagation delay can be combined with a CDF trimmed with a 30ns propagation delay, again giving a total propagation delay of 100ns. All parts can therefore be trimmed to have precisely 100ns of propagation delay, thus removing skew and improving EMI robustness.

[0177] The target voltage may be trimmed. A further advantage of this CDF is that it is relatively easy to design it with a particular temperature co-efficient to increase or decrease the delay time to compensate for any temperature co-efficient in the propagation delay in the prior circuitry, thus achieving a constant propagation delay as temperature varies.

[0178] In one embodiment of the invention an optical receiver includes an integrated photodiode with a trimmable area selectable via switches coupling the photodiodes to the TIA input. Varying the photodiode area can adjust the transimpedance bandwidth, thus adjusting the propagation delay. This has the potential advantage of also optimizing the sensitivity of the receiver by increasing the light received.

[0179] The optical input emulation circuit allows connecting an adjustable current source as an input to the optical receiver. The current source can be modulated on and off by means of a switch. The value of the current can be adjusted to emulate light of varying optical powers. The part will respond to the modulated current input as it would to a modulated optical input. This circuit can be integrated into the optical receiver integrated circuit removing the need to provide any optical input to a test or wafer probe environment. The digital control input to the switch can be controlled from the test environment.

[0180] The present invention improves robustness to EMI. The present invention reduces propagation delay skew. The present invention provides a means of electrically testing integrated receiver propagation delay. The solutions to these technical problems combine synergistically to improve EMI, reduce skew, while at the same time providing the means of electrically testing the receiver to affect these improvements.

[0181] Improvements to EMI robustness afforded by the invention allows use of the optical receiver of the invention in increasingly harsh industrial environments such as in power converters with ever increasing switching speeds. Devices with susceptibility to EMI cannot be used in these environments.

[0182] Improvements to skew will translate to higher conversion efficiency for power converters used for example in wind turbines.

[0183] The present invention, through a test mode with an optical input emulation circuit, increases test coverage on parts thus increasing industrial robustness. This circuit also reduces manufacturing costs as it can be used in wafer probe to identify out-of-spec die at the most economical point in the manufacturing process.

Claims

Claims1. An optical receiver apparatus comprising an optical receiver comprising a TIA, and an analog to digital converter to provide a digital output.

2. An optical receiver apparatus as claimed in claim 1, further comprising a constant delay filter, CDF (3), for receiving a digital representation of a received optical signal (DIN) and providing a digital output (Vo), wherein the constant delay filter receives a digital input signal and outputs a digital signal to said digital output delayed by a delay time and prevents any pulses of duration shorter than said delay time being sent to the output.

3. An optical receiver apparatus as claimed in claim 2, wherein the CDF comprises a differential voltage ramp generator (11) with differential voltage outputs (RAMP_P, RAMP M) connected to at least one comparator.

4. An optical receiver apparatus as claimed in claim 3, wherein the differential voltage ramp generator further comprises a first charging element (RO, 10) to a positive supply, a second charging element (Rl, II) to a negative supply, and wherein a first output (RAMP_P) is connected to the first charging element through a first switch (SI) and connected to the second charging element through a second switch (S3), and wherein a second output (RAMP_M) is connected to the first charging element through a third switch (SO) and connected to the second charging element through a fourth switch (S2), and further consisting of a switch control circuit (21) to open and close said switches to generate the differential voltage outputs whose polarity depends on the digital input (DIN).

5. An optical receiver apparatus as claimed in claims 3 to 4, wherein the first output of the differential voltage ramp generator (RAMP P) is connected to a first capacitor (CO) and the second output of the differential voltage ramp generator (RAMP_M) is connected to a second capacitor (Cl).

6. An optical receiver apparatus as claimed in any of claims 3 to 5, wherein a capacitor (CD) connects between the outputs (RAMP_P, RAMP_M) of the differential voltage ramp generator.

7. An optical receiver apparatus as claimed in any of claims 3 to 6, wherein the differential voltage ramp generator has two charging states which are selected by the polarity of the digital input (DIN), wherein in a first charging state the first (SI) and fourth (S2) switches are closed while the second (S3) and third (SO) switches are open, and in a second charging state the first (SI) and fourth (S2) switches are open while the second (S3) and third (SO) switches are closed.

8. An optical receiver apparatus as claimed in any of claims 3 to 7, wherein the switch control circuit (21) is configured to implement a break-before-make control over the switches.

9. An optical receiver apparatus as claimed in any of claims 3 to 8, wherein the CDF is configured to reset its voltage ramp (S4, S5) once the comparator has detected that the differential ramp voltage has reached a target differential voltage, so that it is ready to start the next ramp as quickly as possible.

10. An optical receiver apparatus (200) as in any of claims 3 to 9, wherein the differential voltage ramp generator comprises two linear voltage ramp generation circuits of opposite polarity (204).

11. An optical receiver apparatus (200, 210) as in claims 3 to 10, further comprising a dualdifferential amplifier (201), which takes two pairs of differential signals as input, applies the same gain to them and sums them to provide a single differential pair output to a comparator (202), and a circuit (203) which provides reference differential voltages (REF_P, REF_M) whose polarity is selected by the comparator (202) output, and provides one differential input to the dual differential amplifier DDA (201) and provides a means of adjusting the delay time, as well as acting as a hysteresis voltage to the comparator, and wherein the other differential input to the DDA is provided by the differential voltage ramp generator.

12. An optical receiver apparatus as claimed in any of claims 3 to 11, wherein the differential voltage ramp generator (204) comprises two single-ended voltage ramp generators (205, 206), and each single-ended voltage ramp generator comprises a charging element (IT2, IT4) and a discharging element (IT3, IT5) and charging capacitors (CT3, CT4), in which one or more of the charging / discharging elements (IT2, IT3, IT4, IT5) or the capacitors (CT3, CT4) are trimmable.

13. An optical receiver apparatus (140) as claimed in any of claims 5 to 12, wherein the capacitor is trimmable so as to adjust the delay time.

14. An optical receiver apparatus (140) as claimed in any of claims 4 to 13, wherein the charging elements (RTO, RT1) are trimmable so as to adjust the delay time.

15. An optical receiver apparatus as claimed in any of claims 4 to 14, wherein the charging and discharging elements in the voltage ramp generator are resistors or current sources.

16. An optical receiver apparatus as claimed in any preceding claim, further comprising a means of trimming or adjusting a propagation delay of signals through the optical receiver apparatus.

17. An optical receiver apparatus as claimed in claim 16, further comprising a CDF and a trimming or adjusting circuit to adjust said delay time of the CDF (86).

18. An optical receiver apparatus as claimed in claim 16 or claim 17, further comprising a digital fdter and a trimming or adjusting circuit to adjust the propagation delay of the digital filter (89).

19. An optical receiver apparatus as claimed in any of claims 16 to 18, further comprising an adjustable capacitance to adjust the propagation delay of the apparatus by adjusting the input capacitance seen by the receiver at the input to the TIA.

20. An optical receiver apparatus as claimed in any of claims 16 to 19, further comprising a photodiode connected to the input of the TIA, in which the area of the photodiode may be adjusted by connecting or disconnecting parallel photodiodes, thus altering the input capacitance and affecting the propagation delay.

21. An optical receiver apparatus as claimed in any preceding claim, wherein the TIA has a trimmable or adjustable bandwidth.

22. An optical receiver apparatus as claimed in claim 21, comprising a feedback network to adjust the transimpedance bandwidth of the TIA.

23. An optical receiver apparatus as claimed in claim 22, comprising an adjustable capacitor connected in the TIA feedback network to adjust the bandwidth of the TIA.

24. An optical receiver apparatus as claimed in any of claims 21 to 23, wherein the apparatus comprises a circuit configured to adjusting a transimpedance bandwidth of the TIA by adjusting a feedback network comprising an RC combination (63) across the TIA (61), which receives inputs from a trim memory (64).

25. An optical receiver apparatus as claimed in any of claims 16 to 24, further comprising an analog filter and a trimming or adjusting circuit to adjust the propagation delay of the analog filter (89).

26. An optical receiver apparatus as claimed in claim 25, wherein said analog filter comprises a low-pass RC filter with trimmable components.

27. An optical receiver apparatus as claimed in any of claims 21 to 26, wherein the TIA comprises a trimmable resistor connected between a TIA output and a TIA input.

28. An optical receiver apparatus as claimed in any preceding claim, further comprising an optical input emulation circuit that can be connected to the TIA via a test mode switch, wherein said optical input emulation circuit comprises at least a current source that can be modulated on and off.

29. An optical receiver apparatus as claimed in claim 28, wherein said optical input emulation circuit further includes a load network to emulate a photodiode load.

30. An optical receiver apparatus as claimed in either of claims 28 or 29, wherein the digital output is coupled to the optical input emulation circuit so as to set the receiver digital output to oscillate.

31. An optical receiver apparatus as claimed in any of claims 28 to 30, wherein the optical input emulation circuit comprises an adjustable current source and a switch.

32. An optical receiver apparatus as claimed in any of claims 28 to 31, wherein the optical input emulation circuit comprises an adjustable current source, a switch, and a load network.

33. An optical receiver apparatus as claimed in any of claims 28 to 32, wherein the optical input emulation circuit comprises an adjustable current source and a switch and a load network comprising a load capacitance to emulate the photodiode capacitance load, a load resistor to emulate photodiode leakage, and a series resistor to emulate photodiode output impedance.

34. An optical receiver apparatus as claimed in any of claims 28 to 33, wherein the optical input emulation circuit comprises a digital control input to modulate test current on and off, in which the input signal to this digital control input can be configured to come from external to the optical receiver apparatus or from an internal source within the optical receiver apparatus.

35. An optical receiver apparatus as claimed in any of claims 28 to 34, further comprising a circuit configured to electrically test the propagation delay, and the output digital signal is arranged to be coupled to the input signal on the digital control input on the optical input emulation circuit, with the polarity such that the optical receiver apparatus oscillates.

36. An optical receiver apparatus as claimed in any of claims 30 to 35, wherein the receiver apparatus comprises an external delay circuit between the output digital signal and the optical input emulation circuit input, configured to add a known constant propagation delay to the oscillating signal.

37. An optical receiver apparatus as claimed in any preceding claim, comprising a PD emulator (103) connected to the optical receiver (101) via a switch (102), a test mode enable switch (105) to allow coupling an on / off signal to the switch (102), a test mode select switch (106) to select between internal signal input to the switch (102) or external input to the switch (102), and an internal feedback logic inverter (107) to couple the correct polarity to cause oscillation when the internal test mode is selected and the test mode is enabled.

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