Confinement apparatus system with integrated ferromagnetic structures

Abstract

A confinement apparatus system with one or more integrated ferromagnetic structures is provided. The confinement apparatus system includes a confinement apparatus chip; a plurality of electrodes formed on the confinement apparatus chip to form a confinement apparatus; and a spaced flip chip having at least one ferromagnetic structure formed thereon. The confinement apparatus is configured to confine one or more quantum objects and the spaced flip chip is mounted to the confinement apparatus chip with a set distance therebetween.

Description

CONFINEMENT APPARATUS SYSTEMWITH INTEGRATED FERROMAGNETIC STRUCTURESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 18 / 667,007, filed May 17, 2024, which claims priority to U.S. Application No. 63 / 509,098, filed June 20, 2023, the contents of which are incorporated by reference herein in their entireties.TECHNICAL FIELD

[0002] Various embodiments relate to apparatuses, systems, and methods relating to confinement apparatus systems having integrated ferromagnetic structures, quantum processors comprising confinement apparatus systems having integrated ferromagnetic structures, quantum computers comprising confinement apparatus systems having integrated ferromagnetic structures, and / or the like. An example embodiment relates to an confinement apparatus system comprising a confinement apparatus substrate having electrodes defining a confinement apparatus formed thereon and a spaced flip chip having one or more ferromagnetic structures formed thereon where the spaced flip chip is a chip that is flip-chip mounted to the confinement apparatus chip with a set distance between the confinement apparatus chip and the spaced flip chip.BACKGROUND

[0003] For various reasons, it may be desired to generate a magnetic field (or magnetic field gradient, higher order derivatives, and / or any combination thereof) at particular locations of an ion trap or confinement apparatus. Conventional techniques for generating local magnetic fields and / or magnetic field gradients at particular locations of an ion trap, such as current carrying wires, magnets external to the confinement apparatus structure, or current carrying coils, may cause significant heating or may not enable sufficient control of the magnetic field or magnetic field gradient at the particular location. Through applied effort, ingenuity, and innovation many deficiencies of prior confinement apparatuses have been solved by developing solutions that are structured in accordance with the embodiments of the present invention, many examples of which are described in detail herein.BRIEF SUMMARY OF EXAMPLE EMBODIMENTS

[0004] Example embodiments provide apparatuses, systems, and corresponding methods for confinement apparatus systems comprising one or more integrated ferromagnetic structures, various systems comprising at least one confinement apparatus system having one or more integrated ferromagnetic structures, including quantum processors, such as quantum charge coupled device (QCCD)-based quantum processors, for example, and / or quantum computers comprising at least one confinement apparatus system having integrated ferromagnetic structures. In various embodiments, a confinement apparatus system comprises a confinement apparatus chip on which electrical components are disposed and / or formed. The electrical components include electrodes configured for defining a confinement apparatus defining one or more confinement regions within which quantum objects may be confined. In various embodiments, a quantum object is a neutral or ionic atom; neutral, ionic, or multipole molecule; quantum particle; quantum dot; and / or other object having quantum states that can be manipulated and / or controlled.

[0005] In various embodiments, the confinement apparatus system further includes a spaced flip chip that is mounted to the confinement apparatus chip with a set distance between the spaced flip chip and the confinement apparatus. One or more ferromagnetic structures are formed on the spaced flip chip. In various embodiments, the one or more ferromagnetic structures include one or more ferromagnetic materials (e.g., iron, cobalt, nickel, ferromagnetic alloy, and / or the like).

[0006] According to an aspect of the present disclosure, a confinement apparatus system having one or more integrated ferromagnetic structures is provided. In an example embodiment, the confinement apparatus system includes a confinement apparatus chip; a plurality of electrodes formed on the confinement apparatus chip to form a confinement apparatus; and a spaced flip chip having at least one ferromagnetic structure formed thereon. The spaced flip chip is mounted to the confinement apparatus chip with a set distance therebetween. The confinement apparatus is configured to confine one or more quantum objects.

[0007] In an example embodiment, the confinement apparatus defines at least one gradient gate position and the at least one ferromagnetic structure is positioned to cause a magnetic field or magnetic field gradient in the at least one gradient gate position.

[0008] In an example embodiment, a geometry of the magnetic field formed by the at least one ferromagnetic structure at a position defined by the confinement apparatus is one of uniform, dipole, multipole, or a combination of two or more thereof.

[0009] In an example embodiment, the confinement apparatus defines at least one measurement position and a portion of the spaced flip chip that corresponds to the at least one measurement position is transparent to light of a detection frequency.

[0010] In an example embodiment, the detection frequency is a fluorescence frequency of a quantum object of the one or more quantum objects.

[0011] In an example embodiment, the confinement apparatus defines at least one measurement position and the spaced flip chip comprises a through window that corresponds to the at least one measurement position.

[0012] In an example embodiment, the at least one ferromagnetic structure comprises a ferromagnetic material.

[0013] In an example embodiment, the spaced flip chip is flip-chip mounted to the confinement apparatus chip using a plurality of spacers such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are separated from one another by the set distance and the set distance is configured to provide a desired magnetic field geometry at a position defined by the confinement apparatus.

[0014] In an example embodiment, the plurality of spacers are positioned at respective positions the enable one or more manipulation signals to be applied to one or more positions defined by the confinement apparatus via a space between the quantum -object facing surface of the confinement apparatus chip and the quantum-object-facing surface of the spaced flip chip.

[0015] In an example embodiment, the spaced flip chip is flip-chip mounted to the confinement apparatus chip such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are parallel to one another.

[0016] In an example embodiment, a quantum-object-facing surface of the spaced flip chip has a conductive coating disposed thereon.

[0017] In an example embodiment, the spaced flip chip comprises one or more of an anti- reflective coating or a transparent conductive coating.

[0018] In an example embodiment, one or more optical elements are formed or disposed on or in the spaced flip chip.

[0019] In an example embodiment, the spaced flip chip is flip chip mounted to the confinement apparatus chip using one or more spacers to maintain the set distance between the spaced flip chip and the confinement apparatus chip.

[0020] According to another aspect of the present disclosure, a quantum computer (e.g., a QCCD-based quantum computer) is provided. In an example embodiment, the quantum computer includes a confinement apparatus system having one or more integrated ferromagnetic structures. In an example embodiment, the confinement apparatus system includes a confinement apparatus chip; a plurality of electrodes formed on the confinement apparatus chip to form a confinement apparatus; and a spaced flip chip having at least one ferromagnetic structure formed thereon. The spaced flip chip is mounted to the confinement apparatus chip with a set distance therebetween. The confinement apparatus is configured to confine one or more quantum objects.

[0021] In an example embodiment, the confinement apparatus defines at least one gradient gate position and the at least one ferromagnetic structure is positioned to cause a magnetic field or magnetic field gradient in the at least one gradient gate position.

[0022] In an example embodiment, a geometry of the magnetic field formed by the at least one ferromagnetic structure at a position defined by the confinement apparatus is one of uniform, dipole, or multipole, or a combination of two or more thereof.

[0023] In an example embodiment, the confinement apparatus defines at least one measurement position and a portion of the spaced flip chip that corresponds to the at least one measurement position is transparent to light of a detection frequency.

[0024] In an example embodiment, the detection frequency is a fluorescence frequency of a quantum object of the one or more quantum objects.

[0025] In an example embodiment, the confinement apparatus defines at least one measurement position and the spaced flip chip comprises a through window that corresponds to the at least one measurement position.

[0026] In an example embodiment, the at least one ferromagnetic structure comprises a ferromagnetic material.

[0027] In an example embodiment, the spaced flip chip is flip-chip mounted to the confinement apparatus chip using a plurality of spacers such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are separated from one another by the set distance and the set distance is configured to provide a desired magnetic field geometry at a position defined by the confinement apparatus.

[0028] In an example embodiment, the plurality of spacers are positioned at respective positions the enable one or more manipulation signals to be applied to one or more positions defined by the confinement apparatus via a space between the quantum -object facing surfaceof the confinement apparatus chip and the quantum-object-facing surface of the spaced flip chip.

[0029] In an example embodiment, the spaced flip chip is flip-chip mounted to the confinement apparatus chip such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are parallel to one another.

[0030] In an example embodiment, a quantum-object-facing surface of the spaced flip chip has a conductive coating disposed thereon.

[0031] In an example embodiment, the spaced flip chip comprises one or more of an anti- reflective coating or a transparent conductive coating.

[0032] In an example embodiment, one or more optical elements are formed or disposed on or in the spaced flip chip.

[0033] In an example embodiment, the spaced flip chip is flip chip mounted to the confinement apparatus chip using one or more spacers to maintain the set distance between the spaced flip chip and the confinement apparatus chip.

[0034] According to still another aspect, a method for fabricating a confinement system having one or more integrated ferromagnetic structures is provided. In an example embodiment, the method includes providing a confinement apparatus chip having a confinement apparatus configured to confine one or more quantum objects formed thereon; providing a spaced flip chip having at least one ferromagnetic structure formed thereon; and mounting the spaced flip chip to the confinement apparatus chip such that there is a set distance between the spaced flip chip and the confinement apparatus chip.

[0035] In an example embodiment, the method further includes setting a magnetic field profile of the at least one ferromagnetic structure.

[0036] In an example embodiment, the magnetic field profile of the at least one ferromagnetic structure is set by leveraging shape anisotropy of the at least one magnetic field structure, leveraging crystalline anisotropy of the at least one magnetic field structure, leveraging magnetostatic energy of the at least one magnetic field structure, using pinning layers, or using field annealing.

[0037] In an example embodiment, the spaced flip chip is flip-chip mounted to the confinement apparatus chip using a plurality of spacers such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are separated from one another by the set distance and the set distance is configuredto provide a desired magnetic field geometry at a position defined by the confinement apparatus.

[0038] In an example embodiment, the method further includes forming one or more windows in the spaced flip chip that are disposed at respective locations corresponding to respective measurement zones defined by the confinement apparatus.

[0039] In an example embodiment, the method further includes at least one of (a) backside polishing the spaced flip chip, (b) depositing a conductive coating to a quantumobject-facing surface of the spaced flip chip, (c) applying an anti -reflective coating to at least one of the quantum-object-facing surface or the backside surface of the spaced flip chip, or (d) applying a transparent conductive coating to at least one of the quantum-object-facing surface or the backside surface of the spaced flip chip.

[0040] In an example embodiment, the method further includes fabricating one or more optical elements on or in the spaced flip chip prior to flip-chip mounting the spaced flip chip to the confinement apparatus chip.

[0041] In an example embodiment, the spaced flip chip is flip chip mounted to the confinement apparatus chip.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0042] Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0043] Figure 1 is a schematic diagram illustrating an example quantum computing system comprising confinement apparatus system having integrated ferromagnetic structures, according to an example embodiment.

[0044] Figure 2 is a schematic cross-section view of a confinement apparatus system having integrated ferromagnetic structures, according to an example embodiment.

[0045] Figure 3 is a schematic perspective of a confinement apparatus system having integrated ferromagnetic structures, according to an example embodiment.

[0046] Figure 4 provides a flowchart illustrating various processes, procedures, and / or operations for fabricating a confinement apparatus system having integrated ferromagnetic structures, according to an example embodiment.

[0047] Figure 5 provides a schematic diagram of an example controller of a quantum computer configured to control operation of one or more components of the quantum computer, according to various embodiments.

[0048] Figure 6 provides a schematic diagram of an example computing entity of a quantum computer system that may be used in accordance with an example embodiment.DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

[0049] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term “or” (also denoted “ / ”) is used herein in both the alternative and conjunctive sense, unless otherwise indicated. The terms “illustrative” and “exemplary” are used to be examples with no indication of quality level. The terms “generally,” “substantially,” and “approximately” refer to within engineering and / or manufacturing tolerances and / or within user measurement capabilities, unless otherwise indicated. Like numbers refer to like elements throughout.

[0050] Example embodiments provide apparatuses, systems, and corresponding methods for confinement apparatus systems having one or more integrated ferromagnetic structures, various systems comprising at least one confinement apparatus system having one or more integrated ferromagnetic structures, including quantum processors (e.g., quantum charge coupled device (QCCD)-based quantum processors) and / or quantum computers comprising at least one confinement apparatus system having one or more integrated ferromagnetic structures.

[0051] In various embodiments, a confinement apparatus system comprises a confinement apparatus chip on which electrical components are disposed and / or formed. The electrical components include electrodes configured for defining confinement regions within which quantum objects may be confined. The confinement apparatus system further comprises one or more ferromagnetic structures. In various embodiments, the one or more ferromagnetic structures are formed on a spaced flip chip that is a chip that is flip chip mounted to the confinement apparatus chip with a set distance (e.g., greater than 10 microns) between the confinement apparatus chip and the spaced flip chip.

[0052] In various embodiments, the confinement apparatus defines a plurality and / or an array of defined positions. For example, the electrical components (e.g., electrodes) formed on the confinement apparatus chip may be configured such that when appropriate voltage signals are applied to electrical components (e.g., electrodes) thereof, an electric potential is generated that is configured to confine quantum objects at the defined positions. In variousembodiments, a sub-array of defined positions may be configured for performing a particular function (e.g., a reading function, performance of a single qubit or multi -qubit (e.g., two qubit) gate, and / or the like. For example, a first sub-set of defined positions are configured for performing reading and / or measurement operations that are performed to determine, measure, and / or read the quantum state of a quantum object on which the reading and / or measurement operation is performed. A second sub-set of defined positions are configured for performing quantum sate manipulations that are mitigated and / or caused by magnetic fields and / or magnetic field gradients. For example, a two-qubit entangling gate (e.g., a quantum logic gate configured to entangle the quantum states of two quantum objects) that is mediated and / or caused by a magnetic field or a magnetic field gradient may be performed at a defined position of the second sub-set of defined positions. For example, a two or more qubit gate similar to those disclosed in Application No. 63 / 487,076, filed February 27, 2023 or Application No. 63 / 374,811, filed September 7, 2022, may be performed at a defined position of the second sub-set of defined positions.

[0053] In various embodiments, the confinement apparatus system comprises one or more ferromagnetic structures. In various embodiments, the one or more ferromagnetic structures are configured to control the magnetic field and / or magnetic field gradient at the defined positions of the second sub-set of defined positions. For example, a ferromagnetic structure that is integrated into the confinement apparatus system may be configured to generate a magnetic field and / or magnetic field gradient a defined position that is configured to cause controlled quantum state evolution of one or more quantum objects when the quantum objects are disposed and / or located at the defined position. In an example embodiment, at least one ferromagnetic structure integrated into the confinement apparatus system is configured to control the magnetic field and / or magnetic field gradient at a defined position that is not in the second sub-set of defined positions.

[0054] In various embodiments, the confinement apparatus system having one or more integrated ferromagnetic structures is part of a system (e.g., quantum processor, quantum computer, and / or other atomic and / or quantum system) comprising a signal management system. For example, in various embodiments, a QCCD-based quantum system is provided comprising a confinement apparatus system and a signal management system. In various embodiments, the signal management system is configured to provide one or more manipulation signals (e.g., laser beams, laser pulses, and / or the like) through a space defined between the confinement apparatus chip and a spaced flip chip having one or more ferromagnetic structures thereon that is flip chip mounted to the confinement apparatus chip.For example, the confinement apparatus chip may comprise a quantum-object-facing surface (e.g., the side or surface of the confinement apparatus chip configured to be closest to the quantum objects when the quantum objects are confined by the confinement apparatus). The spaced flip chip that is mounted to the confinement apparatus chip and that has the one or more ferromagnetic structures formed thereon may have a quantum-object-facing surface (e.g., the side or surface of the spaced flip chip that is closest to the quantum objects when the quantum objects are confined by the confinement apparatus). The signal management system is configured to propagate manipulation signals through the space defined between the quantum-object-facing surface of the confinement apparatus chip and the quantum-objectfacing surface of the spaced flip chip, in an example embodiment.

[0055] In various embodiments, the QCCD-based quantum system includes an optics collection system. For example, the optics collection system comprise one or more photodetectors configured to capture, collect, sample, and / or the like light emitted by a quantum object disposed at a defined position of the first sub-set of defined positions (e.g., reading and / or measurement operation positions). In various embodiments, the spaced flip chip is configured to enable light emitted by a quantum object disposed and / or located at a defined position of the first sub-set of defined positions (e.g., reading and / or measurement operation positions) to pass through the spaced flip chip so as to reach the photodetector. For example, the spaced flip chip is transparent to light characterized by the detection frequency, at least in one or more areas corresponding to respective photodetectors. In an example embodiment, the spaced flip chip comprises a through window (e.g., a hole or opening) that corresponds to the location of a photodetector so as to allow light to pass therethrough and reach the photodetector. In an example embodiment, the photodetector is fabricated on and / or disposed on the spaced flip chip. For example, the spaced flip chip is configured to allow light emitted at defined positions of the first sub-set of defined positions and characterized by the detection frequency to reach corresponding photodetectors.

[0056] As used herein, the detection frequency is the frequency that characterizes light emitted by a quantum object via a fluorescence mechanism when the quantum object is read when the quantum object is in a bright state of a qubit sub-space of the energy levels of the quantum object. For example, a qubit sub-space may be defined in the energy space of the quantum object. The qubit sub-space comprises two energy levels, in various embodiments. In an example embodiment, two energy levels of the qubit sub-space are hyperfine energy levels. When the quantum object is in a first state of the qubit sub-space and a reading and / or measurement operation is performed thereon, the quantum object fluoresces at the detectionfrequency. When the quantum object is in a second state of qubit sub-space and a reading and / or measurement operation is performed thereon, the quantum object does not fluoresce.

[0057] In various embodiments, a quantum object is a neutral or ionic atom; neutral, ionic, or multipole molecule; quantum particle; quantum dot; and / or other object having quantum states that can be manipulated and / or controlled. The quantum object may be qubit quantum object of a quantum object crystal comprising two or more quantum objects, with, in an example embodiment, the two or more quantum objects of the quantum object crystal comprising, for example, ions of at least two different atomic numbers. In an example embodiment, the confinement apparatus of the confinement apparatus system having one or more integrated ferromagnetic structures is an ion trap (e.g., a surface ion trap, Paul trap, and / or the like). For example, the ion trap may be formed, defined, and / or disposed on a confinement apparatus chip.

[0058] Performance of conventional quantum logic gates requires oscillating fields such as laser beams, microwaves, oscillating magnetic fields, and / or the like to enact, mediate, and / or cause the entanglement of qubits. However, these oscillating fields may lead to various gate errors such as photon scattering and / or affecting transitions in spectator qubits, which can lead to crosstalk problems, phase noise, and / or the like. These gate errors can lead to low fidelity logic gates and noisy computations. Moreover, quantum logic gates that use oscillating fields are highly sensitive to the state of one or more motional modes of the qubits. Therefore, spin-motion coupling can lead to additional gate errors and / or a significant amount of time is needed to cool the qubits to close to their motional ground states prior to performance of a quantum logic gate. Thus, various technical problems exist regarding the performance of quantum logic gates.

[0059] As disclosed in disclosed in Application No. 63 / 487,076, filed February 27, 2023 or Application No. 63 / 374,811, filed September 7, 2022, quantum logic gates can be performed where a magnetic field and / or magnetic field gradient is used to mediate, enact, mediate, and / or cause entanglement of two or more qubits. However, performance of such quantum logic gates requires that the magnetic field and / or magnetic field gradient at the defined position where the quantum logic gate is to be performed is well known, well controlled, and consistent. If the magnetic field and / or magnetic field gradient at the defined position where the quantum logic gate is to be performed is not well known, well controlled, and consistent, the quantum logic gate may not be performed with sufficient fidelity. Moreover, if the magnetic field and / or magnetic field gradient used to perform the quantum logic gate at the defined position is not well controlled, the magnetic field and / or magneticfield gradient may affect quantum objects disposed and / or located at other positions (e.g., positions other than the defined position at which the quantum logic gate is to be performed), resulting in memory errors. Thus, technical challenges exist regarding how to provide a magnetic field and / or magnetic field gradient at defined positions of a confinement apparatus.

[0060] Various embodiments provide technical solutions to these technical problems by providing a confinement apparatus system that includes one or more integrated ferromagnetic structures. In various embodiments, the one or more integrated ferromagnetic structures include a ferromagnetic material (e.g., iron, cobalt, nickel, ferromagnetic alloy, and / or the like). In various embodiments, the one or more integrated ferromagnetic structures are formed on a spaced flip chip such that the integrated ferromagnetic structures form magnetic fields and / or magnetic field gradients that are well known, well controlled, and consistent. For example, the shape, dimensions, internal magnetic alignment, and / or the like of the ferromagnetic structures may be controlled, designed, and / or configured to provide magnetic fields and / or magnetic field gradients that are configured to cause performance of desired quantum logic operations at certain positions defined by the confinement apparatus while substantially not affecting other positions defined by the confinement apparatus.Additionally, the flip-chip mounting of the spaced flip chip to the confinement apparatus chip enables for accurate and precise placement and / or alignment of the ferromagnetic structures and any windows of the spaced flip chip with the corresponding defined positions of the confinement apparatus. Thus, various embodiments provide improvements and technical advantages in the fields of trapped atomic systems and QCCD-based quantum computing.Example Quantum Computing System Comprising a Confinement Apparatus System

[0061] Figure 1 provides a schematic diagram of an example quantum computing system 100 comprising a confinement apparatus system 200, in accordance with an example embodiment. In various embodiments, the confinement apparatus system 200 comprises a confinement apparatus chip 210 having a confinement apparatus 212 formed thereon and one or more spaced flip chips 215 having one or more integrated ferromagnetic structures 220 (e.g., 220A, 220B) formed thereon. In various embodiments, the confinement apparatus system 200 is disposed within a cryogenic and / or vacuum chamber 40. For example, the confinement apparatus chip 210 and spaced flip chip 215 are disposed within the cryogenic and / or vacuum chamber 40. In various embodiments, the electrical elements that define and / or form the confinement apparatus 212 are formed and / or disposed on the confinement apparatus chip 210.

[0062] In various embodiments, the confinement apparatus chip 210 defines an apparatus plane. For example, the apparatus plane may be defined by the quantum-object-facing surface of the confinement apparatus chip 210. In various embodiments, the quantum-object-facing surface 211 (see Figure 2) of the confinement apparatus chip 210 is the side or surface of the confinement apparatus chip configured to be closest to the quantum objects when the quantum objects are confined by the confinement apparatus 212. In various embodiments, the confinement apparatus system 200 comprises one or more spaced flip chips 215 that each define a respective cloud plane that is parallel to the apparatus plane but not coplanar with the apparatus plane. For example, a respective cloud plane is defined by the quantum-objectfacing surface of the respective spaced flip chip 215. In various embodiments, the quantumobject-facing surface 216 of the spaced flip chip 215 is the side or surface of the spaced flip chip configured to be closest to the quantum objects when the quantum objects are confined by the confinement apparatus 212. In various embodiments, the confinement apparatus chip 210 and the spaced flip chip 215 are mounted to one another such that a fixed distance h.

[0063] In various embodiments, the quantum computing system 100 comprises a signal management system. In various embodiments, the signal management system is configured to provide one or more manipulation signals (e.g., laser beams, laser pulses, and / or the like generated by one or more manipulation sources 60) through a space defined between the confinement apparatus chip and a spaced flip chip having one or more ferromagnetic structures formed thereon. For example, the signal management system is configured to propagate manipulation signals 62 (see Figure 3) through the space defined between the quantum-object-facing surface 211 of the confinement apparatus chip 210 and the quantumobject-facing surface 216 of the spaced flip chip 215, in an example embodiment. For example, the signal management system may include one or more optical fibers 86, waveguides, photonic integrated circuits (PICs), free space / bulk optics, and / or the like to provide the manipulation signals to respective defined positions of the confinement apparatus 212.

[0064] In various embodiments, the quantum computing system 100 comprises a computing entity 10 and a quantum computer 110. In various embodiments, the quantum computer 110 comprises a controller 30 and a quantum processor 115. In various embodiments, the quantum processor comprises a cryogenic and / or vacuum chamber 40 enclosing a confinement apparatus system 200 (e.g., an ion trap), , one or more voltage sources 50 configured to provide voltage signals to the electrical components of the confinement apparatus system 200, one or more manipulation sources 60 configured togenerate manipulation signals 62 (e.g., laser beams, laser pulses, microwaves, and / or the like) to defined locations of the confinement apparatus 212, an optics collection system comprising one or more photodetectors 70, and / or the like.

[0065] In various embodiments, the cryogenic and / or vacuum chamber 40 is a temperature and / or pressure-controlled chamber. For example, the quantum computing system 100 may comprise vacuum and / or temperature control components that are operatively coupled to the cryogenic and / or vacuum chamber 40.

[0066] In various embodiments, the quantum computer 110 comprises one or more voltage sources 50. For example, the voltage sources 50 may comprise a plurality of voltage drivers and / or voltage sources and / or at least one RF driver and / or voltage source. The voltage sources 50 may be electrically coupled to the corresponding electrode elements (e.g., electrodes) of the confinement apparatus 212, in an example embodiment. For example, the electric and / or field formed at least in part by applying the voltage signals generated by the voltage source 50 to the electrical elements (e.g., electrodes) of the confinement apparatus cause and / or form the confinement region(s) of the confinement apparatus.

[0067] In various embodiments, a computing entity 10 is configured to allow a user to provide input to the quantum computer 110 (e.g., via a user interface of the computing entity 10) and receive, view, and / or the like output from the quantum computer 110. The computing entity 10 may be in communication with the controller 30 of the quantum computer 110 via one or more wired or wireless networks 20 and / or via direct wired and / or wireless communications. In an example embodiment, the computing entity 10 may translate, configure, format, and / or the like information / data, quantum computing algorithms and / or circuits, and / or the like into a computing language, executable instructions, command sets, and / or the like that the controller 30 can understand and / or implement.

[0068] In various embodiments, the controller 30 is configured to control and / or in electrical communication with the voltage sources 50, cryogenic system and / or vacuum system controlling the temperature and / or pressure within the cryogenic and / or vacuum chamber 40, manipulation sources 60, photodetectors 70, and / or other systems controlling various environmental conditions (e.g., temperature, pressure, and / or the like) within the cryogenic and / or vacuum chamber 40 and / or configured to manipulate and / or cause a controlled evolution of respective quantum states of one or more quantum objects confined by the confinement apparatus 212. For example, the controller 30 may cause a controlled evolution of quantum states of one or more quantum objects within the confinement apparatus to execute a quantum circuit and / or algorithm. For example, the controller 30 maycause a reading and / or measurement operation to be performed, possibly as part of executing a quantum circuit and / or algorithm. In various embodiments, the quantum objects confined by the confinement apparatus 212 are used as qubits of the quantum processor 115 and / or quantum computer 110.Example Confinement Apparatus System

[0069] Figures 2 and 3 illustrate example confinement apparatus systems 200. In various embodiments, the confinement apparatus system 200 comprises a confinement apparatus chip 210. A plurality of electrical elements, such as electrodes, are formed on the confinement apparatus chip 210. confinement apparatus 212. For example, in the embodiment illustrated in Figure 3, the plurality of electrical elements include radio frequency (RF) rails 202 and segmented electrodes 204. The plurality of electrical elements define the confinement apparatus 212. For example, application of appropriate voltage signals (e.g., generated by voltage sources 50) to the electrodes (e.g., RF rails 202 and segmented electrodes 204) causes the generation of a confining potential configured to confine one or more quantum objects at one or more defined positions and / or to transport quantum objects between arbitrary pairs of the defined positions. For example, the controller 30 may control the voltage sources 50 to provide electrical signals to the electrodes of the confinement apparatus 212 such that the electrodes generate a confining potential. The confining potential is configured to confine a plurality of quantum objects within a confinement volume defined by the confinement apparatus 212. For example, in an example embodiment, the confinement apparatus 212 is a surface ion trap and the confinement volume is a volume located proximate the surface of the surface ion trap. In various embodiments, the electrodes and / or confining potential are configured to define a plurality of defined positions within the confinement volume.

[0070] In various embodiments, the confinement apparatus system 200 further comprises one or more integrated ferromagnetic structures 220. In the illustrated embodiment, the one or more integrated ferromagnetic structures are formed either on a quantum-object-facing surface 216 of a spaced flip chip 215, on a backside surface 217 of the spaced flip chip 215, or within the spaced flip chip 215 (e.g., between the quantum-object-facing surface 216 and the backside surface 217). In the illustrated embodiment, the spaced flip chip 215 is flip-chip mounted to the confinement apparatus chip 210 such that the quantum-object-facing surface 211 of the confinement apparatus chip 210 faces the quantum-object-facing surface 216 of the spaced flip chip 215.

[0071] In various embodiments, the spaced flip chip 215 is flip chip mounted to the confinement apparatus chip 210 using spacers 240 (e.g., bump bonds, ball bonds, silicon spacers, and / or other spacers). In various embodiments, the spaced flip chip 215 is mounted to the confinement apparatus chip 210 such that the quantum-object-facing surface 211 of the confinement apparatus chip 210 is parallel to the quantum-object-facing surface 216 of the spaced flip chip 215. For example, the quantum-object-facing surface 211 of the confinement apparatus chip 210 is a set and consistent distance h from the quantum-object-facing surface 216 of the spaced flip chip 215. In various embodiments, the distance h is in a range of 1 - 1000 microns. In various embodiments, the distance h is in a range of 50 - 300 microns. In an example embodiment, the distance h is in a range of 100 - 200 microns.

[0072] In various embodiments, a respective ferromagnetic structure 220 of the one or more integrated ferromagnetic structures are configured to generate a respective well known, well controlled, and consistent magnetic field and / or magnetic field gradient at a respective gradient gate position 255. In various embodiments, the magnetic field generated, formed, and / or caused by a respective ferromagnetic structure 220 is generated by a ferromagnetic material of the ferromagnetic structure. For example, in various embodiments, the ferromagnetic structure 220 comprises at least one magnetic material (e.g., ferromagnetic material such as iron, cobalt, nickel, ferromagnetic alloy, and / or the like).

[0073] In various embodiments, the shape, size, topology, and / or particle density of the ferromagnetic material of the ferromagnetic structure 220 control the magnetic field profile of the ferromagnetic structure 220. In various embodiments, respective ferromagnetic structures 220 are configured to generate respective magnetic fields profiles at the respective gradient gate positions 255 having various geometries such as uniform (e.g., the ferromagnetic structure may be formed as a Halbach array and / or the like), dipole, multipole geometries (e.g., quadrupole, octupole, hexapole, etc.), a combination of two or more of uniform, dipole, or multipole geometries, and / or the like.

[0074] In various embodiments, the defined positions defined by the confinement apparatus 212 are disposed in a one-dimensional or two-dimensional lay out. For example, in an example embodiment, the defined positions are disposed along an axis of a linear configuration of electrical elements of the confinement apparatus 212, such as the RF null 206 illustrated in Figure 3. In another example embodiment, the defined positions are disposed in a two-dimensional array or layout defined by a two-dimensional configuration of electrical elements of the confinement apparatus 212. An example confinement apparatus 212 comprising a linear configuration of electrical elements is described by U.S. Application No.16 / 717,602, filed December 17, 2019, though various other confinement apparatuses having linear electrical element configurations may be used in various embodiments. Some example confinement apparatuses 212 having two-dimensional electrical element configurations are described by U.S. Application No. 17 / 533587, filed November 23, 2021, and U.S. Application 17 / 810,082, filed June 30, 2022, though various other confinement apparatuses having two-dimensional electrical element configurations may be used in various embodiments. The contents of U.S. Application No. 16 / 717,602, filed December 17, 2019, U.S. Application No. 17 / 533587, filed November 23, 2021, U.S. Application 17 / 810,082, filed June 30, 2022, are incorporated herein by reference in their entireties.

[0075] In various embodiments, the voltage sources 50 provide respective electrical signals to the respective electrical elements (e.g., respective RF rails 202 and / or segmented electrodes 204) of the confinement apparatus 212, such that a confining potential is formed. Based on the contours and time evolution of the confining potential (controlled by the controller 30 via controlling the operation of the voltage sources 50) one or more quantum objects are confined at respective defined positions (e.g., gradient gate position 255, measurement position 250), moved between defined positions and / or the like. When a quantum object is located at a defined position, one or more functions (e.g., quantum computing functions) may be performed on the quantum object. For example, a reading or measurement operation may be performed on a quantum object disposed and / or located at the measurement position 250 and a magnetic field gradient-mediated quantum logic gate may be performed on a quantum object (or pair of quantum objects) disposed and / or located at the gradient gate position 255.

[0076] In various embodiments, to perform a reading and / or measurement operation, a manipulation signal (e.g., a reading signal) is applied to the quantum object located and / or disposed at a measurement position 250. When the quantum object’s wave function collapses into a first state of the qubit subspace, the quantum object will fluoresce in response to the reading signal being applied thereto. When the quantum object’s wave function collapses into a second state of the qubit subspace, the quantum object will not fluoresce in response to the reading signal being applied thereto.

[0077] For example, the reading signal may be provided such that the reading signal propagates through the space between the quantum-object-facing surface 211 of the confinement apparatus chip 210 and the quantum-object-facing surface 216 of the spaced flip chip 215. A photodetector 70 configured to receive signals emitted by a quantum object disposed at a respective measurement position 250 may then detect whether or not thequantum object fluoresced such that the quantum state of the quantum object is determined. As shown in Figure 2, the photodetector 70 corresponding to the measurement position 250 may be disposed such that the spaced flip chip 215 is disposed between the photodetector 70 and the measurement position 250.

[0078] In various embodiments, at least a portion of the spaced flip chip 215 disposed between the photodetector 70 and the measurement position 250 is transparent to light of the detection frequency. The detection frequency is the frequency of light that is expected that the photodetector 70 will detect when a quantum object being read and / or measured at the measurement position 250 is in the “bright state” of the qubit subspace. For example, the detection frequency corresponds to a fluorescence of the quantum object related to one of the qubit states of the qubit subspace. For example, in an example embodiment, a bulk substrate of the spaced flip chip 215 is glass. For example, in various embodiments, the spaced flip chip 215 is formed on a glass substrate.

[0079] In various embodiments, the spaced flip chip 215 comprises one or more windows 230 that each corresponds to a respective measurement position 250 and photodetector 70. For example, a window 230 may be a through window or a through hole that is a hole or opening in the substrate of the spaced flip chip 215 that extends from the quantum -objectfacing surface 216 of the spaced flip chip 215 to the backside surface 217 of the spaced flip chip 215 such that light can pass through the spaced flip chip 215 via the through window. In an example embodiment, the window 230 is a window or hole formed or etched through one or more conductive coatings of the spaced flip chip 215, but not through the substrate of the spaced flip chip 215 itself (e.g., the substrate of the spaced flip chip 215 may be transparent at least to light of the detection frequency). In an example embodiment, the window is a portion of the spaced flip chip 215 where the spaced flip chip 215 has been physically and / or optically thinned to reduce the optical thickness of the spaced flip chip at the location of the window 230. In an example embodiment, the window 230 is a portion of the spaced flip chip 215 where a material that is different (and optically thinner at the detection frequency) than the bulk material of the spaced flip chip 215 substrate is embedded in the spaced flip chip substrate, and / or the like.

[0080] In various embodiments, a conductive film (e.g., comprising gold and / or other conductive material) may be deposited on the quantum-object-facing surface 216 of the spaced flip chip 215. In various embodiments, the conductive film is a uniform film. In various embodiments, the conductive film is configured to reduce the presence of stray electric fields within the confinement regions of the confinement apparatus 212. For example,stray electric fields may cause heating or displacement of quantum objects confined by the confinement apparatus 212. Thus, the conductive film may shield the defined positions and confinement regions enabling transportation of quantum objects between defined positions from stray electric fields. In various embodiments, when the bulk substrate of the spaced flip chip 215 is transparent (at least at the detection frequency), a transparent conductive coating or film may be applied to the quantum-object-facing surface 216.

[0081] In various embodiments, an anti -reflective coating may be applied to the quantumobject-facing surface 216 and / or the backside surface 217 of the spaced flip chip 215.Example Method of Manufacturing a Confinement Apparatus System

[0082] Figure 4 provides a flowchart illustrating various processes, procedures, operations, and / or the like for fabricating and / or manufacturing a confinement apparatus system, according to various embodiments. Starting at step 402, the plurality of electrical elements that define the confinement apparatus 212 (e.g., RF rails 202, segmented electrodes 204, and / or the like) are fabricated on the confinement apparatus chip 210. For example, a plurality of electrodes and / or other electrical components are formed on the quantum-objectfacing surface 211 of the confinement apparatus chip 210, in an example embodiment. In various embodiments, fabricating the confinement apparatus 212 comprises depositing one or more layers of conductive material on the quantum-object-facing surface 211 of the confinement apparatus chip 210 and patterning the one or more layers of conductive material to form the plurality of electrical elements (e.g., RF rails 202, segmented electrodes 204).

[0083] At step 404, one or more ferromagnetic structures 220 are formed on the spaced flip chip 215. For example, a magnetic material (e.g., comprising a ferromagnetic material and / or ferromagnetic material) is deposited and patterned onto a region of the spaced flip chip 215. In various embodiments, the magnetic material is deposited on the quantum-objectfacing surface 216 of the spaced flip chip 215. In various embodiments, the magnetic material is deposited on the backside surface 217 of the spaced flip chip 215. In an example embodiment, the ferromagnetic structure is formed within the spaced flip chip 215 (e.g., between the quantum-object-facing surface 216 and the backside surface 217).

[0084] In various embodiments, the size, shape, topology, particle density, and / or the like of each of the one or more ferromagnetic structures 220 is determined, selected, and / or configured to provide a respective magnetic field or magnetic field gradient at a distance and relative location from the respective ferromagnetic structure corresponding to the location of a respective gradient gate position 255 (or other position where a well-known, well-controlled, consistent magnetic field or magnetic field gradient is desired) when the spaced flip chip 215 is mounted to the confinement apparatus chip 210. For example, various embodiments may leverage the anisotropy and / or various symmetries or lack thereof of the shape, topology, particle density, and / or the like of a ferromagnetic structure 220 to control the geometry of the magnetic field and / or magnetic field gradient generated at a corresponding gradient gate position 255 (when the confinement apparatus system is assembled). In an example embodiment, a ferromagnetic structure is deposited and / or patterned to have a particular crystalline anisotropy that is used to define, at least in part, the geometry of the magnetic field and / or magnetic field gradient at a corresponding gradient gate position 255 (when the confinement apparatus system is assembled). In an example embodiment, the magnetostatic energy of a ferromagnetic structure is leveraged to define, at least in part, the geometry of the magnetic field and / or magnetic field gradient at a corresponding gradient gate position 255 (when the confinement apparatus system is assembled). The magnetization configuration intended to generate the desired magnetic field may be deterministically designed to be the magnetostatic energy minimum by using standard magnetic film engineering techniques such as magnetoelastic (strain) anisotropy, magnetocrystalline anisotropy, and demagnetization energies. For example, the size, shape, topology, particle density, and / or the like of a ferromagnetic structure is configured to generate respective magnetic fields profiles at the respective gradient gate position 255 having a geometry such as a uniform geometry (e.g., the ferromagnetic structure may be formed as a Halbach array and / or the like), dipole geometry, multipole geometry (e.g., quadrupole, octupole, hexapole, and / or the like), a combination of two or more of uniform, dipole, or multipole geometries, or other geometry. In various embodiments, the geometry of the magnetic field is configured to not substantially affect the energy level structure of a quantum object disposed at a defined position (e.g., measurement position 250) that is nearby or neighboring the respective gradient gate position 255.

[0085] At step 406, one or more optical elements are formed on the spaced flip chip 215. For example, in various embodiments, one or more optical elements (e.g., waveguides, grating couplers, metasurfaces, diffractive optics, lenses, and / or the like) are formed on and / or in the spaced flip chip 215.

[0086] At step 408, a conductive coating or film is deposited on or applied to the quantum-object-facing surface of the spaced flip chip 215. For example, in an example embodiment, the conductive coating comprises gold. In an example embodiment, the conductive coating or film is transparent, at least at the detection frequency.

[0087] At step 410, the magnetic field profile of the ferromagnetic structure(s) 220 are set. For example, magnetic annealing may be performed to set the magnetic field profile of the ferromagnetic structure(s) formed on the spaced flip chip 215. For example, an annealing process may be performed in the presence of an external magnetic field that causes, when the magnetic material of the ferromagnetic structures is heated during the annealing process, the individual magnetic dipoles of the magnetic material to be aligned in a desired pattern to provide the desired magnetic field and / or magnetic field gradient geometry at the a corresponding gradient gate position 255 (when the confinement apparatus system is assembled). As the ferromagnetic structures cool, the individual magnetic dipoles of the magnetic material are set and / or “frozen” in the desired pattern. Various other techniques to pin the magnetic field profile of the ferromagnetic structure(s) 220 may be used in various embodiments, as appropriate for the application.

[0088] At step 412, one or more windows 230 are formed in the spaced flip chip 215. For example, one or more through windows may be formed, etched, or milled through the spaced flip chip 215 (e.g., from the quantum-object-facing surface 216 to the backside surface 217). For example, in an example embodiment where the substrate of the spaced flip chip 215 is not transparent at the detection frequency, the one or more through windows 230 are formed, etched, or milled through the spaced flip chip 215. In an example embodiment, wherein the substrate of the spaced flip chip 215 is transparent at the detection frequency but a conductive coating applied and / or deposited on the quantum-object-facing surface 216 is not transparent at the detection frequency, a window may be formed in the spaced flip chip 215 by etching through the conductive coating. In an example embodiment, a window 230 is formed by embedding a material that is transparent at the detection frequency into an opening or hole formed in the spaced flip chip 215.

[0089] In various embodiments, the one or more windows 230 are formed at locations on the spaced flip chip 215 that correspond to (when the confinement apparatus system 200 is assembled) the location of respective measurement positions 250. For example, each of the windows 230 are configured to align with a respective measurement position 250, and / or other position defined by the confinement apparatus for which optical access through the spaced flip chip 215 is desired, when the confinement apparatus system is assembled.

[0090] At step 414, one or more anti -reflective coatings are applied to one or more surfaces (e.g., the quantum-object-facing surface 216, the backside surface 217, and / or other surface) of the spaced flip chip 215. In an example embodiment, the backside surface 217 of the spaced flip chip 215 may be polished.

[0091] In various embodiments, the ordering of steps 402-414 may vary and / or one or more of steps 406, 410, 412, or 414 may be omitted. For example, in an example embodiment, the steps 402-414 are performed in the order 406, 412, 404, 410, 408, 402, 414. In various embodiments, step 402 may be performed simultaneously to one or more of steps 404-414. In particular, the fabrication of the confinement apparatus (e.g., the plurality of electrical components that define the confinement apparatus 212) is performed independently of the fabrication of the spaced flip chip 215. In an example embodiment, the steps 404 and 410 are repeated multiple times to form a plurality of pinned layers of the ferromagnetic structure. For example, in an example embodiment, a ferromagnetic structure 220 comprises a plurality of layers where the magnetic field profile of each layer has been individually pinned such that the composite magnetic field profile of the plurality of layers of the ferromagnetic structure causes the desired magnetic field and / or magnetic field gradient geometry at the a corresponding gradient gate position 255 (when the confinement apparatus system is assembled).

[0092] At step 416, the confinement apparatus chip 210 and the spaced flip chip 215 are mounted to one another. In an example embodiment, one or more alignment features on the confinement apparatus chip 210 are aligned with one or more corresponding alignment features on the spaced flip chip 215 such that the windows 230 of the spaced flip chip 215 align with respective measurement positions 250 defined by the confinement apparatus chip 210 and the ferromagnetic structures 220 of the spaced flip chip 215 align with respective gradient gate positions 255 defined by the confinement apparatus chip 210.

[0093] In an example embodiment, the spaced flip chip 215 is flip chip mounted to the confinement apparatus chip 210. In various embodiments, the spaced flip chip 215 is mounted to the confinement apparatus chip 210 using spacers 240. In various embodiments, the spacers 240 are configured to cause the quantum-object-facing surface 211 of the confinement apparatus chip 210 to be parallel to the quantum-object-facing surface 216 of the spaced flip chip 215. In various embodiments, the spacers 240 are configured to cause the distance h between the quantum-object-facing surface 211 of the confinement apparatus chip 210 and the quantum-object-facing surface 216 of the spaced flip chip 215 between any pair of points where a first point of the pair of points is disposed on the quantum-object-facing surface 211 of the confinement apparatus chip 210, the second point of the pair of points is disposed on the quantum-object-facing surface 216 of the spaced flip chip 215, and the first point and the second point are connectable by a line that is perpendicular to the quantumobject-facing surface 211 of the confinement apparatus chip 210 and / or the quantum -object-facing surface 216 of the spaced flip chip 215, to be consistent between any two such pairs of points. In various embodiments, the distance h is in a range of 50-300 microns. In various embodiments, the distance h is in a range of 100-200 microns. In various embodiments, the plurality of spacers 240 are positioned to enable manipulation signals 62 (e.g., laser beams, laser pulses, microwaves, and / or the like) to be provided from the side of the confinement apparatus system 200 such that the manipulation signals propagate through the space between the quantum-object-facing surface 211 of the confinement apparatus chip 210 and the quantum-object-facing surface 216 of the spaced flip chip 215. In an example embodiment, the spacers 240 are configured to place the conductive coating on the quantum-object-facing surface 216 of the spaced flip chip 215 into electrical contact with a ground circuit of the confinement apparatus chip 210.Technical Advantages

[0094] Performance of conventional quantum logic gates requires oscillating fields such as laser beams, microwaves, oscillating magnetic fields, and / or the like to enact, mediate, and / or cause the entanglement of qubits. However, these oscillating fields may lead to various gate errors such as photon scattering and / or affecting transitions in spectator qubits, which can lead to crosstalk problems, phase noise, and / or the like. These gate errors can lead to low fidelity logic gates and noisy computations. Moreover, quantum logic gates that use oscillating fields are highly sensitive to the state of one or more motional modes of the qubits. Therefore, spin-motion coupling can lead to additional gate errors and / or a significant amount of time is needed to cool the qubits to close to their motional ground states prior to performance of a quantum logic gate. Thus, various technical problems exist regarding the performance of quantum logic gates.

[0095] As disclosed in disclosed in Application No. 63 / 487,076, filed February 27, 2023 or Application No. 63 / 374,811, filed September 7, 2022, quantum logic gates can be performed where a magnetic field and / or magnetic field gradient (or higher order derivatives and / or combinations thereof) is used to mediate, enact, mediate, and / or cause entanglement of two or more qubits. However, performance of such quantum logic gates requires that the magnetic field and / or magnetic field gradient at the defined position where the quantum logic gate is to be performed is well known, well controlled, and consistent. If the magnetic field and / or magnetic field gradient at the defined position where the quantum logic gate is to be performed is not well known, well controlled, and consistent, the quantum logic gate may not be performed with sufficient fidelity. Moreover, if the magnetic field and / or magnetic fieldgradient used to perform the quantum logic gate at the defined position is not well controlled, the magnetic field and / or magnetic field gradient may affect quantum objects disposed and / or located at other positions (e.g., positions other than the defined position at which the quantum logic gate is to be performed), resulting in memory errors. Thus, technical challenges exist regarding how to provide a magnetic field and / or magnetic field gradient at defined positions of a confinement apparatus.

[0096] Various embodiments provide technical solutions to these technical problems by providing a confinement apparatus system that includes one or more integrated ferromagnetic structures. In various embodiments, the one or more integrated ferromagnetic structures include a ferromagnetic material (e.g., iron, cobalt, nickel, ferromagnetic alloy, and / or the like). In various embodiments, the one or more integrated ferromagnetic structures are formed on a spaced flip chip such that the integrated ferromagnetic structures form magnetic fields and / or magnetic field gradients that are well known, well controlled, and consistent. For example, the shape, dimensions, internal magnetic alignment, and / or the like of the ferromagnetic structures may be controlled, designed, and / or configured to provide magnetic fields and / or magnetic field gradients that are configured to cause performance of desired quantum logic operations at certain positions defined by the confinement apparatus while substantially not affecting other positions defined by the confinement apparatus.Additionally, the flip-chip mounting of the spaced flip chip to the confinement apparatus chip enables for accurate and precise placement and / or alignment of the ferromagnetic structures and any windows of the spaced flip chip with the corresponding defined positions of the confinement apparatus. Thus, various embodiments provide improvements and technical advantages in the fields of trapped atomic systems and QCCD-based quantum computing.Exemplary Controller

[0097] In various embodiments, a confinement apparatus system 200 (having one or more integrated ferromagnetic structures 220) is incorporated into a system (e.g., a quantum computer 110) comprising a controller 30. In various embodiments, the controller 30 is configured to control various elements of the system (e.g., quantum computer 110). For example, the controller 30 may be configured to control the voltage sources 50, a cryogenic system and / or vacuum system controlling the temperature and pressure within the cryogenic and / or vacuum chamber 40, manipulation sources 60, cooling system, and / or other systems controlling the environmental conditions (e.g., temperature, humidity, pressure, and / or the like) within the cryogenic and / or vacuum chamber 40 and / or configured to manipulate and / orcause a controlled evolution of quantum states of one or more quantum objects confined by the confinement apparatus 212 of the confinement apparatus system 200. In various embodiments, the controller 30 may be configured to receive signals from one or more photodetectors or other sensors of the system.

[0098] As shown in Figure 5, in various embodiments, the controller 30 may comprise various controller elements including processing devices 505, memory 510, driver controller elements 515, a communication interface 520, analog-digital converter elements 525, and / or the like. For example, the processing device 505 may comprise one or more processing elements such as programmable logic devices (CPLDs), microprocessors, coprocessing entities, application-specific instruction-set processors (ASIPs), integrated circuits, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), hardware accelerators, other processing devices and / or circuitry, and / or the like. The term circuitry may refer to an entirely hardware embodiment or a combination of hardware and computer program products. In an example embodiment, the processing device 505 of the controller 30 comprises a clock and / or is in communication with a clock.

[0099] For example, the memory 510 may comprise non-transitory memory such as volatile and / or non-volatile memory storage such as one or more of as hard disks, ROM, PROM, EPROM, EEPROM, flash memory, MMCs, SD memory cards, Memory Sticks, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and / or the like. In various embodiments, the memory 510 may store a queue of commands to be executed to cause a quantum algorithm and / or circuit to be executed (e.g., an executable queue), qubit records corresponding the qubits of quantum computer (e.g., in a qubit record data store, qubit record database, qubit record table, and / or the like), a calibration table, computer program code (e.g., in a one or more computer languages, specialized controller language(s), and / or the like), and / or the like. In an example embodiment, execution of at least a portion of the computer program code stored in the memory 510 (e.g., by a processing device 505) causes the controller 30 to perform one or more steps, operations, processes, procedures and / or the like for providing manipulation signals to positions defined by the confinement apparatus 212 and / or collecting, detecting, capturing, and / or measuring indications of emitted signals emitted by quantum objects located at corresponding defined positions of the confinement apparatus 212.

[0100] In various embodiments, the driver controller elements 515 may include one or more drivers and / or controller elements each configured to control one or more drivers. In various embodiments, the driver controller elements 515 may comprise drivers and / or driver controllers. For example, the driver controllers may be configured to cause one or more corresponding drivers to be operated in accordance with executable instructions, commands, and / or the like scheduled and executed by the controller 30 (e.g., by the processing device 505). In various embodiments, the driver controller elements 515 may enable the controller 30 to operate a voltage sources 50, manipulation sources 60, cooling system, and / or the like. In various embodiments, the drivers may be laser drivers configured to operate one or manipulation sources 60 to generate manipulation signals; vacuum component drivers; drivers for controlling the flow of current and / or voltage applied to electrodes used for maintaining and / or controlling the trapping potential of the confinement apparatus 212 (and / or other drivers for providing driver action sequences to potential generating / electrical elements of the confinement apparatus system); cryogenic and / or vacuum system component drivers; cooling system drivers, and / or the like. In various embodiments, the controller 30 comprises means for communicating and / or receiving signals from one or more optical receiver components (e.g., photodetectors 70) and / or other sensors of the quantum computing system 100. For example, the controller 30 may comprise one or more analog-digital converter elements 525 configured to receive signals from one or more optical receiver components (e.g., a photodetector 70 of the optics collection system), calibration sensors, and / or the like.

[0101] In various embodiments, the controller 30 may comprise a communication interface 520 for interfacing and / or communicating with a computing entity 10. For example, the controller 30 may comprise a communication interface 520 for receiving executable instructions, command sets, and / or the like from the computing entity 10 and providing output received from the quantum computer 110 (e.g., from an optical collection system) and / or the result of a processing the output to the computing entity 10. In various embodiments, the computing entity 10 and the controller 30 may communicate via a direct wired and / or wireless connection and / or via one or more wired and / or wireless networks 20.Exemplary Computing Entity

[0102] Figure 6 provides an illustrative schematic representative of an example computing entity 10 that can be used in conjunction with embodiments of the present invention. In various embodiments, a computing entity 10 is configured to allow a user toprovide input to the quantum computer 110 (e.g., via a user interface of the computing entity 10) and receive, display, analyze, and / or the like output from the quantum computer 110.

[0103] As shown in Figure 6, a computing entity 10 can include an antenna 612, a transmitter 604 (e.g., radio), a receiver 606 (e.g., radio), and a processing device 608 that provides signals to and receives signals from the transmitter 604 and receiver 606, respectively. The signals provided to and received from the transmitter 604 and the receiver 606, respectively, may include signaling information / data in accordance with an air interface standard of applicable wireless systems to communicate with various entities, such as a controller 30, other computing entities 10, and / or the like. In this regard, the computing entity 10 may be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. For example, the computing entity 10 may be configured to receive and / or provide communications using a wired data transmission protocol, such as fiber distributed data interface (FDDI), digital subscriber line (DSL), Ethernet, asynchronous transfer mode (ATM), frame relay, data over cable service interface specification (DOCSIS), or any other wired transmission protocol. Similarly, the computing entity 10 may be configured to communicate via wireless external communication networks using any of a variety of protocols, such as general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 IX (IxRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division-Synchronous Code Division Multiple Access (TD- SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed Packet Access (HSPA), High-Speed Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), ultra wideband (UWB), infrared (IR) protocols, near field communication (NFC) protocols, Wibree, Bluetooth protocols, wireless universal serial bus (USB) protocols, and / or any other wireless protocol. The computing entity 10 may use such protocols and standards to communicate using Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / S ecure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP),Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), HyperText Markup Language (HTML), and / or the like.

[0104] Via these communication standards and protocols, the computing entity 10 can communicate with various other entities using concepts such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identity Module Dialer (SIM dialer). The computing entity 10 can also download changes, add-ons, and updates, for instance, to its firmware, software (e.g., including executable instructions, applications, program modules), and operating system.

[0105] In various embodiments, the computing entity 10 may comprise a network interface 620 for interfacing and / or communicating with the controller 30, for example. For example, the computing entity 10 may comprise a network interface 620 for providing executable instructions, command sets, and / or the like for receipt by the controller 30 and / or receiving output and / or the result of a processing the output provided by the quantum computer 110. In various embodiments, the computing entity 10 and the controller 30 may communicate via a direct wired and / or wireless connection and / or via one or more wired and / or wireless networks 20.

[0106] In various embodiments, the processing device 608 may comprise one or more processing elements such as programmable logic devices (CPLDs), microprocessors, coprocessing entities, application-specific instruction-set processors (ASIPs), integrated circuits, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), hardware accelerators, other processing devices and / or circuitry, and / or the like. The term circuitry may refer to an entirely hardware embodiment or a combination of hardware and computer program products.

[0107] The computing entity 10 may also comprise a user interface device comprising one or more user input / output interfaces (e.g., a display 616 and / or speaker / speaker driver coupled to a processing device 608 and a touch screen, keyboard / keypad 618, mouse, and / or microphone coupled to a processing device 608). For instance, the user output interface may be configured to provide an application, browser, user interface, interface, dashboard, screen, webpage, page, and / or similar words used herein interchangeably executing on and / or accessible via the computing entity 10 to cause display or audible presentation of information / data and for interaction therewith via one or more user input interfaces. The user input interface can comprise any of a number of devices allowing the computing entity 10 to receive data, such as a keypad 618 (hard or soft), a touch display, voice / speech or motioninterfaces, scanners, readers, or other input device. In embodiments including a keypad 618, the keypad 618 can include (or cause display of) the conventional numeric (0-9) and related keys (#, *), and other keys used for operating the computing entity 10 and may include a full set of alphabetic keys or set of keys that may be activated to provide a full set of alphanumeric keys. In addition to providing input, the user input interface can be used, for example, to activate or deactivate certain functions, such as screen savers and / or sleep modes. Through such inputs the computing entity 10 can collect information / data, user interaction / input, and / or the like.

[0108] The computing entity 10 can also include volatile storage or memory 622 and / or non-volatile storage or memory 624, which can be embedded and / or may be removable. For instance, the non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMCs, SD memory cards, Memory Sticks, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, and / or the like. The volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and / or the like. The volatile and non-volatile storage or memory can store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like to implement the functions of the computing entity 10.Conclusion

[0109] Many modifications and other embodiments of the invention set forth herein will come to mind to one skilled in the art to which the invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

That which is claimed:

1. A confinement apparatus system comprising: a confinement apparatus chip; a plurality of electrodes formed on the confinement apparatus chip to form a confinement apparatus, wherein the confinement apparatus is configured to confine one or more quantum objects; and a spaced flip chip having at least one ferromagnetic structure formed thereon, wherein the spaced flip chip is mounted to the confinement apparatus chip with a set distance therebetween.

2. The confinement apparatus system of claim 1, wherein the confinement apparatus defines at least one gradient gate position and the at least one ferromagnetic structure is positioned to cause a magnetic field or magnetic field gradient in the at least one gradient gate position.

3. The confinement apparatus of claim 1, wherein a geometry of the magnetic field formed by the at least one ferromagnetic structure at a position defined by the confinement apparatus is one of uniform, dipole, multipole, or combination of two or more thereof.

4. The confinement apparatus system of claim 1, wherein the confinement apparatus defines at least one measurement position and a portion of the spaced flip chip that corresponds to the at least one measurement position is transparent to light of a detection frequency.

5. The confinement apparatus system of claim 4, wherein the detection frequency is a fluorescence frequency of a quantum object of the one or more quantum objects.

6. The confinement apparatus system of claim 1, wherein the confinement apparatus defines at least one measurement position and the spaced flip chip comprises a through window that corresponds to the at least one measurement position.

7. The confinement apparatus system of claim 1, wherein the at least one ferromagnetic structure comprises a ferromagnetic material.

8. The confinement apparatus system of claim 1, wherein the spaced flip chip is flip-chip mounted to the confinement apparatus chip using a plurality of spacers such that a quantumobject-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are separated from one another by the set distance and the set distance is configured to provide a desired magnetic field geometry at a position defined by the confinement apparatus.

9. The confinement apparatus system of claim 8, wherein the plurality of spacers are positioned at respective positions the enable one or more manipulation signals to be applied to one or more positions defined by the confinement apparatus via a space between the quantum-object facing surface of the confinement apparatus chip and the quantum -objectfacing surface of the spaced flip chip.

10. The confinement apparatus system of claim 1, wherein the spaced flip chip is flip-chip mounted to the confinement apparatus chip such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are parallel to one another.

11. The confinement apparatus system of claim 1, wherein a quantum-object-facing surface of the spaced flip chip has a conductive coating disposed thereon.

12. The confinement apparatus system of claim 1, wherein the spaced flip chip comprises one or more of an anti -reflective coating or a transparent conductive coating.

13. The confinement apparatus system of claim 1, wherein one or more optical elements are formed or disposed on or in the spaced flip chip.

14. The confinement apparatus system of claim 1, wherein the spaced flip chip is flip chip mounted to the confinement apparatus chip using one or more spacers to maintain the set distance between the spaced flip chip and the confinement apparatus chip.

15. A method of fabricating a confinement apparatus system, the method comprising:providing a confinement apparatus chip having a confinement apparatus configured to confine one or more quantum objects formed thereon; providing a spaced flip chip having at least one ferromagnetic structure formed thereon; and mounting the spaced flip chip to the confinement apparatus chip such that there is a set distance between the spaced flip chip and the confinement apparatus chip.

16. The method of claim 15, wherein the magnetic field profile of the at least one ferromagnetic structure is set by leveraging shape anisotropy of the at least one magnetic field structure, leveraging crystalline anisotropy of the at least one magnetic field structure, leveraging magnetostatic energy of the at least one magnetic field structure, using pinning layers, or using field annealing.

17. The method of claim 15, wherein the spaced flip chip is flip-chip mounted to the confinement apparatus chip using a plurality of spacers such that a quantum-object-facing surface of the confinement apparatus chip and a quantum-object-facing surface of the spaced flip chip are separated from one another by the set distance and the set distance is configured to provide a desired magnetic field geometry at a position defined by the confinement apparatus.

18. The method of claim 15, further comprising forming one or more through windows in the spaced flip chip that are disposed at respective locations corresponding to respective measurement zones defined by the confinement apparatus.

19. The method of claim 15, further comprising at least one of (a) backside polishing the spaced flip chip, (b) depositing a conductive coating to a quantum-object-facing surface of the spaced flip chip, (c) applying an anti -reflective coating to at least one of the quantumobject-facing surface or the backside surface of the spaced flip chip, or (d) applying a transparent conductive coating to at least one of the quantum-object-facing surface or the backside surface of the spaced flip chip.

20. The method of claim 15, further comprising fabricating one or more optical elements on or in the spaced flip chip prior to flip-chip mounting the spaced flip chip to the confinement apparatus chip.

21. The method of claim 15, further comprising setting a magnetic field profile of the at least one ferromagnetic structure.

22. The method of claim 15, wherein the spaced flip chip is flip chip mounted to the confinement apparatus chip.

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