Ultrasound imaging probe

Abstract

The invention relates to an ultrasonic imaging probe (100), comprising first (110), second (120) and third (130) circuits, wherein: - the first circuit (110) is an ultrasonic transduction circuit comprising an array of elementary ultrasonic transduction chips (111) each comprising an array of elementary ultrasonic transducers (113); - the second circuit (120) is a transceiver circuit comprising, for each elementary ultrasonic transduction chip (111), an elementary transceiver chip (121); and - the third circuit (130) is a digital pre-processing circuit comprising, for each elementary transceiver chip (121), an elementary digital pre-processing chip (131).

Description

DESCRIPTION TITLE: Ultrasound Imaging Probe This application is based on, and claims priority from, French patent application No. 23 / 06703 filed on June 27, 2023, entitled "Ultrasonic Imaging Probe", which is considered to form an integral part of this description within the limits provided by law. technical field

[0001] This description relates to the field of ultrasound imaging, and more specifically to an ultrasound imaging probe intended to be connected to an external control and processing system via a cable, the probe integrating a plurality of ultrasound transducers and electronic circuits for controlling these transducers. Prior art

[0002] Various architectures for ultrasound imaging probes have already been proposed.

[0003] It would be desirable to improve at least some aspects of known ultrasound imaging probes.

[0004] We are particularly interested here in the realization of ultrasonic imaging probes adapted to implement, as close as possible to the ultrasonic sensor, digital and / or analog processing such as, for example, micro-beam forming processing, for example in the context of ultra-fast acquisition scenarios. Summary of the invention

[0005] One embodiment provides for an ultrasound imaging wave comprising first, second and third circuits, in which: the first circuit is an ultrasonic transduction circuit comprising an array of elementary ultrasonic transduction chips, each comprising an array of elementary ultrasonic transducers; - the second circuit is a transmit-receive circuit comprising, for each elementary ultrasonic transduction chip, a corresponding specific elementary transmit-receive chip comprising, for each elementary ultrasonic transducer of the elementary ultrasonic transduction chip, an elementary transmit-receive cell electrically connected to an electrode of the transducer; in each elementary transmit-receive chip, the elementary transmit-receive cells of the chip are distributed into several elementary transmit-receive groups each comprising N elementary transmit-receive cells, with N an integer greater than or equal to 1; - The probe comprises, for each elementary transmit-receive chip, for each elementary transmit-receive group of the chip, an analog preprocessing circuit having N input terminals connected respectively to one output terminal of each elementary transmit-receive cell of the elementary transmit-receive group, and M output terminals, with M less than or equal to NN; the probe comprises, for each elementary transmit-receive group of each elementary transmit-receive chip, M analog-to-digital converters each having one input terminal and one output terminal, the input terminals of the M analog-to-digital converters being connected respectively to the M output terminals of the analog preprocessing circuit of the elementary transmit-receive group; the third circuit is a preprocessing circuit digital comprising, for each elementary transmit-receive chip, a corresponding specific elementary digital preprocessing chip comprising, for each elementary transmit-receive group of the elementary transmit-receive chip, M elementary digital preprocessing cells connected respectively to the output terminals of the M analog-to-digital converters associated with the elementary transmit-receive group; - each elementary digital preprocessing chip comprises one or more binary connection elements, each intended to provide a serialized digital signal, connected to all the elementary digital preprocessing cells of the chip via one or more serialization circuits, wherein each elementary digital preprocessing cell comprises an elementary memory circuit and a processing unit, and wherein each elementary digital preprocessing chip comprises an overall control circuit connected to respective control nodes of the MxN elementary digital preprocessing cells of the chip and adapted to command the execution of a sequence of operations by the elementary digital preprocessing cells of the chip.

[0006] According to one embodiment, in each elementary digital preprocessing cell the elementary memory circuit is adapted to store the complete signal provided by the corresponding analog-to-digital converter during a reception time window following an ultrasonic shot.

[0007] According to one embodiment, each analog preprocessing circuit is a selector combiner circuit adapted to provide, on each of its M output terminals, a analog summation, or superposition, of all or part of the signals applied to its N input terminals.

[0008] According to one embodiment, each transmit-receive cell includes a transmit circuit adapted to generate an electrical excitation signal applied to the electrode of the associated elementary transducer.

[0009] According to one embodiment, each transmit-receive cell comprises a receiving circuit including an amplifier having an input node connected to the electrode of the elementary transducer and an output node connected to the output terminal of the transmit-receive cell.

[0010] According to one embodiment, for each transmit-receive cell, the receiving circuit further includes a delay circuit configured to apply a delay of adjustable duration to the electrical output signal of the transducer.

[0011] According to one embodiment, each elementary digital preprocessing cell includes data input / output ports for exchanging data between the cell's elementary memory circuit and the elementary memory circuits of neighboring elementary cells.

[0012] According to one embodiment, the first, second and third circuits are stacked vertically, with the second circuit being placed between the first and third circuits.

[0013] According to one embodiment, two of the first, second and third circuits are stacked vertically, the remaining circuit of the first, second and third circuits being offset laterally.

[0014] According to one embodiment, M is strictly less than N.

[0015] Another embodiment provides for an ultrasound imaging system comprising an imaging probe ultrasonic as defined above, an external processing device, and a digital data transmission channel linking the probe to the external processing device.

[0016] According to one embodiment, the digital data transmission channel comprises one or more wired electrical or optical data transmission elements per digital preprocessing elementary chip, electrically connected respectively to said one or more binary connection elements of the elementary chip.

[0017] According to one embodiment, the external processing device is configured to apply delays and combine signals from the analog-to-digital converters. Brief description of the drawings

[0018] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

[0019] Figure 1 is a perspective view schematically and partially representing an example of an ultrasound imaging system according to one embodiment;

[0020] Figure 2 schematically and partially represents an example of the implementation of a transmission-reception circuit for an ultrasound imaging probe according to one embodiment;

[0021] Figure 3 schematically and partially represents an example of the implementation of a digital preprocessing circuit for an ultrasound imaging probe according to one embodiment;

[0022] Figure 4 is a perspective view schematically and partially representing a variant of an ultrasound imaging system according to one embodiment; and

[0023] Figure 5 is a cross-sectional view schematically and partially representing another variant of an ultrasound imaging system according to one embodiment. Description of the implementation methods

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, the various applications of the described ultrasound probes and imaging systems have not been detailed, as the described embodiments are compatible with the usual applications of ultrasound imaging probes. Furthermore, the properties (frequencies, shapes, amplitudes, etc.) of the electrical excitation signals applied to the ultrasound transducers have not been detailed, as the described embodiments are compatible with the excitation signals commonly used in ultrasound imaging systems, which can be chosen according to the application and, in particular, the nature of the body to be analyzed and the type of information to be acquired.Similarly, the various processing steps applied to the electrical signals provided by the ultrasonic transducers and read by the control circuit to extract useful information about the body being analyzed were not detailed, as the described embodiments are compatible with the processing commonly used in ultrasonic imaging systems. Furthermore, the implementation of the ultrasonic transducers and circuits... The electronic control of the transducers has not been described in detail, the detailed realization of these elements being within the reach of a person skilled in the art from the indications of this description, using known techniques for the realization of ultrasonic transducers and electronic circuits.

[0026] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0027] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0029] Figure 1 is a perspective view schematically and partially representing an example of an ultrasound imaging system according to one embodiment.

[0030] The system in Figure 1 includes an ultrasonic imaging probe 100 intended to be electrically connected to an external control and processing device 160, for example a computer, via an electrical connection cable 150.

[0031] The probe 100 comprises a plurality of elementary ultrasonic transducers, and electronic circuits for controlling the transducers.

[0032] In operation, the probe's ultrasonic transducers are positioned facing the object to be imaged. The electronic control circuits are configured to apply electrical excitation signals to the transducers, causing them to emit ultrasonic waves towards the object being analyzed. These ultrasonic waves are reflected, in whole or in part, by the object (through its internal and / or surface structure) and then return to the transducers, which convert them back into electrical signals. These electrical response signals are read, digitized, and pre-processed by the electronic control circuits. The digital output signals from the electronic control circuits are transmitted to the external device 160 via the connecting cable 150.These signals can be stored and analyzed by the external device 160 to deduce information about the body being studied.

[0033] The 100 probe, for example, is a portable probe designed to be positioned and, possibly moved, manually on a patient's body.

[0034] In the example in Figure 1, the ultrasonic imaging probe 100 comprises a stack of an ultrasonic transduction circuit 110, a transmit-receive circuit 120, and a digital preprocessing circuit 130.

[0035] For example, the entire set of circuits 110, 120 and 130 is arranged in a housing, not shown, of the probe.

[0036] The ultrasonic transduction circuit 110 comprises a plurality of elementary ultrasonic transducers (not detailed in the figures), for example arranged in a matrix according to rows and columns. As an example, the ultrasonic transduction circuit 110 comprises several thousand to several hundred thousand individually addressable elementary ultrasonic transducers, for example on the order of one hundred thousand elementary ultrasonic transducers.

[0037] More specifically, in this example, the ultrasonic transduction circuit 110 comprises an array of identical (within manufacturing variations) or similar AxB ultrasonic transduction element chips 111. In the example shown, A=B=4. However, the described embodiments are not limited to this particular case. As an alternative, A may be different from B, and A and B may be different from 4. For example, A may be greater than 10, for example, between 10 and 100, or even greater than 100. Similarly, B may be greater than 10, for example, between 10 and 100, or even greater than 100. For example, A=120 and B=60.

[0038] Each chip 111 comprises an array of identical (within manufacturing variations) or similar CxD elementary transducers 113, integrated into and onto the same substrate, for example, silicon. For example, each chip 111 comprises a few dozen to a few thousand elementary ultrasonic transducers 113. For example, with C=D=32, each elementary chip 111 thus comprises 1024 elementary ultrasonic transducers.

[0039] As an example, in each elementary chip 111, the inter-transducer pitch is on the order of a few tens to a few hundred micrometers in the row direction and in the column direction, for example on the order of 150 pm in the row direction and in the column direction.

[0040] The elementary chips 111 are preferably joined, so as to respect, between two neighboring transducers of two neighboring elementary chips 111, an intertransducer pitch identical or substantially identical to the pitch internal to the chip in the direction considered.

[0041] The elementary transducers of the 111 chips are for example CMUT type transducers (capacitive ultrasonic membrane transducers), piezoelectric transducers, for example of PMUT type (micro-machined piezoelectric ultrasonic transducer), piezoelectric crystal transducers, or any other type of ultrasonic transducer.

[0042] Each elementary transducer comprises two electrodes for applying an electrical excitation signal to the transducer and for reading a response electrical signal from the transducer. As an example, the elementary transducers of each chip 111 are individually controllable. For this purpose, each elementary chip 111 includes, for example, an array of individual contact metallizations (CxDs) electrically isolated from one another, connected respectively to a first electrode of each of the chip's elementary CxD transducers. Each chip 111 may also include a common contact metallization connected to a second electrode of each of the chip's elementary CxD transducers.

[0043] In the example shown, the ultrasonic transduction circuit 110 includes a support and interconnection structure 115, for example a rigid or flexible printed circuit board, on which the elementary ultrasonic transduction chips 110 are fixed and electrically connected. By way of example, the elementary chips 111 are surface-mount chips (or surface mount chips). (flip-chip), having all their contact metallizations arranged on the same face, called the connection face, of the chip (lower face in the representation of Figure 1). The support and interconnection structure 115 is, for example, a plate made up of a stack of metallic and insulating layers (not detailed in the figure), in which electrically conductive elements are formed, creating an interconnection network (not visible in the figure). The structure 115 includes, for example, on one side (upper face in the representation of Figure 1), a set of contact metallizations intended to be fixed and electrically connected to the contact metallizations of the chips 111. As an example, the chips 111 are formed in parallel in and / or on one or more semiconductor substrates, for example silicon, and then the substrate(s) are cut to individualize the chips 111.The chips 111 are then fixed and electrically connected, via their contact metallizations, to the structure 115, for example using a pick and place tool. During this step, the contact metallizations of the chips 111 are positioned opposite the corresponding contact metallizations on the upper face of the support and interconnection structure 115.

[0044] The transmit-receive circuit 120 comprises, for each elementary ultrasonic transduction chip 111, an elementary transmit-receive chip 121 having, for each elementary ultrasonic transducer 113 of the chip 111, an elementary transmit-receive cell 123 electrically connected to an electrode of the elementary ultrasonic transducer to allow individual control of the transducer in transmit and receive modes. An example of an embodiment of an elementary transmit-receive cell is shown. 123 will be described in more detail below in relation to figure 2.

[0045] Thus, the circuit 120 comprises an array of AxB elementary transmit-receive chips 121, each elementary chip 121 comprising an array of CxD elementary transmit-receive cells 123.

[0046] For example, each elementary transmit-receive chip 121 comprises, on the side of a first connection face (upper face in the representation of Figure 1), an array of contact metallizations (not visible in the figure) connected respectively to the elementary transducers of the corresponding chip 111 via the support and interconnection structure 115. The transmit-receive chips 121 are, for example, fixed and electrically connected to the face of the structure 115 opposite to the chips 111, namely its lower face in the representation of Figure 1. For example, the structure 115 comprises an electrically conductive via per elementary transducer of the circuit 110, electrically and individually connecting one electrode of the transducer to the corresponding elementary transmit-receive cell of the circuit 120.

[0047] In each elementary transmit-receive chip, the elementary transmit-receive cells 123 are divided into several elementary transmit-receive groups, each containing N elementary transmit-receive cells, where N is an integer, for example, greater than or equal to 4. In this example, each elementary transmit-receive cell 123 belongs to one and only one elementary transmit-receive group. Thus, in this example, each elementary transmit-receive chip 121 comprises CxD / N elementary groups of N elementary cells each. The N elementary cells in each group are, for example adjacent. The N elementary cells of each group are arranged, for example, in a row, column, or matrix. As a non-limiting example, N is equal to 16.

[0048] Each elementary chip 121 further includes a switching circuit 125 (Figure 2) per elementary group, i.e., CxD / N switching circuits 125. The switching circuit 125 comprises a programmable switching matrix network from N inputs to M outputs, where M is an integer, for example, greater than or equal to 2 and less than N. As an example, M is equal to 4. The switching circuit 125 is, for example, adapted to provide, at each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals. In other words, the circuit 125 implements a combiner selector function. The input and output signals of the switching circuit 125 are, in this example, analog signals, for example, voltages.

[0049] Each elementary transceiver chip 121 further comprises M analog-to-digital converter circuits 127 (Figure 2) per summing circuit 125 connected respectively to the M output terminals of the switching circuit. Thus, each transceiver chip 121 comprises (CxD / N) xM analog-to-digital converter (ADC) circuits 127. Each analog-to-digital converter circuit comprises an analog input terminal connected, for example, to an output terminal of a switching circuit 125, and a digital output terminal, providing a serialized binary digital signal, for example, on 8, 10, or 12 bits, representative of the signal applied to its analog input terminal. Thus, each elementary transceiver chip 121 comprises (CxD / N) xM digital output terminals.

[0050] As an example, each elementary transmit-receive chip 121 comprises, on the side of a second face of connection (lower face in the representation of Figure 1), (CxD / N)xM contact metallizations e2 connected, for example connected, respectively to the digital output terminals of the (CxD / N)xM analog-to-digital converters 127 of the chip. Each chip 121 comprises, for example, a silicon substrate, for example monocrystalline, in and on which the chip components are integrated, electrically conductive, laterally insulated vias vertically traversing the substrate (TSV - from the English "Through Silicon Via") and connecting the lower face metallizations e2 to the upper face metallizations of the chip.

[0051] For example, the transmit-receive chips 121 are formed in parallel in and / or on one or more semiconductor substrates, for example silicon, and then the substrate(s) are cut into elementary chips 121. The chips 121 are then attached and electrically connected, via their contact metallizations, to the underside of the structure 115, for example using a pick-and-place tool. During this step, the top-side contact metallizations of the chips 121 are positioned opposite corresponding contact metallizations on the underside of the support and interconnection structure 115.

[0052] The digital preprocessing circuit 130 includes, for each elementary transmit-receive chip 121 of the analog transmit-receive circuit 120, an elementary digital preprocessing chip 131.

[0053] Each chip 131 comprises, for each elementary transmit-receive group of the corresponding elementary transmit-receive chip 121, M elementary digital preprocessing cells 133 connected, for example connected, respectively to the output terminals e2 M analog-to-digital converters associated with the elementary transmit-receive group.

[0054] Thus, the circuit 130 comprises a matrix of AxB elementary digital preprocessing chips 131, each elementary chip 131 comprising a set of (CxD / N)xM elementary digital preprocessing cells 133, for example arranged in matrix form.

[0055] An example of the realization of an elementary digital preprocessing chip 131 will be described in more detail below in relation to figure 3.

[0056] In this example, each elementary digital preprocessing chip 131 includes a single output terminal e3 (Figure 3) for providing a serialized binary digital signal. Each chip 131 further includes a serialization circuit 301 (Figure 3) connecting the respective output nodes of the (CxD / N)xM elementary cells 133 of the chip to the single digital output terminal of the chip.

[0057] For example, each elementary digital preprocessing chip 131 comprises, on the side of a first connection face (upper face in the representation of Figure 1), an array of (CxD / N)xM contact metallizations (not visible in the figure) connected respectively to the output terminals e2 of the (CxD / N)xM analog-to-digital converters of the corresponding chip 121. Each analog preprocessing chip 131 is, for example, fixed and electrically connected directly to the lower face of the associated transmit-receive chip 121. For example, the inter-chip pitch 121 (center-to-center distance between two adjacent chips 121) is identical to the inter-chip pitch 131, in both the row and column directions.

[0058] In each elementary digital preprocessing chip 131, the digital output terminal e3 of the chip is for example connected to a contact metallization disposed on the side of a face of the chip opposite to the analog transmit-receive chips 121, namely on the side of the bottom face of the chip 131. Each chip 131 includes for example a silicon substrate, for example single-crystal, in and on which are integrated the chip components, electrically conductive laterally insulated vias, of the TSV type, vertically traversing the substrate and connecting the bottom face metallizations to the top face metallizations of the chip.

[0059] As an example, the digital preprocessing chips 131 are formed in parallel in and / or on one or more semiconductor substrates, for example silicon, and then the substrate(s) are cut into elementary chips 131. The chips 131 are then attached and electrically connected, by their contact metallizations, to the underside of the chips 121. During this step, the top-side contact metallizations of the chips 131 are positioned opposite corresponding contact metallizations on the underside of the chips 121.

[0060] The probe 100 is intended to be electrically connected to an external control and processing device 160, for example a computer, via a digital data transmission channel, for example an electrical connecting cable 150. More specifically, in this example, the electrical connecting cable 150 comprises a single conductor for transmitting 1-bit serialized digital data 151 per digital preprocessing element 131, electrically connected to the digital output terminal e3 of the chip. Alternatively, terminal e3 can be replaced by any other element of A connection suitable for providing a 1-bit serialized digital signal, for example, a differential terminal pair. The conductor wire 151 can be replaced by any wired element for transmitting 1-bit serialized digital data, for example, shielded coaxial cable or twisted-pair wire. Alternatively, the digital data transmission conductors can be replaced by optical fibers. In this case, an electrical-to-optical conversion component can be provided between terminal e3 and wire 151, for example, via card 115.

[0061] Thus, in this example, the cable 150 comprises only AxB elementary conductive wires for transmitting digital output data 151 from the probe, connected respectively to the digital output terminals e3 of the AxB elementary digital preprocessing chips 131 of the probe.

[0062] The cable 150 may also include conductive wires intended to carry electrical power supply signals to the circuits of probe 100.

[0063] The cable 150 may also include conductive wires intended to carry electrical signals for controlling the circuits of probe 100.

[0064] Preferably, the electrical control signals of the probe are carried by the same AxB conductive wires 151 as the digital output data signals of the probe, and pass through the digital preprocessing chips 131.

[0065] Figure 2 schematically and partially represents an example of the implementation of the circuits of an elementary chip 121 of the analog transmit-receive circuit 120 of the probe 100 of Figure 1.

[0066] Figure 2 shows an elementary transmit-receive cell 123, a circuit of switching 125, and an analog-to-digital converter 127 As explained above, each chip 121 practically comprises CxD elementary cells 123, CxD / N switching circuits 125, and (CxD / N) xM analog-to-digital converters 127.

[0067] In this example, each elementary transmit-receive cell 123 comprises a transmit circuit 210, a receive circuit 220, and a switching circuit 230 (T / R SW).

[0068] The transmitting circuit 210 is adapted to apply an electrical excitation signal to the corresponding elementary transducer 113 during the transmission phase of an ultrasonic wave. The receiving circuit 220 is adapted to condition and amplify an electrical response signal generated by the transducer 113 during the reception phase of an ultrasonic wave.

[0069] The transmitting circuit 210 includes an output terminal ni intended to be connected, for example, connected, to an electrode el of the associated transducer 113. In this example, the transmitting circuit 210 includes a pulse generator TX having an input node in for receiving a control logic signal, and an output node out connected, for example, connected, to the terminal ni. The input node in of the pulse generator TX can be connected, for example, connected, to an output node of a control logic circuit, not shown, of the probe. When the logic signal applied to the input node in of the generator TX is in a first state, the generator TX provides a high-level voltage at its output node out, and when the logic signal applied to the input node in of the generator TX is in a second state, the generator TX provides a low-level voltage at its output node out. The output signal of the pulse generator TX corresponds to a signal excitation of transducer 113, which can be applied directly to the transducer's electrode el.

[0070] As an alternative, the TX pulse generator is adapted to provide several distinct voltage levels at its output node, generated from the same supply voltage HV. The TX pulse generator is then adapted to generate an excitation signal whose shape can be controlled by means of a multi-bit control signal applied to its input.

[0071] The receiving circuit 220 includes an input terminal n2 intended to be connected, for example connected, to the electrode el of the transducer 113, and an output node n3 intended to be connected, for example connected, to one of the N input nodes of the switching circuit 125 of the elementary transmit-receive group to which the cell 123 belongs.

[0072] In this example, the receiving circuit 220 includes a receiving amplifier 221, preferably a low-noise amplifier (LNA), having an input node connected to terminal n2 and an output node connected to terminal n3. The amplifier 221 is, for example, a linear amplifier. Furthermore, in this example, the receiving circuit 220 also includes, between terminal n2 and the input of the amplifier 221, a time-dependent gain adjustment (TGC) circuit 223. The circuit 223 is configured to apply a time-varying analog gain to the transducer response signal applied to terminal n2 during a receiving phase. More specifically, during a phase of receiving a return ultrasonic wave by transducer 113, the gain applied by circuit 223 to the transducer's response signal increases progressively over time, and therefore with the depth of the area explored, in order to compensate for the attenuation of the ultrasonic signal by the The environment is explored. This allows for optimal use of the dynamic range of the analog-to-digital converter 127 throughout the reception phase, thus limiting the quantization noise introduced by the analog-to-digital converter 127, particularly for the most distant ultrasonic echoes. As an alternative, not shown, the time-domain gain adjustment circuit 223 can be placed between the output of the amplifier 221 and the output terminal n3 of the receiving circuit 220. In another alternative, also not shown, the time-domain gain adjustment circuit can be omitted, and the amplifier 221 replaced by a non-linear amplifier.

[0073] In the example shown in Figure 2, the receiving circuit 220 further includes a circuit 225 for applying a controllable delay to the response signal of the ultrasonic transducer. In the example shown, the circuit 225 is placed downstream of the amplification circuit 221, between the output of the amplification circuit 221 and terminal n3. Alternatively, the circuit 225 can be placed upstream of the amplification circuit 221.

[0074] In each elementary transmit-receive cell 123, the switching circuit 205 is adapted to electrically connect the electrode el of the associated elementary transducer 113 either to the output terminal ni of the transmitting circuit 210 or to the input terminal n2 of the receiving circuit 220. By way of example, the switching circuit 205 includes a first switch K1 having a first conduction node connected, for example connected, to the electrode el and a second conduction node connected, for example connected, to the terminal ni, and a second switch K2 having a first conduction node connected, for example connected, to the electrode el and a second conduction node connected, for example connected, to the terminal n2.

[0075] The control signals for the shape of the emitted pulses applied to the input in of the pulse generator TX are for example generated by control circuits (not shown) internal to probe 100, or transmitted by dedicated conductive wires (not shown) of cable 150.

[0076] As an alternative, the pulse shape control signals, applied to the input in of the pulse generator TX, are transmitted via the data transmission wires 151 (Figure 1), the elementary digital preprocessing chips 131, and the switching circuits 125. For this purpose, additional routing circuits, not detailed, may be provided in the transmit-receive chips 121 and in particular in the elementary transmit-receive cells 123.

[0077] Similarly, the control signals for the delay applied by the analog circuit 225 to the electrical response signal of the ultrasonic transducer are, for example, generated by control circuits (not shown) internal to the probe 100, or transmitted by dedicated conductive wires (not shown) of the cable 150. Similarly, control signals for the circuit 223 can be generated by control circuits (not shown) internal to the probe 100, or transmitted by dedicated conductive wires (not shown) of the cable 150.

[0078] As an alternative, the control signals for the delay applied by the analog circuit 225 are transmitted by the data transmission wires 151 (Figure 1), the elementary digital preprocessing chips 131, and the switching circuits 125, so as to limit the number of conductive wires in the cable 150.

[0079] Figure 3 schematically and partially represents an example of the implementation of a basic chip. digital preprocessing 131 of the digital preprocessing circuit 130 of the probe 100 of figure 1.

[0080] The elementary chip 131 in Figure 3 comprises a plurality of digital preprocessing (DP) elementary cells 133. In Figure 3, 16 elementary cells 133 arranged in a matrix are shown. In practice, each elementary chip 131 comprises (CxD / N)xM elementary cells 133, for example, arranged in a matrix.

[0081] A larger and more detailed view of cell 133 has also been shown in Figure 3.

[0082] The elementary chip 131 also includes a serialization circuit 301 (SERDES) connecting the respective output nodes of the (CxD / N)xM elementary cells 133 of the chip to the single digital output terminal e3 of the chip. For example, each elementary cell 133 includes a digital output node n4 connected, for example, to a specific input terminal of the circuit 301 via a data transmission bus 305. Thus, the circuit 301 receives in parallel digital signals provided by the (CxD / N)xM elementary cells 133 at their respective nodes n4, and provides a serialized digital signal applied to the single output terminal e3 of the chip.

[0083] The 301 circuit can also be adapted to implement a deserialization function to transmit in parallel on the n4 nodes of the (CxD / N)xM elementary cells 133 of the chip, serialized control signals applied to the e3 terminal.

[0084] The elementary chip 131 further includes a global control circuit 303 (GCTRL) connected, for example, to the respective control nodes n5 of the (CxD / N)xM elementary cells 133 via one or more control buses 307. The global control circuit 303 is adapted to command the execution of a sequence of operations by the elementary digital preprocessing cells 133 according to a program specified in a memory of the circuit 303. The circuit 303 sends the signals necessary for the elementary cells 133 to execute the requested operations.

[0085] Each elementary digital preprocessing cell 133 includes, for example, an elementary memory circuit 311 (MEM) adapted to store control data and data supplied by the analog-to-digital converter 127 connected to the cell 131. As an example, the elementary memory circuit 311 is adapted to store data read on nodes e2, n4 and / or n5 of the cell, or to write data on nodes e2, n4 and / or n5 of the cell.

[0086] Each elementary digital preprocessing cell 133 may further include an elementary arithmetic unit 313 adapted to implement arithmetic operations whose operands are data stored in the elementary memory circuit 311 of the cell. In the example shown in Figure 3, the elementary arithmetic unit 313 is an arithmetic and logic unit adapted to implement various arithmetic operations, for example addition, subtraction, multiplication, division, or other types of operations, for example minimum or maximum operations.

[0087] In this example, each elementary digital preprocessing cell 133 further includes data input / output ports 315 for exchanging data between the cell's elementary memory circuit 311 and the elementary memory circuits 311 of neighboring elementary cells 133, for example, according to a sequence controlled by the chip's global control circuit 303. Neighboring cells here are understood to be adjacent cells or cells separated by a significant number of cells. less than the total number of cells in circuit 131 in the direction considered, for example cells separated by a maximum of one cell (i.e. the immediate neighbor of an immediate neighbor) or by a maximum of two cells (i.e. the immediate neighbor of an immediate neighbor of an immediate neighbor).

[0088] One advantage of the 100 ultrasonic imaging probe described in relation to Figures 1 to 3 is that it incorporates closely spaced electronic control circuits enabling the implementation of micro-beam forming processes in ultra-fast acquisition scenarios, and thus considerably limiting the number of electrically conductive wires needed to connect the probe to an external processing device, for example a computer.

[0089] As an example, during a phase of acquiring characteristic data of a body to be analyzed, an ultrasonic wave is first sent towards the body to be analyzed during an emission phase, then a return ultrasonic wave, reflected by the body to be analyzed, is measured during a reception phase.

[0090] During the transmission phase, the transmitting-receiving cells 123 are, for example, controlled in parallel to emit an ultrasonic excitation pulse, for example in the form of a plane wave, towards the body to be analyzed. As an example, during the transmission phase, also called the ultrasonic firing, all the elementary transducers 113 can be controlled simultaneously in the same way (via the respective associated transmission circuits 210).

[0091] During the reception phase, a measurement is taken using each elementary transducer 113, during a predetermined acquisition window, acoustic signal reflected by the surface or internal structure of the body to be analyzed (via the respective associated 220 reception circuits).

[0092] The summation of the response signals provided at the output nodes n3 of the receive circuits 220 of the transmit-receive cells 123 of each elementary transmit-receive group of each chip 121 is performed by the switching circuits 125, thus carrying out micro-beamforming processing at the scale of the elementary groups. The delay laws applied in the different elementary groups by the circuits 225 of each group are, for example, all identical. This results in a relatively low memory requirement for storing the delays.

[0093] After digitization by the analog-to-digital converter circuits 127, the signals provided by the various combiner circuits 125 can undergo various conditioning processes in the digital preprocessing chips 131 before being transmitted to an external processing device via the cable 150. For example, in each elementary digital preprocessing cell 133, the cell's memory circuit 311 is adapted to store several hundred samples of the output signal from the associated analog-to-digital converter 127, for example, more than 256 samples, for example, a few thousand to a few tens of thousands of samples, for example, 1,000 to 100,000 samples. As an example, the memory circuit 311 is adapted to store the complete signal provided by the analog-to-digital converter 127 during the reception window following an ultrasonic pulse.The memory circuit 311 can be adapted to store the complete signal supplied by the analog-to-digital converter 127 during. several reception windows following respectively several successive ultrasonic shots.

[0094] Other delays, called macro-delays, can be applied by the external processing device 160, outside the probe 100, to perform macro-beam forming operations, by combining signals supplied by the different analog-to-digital converters 127.

[0095] For example, each elementary group of transmitting cells 123 addresses one and only one column of ultrasonic transducers 113 of the associated ultrasonic transduction chip 111. The delay laws applied in the different elementary groups are identical. In each column, the delay law applied by the circuits 225 of the column is chosen to point or focus the reception at a fixed elevation point in the plane of the column. For example, the reception is focused on the same elevation in all columns.

[0096] Other combinations can then be made post-acquisition outside the probe (macro-beam forming operations), using the external device 160, to focus the reception on the different azimuths of the elevation line fixed during the acquisition.

[0097] Thus, the implementation of beam microformation operations inside the probe makes it possible to compromise on the amount of data to be transmitted outside the probe and thus implement varied and complete acquisition scenarios with great flexibility.

[0098] It should be noted that the embodiments described are not limited to the detailed example above in which the ultrasonic transduction circuit 110, the circuit The transmit-receive circuit 120 and the digital preprocessing circuit 130 are stacked vertically.

[0099] Given the large number of electrical connections between circuits 110 and 120, circuits 110 and 120 are preferably stacked vertically, on either side of the interconnection structure 115. The digital pre-processing circuit 130 can, however, be moved laterally.

[0100] Figure 4 is an exploded perspective view schematically and partially representing a variant embodiment of the ultrasonic imaging system of Figure 1.

[0101] In this variant, the ultrasonic transduction circuit 110 and the transmit-receive circuit 120 are stacked vertically on either side of the interconnecting support 115 in a manner similar to that described previously in relation to Figure 1.

[0102] In the variant shown in Figure 4, the interconnecting support 115 extends laterally beyond the circuits 110 and 120. The digital preprocessing circuit 130 is fixed and electrically connected to one face of the interconnecting support 115, next to either circuit 110 or 120. In the example shown, circuit 130 is on the same side of the support 115 as circuit 120, namely, on the underside of the support 115 in the orientation of the figures. Circuit 130 is connected to circuit 120 by conductive traces on the interconnecting support 115.

[0103] The conductors 151 of the cable 150 are for example connected on the side of the face of the support 115 opposite to the circuit 130, directly above the circuit 130.

[0104] In the example shown, the interconnection support 115 is substantially flat. As an alternative, not shown, the interconnection support 115 can be folded so that the connection plane of circuit 130 forms an angle, for example of the order of 90°, with the connection planes of circuits 110 and 120. This allows a different arrangement of the circuits, for example to promote heat dissipation.

[0105] Figure 5 is a cross-sectional view schematically and partially representing another variant of the ultrasonic imaging system of Figure 1.

[0106] In this variant, the digital preprocessing circuit 130 is fixed next to the transmit-receive circuit 120, on the same face of the interconnection support 115 as the transmit-receive circuit 120, in a manner similar to that described in relation to Figure 4. The interconnection support 115 is then folded 180° so as to place the circuit 130 opposite the circuit 120 and obtain a vertical stacking of the circuits 110, 120 and 130.

[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the embodiments described are not limited to the numerical examples mentioned in this description.

[0108] In addition, as an alternative, the analog-to-digital converters 127 can be integrated into the elementary chips 131 of the circuit 130 rather than into the elementary chips 121 of the circuit 120.

[0109] Alternatively, the number N of elementary transmit-receive cells 123 in each elementary transmit-receive group of each elementary transmit-receive chip 121 may be less than 4, or even equal to 1 (i.e. a single elementary transmission-reception cell 123 per elementary group).

[0110] In addition, as an alternative, in each elementary transmit-receive chip 121, the number M of outputs of the switching circuit 125 can be equal to N.

[0111] In the examples described above, the analog preprocessing circuit integrated into each transceiver chip 121, including the switch 125, implements analog micro-beamforming processing, thereby reducing the number of input channels for the digital preprocessing circuit 131. Alternatively, other analog processing methods can be implemented within the chips 121, either replacing or supplementing the micro-beamforming processing. If N equals 1, the switch 125 can be omitted. If N equals 1, the analog preprocessing circuits can be integrated into the individual chips 131 of the digital preprocessing circuit 130.

[0112] Furthermore, in the examples described above, each elementary chip 131 of the digital preprocessing circuit comprises a single output terminal or a single element for supplying a binary data signal e3. The described embodiments are not limited to this particular case. As an alternative, the number of output terminals or binary connection elements e3 per elementary chip 131 may be different from 1. Preferably, the number of output terminals or binary connection elements e3 of each elementary chip 131 is less than the number of elementary digital preprocessing cells 133 of the chip.

Claims

CLAIMS 1. An ultrasound imaging probe (100) comprising first (110), second (120) and third (130) circuits, in which: - the first circuit (110) is an ultrasonic transduction circuit comprising a matrix of elementary chips (111) of ultrasonic transduction each comprising a matrix of elementary ultrasonic transducers (113); - the second circuit (120) is a transmission-reception circuit comprising, for each elementary ultrasonic transduction chip (111), a corresponding specific elementary transmission-reception chip (121) comprising, for each elementary ultrasonic transducer (113) of the elementary ultrasonic transduction chip (111), an elementary transmission-reception cell (123) electrically connected to an electrode (el) of the transducer (113); - in each elementary transmission-reception chip (121), the elementary transmission-reception cells (123) of the chip are distributed into several elementary transmission-reception groups each comprising N elementary transmission-reception cells (123), with N being an integer greater than or equal to 1; the probe comprises, for each elementary transmission-reception chip (121), for each elementary transmission-reception group of the chip, an analog preprocessing circuit (125) comprising N input terminals connected respectively to an output terminal (n3) of each elementary transmission-reception cell (123) of the elementary transmission-reception group, and M output terminals, with M less than or equal to NN; the probe comprises, for each elementary transmission-reception group of each elementary chip transceiver (121), M analog-digital converters (127) each having an input terminal and an output terminal (e2), the input terminals of the M analog-digital converters (127) being connected respectively to the M output terminals of the analog preprocessing circuit (125) of the elementary transceiver group; the third circuit (130) is a digital preprocessing circuit comprising, for each elementary transceiver chip (121), a corresponding specific elementary digital preprocessing chip (131) comprising, for each elementary transceiver group of the elementary transceiver chip (121), M elementary digital preprocessing cells (133) connected respectively to the output terminals of the M analog-digital converters (127) associated with the elementary transceiver group; - each elementary digital preprocessing chip (131) comprises one or more binary connection elements (e3) each intended to provide a serialized digital signal, connected to all of the elementary digital preprocessing cells of the chip via one or more serialization circuits (301), in which each elementary digital preprocessing cell (133) comprises an elementary memory circuit (311) and a calculation unit (313), and in which each elementary digital preprocessing chip (131) comprises a global control circuit (303) connected to respective control nodes of the MxN elementary digital preprocessing cells (133) of the chip (131) and adapted to control the execution of a sequence of operations by the elementary digital preprocessing cells (133) of the chip (131).

2. Probe (100) according to claim 1, in which, in each elementary digital preprocessing cell (133) the elementary memory circuit (311) is adapted to memorize the complete signal provided by the corresponding analog-digital converter (127) during a reception time window following an ultrasonic shot.

3. Probe (100) according to claim 1 or 2, in which each analog pre-processing circuit (125) is a combiner selector circuit adapted to provide, on each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals.

4. Probe (100) according to any one of claims 1 to 5. 3, in which each transmission-reception cell (123) comprises a transmission circuit (210) adapted to generate an electrical excitation signal applied to the electrode (el) of the associated elementary transducer (113).

5. Probe (100) according to any one of claims 1 to 5. 4, in which each transmission-reception cell (123) comprises a reception circuit (220) comprising an amplifier (221) having an input node connected to the electrode (el) of the elementary transducer (113) and an output node connected to the output terminal (n3) of the transmission-reception cell (123).

6. Probe (100) according to claim 5, wherein, in each transmission-reception cell (123), the reception circuit (220) further comprises a delay circuit (225) configured to apply a delay of an adjustable duration to the output electrical signal of the transducer (113).

7. Probe (100) according to claim 6, in which each elementary digital preprocessing cell (133) includes data input-output ports (315) allowing data to be exchanged between the elementary memory circuit (311) of the cell and the elementary memory circuits (311) of neighboring elementary cells (133).

8. A probe (100) according to any one of claims 1 to 7, wherein the first (110), second (120) and third (130) circuits are stacked vertically, the second circuit (120) being disposed between the first (110) and third (130) circuits.

9. A probe according to any one of claims 1 to 7, wherein two (110, 120) of the first (110), second (120) and third (130) circuits are stacked vertically, the remaining circuit (130) of the first (110), second (120) and third (130) circuits being laterally offset.

10. Probe (100) according to any one of claims 1 to 9, in which M is strictly less than N.

11. An ultrasound imaging system comprising an ultrasound imaging probe (100) according to any one of claims 1 to 10, an external processing device (160), and a digital data transmission channel (150) connecting the probe to the external processing device (160).

12. System according to claim 11, in which the digital data transmission channel (150) comprises one or more wired electrical or optical data transmission elements (151) per elementary digital preprocessing chip (131), electrically connected respectively to said one or more binary connection elements (e3) of the elementary chip.

13. The system of claim 11 or 12, wherein the external processing device (160) is configured to apply delays and combine signals from analog-to-digital converters (127).

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