Pixel circuit driving method, apparatus, and device

Abstract

This application discloses a method for driving a pixel circuit, an apparatus, and a device, and relates to the field of display technologies, to resolve an excessively large brightness difference between a non-emitting phase and an emitting phase in a picture display process, an excessively long non-emitting time, and excessively strong flickers caused by non-emitting or weak emitting in a part of periods. In this application, duty cycles can be flexibly and unevenly configured for duration of level phases in control periods. For example, duration of one or more level phases that are used for emitting and that are after anode reset is flexibly configured depending on whether each control period is used for the anode reset, or differentiated driving is performed, in a refresh frame period and a holding frame period based on different reset frequencies and / or different displaying refresh rates, for level phases not used for the emitting. On a premise that it is ensured that pixels can normally emit in the control periods, emitting in a plurality of control periods is uniform, or an emitting duty cycle is increased to optimize screen flickering, thereby achieving better display and eye comfort effect.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410175957.3, filed with the China National Intellectual Property Administration on February 7, 2024 and entitled "METHOD FOR DRIVING PIXEL CIRCUIT, APPARATUS, AND DEVICE", which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] This application relates to the field of display technologies, and in particular, to a method for driving a pixel circuit, an apparatus, and a device.BACKGROUND

[0003] Currently, when a display of an electronic device displays a picture, a dimming strategy such as pulse-width modulation (pulse-width modulation, PWM) or direct current (direct current, DC) modulation is usually used to perform dimming, to achieve good display effect and improve visual experience of a user. For example, in a conventional technology, an error of emitting duration of each emitting period in a picture frame is usually controlled to be kept within a given range, to implement consistency of emitting periods, thereby improving the visual experience of the user.

[0004] However, because the display usually further includes other components such as an electroluminance (electroluminance, EL) component and an anode of a pixel circuit, or operations such as data writing, anode reset, and gate reset need to be performed in some periods, the data writing, the gate reset, or anode reset of the EL component may shorten emitting duration of one or more periods, or cause a part or all of emitting currents in a period to be used for charging a component (such as a capacitor) instead of pixel emitting, leading to an excessively large brightness difference between a non-emitting phase and an emitting phase in a picture display process, an excessively long non-emitting time, and excessively strong flickers caused by non-emitting or weak emitting in a part of periods.SUMMARY

[0005] This application provides a method for driving a pixel circuit, an apparatus, and a device, to resolve an excessively large brightness difference between a non-emitting phase and an emitting phase in a picture display process, an excessively long non-emitting time, and excessively strong flickers caused by non-emitting or weak emitting in a part of periods, thereby improving visual experience of a user upon use.

[0006] To achieve the foregoing objective, this application uses the following technical solutions.

[0007] According to a first aspect, a method for driving a pixel circuit is provided. A display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods include a first control period, the first control period is used for anode reset, the pixel circuit includes an emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls the anode reset based on the first control period, and the method includes: detecting a screen brightness value; when the screen brightness value is less than a first brightness threshold, configuring duration of second level phases in the plurality of control periods based on the first control period; and receiving, by the emitting control circuit, an emitting control signal, and controlling the emitting based on duration of first level phases and the duration of the second level phases in the plurality of control periods.

[0008] For example, the foregoing method may be applied to a display panel, a display, or an electronic device including a display, such as a mobile phone or a tablet computer. This is not limited.

[0009] For example, the first level phase in the control period is, for example, a high level phase, and the second level phase is, for example, a low level phase. Alternatively, the first level phase is, for example, a low level phase, and the second level phase is, for example, a high level phase. This is not limited.

[0010] According to the solution provided in the first aspect, in a scenario in which the screen brightness value is less than the first brightness threshold, for example, in a medium and low brightness scenario, duty cycles are flexibly and unevenly configured, based on an actual case such as whether the control periods are used for the anode reset, for duration of level phases (for example, second level phases) used for the emitting in the control periods. For example, duration of one or more second level phases after the anode reset is flexibly configured. On a premise that it is ensured that pixels can normally emit in the control periods, the emitting in the plurality of control periods is uniform, and screen flickering is optimized, thereby achieving better display and eye comfort effect.

[0011] In a possible implementation, the plurality of control periods further include a second control period, the second control period is not used for the anode reset, and the configuring the duration of the second level phases in the plurality of control periods based on the first control period includes: configuring duration of a second level phase in the first control period as first duration, and configuring duration of a second level phase in the second control period as second duration. The first duration is greater than the second duration. In view of this, duration of a second level phase in a control period used for the anode reset may be greater than duration of a second level phase in a control period not used for the anode reset. This improves applicability, compatibility, and flexibility of the solution in different scenarios while ensuring uniform emitting of a plurality of low level phases of a same picture frame.

[0012] In a possible implementation, the first control period includes at least one second level phase, and the first duration includes total duration of the at least one second level phase in the first control period. In view of this, in various manners, the duration of the second level phase in the control period used for the anode reset may be greater than the duration of the second level phase in the control period not used for the anode reset. For example, in comparison with another period, duration of a second level phase in a display drive period used for the anode reset is prolonged, or a quantity of second level phases in a plurality of display drive periods used for the anode reset is increased. This improves the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0013] For example, the first control period includes one second level phase, and duration of the second level phase in the first control period is greater than the duration of the second level phase in the second control period.

[0014] Alternatively, for example, the first control period includes a plurality of second level phases, and a sum of duration (that is, total duration) of the plurality of second level phases in the first control period is greater than the duration of the second level phase in the second control period.

[0015] In a possible implementation, the plurality of control periods further include a third control period, the third control period is a control period after the first control period, the third control period is not used for the anode reset, and the configuring the duration of the second level phases in the plurality of control periods based on the first control period includes: configuring duration of a second level phase in the third control period as third duration. The third duration is greater than the second duration. In view of this, duration of a second level phase in a control period that is of a picture frame and that is not used for the anode reset may be flexibly adjusted based on an actual case to perform emitting compensation, to ensure that the pixel can keep normally emitting in each control period. In this way, emitting yields of pixels in the control periods are the same or close, thereby ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0016] In a possible implementation, the third control period includes at least one second level phase, and the third duration includes total duration of the at least one second level phase in the third control period. In view of this, this can improve, in the various manners, the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0017] In an example, the third duration is less than or equal to the first duration.

[0018] In a possible implementation, the first control period includes at least one control period; and / or the second control period includes at least one control period; and / or the third control period includes at least one control period. In other words, there may be one or more first control periods, one or more second control periods, and one or more third control periods. In view of this, when there are a plurality of first control periods, a plurality of second control periods, or a plurality of third control periods, a similar operation of configuring the duration of the second level phases may be performed for each control period, so that duration of second level phases in a plurality of control periods used for the anode reset is greater than duration of a second level phase in the control period not used for the anode reset, and / or duration of second level phases in a plurality of 1 st< control periods after the anode reset is greater than duration of a second level phase in another control period not used for the anode reset. This improves the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0019] According to a second aspect, a method for driving a pixel circuit is provided. A display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods include a refresh frame period, the refresh frame period is used for displaying refresh and gate reset, the pixel circuit includes an emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls the gate reset and the displaying refresh based on the refresh frame period, and the method includes: detecting a screen brightness value; when the screen brightness value is greater than a second brightness threshold, configuring duration of first level phases in the plurality of control periods based on a displaying refresh rate corresponding to an emitting control signal and / or a reset frequency corresponding to the reset control signal; and receiving, by the emitting control circuit, the emitting control signal, and controlling the emitting based on the duration of the first level phases and duration of the second level phases in the plurality of control periods.

[0020] For example, the foregoing method may be applied to a display panel, a display, or an electronic device including a display, such as a mobile phone or a tablet computer. This is not limited.

[0021] For example, the displaying refresh rate is 120 Hz, 60 Hz, or 1 Hz, and is not limited. The reset frequency is a source reset frequency or a drain reset frequency, for example, 120 Hz, 240 Hz, or 360 Hz, and is not limited.

[0022] For example, the first level phase in the control period is, for example, a high level phase, and the second level phase is, for example, a low level phase. Alternatively, the first level phase is, for example, a low level phase, and the second level phase is, for example, a high level phase. This is not limited.

[0023] According to the solution provided in the second aspect, in a scenario in which the screen brightness value is greater than the second brightness threshold, for example, in a high brightness scenario, duty cycles are flexibly and unevenly configured, based on an actual case, for duration of level phases (for example, first level phases) not used for the emitting in the control periods. For example, differentiated driving is performed on the first level phases in the refresh frame period and a holding frame period based on different reset frequencies and / or different displaying refresh rates. On a premise that it is ensured that pixels operate normally in the control periods, an emitting duty cycle is increased to optimize screen flickering. In addition, the duty cycles are kept equivalent in different displaying refresh rates and / or different reset frequencies, and flickers generated when the displaying refresh rate or the reset frequency is switched are avoided, thereby achieving better display and eye comfort effect.

[0024] In a possible implementation, the plurality of control periods further include the holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level phases in the plurality of control periods based on the displaying refresh rate corresponding to the emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring duration of a first level phase in the refresh frame period as fourth duration, and configuring duration of a first level phase in the holding frame period as fifth duration. The fifth duration is less than the fourth duration. In view of this, it can be ensured that the pixels operate normally in the control periods, and the emitting duty cycle is increased to optimize the screen flickering, thereby achieving the better display and eye comfort effect.

[0025] For example, a display period of a picture frame includes N control periods, where N=F1 / F2, F1 is the source reset frequency or the drain reset frequency, and F2 is the displaying refresh rate. The configuring the duration of the first level phases in the plurality of control periods based on the displaying refresh rate corresponding to the emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring duration of first level phases in N-1 holding frame periods, to enable the duration of the first level phases in the N-1 holding frame periods to be less than the duration of the first level phase in the refresh frame period.

[0026] In a possible implementation, the plurality of control periods further include a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a second refresh rate, the second refresh rate is less than a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level phases in the plurality of control periods based on the displaying refresh rate corresponding to the emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring duration of a first level phase in the refresh frame period as fourth duration, and configuring duration of a first level phase in the holding frame period as sixth duration. The sixth duration is less than the fourth duration, and the sixth duration is greater than fifth duration. In view of this, it can be ensured that the pixels operate normally in the control periods, the emitting duty cycle is increased to optimize the screen flickering, the duty cycles can be kept equivalent in the different displaying refresh rates and / or the different reset frequencies, and the flickers generated when the displaying refresh rate or the reset frequency is switched are avoided, thereby achieving the better display and eye comfort effect.

[0027] In a possible implementation, the refresh frame period includes one control period; and / or the holding frame period includes at least one control period. In other words, there may be one refresh frame period, and there may be one or more holding frame periods. In view of this, when there is the one refresh frame period and the one or more holding frame periods, a similar operation of configuring the duration of the first level phase may be performed for each control period, to implement the differentiated driving on the first level phases in the refresh frame period and the holding frame period.

[0028] Certainly, in some examples, there may be no holding frame period. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0029] According to a third aspect, a display is provided. The display includes an integrated circuit, a gate drive unit, and a pixel circuit, a display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods include a first control period, the first control period is used for anode reset, and the pixel circuit includes an emitting control circuit and an anode reset circuit. The anode reset circuit is configured to: receive an anode reset control signal, and control the anode reset based on the first control period. The integrated circuit is configured to: detect a screen brightness value, and when the screen brightness value is less than a first brightness threshold, configure duration of the second level phases in the plurality of control periods based on the first control period. The emitting control circuit is configured to: receive an emitting control signal, and control the emitting based on duration of first level phases and duration of second level phases in the plurality of control periods.

[0030] For example, the integrated circuit is, for example, a driver integrated circuit (integrated circuit, IC), and the gate drive unit may include but is not limited to a gate driver on array (gate driver on array, GOA).

[0031] According to the solution provided in the third aspect, in a scenario in which the screen brightness value is less than the first brightness threshold, for example, in a medium and low brightness scenario, duty cycles are flexibly and unevenly configured, based on an actual case such as whether the control periods are used for the anode reset, for duration of level phases (for example, second level phases) used for the emitting in the control periods. Duration of one or more second level phases after the anode reset is flexibly configured. On a premise that it is ensured that the display can normally emit in the control periods, the emitting in the plurality of control periods is uniform, and screen flickering is optimized, thereby achieving better display and eye comfort effect.

[0032] In a possible implementation, the plurality of control periods further include a second control period, the second control period is not used for the anode reset, and the integrated circuit is specifically configured to: configure duration of a second level phase in the first control period as first duration, and configure duration of a second level phase in the second control period as second duration. The first duration is greater than the second duration. In view of this, duration of a second level phase in a control period used for the anode reset may be greater than duration of a second level phase in a control period not used for the anode reset. This improves applicability, compatibility, and flexibility of the solution in different scenarios while ensuring uniform emitting of a plurality of low level phases of a same picture frame.

[0033] In a possible implementation, the first control period includes at least one second level phase, and the first duration includes total duration of the at least one second level phase in the first control period. In view of this, in various manners, the duration of the second level phase in the control period used for the anode reset may be greater than the duration of the second level phase in the control period not used for the anode reset. For example, in comparison with another period, duration of a second level phase in a display drive period used for the anode reset is prolonged, or a quantity of second level phases in a plurality of display drive periods used for the anode reset is increased. This improves the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0034] For example, the first control period includes one second level phase, and duration of the second level phase in the first control period is greater than the duration of the second level phase in the second control period.

[0035] Alternatively, for example, the first control period includes a plurality of second level phases, and a sum of duration (that is, total duration) of the plurality of second level phases in the first control period is greater than the duration of the second level phase in the second control period.

[0036] In a possible implementation, the plurality of control periods further include a third control period, the third control period is a control period after the first control period, the third control period is not used for the anode reset, and the integrated circuit is specifically configured to: configure duration of a second level phase in the third control period as third duration. The third duration is greater than the second duration. In view of this, duration of a second level phase in a control period that is of a picture frame and that is not used for the anode reset may be flexibly adjusted based on an actual case to perform emitting compensation, to ensure that the display can keep normally emitting in each control period. In this way, emitting yields of pixels of the display in the control periods are the same or close, thereby ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0037] In a possible implementation, the third control period includes at least one second level phase, and the third duration includes total duration of the at least one second level phase in the third control period. In view of this, this can improve, in the various manners, the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0038] In an example, the third duration is less than or equal to the first duration.

[0039] In a possible implementation, the first control period includes at least one control period; and / or the second control period includes at least one control period; and / or the third control period includes at least one control period. In other words, there may be one or more first control periods, one or more second control periods, and one or more third control periods. In view of this, when there are a plurality of first control periods, a plurality of second control periods, or a plurality of third control periods, a similar operation of configuring the duration of the second level phases may be performed for each control period, so that duration of second level phases in a plurality of control periods used for the anode reset is greater than duration of a second level phase in the control period not used for the anode reset, and / or duration of second level phases in a plurality of 1 st< control periods after the anode reset is greater than duration of a second level phase in another control period not used for the anode reset. This improves the applicability, the compatibility, and the flexibility of the solution in the different scenarios while ensuring the uniform emitting of the plurality of low level phases of the same picture frame.

[0040] According to a fourth aspect, a display is provided. The display includes an integrated circuit, a gate drive unit, and a pixel circuit, a display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods include a refresh frame period, the refresh frame period is used for displaying refresh and gate reset, and the pixel circuit includes an emitting control circuit and a reset circuit. The reset circuit is configured to: receive a reset control signal, and control the gate reset and the displaying refresh based on the refresh frame period. The integrated circuit is configured to: detect a screen brightness value, and when the screen brightness value is greater than a second brightness threshold, configure duration of first level phases in the plurality of control periods based on a displaying refresh rate corresponding to an emitting control signal and / or a reset frequency corresponding to the reset control signal. The emitting control circuit is configured to: receive the emitting control signal, and control the emitting based on the duration of the first level phases and duration of second level phases in the plurality of control periods.

[0041] According to the solution provided in the fourth aspect, in a scenario in which the screen brightness value is greater than the second brightness threshold, for example, in a high brightness scenario, duty cycles are flexibly and unevenly configured, based on an actual case, for duration of level phases (for example, first level phases) not used for the emitting in the control periods. For example, differentiated driving is performed on the first level phases in the refresh frame period and a holding frame period based on different reset frequencies and / or different displaying refresh rates. On a premise that it is ensured that the display operates normally in the control periods, an emitting duty cycle is increased to optimize screen flickering. In addition, the duty cycles are kept equivalent in different displaying refresh rates and / or different reset frequencies, and flickers generated when the displaying refresh rate or the reset frequency is switched are avoided, thereby achieving better display and eye comfort effect.

[0042] In a possible implementation, the plurality of control periods further include a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: configure duration of a first level phase in the refresh frame period as fourth duration, and configure duration of a first level phase in the holding frame period as fifth duration. The fifth duration is less than the fourth duration. In view of this, it can be ensured that the display operates normally in the control periods, and the emitting duty cycle is increased to optimize the screen flickering, thereby achieving the better display and eye comfort effect.

[0043] In a possible implementation, the plurality of control periods further include a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a second refresh rate, the second refresh rate is less than a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: configure duration of a first level phase in the refresh frame period as fourth duration, and configure duration of a first level phase in the holding frame period as sixth duration. The sixth duration is less than the fourth duration, and the sixth duration is greater than fifth duration. In view of this, it can be ensured that the pixels operate normally in the control periods, the emitting duty cycle is increased to optimize the screen flickering, the duty cycles can be kept equivalent in the different displaying refresh rates and / or the different reset frequencies, and the flickers generated when the displaying refresh rate or the reset frequency is switched are avoided, thereby achieving the better display and eye comfort effect.

[0044] In a possible implementation, the refresh frame period includes one control period; and / or the holding frame period includes at least one control period. In other words, there may be one refresh frame period, and there may be one or more holding frame periods. In view of this, when there is the one refresh frame period and the one or more holding frame periods, a similar operation of configuring the duration of the first level phase may be performed for each control period, to implement the differentiated driving on the first level phases in the refresh frame period and the holding frame period.

[0045] Certainly, in some examples, there may be no holding frame period. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0046] According to a fifth aspect, an electronic device is provided. The electronic device includes: a display, configured to display an interface; a memory, configured to store computer program instructions; and a processor, configured to execute the computer program instructions, to support the electronic device to implement the method according to any one of the possible implementations of the first aspect or the second aspect.

[0047] According to a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions. When the computer program instructions are executed by a processor, the method according to any one of the possible implementations of the first aspect or the second aspect is implemented.

[0048] According to a seventh aspect, a computer program product including instructions is provided. When the computer program product runs on a computer, the computer is enabled to implement the method according to any one of the possible implementations of the first aspect or the second aspect.

[0049] According to an eighth aspect, a chip system is provided. The chip system includes a processing circuit and a storage medium. The storage medium stores computer program instructions. When the computer program instructions are executed by the processor, the method according to any one of the possible implementations of the first aspect or the second aspect is implemented. The chip system may include a chip, or may include a chip and another discrete component.BRIEF DESCRIPTION OF DRAWINGS

[0050] FIG. 1 is a diagram of a principle of controlling emitting based on a conventional light-emitting (Emitting, EM) control signal; FIG. 2 is a diagram of emitting effect of pixels driven by a conventional EM control signal; FIG. 3 is a diagram of a principle of controlling emitting based on other two conventional EM control signals; FIG. 4 is a diagram of a hardware structure of an electronic device according to an embodiment of this application; FIG. 5 is a diagram 1 of emitting effect of pixels driven by an EM control signal according to an embodiment of this application; FIG. 6 is a diagram 2 of emitting effect of pixels driven by an EM control signal according to an embodiment of this application; FIG. 7 is a diagram 3 of emitting effect of pixels driven by an EM control signal according to an embodiment of this application; FIG. 8 is a diagram 4 of emitting effect of pixels driven by an EM control signal according to an embodiment of this application; FIG. 9 is a diagram 5 of emitting effect of pixels driven by an EM control signal according to an embodiment of this application; FIG. 10 is a principle diagram 1 of controlling emitting based on an EM control signal according to an embodiment of this application; FIG. 11 is a principle diagram 2 of controlling emitting based on an EM control signal according to an embodiment of this application; FIG. 12 is a principle diagram 3 of controlling emitting based on an EM control signal according to an embodiment of this application; FIG. 13 is a diagram of a pixel circuit according to an embodiment of this application; FIG. 14 is a diagram of driving timing corresponding to a refresh frame period according to an embodiment of this application; FIG. 15 is a diagram 1 of driving timing corresponding to a holding frame period according to an embodiment of this application; FIG. 16 is a diagram 2 of driving timing corresponding to a holding frame period according to an embodiment of this application; FIG. 17 is a diagram 3 of driving timing corresponding to a holding frame period according to an embodiment of this application; and FIG. 18 is a block diagram of a structure of a display panel according to an embodiment of this application. DESCRIPTION OF EMBODIMENTS

[0051] The following describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application. In the description of embodiments of this application, unless otherwise specified, " / " means "or". For example, A / B may represent A or B. In this specification, "and / or" describes only an association relationship between associated objects and represents that three relationships may exist. For example, A and / or B may represent the following three cases: Only A exists, both A and B exist, and only B exists. In addition, in the descriptions in embodiments of this application, "a plurality of" means two or more.

[0052] In the following, terms "first", "second", and the like are merely used to distinguish between different described objects, and constitute no limitation on locations, a sequence, priorities, a quantity, content, or the like of the described objects. For example, if the described object is a "field", ordinal numbers before "field" in a "first field" and a "second field" do not limit locations or a sequence of the "fields", and "first" and "second" do not limit whether "fields" modified by "first" and "second" are in a same message, and do not limit a sequence of the "first field" and the "second field". For another example, if the described object is a "level", ordinal numbers before "level" in a "first level" and a "second level" do not limit priorities of the "levels". For another example, a quantity of described objects is not limited by an ordinal number, and may be one or more. In an example of a "first apparatus", a quantity of "apparatuses" may be one or more. In addition, objects modified by different prefix words may be the same or different. For example, if a described object is an "apparatus", a "first apparatus" and a "second apparatus" may be apparatuses of a same type, or apparatuses of different types. For another example, if a described object is "information", "first information" and "second information" may be information of same content or information of different content. In conclusion, in embodiments of this application, use of prefix words such as ordinal numbers used to distinguish between the described objects constitutes no limitation on the described objects. For descriptions of the described objects, refer to context descriptions in the claims or embodiments. The use of such prefix words should not constitute an unnecessary limitation.

[0053] In addition, in embodiments of this application, a "connection" may be a direct connection or an indirect connection, and may be an electrical connection or a communication connection. For example, a connection between two electrical elements A and B may mean that A is directly connected to B, or may mean that A is indirectly connected to B through another electrical element or a connection medium, or may mean that A is indirectly connected to B through another communication apparatus or a communication medium, provided that A and B can communicate with each other.

[0054] As described in the background, dimming policies such as PWM and DC modulation are usually used by a display, for example, an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) panel, of an existing electronic device to perform dimming. For example, the PWM dimming strategy is used in a medium and low brightness scenario, and the DC modulation dimming strategy is used in a high brightness scenario, to achieve better display effect by adjusting a duty cycle and / or a brightness value of the display, thereby improving visual experience of a user. However, the foregoing dimming method is a strategy in an ideal case, and an actual case of the display during operation is not considered.

[0055] For example, in the medium and low brightness scenario, impact of anode reset and charging of components such as an EL capacitor and an anode of a pixel circuit of the display on emitting time of the display is not considered in an existing dimming method.

[0056] As shown in FIG. 1, for example, emitting is controlled based on a light-emitting (Emitting, EM) control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 120 Hz, and a display period of one frame of picture includes 12 control periods. Generally, the PWM dimming strategy may be used to control the brightness value by adjusting the duty cycle, to achieve uniform dimming effect. The displaying refresh rate may be simply understood as a screen-on quantity in unit time, and the duty cycle may be simply understood as a proportion of time for driving pixels to emit to total time. A pulse sequence whose pulse width is 1 µs and control period is 4 µs is used as an example, and a duty cycle of the pulse sequence is 1 µs / 4 µs=0.25. In FIG. 1, when the EM control signal is at a low level, the display is on; or when the EM control signal is at a high level, the display is off. It should be noted that, in FIG. 1, only an example in which the display emits when the EM control signal is at the low level. This is not specifically limited during actual application. For example, in some embodiments, the high level corresponds to that the pixel emits, and the low level corresponds to that the pixel is off. This is determined based on a specific case.

[0057] However, using the dimming method shown in FIG. 1 has the following problems: The display such as the AMOLED usually includes the components such as the EL capacitor and the anode of the pixel circuit. As shown in FIG. 2, in a 1 st< control period of a picture frame, for example, the display performs the anode reset at a frequency of 120 Hz, when the EM control signal is switched to the low level, because the components such as the EL capacitor and the anode of the pixel circuit need to be charged, actual emitting duration of the display in the 1 st< control period is shortened, and the display may not even emit in a serious case, as shown in FIG. 2. As a result, low-frequency component flickers caused due to no emitting or weak emitting in some control periods in a picture display process can be perceived by human eyes. In other words, an increase of stroboscopic effect visibility measure (stroboscopic effect visibility measure, SVM) results in the strong picture flickers.

[0058] For another example, in the high brightness scenario, for example, when the screen brightness value is greater than 90 nits, impact of a length of a high level phase in a refresh frame period being consistent with a length of a high level phase in a holding frame period on emitting time of the display is not considered in an existing dimming method.

[0059] As shown in FIG. 3, for example, emitting control is performed based on the EM control signal at a screen brightness value of 500 nits, and the display emits when the EM control signal is at a low level. Generally, duration of the control signal at the low level in the refresh frame period is controlled to be consistent with duration of the control signal at the low level in the holding frame period (or an error is within an acceptable range), so that emitting duration of the display in the refresh frame period is consistent with emitting duration of the display in the holding frame period, thereby achieving uniform dimming effect. In addition, for different displaying refresh rates, as shown in FIG. 3, the displaying refresh rates are 120 Hz and 60 Hz, and the duration of the EM control signal at the low level in the refresh frame period is also consistent with the duration of the EM control signal at the low level in the holding frame period (or the error is within the acceptable range), so that duty cycles are consistent at the different displaying refresh rates, thereby avoiding a brightness difference caused by displaying refresh rate switching.

[0060] However, using the dimming method shown in FIG. 3 has the following problem: During actual application, because gate reset and data writing (for example, for displaying refresh) need to be performed in the refresh frame period, duration of the high level phase is long, that is, time in which the display does not emit is long. Therefore, the duration of the EM control signal at the low level is definitely shortened. If the duration of the EM control signal at the low level in the refresh frame period needs to be kept consistent with the duration of the EM control signal at the low level in the holding frame period, screen-on duration of the holding frame period is shortened. As a result, a higher brightness amplitude is required for the display when the EM control signal is at the low level to achieve a specified brightness target value, and an average emitting time proportion in a frame of picture is low. The two impacts both cause a problem that SVM increases, that is, picture flickers are excessively strong.

[0061] It should be noted that in the examples shown in FIG. 1 to FIG. 3, when the EM control signal is at the low level, the display emits; and when the EM control signal is at the high level, the display is off. Certainly, during actual application, alternatively, the high level may correspond to that the display emits, and the low level may correspond to that the display does not emit. This is determined based on a specific case.

[0062] When an existing dimming method is applied, to resolve excessively strong flickers caused, in a process of displaying a picture by a display, by an excessively large brightness difference between a non-emitting phase and an emitting phase, an excessively long non-emitting time, and a large SVM value caused by non-emitting or weak emitting in a part of periods, an embodiment of this application provides a method for driving a pixel circuit. The method can resolve a screen flicker problem in brightness scenarios such as a medium and low brightness scenario or a high brightness scenario.

[0063] For example, according to the solution provided in this embodiment of this application, in the medium and low brightness scenario, a non-uniform duty cycle configuration may be used in each control period (for example, an EM period, and the EM period is used as an example for related description below) in a display period. In this implementation, a display can normally emit in a low level phase after operations such as anode reset and component charging are performed, and emitting is uniform in a plurality of low level phases, thereby optimizing screen flickering and achieving better display and eye comfort effect.

[0064] For another example, according to the solution provided in this embodiment of this application, in the high brightness scenario, a parameter, for example, duration of a first level phase, of at least one control period corresponding to a picture frame may be adjusted based on one or more of a screen brightness value, a displaying refresh rate, reset frequencies (such as a source reset frequency and a drain reset frequency), and the like. Finally, an interface is displayed based on an adjusted parameter of the control period. For example, differentiated driving may be performed in a refresh frame period and a holding frame period based on different reset frequencies (for example, 120 Hz, 240 Hz, and 360 Hz) and / or different displaying refresh rates (for example, 1 Hz, 60 Hz, and 120 Hz), to enable a difference between duration (that is, duration in which the display does not emit) of a first level phase (for example, a high level phase, where the following uses an example in which the first level phase is the high level phase for related descriptions) in the refresh frame period and duration of a first level phase in the holding frame period to be greater than 1H, and enable duty cycles at the different displaying refresh rates and / or the different reset frequencies to be high and basically equivalent (for example, a difference is less than 0.2%), thereby optimizing the screen flickering and achieving better display and eye comfort effect. 1H is a unit of scanning time for each row of the display, and is usually between 1 µs and 3 µs.

[0065] The display in embodiments of this application is a display of an electronic device. The electronic device may include but is not limited to a smartphone, a netbook, a tablet computer, a smart drawing board, a handwriting tablet, a smart watch, a smart band, a phone watch, smart glasses, a smart camera, a palmtop computer, a vehicle-mounted computer, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a portable media player (portable media player, PMP), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a smart television, a projection device, a somatic game console in a human-machine interaction scenario, or the like. Alternatively, the electronic device may be an electronic device of another type or structure having a display. This is not limited in this application.

[0066] In an example, FIG. 4 is a diagram of a hardware structure of an electronic device according to an embodiment of this application.

[0067] As shown in FIG. 4, the electronic device may include a processor 410, a memory 420, a charging management module 430, a power management module 440, a battery 450, a display 460, and the like.

[0068] The processor 410 may include one or more processing units. For example, the processor 410 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a flight controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and / or a neural-network processing unit (neural-network processing unit, NPU). Different processing units may be independent components, or may be integrated into one or more processors.

[0069] A memory may be disposed in the processor 410, and is configured to store instructions and data. In some embodiments, the memory in the processor 410 is a cache. The memory may store instructions or data that has just been used or is cyclically used by the processor 410. If the processor 410 needs to use the instructions or data again, the processor 410 may invoke the instructions or data directly from the memory. Therefore, repeated access is avoided, waiting time of the processor 410 is reduced, and system efficiency is improved.

[0070] The charging management module 430 is configured to receive a charging input from the charger. The charger may be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module 430 may receive a charging input of the wired charger through a USB interface. In some embodiments of wireless charging, the charging management module 430 may receive a wireless charging input through a wireless charging coil. The charging management module 430 may further supply power to the electronic device via the power management module 440 while charging the battery 450.

[0071] The power management module 440 is configured to connect to the battery 450, the charging management module 430, and the processor 410. The power management module 440 receives an input from the battery 450 and / or the charging management module 430, and supplies power to the processor 410, the internal memory 420, the display 460, a camera 393, a wireless communication module 360, and the like. The power management module 440 may be further configured to monitor parameters such as a battery capacity, a battery cycle count, and a battery health status (electric leakage or impedance). In some other embodiments, the power management module 440 may alternatively be disposed in the processor 410. In some other embodiments, the power management module 440 and the charging management module 430 may alternatively be disposed in a same component.

[0072] In this embodiment of this application, the power management module 440 receives an input of the battery 450 and / or the charging management module 430, and supplies power to the display 460 to support normal operation of the display, for example, support the display to emit or to be off.

[0073] The electronic device implements a display function via the GPU, the display 460, the AP, and the like. The GPU is a microprocessor for image processing, and is connected to the display 460 and the AP. The GPU is configured to: perform mathematical and geometric calculation, and render an image. The processor 410 may include one or more GPUs that execute program instructions to generate or change display information.

[0074] The display 460 is configured to display an image, a video, and the like. The display 460 includes a display panel. The display panel may be a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (organic light-emitting diode, OLED), an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED), a flexible light-emitting diode (flexible light-emitting diode, FLED), a mini-LED, a micro-LED, a micro-OLED, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), or the like.

[0075] In this embodiment of this application, the display 460 may display a picture based on normal operation of the display panel.

[0076] In some embodiments, in a medium and low brightness scenario, the display may use a non-uniform duty cycle configuration in each EM period in a display period, to ensure that the display can normally emit in an initial second level phase (for example, a low level phase, where the following uses an example in which the second level phase is the low level phase for related descriptions) after anode reset, component charging, and the like are completed, and that emitting is uniform in a plurality of low level phases in a same display period.

[0077] In some embodiments, in a high brightness scenario, the display may perform differentiated driving in a refresh frame period and a holding frame period based on different reset frequencies (for example, 120 Hz, 240 Hz, and 360 Hz) and / or different displaying refresh rates (for example, 1 Hz, 60 Hz, and 120 Hz), to enable duty cycles at the different displaying refresh rates and / or the different reset frequencies to be high and basically equivalent (for example, a difference is less than 0.2%), thereby achieving a small SVM value, optimizing screen flickering, and achieving better display and eye comfort effect.

[0078] In some embodiments, as shown in FIG. 4, the display may include an integrated circuit (for example, a drive integrated circuit (integrated circuit, IC)), a gate drive unit, and a pixel circuit.

[0079] The pixel circuit includes an emitting control circuit and a reset circuit.

[0080] The drive IC is configured to: obtain a screen brightness value; and when the screen brightness value is less than a first brightness value, configure duration of second level phases in a plurality of control periods based on a period (for example, a first control period) used for anode reset; or when the screen brightness value is greater than a second brightness threshold, configure duration of first level phases in a plurality of control periods based on a displaying refresh rate corresponding to an emitting control signal and / or a reset frequency corresponding to a reset control signal. For example, the gate drive unit may include but is not limited to a GOA.

[0081] The emitting control circuit is configured to control, based on the emitting control signal, emitting based on the duration of the first level phases not used for the emitting and the duration of the second level phases used for the emitting that are in the plurality of control periods of the pixel circuit.

[0082] The reset circuit is configured to: control, based on the reset control signal, whether the plurality of control periods are used for reset, for example, control performing of the reset in the first control period. For example, an anode reset circuit is configured to control, based on an anode reset control signal, whether the plurality of control periods are used for the anode reset; a source reset circuit is configured to control, based on a source reset control signal, whether the plurality of control periods are used for source reset; and a drain reset circuit is configured to control, based on a drain reset control signal, whether the plurality of control periods are used for drain reset.

[0083] An interface 320 for external memory may be configured to connect to an external storage card, for example, a micro SD card, to extend a storage capability of the electronic device. The external storage card communicates with the processor 410 through the interface 320 for external memory, to implement a data storage function.

[0084] The internal memory 420 may be configured to store computer executable program code. For example, a computer program may include an operating system program and an application. The executable program code includes instructions. The processor 410 executes various function applications and data processing of the electronic device by running the instructions stored in the memory 420. The memory 420 may include a program storage area and a data storage area. The program storage area may store an operating system, an application required by at least one function, and the like. The data storage area may store data created during use of the electronic device, and the like. In addition, the memory 420 may include a high-speed random access memory, or may include a non-volatile memory, for example, at least one magnetic disk storage component, a flash memory component, or a universal flash storage (universal flash storage, UFS). The processor 410 performs various function applications and data processing of the electronic device by running the instructions stored in the memory 420 and / or instructions stored in the memory disposed in the processor.

[0085] It may be understood that the structure illustrated in FIG. 4 in this application does not constitute a specific limitation on the electronic device. In some other embodiments of this application, the electronic device may include more or fewer components than those shown in the figure, or some components may be combined, or some components may be divided, or different component arrangements may be used. The components shown in the figure may be implemented by using hardware, software, or a combination of software and hardware.

[0086] For example, in some examples, the electronic device may further include one or more components or modules such as a universal serial bus (universal serial bus, USB) interface, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a receiver, a microphone, a headset jack, a sensor module, a button, a motor, an indicator, and a camera. Details are not described herein again.

[0087] The following specifically describes the method for driving a pixel circuit provided in embodiments of this application with reference to specific scenarios.Embodiment 1:

[0088] In Embodiment 1, when an electronic device displays a picture frame based on the pixel circuit, a display period of one picture frame usually includes a plurality of consecutive control periods. The pixel circuit includes an emitting control circuit and an anode reset circuit. The emitting control circuit is configured to receive an emitting control signal, for example, an EM control signal. The anode reset circuit is configured to receive an anode reset control signal. In other words, the pixel circuit may receive the EM control signal, and control emitting based on duration of a level phase not used for the emitting and duration of a level phase used for the emitting that are in the plurality of control periods. The anode reset circuit may control, based on the anode reset control signal, whether the plurality of control periods are used for anode reset.

[0089] In Embodiment 1 of this application, the pixel circuit uses a non-uniform duty cycle configuration in each control period, to ensure that pixels can normally emit in low level phases. In this way, emitting yields of the low level phases are the same or close, to ensure that emitting is uniform in a plurality of low level phases in a same display period.

[0090] In some embodiments, the solution provided in Embodiment 1 may be applied to a scenario in which a screen brightness value is less than a first brightness threshold. For example, the first brightness threshold is 90 nits. To be specific, the solution provided in Embodiment 1 may be applied to a medium and low brightness scenario. A specific value of the first brightness threshold is not specifically limited.

[0091] In some embodiments, duration of the plurality of control periods included in the display period of the pixel circuit is the same, and each of the plurality of control periods includes a first level phase and a second level phase. In other words, each control period includes the first level phase and the second level phase. The first level phase is a level phase used for the anode reset, and the second level phase is a level phase used for the emitting. In Embodiment 1 of this application, duration of second level phases in the plurality of control periods may be configured based on a control period (for example, a first control period) used for the anode reset in the plurality of control periods, and the emitting is controlled based on duration of the first level phases and the duration of the second level phases that are used in the plurality of control periods.

[0092] In some embodiments, the first level phase is a high level phase and the second level phase is a low level phase. Alternatively, the first level phase is a low level phase, and the second level phase is a high level phase. This is not limited in this embodiment of this application. In the following embodiment, an example in which the first level phase is the high level phase and the second level phase is the low level phase is used.

[0093] In a possible implementation, the first control period may include at least one control period, and the second control period may include at least one control period. In other words, there may be one or more first control periods, and one or more second control periods. The first control period is used for the anode reset, and the second control period is not used for the anode reset. In view of this, a similar operation of configuring the duration of the second level phase may be performed for each first control period and each second control period. For example, duration of the second level phase in each first control period and duration of the second level phase in each second control period may be configured based on each first control period, and the emitting is controlled based on duration of first level phases and duration of second level phases in the plurality of control periods (including each first control period and each second control period). For example, the duration of the second level phase in the first control period may be configured as first duration, and the duration of the second level phase in the second control period may be configured as second duration, to enable the first duration to be greater than the second duration. In view of this, duration of an initial second level phase after the anode reset may be greater than duration of a second level phase, in the control period, in which the anode reset is not performed, to ensure that duration of each second level phase is sufficient for charging components such as an EL capacitor and an anode of the pixel circuit and maintaining a sufficient emitting yield, and that emitting yields of the second level phases are the same or close.

[0094] For example, an example is used, where emitting control is performed based on an EM control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 120 Hz, a display period of a frame of picture includes 12 EM periods, the first level phase is the high level phase, and the second level phase is the low level phase. A diagram of the EM control signal and emitting effect of pixels may be shown in FIG. 5. 12 EM periods (an EM period 1, an EM period 2, ..., and an EM period 12 shown in FIG. 5) shown in FIG. 5 each include a high level phase and a low level phase. For example, based on timing, the EM control signal separately includes a high level phase 1, a low level phase 1, a high level phase 2, a low level phase 2, a high level phase 3, a low level phase 3, ..., a high level phase 12, and a low level phase 12 shown in FIG. 5. As shown in FIG. 5, in comparison with duration (that is, the second duration described above) of a low level phase in another EM period (for example, the second control period described above), duration (that is, the first duration described above) of a low level phase in an EM period 1 (that is, the first control period described above) used to perform the anode reset is longer. Therefore, after completing the anode reset, the electronic device may switch to the low level phase in advance to start to charge the components such as the EL capacitor and the anode of the pixel circuit. In this way, it is ensured that an emitting yield of the pixels in an initial low level phase is equal to or close to an emitting yield of the pixels in another low level phase.

[0095] In an example, for the first duration, in comparison with duration (denoted as "duration min") of a low level phase in a control period with shortest duration of the low level phase in the display period, the following relationship is met: (first duration - duration min) / duration min> (or ≥) first preset threshold. For example, the first preset threshold is a value in 10% to 100%, for example, 60%. Certainly, a specific first preset threshold is not limited in this embodiment of this application, and is determined based on a specific case during actual application.

[0096] In some embodiments, the first control period includes one second level phase. In this case, the first duration is duration of the second level phase in the first control period.

[0097] In some embodiments, the first control period includes a plurality of second level phases. In this case, the first duration includes total duration (that is, a sum of duration) of the plurality of second level phases in the first control period.

[0098] For example, an example is used, where emitting control is performed based on an EM control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 120 Hz, a display period of a frame of picture includes 12 EM periods, the first level phase is the high level phase, and the second level phase is the low level phase. A diagram of emitting effect of pixels driven by the EM control signal may be shown in FIG. 6. 12 EM periods (an EM period 1, an EM period 2, ..., and an EM period 12 shown in FIG. 6) each include a high level phase and a low level phase (for ease of reading, high level phases and low level phases are not shown in FIG. 6, and reference may be made to FIG. 5 for this). As shown in FIG. 6, in comparison with duration (that is, the second duration described above) of a low level phase in another EM period (for example, the second control period described above), an EM period 1 (that is, the first control period described above) used to perform anode reset has two low level phases, and total duration (that is, the first duration described above) of the two low level phases is longer. Therefore, in the EM period 1 (that is, the first control period described above), after completing the anode reset, the electronic device may switch to the low level phase in advance to start to charge the components such as the EL capacitor and the anode of the pixel circuit, and start to emit when entering a next low level phase in the same EM period. In this way, it is ensured that an emitting yield of the pixels in an initial emitting phase is equal to or close to an emitting yield of the pixels in another low level phase.

[0099] In addition, it should be noted that, in the examples shown in FIG. 5 and FIG. 6 in this application, an example in which the anode reset is performed in one display period for only one time is used. During actual application, the solution provided in this embodiment of this application is also applicable to a case in which the anode reset is performed for a plurality of times (for example, two or three times, where a quantity is not limited) in one display period. In other words, one display period may include a plurality of first control periods, and duration of second level phases in a plurality of first control periods used for the anode reset may be configured according to the solution provided in this application.

[0100] For example, an example is used, where emitting control is performed based on an EM control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 360 Hz, a display period of a frame of picture includes 12 EM periods, the first level phase is the high level phase, and the second level phase is the low level phase. A diagram of emitting effect of pixels driven by the EM control signal may be shown in FIG. 7. 12 EM periods (an EM period 1, an EM period 2, ..., and an EM period 3 shown in FIG. 7) each include a high level phase and a low level phase (for ease of reading, high level phases and low level phases are not shown in FIG. 7, and reference may be made to FIG. 5 for this). As shown in FIG. 7, in comparison with duration (that is, the second duration described above) of a low level phase in another EM period (for example, the second control period described above), duration (that is, the first duration described above) of low level phases in an EM period 1, an EM period 5, and an EM period 9 (that is, the plurality of first control periods described above) that are used to perform the anode reset is longer. Therefore, after completing the anode reset each time, the electronic device may switch to the low level phase in advance to start to charge the components such as the EL capacitor and the anode of the pixel circuit. In this way, it is ensured that an emitting yield of the pixels in an initial low level phase after the anode reset performed each time is equal to or close to an emitting yield of the pixels in another low level phase.

[0101] For another example, an example is used, where emitting control is performed based on an EM control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 360 Hz, a display period of a frame of picture includes 12 EM periods, the first level phase is the high level phase, and the second level phase is the low level phase. A diagram of emitting effect of pixels driven by the EM control signal may be shown in FIG. 8. 12 EM periods (an EM period 1, an EM period 2, ..., and an EM period 12 shown in FIG. 8) each include a high level phase and a low level phase (for ease of reading, high level phases and low level phases are not shown in FIG. 8, and reference may be made to FIG. 5). As shown in FIG. 8, in comparison with duration (that is, the second duration described above) of a low level phase in another EM period (for example, the second control period described above), an EM period 1, an EM period 5, and an EM period 9 (that is, the first control periods described above) that are used to perform the anode reset each have two low level phases, and total duration (that is, the first duration described above) of the two low level phases in each period is longer. Therefore, after completing the anode reset each time, the electronic device may switch to the low level phase in advance to start to charge the components such as the EL capacitor and the anode of the pixel circuit, and start to emit when entering a next low level phase. In this way, it is ensured that an emitting yield of the pixels in an initial emitting phase after the anode reset performed each time is equal to or close to an emitting yield of the pixels in another low level phase.

[0102] In addition, it should be noted that, in the examples shown in FIG. 5 and FIG. 6 in this application, only duration of the initial emitting phase (that is, the second level phase) after the anode reset is used as an example. During actual application, for one or more other emitting phases after the anode reset, the method provided in this embodiment of this application may also be used to ensure an emitting yield of the one or more other emitting phases.

[0103] In a possible implementation, duration of a second level phase in a third control period may be configured as third duration, so that the third duration is greater than the second duration, and the third control period is not used for the anode reset. In an example, the third control period may be a control period after the first control period, for example, an initial control period after the first control period. In view of this, it can be ensured that a 2 nd< second level phase after the anode reset has a sufficient emitting yield, and emitting yields of the second level phases are the same or close.

[0104] In an example, the third control period may include at least one control period, that is, there may be one or more third control periods. In view of this, a similar operation of configuring the duration of the second level phase may be performed for each third control period. For example, duration of the second level phase in each third control period may be configured based on the first control period, and the emitting is controlled based on duration of first level phases and duration of second level phases in the plurality of control periods (including each third control period).

[0105] In an example, the third duration is less than or equal to the first duration.

[0106] For example, an example is used, where emitting control is performed based on an EM control signal under a screen brightness value of 2 nits, 1440 Hz PWM dimming is used for the EM control signal, a displaying refresh rate is 120 Hz, an anode reset frequency is 120 Hz, a display period of a frame of picture includes 12 EM periods, the first level phase is the high level phase, and the second level phase is the low level phase. A diagram of emitting effect of pixels driven by the EM control signal may be shown in FIG. 9. 12 EM periods (an EM period 1, an EM period 2, ..., and an EM period 12 shown in FIG. 9) each include a high level phase and a low level phase (for ease of reading, high level phases and low level phases are not shown in FIG. 9, and reference may be made to FIG. 5 for this). As shown in FIG. 9, in comparison with duration (that is, the second duration described above) of a low level phase in another EM period (for example, the second control period described above), duration (that is, the third duration described above) of low level phases in an EM period 1 (that is, the first control period described above) used to perform the anode reset and an EM period 1 (that is, the third control period described above) after the EM period 1 is longer. Therefore, after completing the anode reset, the electronic device may switch to the low level phase in advance to start to charge the components such as the EL capacitor and the anode of the pixel circuit. In this way, an emitting yield of the pixels in an initial low level phase after the anode reset is equal to or close to an emitting yield of the pixels in another low level phase. In addition, as shown in FIG. 9, the electronic device may enter a 2 nd< low level phase after the anode reset in advance to perform emitting compensation. In this way, it is ensured that an emitting yield in the phase is equal to or close to the emitting yield of the pixels in the another low level phase.

[0107] In some embodiments, in the example shown in FIG. 9, duration of a low level phase (that is, a low level phase 1) in the EM period 1 may be the same as or different from duration of a low level phase (that is, a low level phase 2) in the EM period 2. The rest may be deduced by analogy.

[0108] It should be noted that, in the examples shown in FIG. 5, FIG. 6, and FIG. 9 of this application, the three possible diagrams of the emitting effect of the EM control signals driving the pixels are described by using only an example in which the 1440 Hz PWM dimming is used for the EM control signals, the displaying refresh rate is 120 Hz, the anode reset frequency is 120 Hz, and the display period, of the frame of picture, includes the 12 EM periods. In the examples shown in FIG. 7 and FIG. 8 of this application, the two possible diagrams of the emitting effect of the EM control signals driving the pixels are described by using only an example in which the 1440 Hz PWM dimming is used for the EM control signals, the displaying refresh rate is 120 Hz, the anode reset frequency is 360 Hz, and the display period, of the frame of picture, includes the 12 EM periods. During actual application, a specific type of the emitting control signal, the dimming frequency of the emitting control signal, the displaying refresh rate, the anode reset frequency, and the like are not specifically limited, which are determined based on actual cases such as a type, structure, or material of an actual display.

[0109] It may be understood that, according to the solution provided in Embodiment 1 of this application, the electronic device flexibly uses the non-uniform duty cycle configuration in each control period in the display period, for example, enables duration of low level phases in some control periods with insufficient brightness to be greater than duration of the another low level phase, to ensure that the pixels of the display can keep normally emitting at each low level phase. In this way, the emitting yields of the low level phases are the same or close, to ensure that the emitting is uniform in the plurality of low level phases in the same display period.

[0110] For example, in comparison with the EM control signal shown in FIG. 2, duration of the initial low level phases after the anode reset in the EM control signals shown in FIG. 5 and FIG. 7 is greater than that of the another low level phase. Therefore, after the charging of the components such as the EL capacitor and the anode of the pixel circuit is completed, there is sufficient low level duration to ensure that the emitting yields of the pixels in the phases are equal to or close to the emitting yield of the pixels in the another low level phase. In view of this, in comparison with the display effect shown in FIG. 2, as shown in FIG. 5 and FIG. 7, in the initial low level phases after the anode reset, the pixels of the display emit normally with emitting effect being basically consistent with that of another low level phase in a same display period.

[0111] For another example, in comparison with the EM control signal shown in FIG. 2, the initial low level phases after the anode reset in the EM control signals shown in FIG. 6 and FIG. 8 are used to charge the components such as the EL capacitor and the anode of the pixel circuit, and the original initial low level phase after the anode reset is used to emit. Therefore, after the charging of the components such as the EL capacitor and the anode of the pixel circuit is completed, there is sufficient low level duration to ensure that the emitting yields of the pixels in the phases are equal to or close to the emitting yield of the pixels in the another low level phase. In view of this, in comparison with the display effect shown in FIG. 2, the pixels of the display in the first EM period shown in FIG. 6 normally emit with emitting effect being basically consistent with that of another low level phase in a same display period, and the pixels of the display in the first EM period, the fifth EM period, and the ninth EM period shown in FIG. 8 normally emit with emitting effect being basically consistent with that of another low level phase in a same display period.

[0112] For another example, in comparison with the EM control signal shown in FIG. 2, duration of the initial low level phase and the 2 nd< low level phase after the anode reset in the EM control signal shown in FIG. 9 is greater than that of the another low level phase. Therefore, after the charging of the components such as the EL capacitor and the anode of the pixel circuit is completed, there is sufficient low level duration to ensure that the emitting yield of the pixels in the initial low level phase is equal to or close to the emitting yield of the pixels in the another low level phase, and entering, in advance, the 2 nd< low level phase after the anode reset can ensure that an emitting yield in the 2 nd< low level phase is equal to or close to the emitting yield of the pixels in the another low level phase. In view of this, in comparison with the display effect shown in FIG. 2, as shown in FIG. 9, in the initial low level phase and the 2 nd< low level phase after the anode reset, the pixels of the display emit normally with emitting effect being basically consistent with that of another low level phase in a same picture frame.Embodiment 2:

[0113] In Embodiment 2, when an electronic device displays a picture frame based on the pixel circuit, a display period of one picture frame usually includes a plurality of consecutive control periods. The pixel circuit includes an emitting control circuit and a reset circuit (for example, a source reset circuit or a drain reset circuit of a driving thin film transistor (driving thin film transistor, DTFT)). The emitting control circuit is configured to receive an emitting control signal, for example, an EM control signal. The reset circuit is configured to receive a reset control signal, for example, the source reset circuit is configured to receive a source reset control signal, and the drain reset circuit is configured to receive a drain reset control signal. In other words, the pixel circuit may receive the EM control signal, and control emitting based on duration of a level phase not used for the emitting and duration of a level phase used for the emitting that are in the plurality of control periods. The reset circuit may control, based on the reset control signal, whether the plurality of control periods are used for reset, for example, control, based on the source reset control signal, whether the plurality of control periods are used for source reset, or control, based on the drain reset control signal, whether the plurality of control periods are used for drain reset.

[0114] In some embodiments, duration of the plurality of control periods included in the display period of the pixel circuit is the same, and each of the plurality of control periods includes a first level phase and a second level phase. In other words, each control period includes the first level phase and the second level phase. The first level phase is a level phase used for the reset (for example, used in the source reset circuit or the drain reset circuit), and the second level phase is a level phase used for the emitting.

[0115] In some embodiments, the first level phase is a high level phase and the second level phase is a low level phase. Alternatively, the first level phase is a low level phase, and the second level phase is a high level phase. This is not limited in this embodiment of this application. In the following embodiment, an example in which the first level phase is the high level phase and the second level phase is the low level phase is used.

[0116] In Embodiment of this application, the electronic device configures duration of first level phases in the plurality of control periods in the display period based on a reset frequency corresponding to the reset control signal and / or a displaying refresh rate corresponding to the emitting control signal, and the emitting is controlled based on the duration of the first level phases and duration of second level phases in the plurality of control periods.

[0117] In an example, the plurality of control periods include a refresh frame period and a holding frame period. For example, there may be one refresh frame period, and there may be one or more holding frame periods. The refresh frame period is used for displaying refresh and gate reset, and the holding frame period is used for display holding. The electronic device may perform, in a refresh frame period and each holding frame period (in a case in which there are a plurality of holding frame periods) in the display period of the picture frame, differentiated driving based on the reset frequency corresponding to the reset control signal and / or the displaying refresh rate corresponding to the emitting control signal, for example, adjust duration of a first level phase in each holding frame period based on different reset frequencies and / or different refresh rates.

[0118] After adjusting the duration of the first level phase in each holding frame period, the electronic device may perform the displaying refresh and the reset when entering a first level phase in the refresh frame period, and control the emitting based on the duration of the first level phases and the duration of the second level phases in the plurality of control periods (including the refresh frame period and the holding frame period). For example, the electronic device does not emit when entering the first level phase in the refresh frame period, the electronic device emits when entering a second level phase in the refresh frame period, the electronic device does not emit when entering the first level phase in the holding frame period, and the electronic device emits when entering a second level phase in the holding frame period.

[0119] In some examples, the plurality of control periods include the refresh frame period but do not include the holding frame period. In this case, the electronic device may set only the duration of the first level phase in the refresh frame period.

[0120] For example, in Embodiment 2, the duration of the first level phase (for example, the high level phase) in the holding frame period in the display period may be reduced based on the different reset frequencies and / or the different displaying refresh rates, so that duty cycles at the different displaying refresh rates and / or the different reset frequencies are maintained at high levels to optimize screen flickering, and the duty cycles at the different displaying refresh rates and / or the different reset frequencies are basically equivalent (for example, a difference is less than a preset threshold), to achieve better display and eye comfort effect.

[0121] In some embodiments, the solution provided in Embodiment 2 may be applied to a scenario in which a screen brightness value is greater than a second brightness threshold. The second brightness threshold is greater than a first brightness threshold. For example, the second brightness threshold is 90 nits. To be specific, the solution provided in Embodiment 2 may be applied to a high brightness scenario. A specific value of the second brightness threshold is not specifically limited.

[0122] It may be understood that, for example, the emitting control signal is an EM control signal, and a display period of one picture frame usually includes a plurality of EM periods. For example, a quantity N of EM periods included in one display period is equal to F1 / F2. 1 EM period is a refresh frame period, N-1 EM periods are holding frame periods, F1 is a source reset frequency or a drain reset frequency, and F2 is a displaying refresh rate. The displaying refresh, the gate reset, the source reset / drain reset, threshold compensation, and the like are generally performed in the refresh frame period in the display period. The displaying refresh, the gate reset, the source reset / drain reset, the threshold compensation, and the like are generally not performed in the holding frame period in the display period.

[0123] For example, the source reset frequency or the drain reset frequency is 360 Hz, and the displaying refresh rate is 120 Hz. N=360 Hz / 120 Hz=3, that is, a display period of one picture frame includes 3 EM periods. A 1 st< EM period is a refresh frame period, and the other 2 EM periods are holding frame periods. For example, the source reset frequency or the drain reset frequency is 360 Hz, and the displaying refresh rate is 60 Hz. N=360 Hz / 60 Hz=6, that is, a display period of one picture frame includes 6 EM periods. A 1 st< EM period is a refresh frame period, and the other 5 EM periods are holding frame periods. The rest may be deduced by analogy. For example, the source reset frequency or the drain reset frequency is 360 Hz, and the displaying refresh rate is 1 Hz. N=360 Hz / 1 Hz=360, that is, a display period of one picture frame includes 360 EM periods. A 1 st< EM period is a refresh frame period, and the other 359 EM periods are holding frame periods.

[0124] For example, the source reset frequency or the drain reset frequency is 240 Hz, and the displaying refresh rate is 120 Hz. N=240 Hz / 120 Hz=2, that is, a display period of one picture frame includes 2 EM periods. A 1 st< EM period is a refresh frame period, and a 2 nd< EM period is a holding frame period. For example, the source reset frequency or the drain reset frequency is 240 Hz, and the displaying refresh rate is 60 Hz. N=240 Hz / 60 Hz=4, that is, a display period of one picture frame includes 4 EM periods. A 1 st< EM period is a refresh frame period, and the other 3 EM periods are holding frame periods. The rest may be deduced by analogy. For example, the source reset frequency or the drain reset frequency is 240 Hz, and the displaying refresh rate is 1 Hz. N=240 Hz / 1 Hz=240, that is, a display period of one picture frame includes 240 EM periods. A 1 st< EM period is a refresh frame period, and the other 239 EM periods are holding frame periods.

[0125] It should be noted that whether the display period includes the holding frame period is not limited in this embodiment of this application. In some cases, the display period of the picture frame may not include the holding frame period.

[0126] For example, the source reset frequency or the drain reset frequency is 120 Hz, and the displaying refresh rate is 120 Hz. N=120 Hz / 120 Hz=1, that is, a display period of one picture frame includes 1 EM period. The 1 EM period is a refresh frame period. For example, the source reset frequency or the drain reset frequency is 120 Hz, and the displaying refresh rate is 60 Hz. N=120 Hz / 60 Hz=2, that is, a display period of one picture frame includes 2 EM periods. A 1 st< EM period is a refresh frame period, and a 2 nd< EM period is a holding frame period. The rest may be deduced by analogy. For example, the source reset frequency or the drain reset frequency is 120 Hz, and the displaying refresh rate is 1 Hz. N=120 Hz / 1 Hz=120, that is, a display period of one picture frame includes 120 EM periods. A 1 st< EM period is a refresh frame period, and the other 119 EM periods are holding frame periods.

[0127] In a conventional method, duration of a first level phase (for example, a high level phase) in a refresh frame period is generally consistent with duration of a first level phase in a holding frame period, and duration of a second level phase (for example, a low level phase) in the refresh frame period is also generally consistent with duration of a second level phase in the holding frame period, to ensure that duration in which a display emits in the refresh frame period is consistent with duration in which the display emits in the holding frame period, thereby achieving uniform dimming effect. However, in the conventional method, long time is required for performing displaying refresh, gate reset, source reset / drain reset, threshold compensation, and the like in the refresh frame period. As a result, total screen-on duration of a display period is shortened, and SVM is increased, that is, picture flickers are excessively strong.

[0128] To resolve the foregoing problem, in some embodiments, the electronic device may configure the duration of the first level phase (for example, the high level phase) in the refresh frame period and the duration of the first level phase in the holding frame period, so that the duration of the first level phase in the holding frame period is less than the duration of the first level phase in the refresh frame period, and total duration of second level phases in display periods at the different displaying refresh rates / reset frequencies is equal or close. It may be understood that, after the duration of the first level phase in the holding frame period is reduced, correspondingly, the duration of the second level phase in the holding frame period is increased, so that total screen-on duration of the display period can be increased, thereby reducing the SVM, optimizing the screen flickering, and achieving the better display and eye comfort effect.

[0129] In an example, the electronic device may configure the duration of the first level phase in the refresh frame period in the display period as fourth duration, and configure the duration of the first level phase in the holding frame period as fifth duration. The fifth duration is less than the fourth duration. For example, the fourth duration is 80H, and the fifth duration is a value between 36H and 75H. In some embodiments, a difference between the fourth duration and the fifth duration is greater than or equal to 1H.

[0130] For example, the first level phase is the high level phase, and the second level phase is the low level phase. In some embodiments, a decrease in the duration of the high level phase in the holding frame period compared with the duration of the high level phase in the refresh frame period may be related to one or more of the following factors: a specific attribute of the display, the displaying refresh rate, the source reset frequency, the drain reset frequency, or the like. For example, the specific attribute of the display is a type, structure, or material of a display panel. The displaying refresh rate is 120 Hz, 60 Hz, or 1 Hz, and is not limited. The source reset frequency or the drain reset frequency is, for example, 120 Hz, 240 Hz, or 360 Hz, and is not limited.

[0131] In some embodiments, when other factors such as the screen brightness value, the specific attribute of the display, and the reset frequency remain unchanged, adjustment amplitude of adjusting the duration of the first level phase in the holding frame period varies with the displaying refresh rate.

[0132] In an example, when the other factors such as the screen brightness value, the specific attribute of the display, and the reset frequency remain unchanged, duration of a high level phase in a refresh frame period whose displaying refresh rate is a first refresh rate is the fourth duration, and the duration of the high level phase in the holding frame period is fifth duration; and duration of a high level phase in a refresh frame period whose displaying refresh rate is a second refresh rate is the fourth duration, and the duration of the high level phase in the holding frame period is sixth duration. The first refresh rate is greater than the second refresh rate, the sixth duration is greater than the fifth duration, and the fifth duration and the sixth duration are values between 36H and 75H.

[0133] When the other factors such as the screen brightness value, the specific attribute of the display, and the displaying refresh rate remain unchanged, adjustment amplitude of adjusting the duration of the first level phase in the holding frame period varies with the reset frequency.

[0134] In an example, when the other factors such as the screen brightness value, the specific attribute of the display, and the displaying refresh rate remain unchanged, duration of a high level phase in a refresh frame period whose reset frequency is a first frequency is the fourth duration, and the duration of the high level phase in the holding frame period is seventh duration; and duration of a high level phase in a refresh frame period whose reset frequency is a second frequency is the fourth duration, and the duration of the high level phase in the holding frame period is eighth duration. The first frequency is greater than the second frequency, the eighth duration is less than the fourth duration, the ninth duration is less than the fourth duration, the eighth duration is different from the ninth duration, and the eighth duration and the ninth duration are values between 36H and 75H. In an example, the eighth duration is less than or equal to the ninth duration.

[0135] For example, when the screen brightness value is 500 nits, the 1440 Hz PWM dimming is used for the EM control signal, the reset frequency is 360 Hz, the first level phase is the high level phase, the second level phase is the low level phase, and the duration of the high level phase in the refresh frame period is 80H, duration of high level phases in refresh frame periods and holding frame periods at the different displaying refresh rates may be shown in the following Table 1: Table 1Reset frequencyDisplaying refresh rateDuration of a high level phaseDuty cycleRefresh frame periodHolding frame period120 Hz80H36H95.13%360 Hz60 Hz80H45H95.11%1 Hz80H50H95.18%

[0136] For example, when the screen brightness value is 500 nits, the 1440 Hz PWM dimming is used for the EM control signal, the reset frequency is 240 Hz, the first level phase is the high level phase, the second level phase is the low level phase, and the duration of the high level phase in the refresh frame period is 80H, duration of high level phases in refresh frame periods and holding frame periods at the different displaying refresh rates may be shown in the following Table 2: Table 2Reset frequencyDisplaying refresh rateDuration of a high level phaseDuty cycleRefresh frame periodHolding frame period120 Hz80H36H96.28%240 Hz60 Hz80H51H96.27%1 Hz80H58H96.28%

[0137] For example, when the screen brightness value is 500 nits, the 1440 Hz PWM dimming is used for the EM control signal, the reset frequency is 120 Hz, the first level phase is the high level phase, the second level phase is the low level phase, and the duration of the high level phase in the refresh frame period is 80H, duration of high level phases in refresh frame periods and holding frame periods at the different displaying refresh rates may be shown in the following Table 3: Table 3Reset frequencyDisplaying refresh rateDuration of a high level phaseDuty cycleRefresh frame periodHolding frame period120 Hz80HNo holding frame period97.44%120 Hz60 Hz80H70H97.60%1 Hz80H75H97.59%

[0138] It should be noted that Table 1, Table 2, and Table 3 are merely used as example values of dynamic adjustment of the holding frame periods at the different reset frequencies and displaying refresh rates. During actual application, an adjustment amplitude of the holding frame period may be another difference compared with the refresh frame period. This is not specifically limited in this embodiment of this application, and is determined based on a specific case.

[0139] In addition, Table 1, Table 2, and Table 3 respectively show the example values of the dynamic adjustment of the holding frame periods when the reset frequencies are: 360 Hz, 240 Hz, and 120 Hz and the displaying refresh rates are: 120 Hz, 60 Hz, and 1 Hz. During actual application, the reset frequencies may alternatively be other frequencies such as 480 Hz, 600 Hz, and 720 Hz, and the displaying refresh rates may alternatively be other values such as 180 Hz and 240 Hz. This is not specifically limited in this embodiment of this application, and is determined based on a specific case.

[0140] It may be understood that, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, in comparison with the holding frame period in which the operations such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation do not need to be performed, the duration of the high level phase in the refresh frame period in which the operations such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation need to be performed is longer. In view of this, the displaying refresh, the gate reset, the source reset / drain reset, the threshold compensation, and the like can be ensured to be normally performed in the refresh frame period, and high and equivalent duty cycles can be maintained at the different displaying refresh rates and / or the different reset frequencies, to optimize the SVM and achieve good high brightness display effect. For example, in comparison with a solution similar to that in which the duration of the high level phases in the EM periods in the display period shown in FIG. 3 is equal, a higher duty cycle can be achieved according to the solution provided in Embodiment 2 of this application. In addition, in the solution provided in Embodiment 2 of this application, differentiated configuration is performed for the duration of the high level phase in the refresh frame period and the duration of the high level phase in the holding frame period, so that a difference between duty cycles of the display periods at the different reset frequencies and / or the different displaying refresh rates is maintained within a range less than 0.2%.

[0141] For example, FIG. 10 shows a driving principle diagram of an EM drive signal according to an embodiment of this application by using the solution shown in Table 1 as an example. For example, the source reset frequency or the drain reset frequency is 360 Hz. As shown in FIG. 10, when the displaying refresh rate is 120 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 3 (that is, N=360 Hz / 120 Hz=3) EM periods. 1 EM period is a refresh frame period, and the other 2 (that is, N-1=2) EM periods are holding frame periods. When the displaying refresh rate is 60 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 6 (that is, N=360 Hz / 60 Hz=6) EM periods. 1 EM period is a refresh frame period, and the other 5 (that is, N-1=5) EM periods are holding frame periods. When the displaying refresh rate is 1 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 360 (that is, N=360 Hz / 1 Hz=360) EM periods. 1 EM period is a refresh frame period, and the other 359 (that is, N-1=359) EM periods are holding frame periods. Because no gate reset, source reset / drain reset, threshold compensation, and the like are performed in the holding frame period, it is not necessary to maintain the duration of the high level phase in the holding frame period consistent with the duration of the high level phase in the refresh frame period. As shown in FIG. 10, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, in comparison with the holding frame period in which the operations such as the displaying refresh, the gate reset, and the source reset / drain reset do not need to be performed, the duration of the high level phase in the refresh frame period in which the operations such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation need to be performed is longer. In view of this, the displaying refresh, the gate reset, the source reset / drain reset, the threshold compensation, and the like can be ensured to be normally performed in the refresh frame period, and the differentiated configuration can be performed for the duration of the high level phase in the refresh frame period and the duration of the high level phase in the holding frame period, so that the difference between the duty cycles of the display periods at the different displaying refresh rates in a case in which the source reset frequency or the drain reset frequency is 360 Hz can be maintained within a very small range.

[0142] In an example, a duty cycle r of the display period may be calculated according to the following formula: r=[120 / F2*row quantity of emitting arrays-first duration-second duration*(F1 / F2-1)] / (120 / F2*row quantity of emitting arrays). F1 is the source reset frequency or the drain reset frequency, F2 is the displaying refresh rate, and the row quantity of emitting arrays is, for example, a row quantity of screen emitting arrays. Alternatively, in a case in which the display includes a front-and-rear porch emitting array, row quantity of emitting arrays=row quantity of screen emitting arrays+row quantity of front-and-rear porch emitting arrays.

[0143] As shown in Table 1, an example in which the row quantity of emitting arrays is 3120 is used. When the source reset frequency or the drain reset frequency is 360 Hz, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, a duty cycle of the display is 95.13% when the displaying refresh rate is 120 Hz, the duty cycle of the display is 95.11% when the displaying refresh rate is 60 Hz, and the duty cycle of the display is 95.18% when the displaying refresh rate is 1 Hz. The duty cycle may be maintained between 95.1% and 95.2%, which is greatly improved in comparison with the duty cycle (for example, 94%) in the solution similar to that shown in FIG. 3. Because the high brightness scenario has a high requirement on the brightness value, a high duty cycle can be maintained according to the solution shown in Table 1, to optimize the SVM and achieve the good high brightness display effect. In addition, as shown in Table 1, the difference between the duty cycles of the display periods at the different displaying refresh rates is maintained within the range less than 0.2%. Therefore, it can be ensured that when the displaying refresh rate changes, overall picture display effect is not greatly different for a user.

[0144] For another example, FIG. 11 shows an emitting control principle diagram of an EM control signal according to an embodiment of this application by using the solution shown in Table 2 as an example. For example, the source reset frequency or the drain reset frequency is 240 Hz. As shown in FIG. 11, when the displaying refresh rate is 120 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 2 (that is, N=240 Hz / 120 Hz=2) EM periods. 1 EM period is a refresh frame period, and the other 1 (that is, N-1=1) EM period is a holding frame period. When the displaying refresh rate is 60 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 4 (that is, N=240 Hz / 60 Hz=4) EM periods. 1 EM period is a refresh frame period, and the other 3 (that is, N-1=3) EM periods are holding frame periods. When the displaying refresh rate is 1 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 240 (that is, N=240 Hz / 1 Hz=240) EM periods. 1 EM period is a refresh frame period, and the other 239 (that is, N-1=239) EM periods are holding frame periods. Because no gate reset, source reset / drain reset, threshold compensation, and the like are performed in the holding frame period, it is not necessary to maintain the duration of the high level phase in the holding frame period consistent with the duration of the high level phase in the refresh frame period. As shown in FIG. 11, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, in comparison with the holding frame period in which the tasks such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation do not need to be performed, the duration of the high level phase in the refresh frame period in which the tasks such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation need to be performed is longer. In view of this, the displaying refresh, the gate reset, the source reset / drain reset, the threshold compensation, and the like can be ensured to be normally performed in the refresh frame period, and the differentiated configuration can be performed for the duration of the high level phase in the refresh frame period and the duration of the high level phase in the holding frame period, so that the difference between the duty cycles of the display periods at the different displaying refresh rates in a case in which the source reset frequency or the drain reset frequency is 240 Hz can be maintained within a range less than 0.2%.

[0145] As shown in Table 2, an example in which the row quantity of emitting arrays is 3120 is used. When the source reset frequency or the drain reset frequency is 240 Hz, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, a duty cycle of the display is 96.28% when the displaying refresh rate is 120 Hz, the duty cycle of the display is 96.27% when the displaying refresh rate is 60 Hz, and the duty cycle of the display is 96.28% when the displaying refresh rate is 1 Hz. The duty cycle may be maintained between 96.2% and 96.3%, which is greatly improved in comparison with the duty cycle (for example, 94.9%) in the solution similar to that shown in FIG. 3. Because the high brightness scenario has a high requirement on the brightness value, a high duty cycle can be maintained according to the solution shown in Table 2, to optimize the SVM and achieve the good high brightness display effect. In addition, as shown in Table 2, the difference between the duty cycles of the display periods at the different displaying refresh rates is maintained within the range less than 0.2%. Therefore, it can be ensured that when the displaying refresh rate changes, overall picture display effect is not greatly different for a user.

[0146] For another example, FIG. 12 shows a driving principle diagram of an emitting control signal according to an embodiment of this application by using the solution shown in Table 3 as an example. For example, the source reset frequency or the drain reset frequency is 120 Hz. As shown in FIG. 12, when the displaying refresh rate is 120 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 1 (that is, N=120 Hz / 120 Hz=1) EM period. The EM period is a refresh frame period. When the displaying refresh rate is 60 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 2 (that is, N=120 Hz / 60 Hz=2) EM periods. 1 EM period is a refresh frame period, and the other 1 (that is, N-1=1) EM period is a holding frame period. When the displaying refresh rate is 1 Hz, it may be learned according to the foregoing formula N=F1 / F2 that: a display period of a frame of picture includes 120 (that is, N=120 Hz / 1 Hz=120) EM periods. 1 EM period is a refresh frame period, and the other 119 (that is, N-1=119) EM periods are holding frame periods. Because no gate reset, source reset / drain reset, threshold compensation, and the like are performed in the holding frame period, it is not necessary to maintain the duration of the high level phase in the holding frame period consistent with the duration of the high level phase in the refresh frame period. As shown in FIG. 12, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, in comparison with the holding frame period in which the tasks such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation do not need to be performed, the duration of the high level phase in the refresh frame period in which the tasks such as the displaying refresh, the gate reset, the source reset / drain reset, and the threshold compensation need to be performed is longer. In view of this, the displaying refresh, the gate reset, the source reset / drain reset, the threshold compensation, and the like can be ensured to be normally performed in the refresh frame period, and the differentiated configuration can be performed for the duration of the high level phase in the refresh frame period and the duration of the high level phase in the holding frame period, so that the difference between the duty cycles of the display periods at the different displaying refresh rates in a case in which the source reset frequency or the drain reset frequency is 120 Hz can be maintained within a range less than 0.2%.

[0147] As shown in Table 3, an example in which the row quantity of emitting arrays is 3120 is used. When the source reset frequency or the drain reset frequency is 120 Hz, after the duration of the high level phase in the holding frame period is optimized (for example, shortened) according to the solution provided in Embodiment 2 of this application, a duty cycle of the display is 97.44% when the displaying refresh rate is 120 Hz, the duty cycle of the display is 97.60% when the displaying refresh rate is 60 Hz, and the duty cycle of the display is 97.59% when the displaying refresh rate is 1 Hz. The duty cycle may be maintained between 97.4% and 97.6%, which is greatly improved in comparison with the duty cycle in the solution similar to that shown in FIG. 3. Because the high brightness scenario has a high requirement on the brightness value, a high duty cycle can be maintained according to the solution shown in Table 3, to optimize the SVM and achieve the good high brightness display effect. In addition, as shown in Table 3, the difference between the duty cycles of the display periods at the different displaying refresh rates is maintained within the range less than 0.2%. Therefore, it can be ensured that when the displaying refresh rate changes, overall picture display effect is not greatly different for a user.

[0148] It should be noted that FIG. 10, FIG. 11, and FIG. 12 are only the diagrams of the driving principles of the emitting control signals at the different displaying refresh rates, and different source reset frequencies or different drain reset frequencies by using an example in which the screen brightness value is 500 nits, the 1440 Hz PWM dimming is used for the EM control signals, and the duration of the high level phase in the refresh frame period is 80H. During actual application, the screen brightness value may alternatively be 21 nits, 249 nits, 1200 nits, or another value, a dimming frequency of the EM control signal may alternatively be of another value, and the duration of the high level phase in the refresh frame period may be of another value. This is not limited in this embodiment of this application, and is determined based on a specific case.

[0149] In a possible implementation, a process in which the EM control signal drives the pixel circuit may be divided into the following four phases.

[0150] Phase 1: gate reset (also referred to as "gate initialization") phase.

[0151] The phase 1 is usually performed in the first level phase in the refresh frame period. For example, the first level phase in the refresh frame period is the high level phase, and the second level phase in the refresh frame period is the low level phase. The gate reset phase is usually performed in the high level phase in the refresh frame period.

[0152] In some embodiments, the first level phase may also be used for writing data, for example, interface data of a to-be-displayed picture, to perform the displaying refresh. This is not limited.

[0153] For example, a pixel circuit is shown in FIG. 13, driving timing of a pixel circuit corresponding to a refresh frame period is shown in FIG. 14, the first level phase is the high level phase, and the second level phase is the low level phase. FIG. 14 is a diagram of driving timing of a pixel circuit according to an embodiment of this application. T1 to T8 shown in FIG. 14 are thin film transistors (thin film transistor, TFT). For example, T1 shown in FIG. 14 may be a DTFT, N1 to N3 are nodes in the circuit, C1 is a capacitor, EM is an emitting control signal received by the circuit, S1n to S4n are control signals received by the circuit and used for reset and data writing, ELVDD and ELVSS are operating voltages, Vinitl to Vinit3 are reset voltages, and Vdata is used to control a current flowing through the TFT to drive the pixel circuit to emit light of different brightness. As shown in FIG. 14, in the refresh frame period, EM shown in FIG. 13 is first set to a high level to turn off an emitting path, and S2n and S4n sequentially switch from low levels to high levels, to initialize the N1 node shown in FIG. 13.

[0154] For example, in the refresh frame period, a switching frequency of EM shown in FIG. 13 may be 360 Hz. In this case, the emitting control signal received by emitting control circuits (as shown in FIG. 13, including a circuit that receives the emitting control signal (EM signal) and circuits of the transistors T5 and T6) in the pixel circuit may be shown in FIG. 10. For another example, a switching frequency of EM shown in FIG. 13 may be 240 Hz, and the emitting control signal received by the emitting control circuit may be shown in FIG. 11. For another example, a switching frequency of EM shown in FIG. 13 may be 120 Hz, and the emitting control signal received by the emitting control circuit may be shown in FIG. 12.

[0155] In some embodiments, the switching frequency of EM shown in FIG. 13 may be the same as a drain reset frequency or a source reset frequency. However, this is not limited in this embodiment of this application. For example, in some embodiments, the switching frequency of EM may be different from the drain reset frequency or the source reset frequency, and may be determined based on a specific case.

[0156] Phase 2: threshold compensation and data writing phase.

[0157] The phase 2 is mainly used to perform threshold compensation and data writing for T1. For example, T1 may be a DTFT, and data is brightness data.

[0158] For example, the pixel circuit is shown in FIG. 13, the driving timing of the pixel circuit corresponding to the refresh frame period is shown in FIG. 14, the first level phase is the high level phase, and the second level phase is the low level phase. As shown in FIG. 14, in the refresh frame period, when S2n is set to a high level and S1n is set to a low level, a threshold of T1 shown in FIG. 13 is compensated, and brightness data is written. In this case, Vdata enters the node N3 through T2, flows to node T2 through T1, and is written into the node N1 through T3. The threshold of T1 is compensated in a process in which Vdata flows through T1, and a voltage corresponding to brightness indicated by the brightness data is written into a gate of T1, that is, the N1 node, to control a current flowing through T1 after EM is turned on subsequently, to accurately emit.

[0159] Phase 3: Drain and anode reset phase.

[0160] For example, the pixel circuit is shown in FIG. 13, the driving timing of the pixel circuit corresponding to the refresh frame period is shown in FIG. 14, the first level phase is the high level phase, and the second level phase is the low level phase. As shown in FIG. 14, in the refresh frame period, the N2 node shown in FIG. 13 is reset when S3n is set to a low level.

[0161] For example, a switching frequency of S3n shown in FIG. 13 may be kept at 360 Hz, that is, a reset frequency of the N2 node is 360 Hz. In this case, the emitting control signal received by the emitting control circuit may be shown in FIG. 10. For another example, a switching frequency of S3n shown in FIG. 13 may be kept at 240 Hz, that is, a reset frequency of the N2 node is 240 Hz. In this case, the emitting control signal received by the emitting control circuit may be shown in FIG. 11. For another example, a switching frequency of S3n shown in FIG. 13 may be kept at 120 Hz, that is, a reset frequency of the N2 node is 120 Hz. In this case, the emitting control signal received by the emitting control circuit may be shown in FIG. 12. In this embodiment of this application, when S3n is set to a low level, the anode reset is performed on the circuit shown in FIG. 13. The anode reset and the N2 node have consistent reset frequencies, where for example, the reset frequencies are 360 Hz. For example, voltage values of Vinit2 and Vinit3 shown in FIG. 13 may be set based on different brightness and different frequencies, to implement the reset of the N2 node and the anode reset.

[0162] Phase 4: emitting phase.

[0163] The phase 4 is usually performed in the second level phase in the refresh frame period. For example, the first level phase in the refresh frame period is the high level phase, the second level phase in the refresh frame period is the low level phase, and the pixels emit in the low level phase. The emitting phase is usually performed in the low level phase.

[0164] For example, the pixel circuit is shown in FIG. 13, the driving timing of the pixel circuit corresponding to the refresh frame period is shown in FIG. 14, the first level phase is the high level phase, and the second level phase is the low level phase. As shown in FIG. 14, in the refresh frame period, EM is set to a low level to turn on T5 and T6 shown in FIG. 13, and the pixels emit.

[0165] For example, in the refresh frame period, the switching frequency of EM shown in FIG. 13 is the same as the drain reset frequency, for example, 360 Hz. The emitting control signal received by the emitting control circuit may be shown in FIG. 10. For another example, the switching frequency of EM shown in FIG. 13 is the same as the drain reset frequency, for example, 240 Hz. The emitting control signal received by the emitting control circuit may be shown in FIG. 11. For another example, the switching frequency of EM shown in FIG. 13 is the same as the drain reset frequency, for example, 120 Hz. The emitting control signal received by the emitting control circuit may be shown in FIG. 12.

[0166] It should be noted that FIG. 13 is merely an example of a pixel circuit. During actual application, another type of pixel circuit may be used. In addition, in FIG. 14, only the pixel circuit shown in FIG. 13 is used as an example to describe possible driving timing of a refresh frame. During actual application, the pixel circuit may alternatively drive the pixel circuit based on other driving timing. The pixel circuit, the driving timing, and the like are not limited in embodiments of this application, and are determined based on a specific case.

[0167] It may be understood that, as shown in FIG. 14, in the refresh frame period, because the reset, the threshold compensation, and the like need to be performed, the first level phase (for example, the high level phase) needs to last for long time, as shown in 80H in FIG. 14. However, in the holding frame period, because only the emitting is required, and the reset, the threshold compensation, and the like do not need to be performed like the refresh frame period, in comparison with the refresh frame period, the duration of the first level phase (for example, the high level phase) in the holding frame period may be adaptively and dynamically adjusted. In addition to that normal emitting of the pixels is ensured, an emitting duty cycle is increased to optimize the screen flickering. In addition, the duty cycles at the different displaying refresh rates and / or the different reset frequencies are kept equivalent (for example, the difference is less than the preset threshold), to avoid the flickers generated when the displaying refresh rate or the reset frequency is switched, and achieve the better display and eye comfort effect.

[0168] For example, the pixel circuit is shown in FIG. 13, the first level phase is the high level phase, the second level phase is the low level phase, and the drain reset frequency (or source reset frequencies for some other pixel circuits) is 360 Hz. Driving timing of the pixel circuit corresponding to the holding frame period may be shown in FIG. 15. As shown in FIG. 15, in the holding frame period, the pixel circuit shown in FIG. 13 may set EM to a high level, keep S1n set to a high level, and set S2n and S4n to low levels. When setting S3n to a low level, the pixel circuit shown in FIG. 13 may enable T7 and T8 shown in FIG. 13 to be turned on for 32H; and when setting EM to a low level and keeping S3n set to a high level, the pixel circuit enables T5 and T6 shown in FIG. 13 to be turned on. The pixels emit. In view of this, in comparison with the driving timing of the refresh frame period shown in FIG. 14, the duration of the first level phase (that is, the high level phase) in the holding frame period is reduced from 80H to a range of 36H to 50H, so that a reset function of the pixel circuit in the holding frame period can be ensured, and the duty cycle can be increased to achieve a small SVM value (for example, reduced to 0.23, which is not limited), thereby optimizing the screen flickering. In addition, a difference between total duty cycles of the EM control signal at the different displaying refresh rates is less than the preset threshold. For example, as shown in Table 1, the duty cycle is maintained between 95.1% and 95.2%, to achieve the better display and eye comfort effect.

[0169] In an example, at the screen brightness value of 500 nits, 360 Hz is used for the EM control signal, the source reset frequency or the drain reset frequency is 360 Hz, and the duration of the high level phase in the refresh frame period is 80H. As shown in Table 1, if the displaying refresh rate is 120 Hz, the duration of the first level phase (for example, the high level phase) in the holding frame period may be 36H; if the displaying refresh rate is 60 Hz, the duration of the first level phase (for example, the high level phase) in the holding frame period may be 45H; and if the displaying refresh rate is 1 Hz, duration of the first level phase (for example, the high level phase) in the holding frame period may be 50H.

[0170] Alternatively, for example, the pixel circuit is shown in FIG. 13, the first level phase is the high level phase, the second level phase is the low level phase, and the drain reset frequency (or source reset frequencies for some other pixel circuits) is 240 Hz. Driving timing of the pixel circuit corresponding to the holding frame period may be shown in FIG. 16. As shown in FIG. 16, in the holding frame period, the pixel circuit shown in FIG. 13 may set EM to a high level, keep S1n set to a high level, and set S2n and S4n to low levels. When setting S3n to a low level, the pixel circuit shown in FIG. 13 may enable T7 and T8 shown in FIG. 13 to be turned on for 32H; and when setting EM to a low level and keeping S3n set to a high level, the pixel circuit enables T5 and T6 shown in FIG. 13 to be turned on. The pixels emit. In view of this, in comparison with the driving timing of the refresh frame period shown in FIG. 14, the duration of the first level phase (that is, the high level phase) in the holding frame period is reduced from 80H to a range of 36H to 58H, so that a reset function of the pixel circuit in the holding frame period can be ensured, and the duty cycle can be increased to achieve a small SVM value (for example, reduced to 0.18, which is not limited), thereby optimizing the screen flickering. In addition, a difference between total duty cycles of the EM control signal at the different displaying refresh rates is less than the preset threshold. For example, as shown in Table 2, the duty cycle is maintained between 96.2% and 96.3%, to achieve the better display and eye comfort effect.

[0171] In an example, at the screen brightness value of 500 nits, 240 Hz is used for the EM control signal, the source reset frequency or the drain reset frequency is 240 Hz, and the duration of the high level phase in the refresh frame period is 80H. As shown in Table 2, if the displaying refresh rate is 120 Hz, the duration of the first level phase (for example, the high level phase) in the holding frame period may be 36H; if the displaying refresh rate is 60 Hz, the duration of the first level phase (for example, the high level phase) in the holding frame period may be 51H; and if the displaying refresh rate is 1 Hz, duration of the first level phase (for example, the high level phase) in the holding frame period may be 58H.

[0172] Alternatively, for example, the pixel circuit of the display is shown in FIG. 13, the first level phase is the high level phase, the second level phase is the low level phase, and the drain reset frequency (or source reset frequencies for some other pixel circuits) is 120 Hz. Driving timing of the pixel circuit corresponding to the holding frame period may be shown in FIG. 17. As shown in FIG. 17, in the holding frame period, the pixel circuit shown in FIG. 13 may set EM to a high level, keep S1n set to a high level, and set S2n and S4n to low levels. When setting S3n to a low level, the pixel circuit shown in FIG. 13 may enable T7 and T8 shown in FIG. 13 to be turned on for 32H; and when setting EM to a low level and keeping S3n set to a high level, the pixel circuit enables T5 and T6 shown in FIG. 13 to be turned on. The pixels emit. In view of this, in comparison with the driving timing of the refresh frame period shown in FIG. 14, the duration of the first level phase (that is, the high level phase) in the holding frame period is reduced from 80H to a range of 70H to 75H, so that a reset function of the pixel circuit in the holding frame period can be ensured, and the duty cycle can be increased to optimize the screen flickering. In addition, a difference between total duty cycles of the EM control signal at the different displaying refresh rates is less than the preset threshold. For example, as shown in Table 3, the duty cycle is maintained between 97.4% and 97.6%, to achieve the better display and eye comfort effect.

[0173] In an example, at the screen brightness value of 500 nits, 120 Hz is used for the EM control signal, the source reset frequency or the drain reset frequency is 120 Hz, and the duration of the high level phase in the refresh frame period is 80H. As shown in Table 3, if the displaying refresh rate is 60 Hz, the duration of the first level phase (for example, the high level phase) in the holding frame period may be 70H; and if the displaying refresh rate is 1 Hz, duration of the first level phase (for example, the high level phase) in the holding frame period may be 75H.

[0174] It should be noted that in FIG. 15, FIG. 16, and FIG. 17, the pixel circuit shown in FIG. 13 is merely used as an example to describe driving timing examples of three different holding frame periods. During actual application, another type of pixel circuit may alternatively be used. In addition, for a specific pixel circuit, other driving timing may be used to drive the pixel circuit. This embodiment of this application imposes no limitation on the pixel circuit, the driving timing, and the like, and is determined based on a specific case.

[0175] It should be understood that the solutions in embodiments of this application may be properly combined for use, and explanations or descriptions of terms in embodiments may be cross-referenced or explained in embodiments. This is not limited.

[0176] It should be understood that sequence numbers of the foregoing processes do not mean execution sequences in various embodiments of this application. The execution sequences of the processes should be determined based on functions and internal logic of the processes, and should not be construed as any limitation on the implementation processes of embodiments of this application.

[0177] It may be understood that, to implement functions of any one of the foregoing embodiments, the electronic device and the like include corresponding hardware structures and / or software modules for performing each function. A person skilled in the art should be easily aware that, in combination with units and algorithm steps of the examples described in embodiments disclosed in this specification, this application can be implemented by hardware or a combination of hardware and computer software. Whether a function is performed by hardware or hardware driven by computer software depends on particular applications and design constraints of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of this application.

[0178] In embodiments of this application, the electronic device and the like may be divided into functional modules. For example, each functional module corresponding to each function may be obtained through division, or two or more functions may be integrated into one processing module. The integrated module may be implemented in a form of hardware, or may be implemented in a form of a software functional module. For example, as shown in FIG. 18, a display panel of the electronic device may include an integrated circuit 1810 (for example, a drive IC), a gate drive unit 1820, and a pixel circuit 1830. The pixel circuit 1830 includes an emitting control circuit and a reset circuit. The emitting control circuit is configured to: receive an emitting control signal, and control emitting based on duration of first level phases and duration of second level phases in a plurality of control periods. The reset circuit is configured to receive a reset control signal to control anode reset, gate reset, source reset, or drain reset. The integrated circuit 1810 is configured to: obtain a screen brightness value; and when the screen brightness value is less than a first brightness value, configure duration of second level phases in a plurality of control periods based on a first control period used for the anode reset; or when the screen brightness value is greater than a second brightness threshold, configure duration of first level phases in a plurality of control periods based on a displaying refresh rate corresponding to the emitting control signal and / or a reset frequency corresponding to the reset control signal.

[0179] It should be noted that, in embodiments of this application, the module division is used as an example, and is merely logical function division. During actual implementation, another division manner may be used. It should be further understood that each module in the electronic device and the like may be implemented in a form of software and / or hardware. This is not specifically limited herein. In other words, the electronic device and the like are presented in a form of functional modules. The "module" herein may be an application-specific integrated circuit ASIC, a circuit, a processor that executes one or more software or firmware programs and a memory, an integrated logic circuit, and / or another component that can provide the foregoing functions.

[0180] In an optional manner, when software is used for implementing data transmission, the data transmission may be completely or partially implemented in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedures or functions according to embodiments of this application are completely or partially implemented. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, through a coaxial cable, an optical fiber, or a digital subscriber line (digital subscriber line, DSL)) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by the computer, or a data storage device like a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a digital video disk (digital video disk, DVD)), a semiconductor medium (for example, a solid state disk (SSD)), or the like.

[0181] Method or algorithm steps described in combination with embodiments of this application may be implemented by hardware, or may be implemented by a processor by executing software instructions. The software instructions may include a corresponding software module. The software module may be stored in a random access memory (random access memory, RAM), a flash memory, a read-only memory (read-only memory, ROM), an erasable programmable read-only memory (erasable programmable read-only memory, EPROM), an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), a register, a hard disk, a removable hard disk, a compact disc read-only memory (compact disc read-only memory, CD-ROM), or any other form of storage medium well known in the art. For example, a storage medium is coupled to the processor, so that the processor can read information from the storage medium or write information into the storage medium. Certainly, the storage medium may be a component of the processor. The processor and the storage medium may be located in an application-specific integrated circuit (application-specific integrated circuit, ASIC). In addition, the ASIC may be located in an electronic device. Certainly, the processor and the storage medium may exist as discrete components.

[0182] Based on the foregoing description of the implementations, a person skilled in the art may clearly understand that for the purpose of convenient and brief description, division into the foregoing function modules is merely used as an example for description. During actual application, the foregoing functions can be allocated to different function modules for implementation based on a requirement, that is, an inner structure of an apparatus is divided into different function modules to implement all or some of the functions described above.

Claims

1. A method for driving a pixel circuit, wherein a display period of the pixel circuit comprises a plurality of consecutive control periods, each of the plurality of control periods comprises a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods comprise a first control period, the first control period is used for anode reset, the pixel circuit comprises an emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls the anode reset based on the first control period, and the method comprises: detecting a screen brightness value; when the screen brightness value is less than a first brightness threshold, configuring duration of second level phases in the plurality of control periods based on the first control period; and receiving, by the emitting control circuit, an emitting control signal, and controlling the emitting based on duration of first level phases and the duration of the second level phases in the plurality of control periods.

2. The method according to claim 1, wherein the plurality of control periods further comprise a second control period, the second control period is not used for the anode reset, and the configuring the duration of the second level phases in the plurality of control periods based on the first control period comprises: configuring duration of a second level phase in the first control period as first duration, and configuring duration of a second level phase in the second control period as second duration, wherein the first duration is greater than the second duration.

3. The method according to claim 2, wherein the first control period comprises at least one second level phase, and the first duration comprises total duration of the at least one second level phase in the first control period.

4. The method according to claim 2 or 3, wherein the plurality of control periods further comprise a third control period, the third control period is a control period after the first control period, the third control period is not used for the anode reset, and the configuring the duration of the second level phases in the plurality of control periods based on the first control period comprises: configuring duration of a second level phase in the third control period as third duration, wherein the third duration is greater than the second duration.

5. The method according to claim 4, wherein the third control period comprises at least one second level phase, and the third duration comprises total duration of the at least one second level phase in the third control period.

6. The method according to claim 4 or 5, wherein the third duration is less than or equal to the first duration.

7. The method according to any one of claims 1 to 6, wherein the first level phase is a high level phase, and the second level phase is a low level phase; or the first level phase is a low level phase, and the second level phase is a high level phase.

8. The method according to any one of claims 1 to 7, wherein the first control period comprises at least one control period; and / or the second control period comprises at least one control period; and / or the third control period comprises at least one control period.

9. A method for driving a pixel circuit, wherein a display period of the pixel circuit comprises a plurality of consecutive control periods, each of the plurality of control periods comprises a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods comprise a refresh frame period, the refresh frame period is used for displaying refresh and gate reset, the pixel circuit comprises an emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls the gate reset and the displaying refresh based on the refresh frame period, and the method comprises: detecting a screen brightness value; when the screen brightness value is greater than a second brightness threshold, configuring duration of first level phases in the plurality of control periods based on a displaying refresh rate corresponding to an emitting control signal and / or a reset frequency corresponding to the reset control signal; and receiving, by the emitting control circuit, the emitting control signal, and controlling the emitting based on the duration of the first level phases and duration of second level phases in the plurality of control periods.

10. The method according to claim 9, wherein the plurality of control periods further comprise a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level phases in the plurality of control periods based on the displaying refresh rate corresponding to the emitting control signal and / or the reset frequency corresponding to the reset control signal comprises: configuring duration of a first level phase in the refresh frame period as fourth duration, and configuring duration of a first level phase in the holding frame period as fifth duration, wherein the fifth duration is less than the fourth duration.

11. The method according to claim 9, wherein the plurality of control periods further comprise a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a second refresh rate, the second refresh rate is less than a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level phases in the plurality of control periods based on the displaying refresh rate corresponding to the emitting control signal and / or the reset frequency corresponding to the reset control signal comprises: configuring duration of a first level phase in the refresh frame period as fourth duration, and configuring duration of a first level phase in the holding frame period as sixth duration, wherein the sixth duration is less than the fourth duration, and the sixth duration is greater than fifth duration.

12. The method according to any one of claims 9 to 11, wherein the first level phase is a high level phase, and the second level phase is a low level phase; or the first level phase is a low level phase, and the second level phase is a high level phase.

13. The method according to any one of claims 10 to 12, wherein the refresh frame period comprises one control period; and / or the holding frame period comprises at least one control period.

14. A display, wherein the display comprises an integrated circuit, a gate drive unit, and a pixel circuit, a display period of the pixel circuit comprises a plurality of consecutive control periods, each of the plurality of control periods comprises a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods comprise a first control period, the first control period is used for anode reset, and the pixel circuit comprises an emitting control circuit and an anode reset circuit; the anode reset circuit is configured to: receive an anode reset control signal, and control the anode reset based on the first control period; the integrated circuit is configured to: obtain a screen brightness value, and when the screen brightness value is less than a first brightness threshold, configure duration of second level phases in the plurality of control periods based on the first control period; and the emitting control circuit is configured to: receive an emitting control signal, and control the emitting based on duration of first level phases and the duration of the second level phases in the plurality of control periods.

15. The display according to claim 14, wherein the plurality of control periods further comprise a second control period, the second control period is not used for the anode reset, and the integrated circuit is specifically configured to: configure duration of a second level phase in the first control period as first duration, and configure duration of a second level phase in the second control period as second duration, wherein the first duration is greater than the second duration.

16. The display according to claim 15, wherein the first control period comprises at least one second level phase, and the first duration comprises total duration of the at least one second level phase in the first control period.

17. The display according to any one of claims 14 to 16, wherein the plurality of control periods further comprise a third control period, the third control period is a control period after the first control period, the third control period is not used for the anode reset, and the integrated circuit is further configured to: configure duration of a second level phase in the third control period as third duration, wherein the third duration is greater than the second duration.

18. The display according to claim 17, wherein the third control period comprises at least one second level phase, and the third duration comprises total duration of the at least one second level phase in the third control period.

19. The display according to claim 17 or 18, wherein the third duration is less than or equal to the first duration.

20. The display according to any one of claims 14 to 19, wherein the first level phase is a high level phase, and the second level phase is a low level phase; or the first level phase is a low level phase, and the second level phase is a high level phase.

21. The display according to any one of claims 14 to 20, wherein the first control period comprises at least one control period; and / or the second control period comprises at least one control period; and / or the third control period comprises at least one control period.

22. A display, wherein the display comprises an integrated circuit, a gate drive unit, and a pixel circuit, a display period of the pixel circuit comprises a plurality of consecutive control periods, each of the plurality of control periods comprises a first level phase not used for emitting and a second level phase used for the emitting, the plurality of control periods comprise a refresh frame period, the refresh frame period is used for displaying refresh and gate reset, and the pixel circuit comprises an emitting control circuit and a reset circuit; the reset circuit is configured to: receive a reset control signal, and control the gate reset and the displaying refresh based on the refresh frame period; the integrated circuit is configured to: obtain a screen brightness value, and when the screen brightness value is greater than a second brightness threshold, configure duration of first level phases in the plurality of control periods based on a displaying refresh rate corresponding to an emitting control signal and / or a reset frequency corresponding to the reset control signal; and the emitting control circuit is configured to: receive the emitting control signal, and control the emitting based on the duration of the first level phases and duration of second level phases in the plurality of control periods.

23. The display according to claim 22, wherein the plurality of control periods further comprise a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: configure duration of a first level phase in the refresh frame period as fourth duration, and configure duration of a first level phase in the holding frame period as fifth duration, wherein the fifth duration is less than the fourth duration.

24. The display according to claim 23, wherein the plurality of control periods further comprise a holding frame period, the holding frame period is used for display holding, the displaying refresh rate corresponding to the emitting control signal is a second refresh rate, the second refresh rate is less than a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: configure duration of a first level phase in the refresh frame period as fourth duration, and configure duration of a first level phase in the holding frame period as sixth duration, wherein the sixth duration is less than the fourth duration, and the sixth duration is greater than fifth duration.

25. The display according to any one of claims 22 to 24, wherein the first level phase is a high level phase, and the second level phase is a low level phase; or the first level phase is a low level phase, and the second level phase is a high level phase.

26. The display according to any one of claims 23 to 25, wherein the refresh frame period comprises one control period; and / or the holding frame period comprises at least one control period.

27. An electronic device, wherein the electronic device comprises: a display, configured to display an interface; a memory, configured to store computer program instructions; and a processor, configured to execute the computer program instructions, to support the electronic device to implement the method according to any one of claims 1 to 8 or claims 9 to 13.

28. A computer-readable storage medium, wherein the computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processing circuit, the method according to any one of claims 1 to 8 or claims 9 to 13 is implemented.

29. A computer program product comprising instructions, wherein when the computer program product runs on a computer, the computer is enabled to perform the method according to any one of claims 1 to 8 or claims 9 to 13.

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