CMOS integrated temperature insensitive, stable, and calibrated oscillator

Abstract

A temperature insensitive oscillator system. The system includes a substrate having a first surface and an opposing second surface, a CMOS device with one or more CMOS circuits attached to the first surface of the substrate, one or more piezoelectric transducers attached to an outer surface of the CMOS device, a voltage-controlled oscillator generating a RF frequency, which is transmitted as a plurality of short pulses to the one or more piezoelectric transducers, and one or more delays and oscillators using resistor and active components arranged alongside the piezoelectric transducers or on the CMOS device such that the voltage-controlled oscillator has minimal dependence on temperature, and has minimal deviation from a programmed frequency. In order to meet the requirement of low phase noise and high clock frequencies, a very quality factor resonator-based oscillator is phase locked with the BAW wave based oscillator to realize both an accurate and low-phase noise oscillator.

Description

CMOS INTEGRATED TEMPERATURE INSENSITIVE, STABLE, AND CALIBRATED OSCILLATOR GOVERNMENT FUNDING

[0001] This invention was made with government support under Award No. 1746710 awarded by the National Science Foundation (NSF). The government has certain rights in the invention. BACKGROUND OF THE INVENTION 1. Field of the Invention

[0002] The present invention generally relates to a piezoelectric transceiver apparatus and, more particularly, to a CMOS device integrated with a temperature insensitive, stable, and calibrated oscillator. 2. Description of Related Art

[0003] Recent work (PCT / US20 / 35537 assigned to the assignee hereof and incorporated herein by reference) has demonstrated the concept of sending short ultrasonic pulses through a silicon wafer to realize an oscillator. Planar thin-film piezoelectric transducers are used to transmit and receive the ultrasonic pulse packets. The transit time between the transmit and receive transducers is proven to be stable over time owing to low loss of ultrasonic energy in high-quality crystals. For the very same reason resonators made of high-quality materials are used to achieve high-quality factor, the pulse-transmit of ultrasonic pulses results in stable time-of-flight. Once the time-of-flight has been stabilized, the stable delay can be used to form an oscillator by locking to the time difference of two signals or from repetition of reflections. This clock architecture can also be termed Bulk-ultrasonic Pulse Packet Delay Locked Oscillator (BB-DLO).

[0004] The piezoelectric transducers are fabricated on top of a CMOS wafer or can be built on planar silicon and non-silicon substrates. Integration with CMOS wafers offers the pathway to integrate clocks and oscillators directly into integrated circuits, eliminating the need for an external resonator structure employed in current systems. One can also use a separate CMOS electronics chip and a separate ultrasonic pulse-transit chip, allowing one to optimize the pulse-transit chips and the CMOS circuits independently of each other.

[0005] The transmitted ultrasonic pulse undergoes diffraction in the medium of pulse transfer, given that the aperture of the transducer is of finite width. Diffraction results in the distribution of the transmitted ultrasonic power in different angles from the transmitters. This angular distribution of ultrasonic wavefront travels along different lengths through the substrates, as they reflect off the backside of the substrate, to arrive at the receiver. For Page 1 of 28 18064335.v2-7 / 10 / 24example, the pulses associated with the first order and second order diffraction peaks can result in two or more pulses, and multiple times of arrivals on the receive transducer. This concept was demonstrated recently and has produced a stable delay element with ~1-ppm stability. In a related work, this delay line is placed in an electronic oscillator and has resulted in an oscillator with 1-5 ppm stability.

[0006] The stability of an oscillator is important to maintain time and frequency over time. An equally important aspect is to maintain accurate time and frequency as output, independent of the temperature. A typical specification for a clock or oscillator for a microcontroller is 1- 5 ppm variation over -45° to 125° C. The temperature independence ensures that the protocols of handshakes between chips and chip components, and clocking of computation across different blocks, operating at different temperatures can still work together.

[0007] The slope of the frequency of an oscillator versus temperature characteristic is often called temperature coefficient of frequency, or the tempco (short form for temperature coefficient). Within the silicon wafer itself, the speed of sound decreases with increasing temperature ten to 100 ppm / C, with the typical value being 20ppm / C. Since the time of flight of the pulses mainly determines the oscillator frequency, the tempco of the BPP-DLO is expected to be nearly identical to the speed of sound temperature coefficient of silicon.

[0008] The temperature coefficient for the delay and the oscillator reported in the previous work based on ultrasonic transmit and receive pulses can be substantial, except at a few values of temperature. Hence, a key challenge in the ultrasonic pulse T / R driven delay and oscillator architecture is to control the delay such that the variation of the delay across temperature can be minimized. In addition to temperature insensitivity, a key challenge is to realize a fixed, desired frequency from the oscillator, despite fabrication dependent differences. A fixed frequency oscillator can then be used to generate different frequencies with devices such as phase locked loops, frequency multipliers, and frequency dividers, to obtain frequencies needed for RF communications.

[0009] In addition to temperature compensation required to have a stable frequency over the temperature, another important aspect of oscillators is to have low phase noise. Phase noise, and jitter control the performance of several electronic components. For example, in an ADC (Analog to Digital Converter) the sampling time is generated from an oscillator, and if the phase noise and jitter are excessive, the signal sampled can be sampled at incorrect times than the times expected, leading to inaccurate representation of the signal. In a radio receiver, the oscillator is used in an RF receiver mixer. Any phase noise and jitter lead to inefficient mixing and sidebands in the demodulated signal that are representatives of the spectrum of the Page 2 of 28 18064335.v2-7 / 10 / 24oscillator phase noise. In a communications link between two electronic systems, the rate at which maximum communication can occur is limited by the phase noise of the oscillators dictating the transmission and sampling of digital or analog signals.

[0010] Oscillators are used in communication systems to create stable periodic signals to serve as RF carriers and as local oscillators in mixer-based RF receivers. Oscillators can also be used as clocks for synchronizing computations in microcontrollers, FPGAs, and as timing references for frequency hopping and real-time-clock-applications to name a few. Precision oscillators are qualified by several metrics of performance. These include stability, accuracy, phase noise, and jitter of the periodic output signal. Most stable oscillators used for microcontrollers, FPGA, or frequency synthesize applications utilize quartz electromechanical resonators utilizing the piezoelectric effect. RF voltages applied across a piezoelectric crystal excite a high-quality factor mechanical resonant mode in the structure. The first mode is typically the ½ wavelength resonance along the thickness of the crystal. The resonance frequency is expected to be f=c / (2t_P ) where c is the speed of sound of the crystal and t_P is thickness of the crystal. Once the frequencies required increase to GHz frequencies, the thickness reaches micron-scale levels. For example, for a 2.4GHz oscillator, the thickness of an AlN piezoelectric layer would be ~1.85 microns. FIG.1 has the value t_P as the thickness of the piezoelectric thin layer in a FBAR. In manufacturing such a resonator, often called FBARs (thin film bulk acoustic wave resonators), thin film-based fabrication approaches, such as lithography, sputtering, etching, are used. In order to get the frequency accurate to a few ppm levels, the level of thickness control needed would be in the ~1.85 picometers. This level of precision control is nearly impossible to control using thin film processing. In contrast, to make a 30MHz resonator, t_P would be 150um, and the ppm level accuracy can be achieved by having thickness control in the 150pm or ~0.15nm. This level of thickness control is possible with chemo mechanical polishing and other thickness trimming methods. Furthermore, if the resonance frequency is at 8 MHz, then the thickness can be in the 600um range and the thickness control for 1 ppm precision can be ~ 1nm, which can be achieved with polishing. Additional approaches to controlling wafer thickness include use of ion-beam etching, plasma etching, and chemical etching.

[0011] The phase noise of a resonator determines the noise in the phase of the periodic signal over time and over frequency range. The phase noise can lead to frequency variations, due to variations of times at which the clock signal crosses zero amplitude (zero crossings). The zero crossing time variations lead to jitter in digital systems and sideband mixing in radio systems using oscillators. Phase noise of an oscillator is inversely related to the quality factor Page 3 of 28 18064335.v2-7 / 10 / 24(Q) of the resonator that supports the oscillation. The higher the Q, the more energy is centered at the center frequency. Furthermore, to generate a high frequency signal from a lower frequency signal, such as with a phase-locked loop (PLL), the multiplication of the reference frequency leads to an increase in the phase noise of the signal by a factor of 20 Log(N) where N is the multiplication factor. Similarly, dividing an oscillator frequency by a factor of N leads to a decrease in the phase noise of the oscillator by 20 Log(N). Hence, it is desirable to not have to multiply an oscillator frequency to the desired frequency and achieve the desired frequency directly from a resonator that is greater than the desired frequency to take advantage of the reduction in phase noise.

[0012] Accordingly, there is a need in the art for high frequency resonators due to lack of control of resonator dimensions such as the thickness, but at the same time there is a need for high frequency signal to realize a low phase noise. There is also a need for an oscillator where the temperature dependence of the oscillator is within a few parts-per-million over the necessary temperature ranges. BRIEF SUMMARY OF THE INVENTION

[0013] In the invention described herein, a CMOS device is integrated with a temperature insensitive, stable, and calibrated oscillator, with low phase noise.

[0014] Embodiments of the present invention are directed to a temperature insensitive oscillator system. According to one aspect, the system includes a voltage-controlled oscillator VCO generating an RF frequency, which is applied as a plurality of short pulses to a piezoelectric transducer. The system also includes a piezoelectric receiver spaced from the piezoelectric transducer and configured to receive the plurality of short pulses, an amplifier, an envelope detector or a RF mixer configured to convert the plurality of short pulses to an amplified signal, and a comparator configured to digitize the amplified signal and add temperature-dependent and programmed fixed delays.

[0015] According to a similar aspect, the system includes a substrate having a first surface and an opposing second surface, a CMOS device with one or more CMOS circuits attached to the first surface of the substrate, one or more piezoelectric transducers attached to an outer surface of the CMOS device, a voltage-controlled oscillator generating an RF frequency, which is transmitted as a plurality of short pulses to the one or more piezoelectric transducers, and one or more resistors arranged alongside the piezoelectric transducers or on the CMOS device such that the voltage-controlled oscillator has a controllable temperature dependence.

[0016] According to an additional aspect, the system includes a substrate having one or more transducers and a first oscillator configured to generate an RF frequency, which excites Page 4 of 28 18064335.v2-7 / 10 / 24the one or more transducers at their respective resonance frequencies. The one or more transducers generate several RF pulses that are used to generate digital pulses corresponding to the multiple ultrasonic reflections and RF coupling signals. The delay generated from the US pulsing can be used to form two oscillators that can be used as clocks. In one clock architecture, one of the returning pulses is used to trigger the next transmit pulse resulting in an oscillator. The system can also be used to implement a second oscillator having a frequency based on the time difference between the arrival times of two different received pulses.

[0017] The present disclosure is directed to CMOS integrated high frequency stable and accurate oscillators.

[0018] According to an aspect is a FBAR resonator whose frequency is adjusted though a phased-locked-loop locking of the FBAR resonator with a BAW-Pulse-Packet Delay Line oscillator.

[0019] According to an aspect is a FBAR resonator and BPP-DLO fabricated monolithically in a CMOS process where CMOS transistors in the substrate are used to functionalize both oscillators and their coupling through a PLL.

[0020] According to an aspect are arrays of BP-DLO oscillators drive and sense transducers are driven in parallel, and their analog signals are added into a receiver to reduce the effect of noise to achieve lower noise BP-DLL.

[0021] These and other aspects of the invention will be apparent from the embodiments described below.

[0022] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. BRIEFDESCRIPTION OFTHESEVERALVIEWS OF THEDRAWING(S)

[0023] The present invention will be more fully understood and appreciated by reading the following Detailed Description in conjunction with the accompanying drawings. The accompanying drawings illustrate only typical embodiments of the disclosed subject matter and are therefore not to be considered limiting of its scope, for the disclosed subject matter may admit to other equally effective embodiments. Reference is now made briefly to the accompanying drawings, in which:

[0024] FIG.1 is a schematic representation of a temperature insensitive oscillator system, according to an embodiment, using one of the received pulses to trigger the next cycle.

[0025] FIG.2 is a schematic representation and equations for measuring multiple pulses corresponding to the diffraction-based pulses;

[0026] FIG.3 is a graph showing the difference in arrival times of two different pulses; Page 5 of 28 18064335.v2-7 / 10 / 24

[0027] FIG. 4 is a graph showing the temperature coefficients of NMOS and PMOS transistor thresholds from -40° to 85° C for a commercial CMOS fab;

[0028] FIG.5 is a graph showing the delay frequency as a function of transducer diameter;

[0029] FIG.6 is a schematic representation of CMOS wafer thickness and the positioning of the received pulse;

[0030] FIG. 7 is schematic of a short pulse generator from a clock cycle of the divider from the LO-VCO.

[0031] FIG.8 is a possible implementation of a LO-VCO as a ring oscillator feeding into the divider counter.

[0032] FIG.9 is a timing diagram demonstrating the signals over time at various points in the oscillator.

[0033] FIG.10 is a schematic representation of how the flip-flop and counter outputs from the schematics in FIGS.8 and 9 are used to control a charge pump to generate a control voltage to lock the oscillator output to the ultrasonic delay time through silicon.

[0034] FIG. 11 is a schematic of a piezoelectric transducer for use with the present invention.

[0035] FIG. 12 is a cross-section view schematic representation of a piezoelectric stack, according to an embodiment.

[0036] FIG.13 is a cross-section view schematic representation of an oscillator according to another embodiment of the invention.

[0037] FIG. 14 is a cross-section view schematic representation of another oscillator according to another embodiment of the invention.

[0038] FIG. 15 is a graph of the reflection amplitudes versus frequency for an ALN ultrasonic transmit / receive device as a function of ultrasonic carrier frequency.

[0039] FIG. 16 is a pair of diagrams of an exemplary circuit for use with an oscillator according to a further embodiment of the invention.

[0040] FIG.17 is a series of graphs of the reflection amplitude of an oscillator according to a further embodiment of the invention versus RF carrier frequency.

[0041] FIG. 18 is a graph of the clock signals produced by an oscillator according to a further embodiment of the invention.

[0042] FIG.19 is a schematic of a device that comprises two oscillators connected to each other, in accordance with an embodiment. Page 6 of 28 18064335.v2-7 / 10 / 24

[0043] FIG. 20 is a device that comprises two oscillators connected to each other and including a trench between the BPP-DLO and the FBAR device, in accordance with an embodiment.

[0044] FIG. 21 is the schematic of a device that comprises two oscillators connected to each other of FIG.19 along with supporting electronics, in accordance with an embodiment.

[0045] FIG. 22 is a schematic of CMOS integrated process to enable piezoelectric thin films integrated with CMOS that enables both FBAR resonators and BAW transducers, in accordance with an embodiment.

[0046] FIG. 23 is a schematic of an array of transmit transducers that are driven simultaneously by an array of amplifiers, with the receive transducers piezoelectrically induced displacement currents added together into a single TIA. DETAILED DESCRIPTION OF THE INVENTION

[0047] Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known structures are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific non-limiting examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and / or arrangements, within the spirit and / or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.

[0048] The apparatus and methods described herein detail several new architectures to enable a practical CMOS integrated clock generator. The methods described are pertinent to reducing the delay temperature dependence. As described herein, a CMOS with a temperature insensitive, stable, and calibrated oscillator is integrated with a piezoelectric transducer. An exemplary embodiment of a piezoelectric transducer for use with the present invention is shown as piezoelectric stack 100 in FIG.11. In FIG.11, the transducer is shown fabricated on a CMOS substrate 107, 108, where FEOL refers to the transistor front-end-of-line CMOS layers 108 and BEOL refers to the back-end-of-line CMOS metallization layers 107. An insulator layer (such as silicon dioxide) 106 may be required to insulate the bottom electrode 102 from the CMOS top metal 107. The insulative layer 106 has metal vias 111 that connect the top-level connections in CMOS (e.g., CMOS BEOL layer 107) to the transducers through more layers of vias 110. These vias 111 connect the various metal layers electrically so that the receive transducer electrodes 102 can be cascaded in series. The vias 111 are also used to Page 7 of 28 18064335.v2-7 / 10 / 24connect the transducer electrodes 102 to the CMOS metallization 107, 108 to connect to the CMOS circuits. The CMOS transistor layer 108 (CMOS FEOL layer 108) can sense and drive the piezoelectric transducers on the devices. The circuit can be connected to one of the piezoelectric transducers and can be used to drive an ultrasonic wave and pulse in the bulk of silicon layer 109. The receive transducer can be connected to transistors for energy processing and generating a power source to power circuitry.

[0049] Referring now to FIG.1, a startup circuit will set all of the digital values in storage elements such as flip-flops and latches, and start the local oscillator LO-VCO 1. This local oscillator will be running at rates at which the output clock is desired in the 8-64 MHz range. The local oscillator is divided down by a divider 2 that generates a signal which dictates the triggering of a short digital pulse of 5-50ns using a digital pulse generator 3, using a circuit shown in Fig.7. The local oscillator also feeds into the state-machine 4 that can generate a slew of digital circuits to trigger or gate different signals during the right time frame with respect to the local oscillator clock. The local oscillator control voltage is controlled by the output of the control loop coming out from the loop-filter 5, and a DC offset generated by a circuit that can compensate for variations in the wafer thickness measured using diffraction in the circuit block 6. The digital pulse from the digital pulse generator 3 gates the RF-VCO 10 output onto the transmit AlN transducer 8. The RF-switch circuitry includes digital circuitry to trigger the VCO at a select phase. The RF-VCO 10 has built-in resistors generating control voltage that have a desired temperature coefficient as described below. The RF-VCO can also be controlled by a circuit to lock to a specific frequency at which two received signals are of equal amplitude, this block shown as 13 and described later in Fig.15. The substrate 14 consists of multiple layers to adjust the temperature coefficient of transit delays as a function of temperature and consist of layers on the edges to absorb the ultrasonic pulses being transmitted to the edge to prevent reflection back into the main substrate. The pulses generated into the substrate are received on the receiver 9 fed into an electronic block 15 consisting of an amplifier / envelope detector 14. The output of the baseband pulse shapes is fed into comparator 16 that converts the received RF pulse into digital signals. The comparator bias 16 can be generated in a way such that the bias itself has a temperature coefficient using resistors of different TCR (temperature coefficient of resistance). The output of the comparator will consist of an output from several reflections and RF pulses. The state machine 4 can be used to select the correct pulses to generate two pulses that are fed into 18 to generate a pulse that turns on the rising edge of the first selected pulse and goes turns off on the arrival of the second selected pulse, this occurring in the block 18. The output pulse from 18 can be further reduced in its duration using a nibbler Page 8 of 28 18064335.v2-7 / 10 / 24circuit 19 with the nibble time being determined by the temperature coefficient of a RC circuit. This reduced pulse can be further delayed using an RC circuit and inverters using block 20. The block 20 delay can also include additional delay to compensate for wafer thickness correction, using a permanent memory digital value 11 feeding into a digital to analog converter DAC 12 to provide a voltage to control the pulse width. The delayed pulse can now be fed into the phase detector and charge pump 21 which generates a signal corresponding to the difference in the pulse width of the local oscillator derived time pulse which is filtered using the loop- filter 5 and used to control the frequency of the local oscillator 1.

[0050] The time difference between two pulses can be used to form an oscillator as described below. The RF coupling, due the coupling of the electric fields at the drive port to the sense port through the air and the silicon substrate itself, from the input to the output transducer can result in another pulse from the receive electronics corresponding to the RF coupling pulse. According to the embodiment described below, a calibrated, temperature stable delay and clock are created through temperature dependent VCO frequency cancellation. The diffraction of the different orders results in two different angles of peaksand ^^2can be approximated by the equation sin ^^^^=. Here, ^^ is the width of a rectangular transducer array, ^^ is the speed of sound in the silicon bulk and ^^ is the order of the diffraction. The diffraction angles are reduced by increases in the drive frequency. In previous work, it has been described that as the temperature changes, the speed of sound is reduced with increasing temperature. The temperature coefficient of the speed of sound can be written as ^^ = ^^0(1 − ^^Δ ^^), where ^^ is a positive value around -50 ppm / °C for silicon and can be a function of the crystalline orientation. The diffraction angles are inversely dependent on the frequency. Hence, the angle of diffraction can be kept invariant with temperature by reducing the frequency by the same amount as the speed of sound is decreased with temperature. As the diffraction angles change, the first and second orders arrive at the receiver at different times resulting in temperature variation. The two different pulses arrive at two different times, and the difference between the two pulses can be used to control the oscillator frequency as this difference in time is very stable owing to the high-quality factor of the silicon wafer. As seen 2 ^^ ^^ ^^ ^^( ^^ ) e FIG.3, the difference in the two times is Δt = t^^ 1−2 ^^ ^^ ^^( ^^ ) in th22− t1= ^^^^ ^^ ^^ ^^ ^^^^ ^^ ^^( ^^1) ^^ ^^ ^^( ^^2) .

[0051] As the temperature increases, the speed of sound decreases, and the angles also decrease as the angles are linearly proportional to the speed of sound. As the angles are reduced, the distance traveled by the diffraction orders is reduced and the difference between Page 9 of 28 18064335.v2-7 / 10 / 24the two pulse times decreases as the two-angle difference becomes smaller. Using the small angle approximation for the angles which are small, one can write this expression as Δt = t2− 7 ^^^^ ^^ ^^(1− ^^Δ ^^) t1= 4 ^^^^ ^^^^^^2^^2. Here, α is the absolute value of the speed of sound tempco. It is apparent from this expression that if the ultrasonic carrier frequency also decreases with temperature, then the overall change in time difference can be minimized. If we assume thatthen using the binomial expansion and keeping the first high-order- we obtain:then the temperature dependence can be eliminated. Since this derivation is approximate, a numerical simulation was conducted in Mathematica. The delay expression with the Cosine terms was calculated without the small angle approximation, and a curve of frequency versus temperature as seen in FIG. 3 was obtained, achieving a small tempco of 0.667 ppm / K over the range of -20° to 125° C.

[0052] To compensate for the diffraction angle change with temperature, the frequency of the ultrasonic pulses is changed. The carrier frequency of the ultrasound can be approximated at ^^ = ^^0(1 − ^^Δ ^^) where ^^ is the coefficient of the carrier frequency. Hence, in order to design a carrier frequency with a specific temperature coefficient, one must consider the temperature coefficients from the different components. One of the main components is the VCO that generated the carrier frequency. Typical VCOs are ring oscillators consisting of digital inverters feeding into each other with a feedback loop. The inverters feed into charging the gate capacitance and wire capacitance of the next stage inverter. The inverter PMOS and NMOS transistors control the charging time and discharging times, respectively of the overall capacitance to be charged by the inverter. The saturation mode current through a NMOS transistor can be approximated as ^^^^ ^^ ^^ ^^ ^^=Similarly, for the PMOS transistor the saturation current can be written as ^^^^ ^^ ^^ ^^ ^^= The mobility of free carriers in n- and p-typedoped silicon typically reduces with temperature. The threshold voltage of NMOS transistors decreases with temperature, while that for PMOS transistors increases, as seen in FIG.4. This result implies that the ring-oscillator and hence the VCO frequency can have an innate temperature coefficient. In FIG.4, the temperature coefficients of NMOS and PMOS transistor thresholds are shown from -40° to 85° C for a commercial CMOS fab. To achieve a given tempco, one can design the RO-VCO with specific temperature dependent current controlling Page 10 of 28 18064335.v2-7 / 10 / 24elements. In addition to the ring-oscillator, other oscillators such as LC oscillators may also be used to generate the RF pulses.

[0053] CMOS technology also consists of many thin films made of metals and semiconductors with different doping levels, that can be patterned as resistors. The temperature coefficient of the resistors can be positive or negative. For example, for diffused resistors, formed by diffusing n- or p-type dopants, temperature increase can increase the number of free carriers and decreases the electron or hole mobility. If the generation of carriers dominates compared to the decrease in mobility, then the resistivity decreases with increasing temperature, resulting in a negative temperature coefficient (tempco) of resistance. However, if the starting semiconductor is highly doped and nearly degenerate, or degenerate, then only the mobility decrease dominates, leading to an increase in resistance resulting in a positive tempco for the resistor. In any CMOS process, many kinds of resistors are available. For example, resistors can be made with diffusion of dopants in semiconductors with metal contacts where the metal-semiconductor contacts are ohmic. Another example of a resistor is that made of polysilicon which can be highly degenerate. If a series combination of a negative tempco of diffusion resistors and that of a polysilicon resistor are in series, one can program the effective tempco of an equivalent resistance. ^^^^ ^^ ^^= ^^^^0+ ^^^^0+ ( ^^^^ ^^^^^^ ^^+ ^^^^0^^^^ ^^)Δ ^^. This approach for tuning the tempco for a VCO oscillator has been implemented. In a configuration of a ring oscillator, a bias voltage can be used to control the current through the inverters by having the PMOS and NMOS transistors in series with the inverters. This configuration of a VCO is often called a current-starved VCO. The resistive divider current source can be designed to produce a bias that changes with temperature to feed into the current starving transistors of the VCO. This voltage bias, as it changes with temperature, owing to the change in the resistance, will control the rate at which the ring-oscillator inverters charge and discharge, obtain a desired temperature coefficient of the VCO frequency. By using a diffusion resistor and a polysilicon resistor in series in the right proportion, a desired temperature coefficient of the VCO can be obtained. In addition to tuning the current source dependence on temperature using different resistors, and the threshold voltage dependence on temperature, we implement a VCO with the correct temperature dependence of output frequency to make the temperature dependence of the ultrasonic delay element to be a controllable value.

[0054] According to the embodiment described below, temperature dependent delays are used to compensate with temperature dependence of the amplifier, envelope detector, Page 11 of 28 18064335.v2-7 / 10 / 24comparator, and digital logic. To form the oscillator 10 using the ultrasonic pulse stable time delay, a control loop to add and reduce delay in the electronic domain is formed that can include several components. The pulse being received on the receive transducer 18 can be detected by a mixer receiver or a simpler diode-like envelope detector 14. In the mixer detector 14, the RF pulse signal is multiplied with the received signal, resulting in a low-noise detector by canceling out any out-of-band RF energy.

[0055] In the diode-based RF energy detector (often also referred to as a “demodulator”) 14, the positive swings of the RF input are rectified into a capacitor. A full-bridge rectifier is used to extract the energy in the negative cycle of the RF cycle. Hence, a net voltage builds up on the capacitor, which can be used to determine if a signal is received at the receiver. The voltage on the capacitor can be a function of temperature because the diode current is a function of temperature. Hence, the output voltage and the time at which the voltage peaks will be a function of the different components used to implement the envelope detector. The envelope detector 20 can be made not only of PN junctions in CMOS, but also diode connected PMOS, NMOS, and BJT transistors. The output of the envelope detector can also be then input into a smoothing amplifier to remove and ripples associated with charging of the capacitor at the output of the rectifier, and discharging through parasitic or intentional resistors in parallel with the capacitor.

[0056] Following the envelope detector 14, a base-band voltage pulse is generated that can be further amplified. The pulses are processed into a comparator 15, which generates a digital voltage close to the supply voltage of the circuit. The digital-like output from comparator 15 can then be used to generate the next ultrasonic pulse to form the oscillator. The comparator 15 itself can have a time delay in placing the digital output as a function of the input voltage difference between the input and the threshold voltage. This time delay ^^^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^can have a temperature dependence that can change the time output frequency of the oscillator.

[0057] In order to control the comparator delay, a resistive divider, made of positive and negative tempco resistors, can be used to provide threshold voltages that can change with the threshold such that the comparator output can be adjusted automatically as a function of temperature as block 16 in Fig. 1. A voltage divider made of two resistorsand ^^2,2connected to ground and ^^1connected to ^^^^ ^^produces a voltage that is: ^^^^ ^^ ^^=

[0058] These approximations are made using the binomial approximations. By controlling the composition of both ^^1and ^^2made of diffusion and poly / metal resistors, we can design Page 12 of 28 18064335.v2-7 / 10 / 24a bias for the comparator that results in a desired tempco.

[0059] The digital pulse generated after the comparator 15 may consist of multiple pulses from which only two are chosen to form the pulse to be compared to the local oscillator half- period. As digital state machine 4 can control the selection of the right pulses by gating of the pulse using and gates with control inputs timed using RC delays. The resulting two pulses are then fed into a D-flip flop such that a square pulse is generated corresponding to the time between the rising edge of one received pulse and the siring edge of the second pulse in block 18. Following this, to add additional temperature control, a nibbler circuit 19 can be used. This circuit consists of a XNOR gate with one input being the pulse from 18 and a second pulse being delayed by a RC delay followed by an inverter such that the delayed pulse will reduce the width of the pulse from 18.

[0060] The goal of this clock architecture is to lock the width of the physics generated clock pulse to that generated by the local oscillator. In order to achieve a close lock of the two pulses, a delay 20 may be needed consisting of inverters and RC delays. Here, the R of the RC delay can be again composed of resistors with predictable temperature coefficients. The delay R can also be made of transmission gates made of NMOS and CMOS transistors that yield a desired temperature coefficient.

[0061] The thickness of the substrate 13 is controlled by polishing, and owing to variance in polishing, the thickness cannot be easily controlled to ppm level accuracy at low cost. Although the thickness of the wafer can be controlled very accurately to a few nanometers using advanced polishing equipment, larger errors of a few microns can be present if only a traditional grinding tool is used. A few microns of thickness error will be present corresponding to a few nanosecond delay that can change the oscillation frequency. Every micron corresponds to ~0.1 ns delay given the speed of sound in silicon is ~9000 m / s. In order to compensate for the errors in wafer thickness and other adjustments in the circuit, the delay 20 can be further controlled by a digitally stored value in non-volatile RAM 11 feeding into the DAC 12 controlling the delay in 20 using the biases of an inverter.

[0062] The embodiment described below details the method of programming the frequency using RF or wired input clock. The voltage needed to control the fixed delay can be generated by sensing the input RF frequency over a channel (either RF fed signal or wired signal) that is divided down, using a counter or fractional PLL, to the desired frequency of the local oscillator 1. This can be especially useful in a training mode during production where each wafer can be exposed to a precise RF signal where the RF signal is fed to the entire wafer. The RF signal is harvested, using integrated capacitive or inductive antennas, to power each Page 13 of 28 18064335.v2-7 / 10 / 24chip to calibrate its clock frequency. Note that since the programming power can be high, the antennas can be very small commensurate with the size of the oscillator part of the CMOS chip. For example, the Wi-Fi or BLE signals can be received and amplified, using power generated though the RF energy harvester, and fed into a digital counter to down count the number of RF cycles to result in a reference clock , against which the US pulse based oscillator can be compared against.

[0063] Once this frequency is obtained, the onboard frequency can then be compared using a frequency-phase detector. The correction digital value required to match the absolute frequency can be stored in a permanent memory on CMOS which can include electrical fuses.

[0064] A second method for thickness calibration can also be integrated. The embodiment described below details the method of programming the frequency using on-chip calibration using differential sensing of the US pulses. The feature dimensions on top of the CMOS chip can be defined using DUV lithography with accuracies to sub-micron level, and the relative matching of features close to each other on the chip can be very high. By laws of ultrasonic wave propagation, the reflected ultrasonic pulses at angles governed by diffraction, received on the receive pixel, will be a function of the wafer thickness, as shown in FIG.6. If the wafer thickness is too thick, then the received pulse will be on the right of the receiver as the path of travel is longer. If the wafer thickness is too thin, then the pulse received is on the left of the transducer. To calibrate the wafer thickness, the receive transducer can be split into two or more transducers connected in a way to measure the difference in the receive transducers using CMOS circuits to amplify the difference using commonly available differential amplifier topologies. The area of the two neighboring receive transducers may need to be different to account for the different distance from the transmitter and the US pulse arriving at the farther electrode being smaller. The difference signal can be conditioned, using analog or digital approaches, to calculate the effective error of the wafer thickness. The difference in the output serves as an error signal to feed into the voltage controlled oscillator 1 by using the output of the circuit to control the delay of one of the stages of the inverter chin in a ring-oscillator.

[0065] In order to implement an oscillator based on the difference in timing of two return pulses, a specific architecture is described below.

[0066] As shown in FIG.8, the output of the LO-VCO 1 with a square wave output is fed into a counter. A 3-bit counter 214 is shown as an example. The 2 least-significant bits (LSB) of the counter output are fed into an AND gate 206 to generate a pulse that generates a pulse with a frequency that is ¼ of the electronic clock. As shown in FIG. 9, the AND gate is configured with inverted inputs, that turns on when two least significant bits, b0 and b1 are Page 14 of 28 18064335.v2-7 / 10 / 24zero. The output of this AND gate can be called ^^^^ ^^ ^^ ^^4, and its inverse ^̅^̅^^̅^̅^ ^̅^ ^̅^4̅is generated using an inverter. All of the counter bits are also fed into a second, three input AND gate 204, to generate a pulse that can be called ^^^^ ^^ ^^ ^^8signal, which is fed through an inverter to generate its inverse,̅^^̅^^̅^̅^̅^^ ^̅^8̅. The ^^^^ ^^ ^^ ^^8signal is used to generate a trigger pulse, ~50 ns wide, that gates the RF VCO into the transmit transducer. This short trigger pulse is generated by driving an AND gate 304 with the signal and its delayed version using a RC 306, 308 delay circuit associated with a delay ^^^^ ^^(FIG.7).

[0067] The excitation of the transmit transducer by the RF pulse generated by the RF switch creates an ultrasonic pulse that travels through the silicon while diffracting. The ultrasonic pulses are reflected off the bottom surface of the silicon and travels back to the top side of the silicon where they are received by the receive transducer. The multiple bounces of this ultrasonic pulse due to reflection from the top and bottom surfaces of the silicon manifest as multiple echoes in the receive voltage waveform.

[0068] The delay time for each echo from the initial transmit time is proportional to ^^Γ^^2 ^^ / ^^ where ^^ is the speed of sound and ^^ is the wafer thickness, ^^ is the echo number, and Γ^^is a correction term used to account for the variation in transit time due to diffraction.

[0069] The received ultrasonic echoes are converted into a digital signal by the following steps: 1) the received echoes from the transducer are fed into an amplifier, followed by an envelope detector in order to down convert the signal from a RF pulse to a baseband pulse; 2) the pulse output from the envelope detector is converted to a digital signal using a comparator or a high gain amplifier (Fig.7.).

[0070] The digital signal generated, containing the multiple reflections received in the receive transducer, from the reflections are then fed into a D flip-flop. As the reflections arrive, the D flip-flop (FF) turns on and off at rising edges of the consecutive pulses arriving, producing a signal ^^^^ ^^. The D flip-flop (FF) turns on with the arrival of a new pulse, and turns off with the next pulse, creating a pulse that is on for the duration corresponding to the time difference between the two pulses. This pulse then is fed through the different time adjusting components 338, 332, 330 in FIG .8. Here the output of the FF 302 is fed into the control circuits for the delays to turn off the delay if the FF output is high, such that the delays are applied only when the transition of the FF is from 0 to 1, therefore effecting the time difference between the delays. Page 15 of 28 18064335.v2-7 / 10 / 24

[0071] The D flip-flop is connected to be reset by the ^^^^ ^^ ^^ ^^8signal, thus ensuring that the output of the D flip-flop is zero when the digital signals corresponding to the reflections arrive (FIG.8).

[0072] For the purpose of forming the oscillator we assume that the D flip-flop pulse output ( ^^^^ ^^) is aligned in time roughly with the of the ^^^^ ^^ ^^ ^^4signal from the local oscillator. This alignment can be achieved by adjusting the nominal operating frequency of the local oscillator. A timing diagram corresponding to the signals is shown in FIG.10. The rising edge of ^^^^ ^^ ^^ ^^8triggers the main ultrasonic pulse shown on the top trace. The trigger leads to the multiple reflections from the receive transducer. The resulting ^^^^ ^^can overlap with the sufficiently for feedback control adjustment. Since the objective of the locked oscillator is to adjust the local oscillator frequency such that the pulse width is the pulse width corresponding to the pulse difference between two reflections, we need a circuit to adjust the local VCO oscillator frequency as a function of the difference.

[0073] A phase detector can be used to generate a signal proportional to the time difference. The phase detector has the ^^^^ ^^and the ^^^^ ^^ ^^ ^^4signals as inputs. This circuit produces an output on the ‘U’ signal if ^^^^ ^^is ahead of ^^^^ ^^ ^^ ^^4, and ‘D’ if ^^^^ ^^is behind ^^^^ ^^ ^^ ^^4. A second phase detector is implemented with ^̅^̅^̅^ ^̅^and̅^^̅^^̅^̅^̅^^ ^̅^4̅that generates the corresponding ‘U’ and ‘D’ signals. The U and D signals from this second phase detector are fed into an OR gate with the D and U signals of the first phase detector as shown in FIG.11. The output of the OR gates fed to a charge pump. As can be seen there are four possibilities of timing errors between the ^^^^ ^^ ^^ ^^4and ^^^^ ^^signals. For each of the cases the output voltage either corrects the VCO frequency or stays at the right frequency even with small amount of shift between the and ^^^^ ^^signals. The output of this charge pump ( ^^^^ ^^ ^^) is used in conjunction with additional voltage to control the local oscillatorcontrol the frequency. For example, ^^^^ ^^ ^^can be formed by the addition of the ^^^^ ^^ ^^signal and another biasing voltage using an op-amp circuit shown as a block 210. Additional digital circuitry with RC delays between stages can be used to align the multiple reflection derived signals to minimize the overlap between the local oscillator clock and the pulse derived between multiple reflections.

[0074] In another embodiment of the invention, several approaches may be used to reduce the temperature coefficient of frequency, known as the “tempco”. First, two clocks with two different tempcos can be used to generate a beat frequency by mixing the two oscillators. The difference frequency can then be used to adjust one of the oscillators. Such approaches have Page 16 of 28 18064335.v2-7 / 10 / 24been realized before using different temperature coefficients of different modes of quartz resonators. With the present invention, two oscillators implemented with different tempcos can be achieved by choosing two different crystalline directions of the BAW strain pulse travel. The anisotropy of the elasticity of silicon direction leads to a direction dependent speed of sound. For example, the speed of sound and the temperature coefficients are different for the <111> crystal direction compared to <100> or <110> directions.

[0075] Another approach is to add a layer or multiple layers of materials on the stack that have different temperature of coefficients. As seen in FIG.12, layer(s) are added on top of the AlN stack on top of the CMOS to launch waves not only downwards, but also upwards into the top stack. The top material can be made of different materials such as fused silica, sapphire, other types of glass, that have distinctly different temperature coefficients. This bonding of blocks of materials can be achieved by flip-chip bonding or wafer scale-die-to wafer bonding. There maybe several other bonding approaches including bonding to a thin layer of ALD (atomic layer deposition) deposited metal layer that melts and bonds the two pieces together. In this approach, the reflected waves traverse both of the materials, and the receiver electronics can be designed to detect the pulses returning at different times from the two surfaces, using digital timing of activating the receiver electronics at time periods defined by the local oscillator derived gating signals. Two or more oscillators can be formed by locking to the time difference between multiple reflections from the top and the bottom substrates. These multiple oscillators can then be mixed to create a difference frequency which would be a predictable function of temperature. This difference frequency can be used to add or subtract counts in a counter which is being primarily counted by one of the two clocks. As one clock up counts a counter, the difference clock can down count the counter resulting in a frequency resulting that is adjusted by temperature.

[0076] The time of flight of return pulses will be 2 ^^^^, 2 ^^^^, 2( ^^^^+ ^^^^)[2 ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^ ^^], 4 ^^^^+ 2 ^^^^, 4tw+ 2 ^^^^, and so forth. Many different reflections can be used to set frequencies corresponding to two different time differences. One such combination leads to:

[0077] Where the time differences between the reflection coming from reflections going through top and bottom is subtracted from the first reflections from the first reflection from the top layer and bottom substrate. Page 17 of 28 18064335.v2-7 / 10 / 24

[0078] Another approach for temperature compensation is to add a layer at the bottom of the silicon wafer, as seen in FIG.13. In this method ultrasonic pulses travel through silicon and then through the bonded layer (BL). Because of the impedance mismatch between the silicon and the new material, there will be reflections at the interface. The transmitted pulse into the bonded layer will reflect from the back side at the air-interface, travel through the bonded material, and then is transmitted through into silicon where it is transduced into the electrical domain via the piezoelectric transducers. If the speed-of-sound tempco of the BL is positive, it can compensate for the negative tempco of the silicon. Fused silica is one such material in which the tempco is positive – the speed of sound increases with increased temperature. In this case, the transit time decrease in silicon can be compensated by the transit time increase in the fused silica layer. In order to control the transmission across silicon and a bonded layer, a thin layer can be placed between the silicon and the bonded layer (matching layer with thickness ^^^^in Fig 14), whose ultrasonic impedance is chosen such that the coupling can be controlled by the thin-film thickness. For example, aluminum can be chosen to bond between silicon and fused silicon with a thickness of aluminum corresponding to the quarter wavelength in silicon at the chosen RF frequency, which ideally should result in perfect matching from silicon to fused silicon. However, since a reflection from the silicon-thin layer-fused silica will also be important, the aluminum layer can be picked to be of thinner or thicker than the quarter wavelength to achieve imperfect matching to enable reflections.

[0079] Furthermore, it is additionally desired that the two reflections through the added layer are of equal amplitude such that the delay time between receiving two RF pulses owing to the amplitude dependence of the electronic receivers can be minimized. The pulses travel though the interface of the main substrate and the bonded layer with different ultrasonic impedance leading to reflections and transmission through the interface. Further, the reflections from the bottom of the bonded layer can be reflected back from the bonded-layer substrate interface. A few of the reflections distances will be 2 ^^^^, 2( ^^^^+ ^^^^), 4tw, 4( ^^^^+ ^^^^). The two time-difference based clocks can be derived at frequencies.

[0080] Locking the RF frequency used to a point where two reflections are of equal amplitude is another approach. Equal amplitudes for multiple reflections can also be achieved using diffraction properties of waves. The net diffraction from the outer and inner transducers and multiple reflections can lead to an optimal set of inner radii and the outer two radii of the Page 18 of 28 18064335.v2-7 / 10 / 24donut-like transducer pair to equalize the amplitudes of two or more reflections. Since the diffraction angles and the overlap of the transducers with the diffracted fields are a function of the carrier frequency, the ultrasonic frequency of the pulses is likely to change the amplitudes of reflections. In many cases, the amplitude of one reflection decreases while the amplitude of the second reflection will increase.

[0081] Many transducer combinations have been observed to have equal amplitudes of reflections at specific frequencies, as seen in FIG. 15. A CMOS circuit can be designed that measures the relative amplitude of the two reflections and adjusts the frequency such that the amplitudes remain equal even as temperature is varied. For example, an exemplary circuit such as that seen in FIG. 16 can be designed such that the first reflection is rectified, and its maximum amplitude is stored in a capacitor though a transistor-based sample / hold circuit (SA / D1 / C1 and SB / D2 / C2) using diodes and capacitors. Each reflection can be stored in different capacitors gated by transmission gates. These capacitors will be connected to the inputs of a differential amplifier that amplifies the difference between the two inputs only when the differential amplifier is enabled through the enabling series NMOS transistor in series with the diff-amp tail current transistor (M6). The switch SC is used to gate the resulting output through a diode ^^3into the C3 capacitor. The initial value into C3 can be set by the voltage divider R1 / R2 through switch SD.

[0082] Initially switches S3, and S4, in parallel with C1 and C2 respectively, will be turned on to discharge the charges on C1 and C2. The timing of S3 / S4 will be to turn on and off for a time period suitable to discharge the capacitors, some time before the expected timing of the first reflection. The timing of the signals would follow every cycle where S1 is turned on during the expected time frame of the first reflection turning on some time before and turning off some time after the expected first reflection. This timing doesn’t need to be accurate as it will only let the pulse coming in to charge the circuit (Fig 18). The signal S2 will be timed to turn on when the second reflection is arriving. Then, ^^^^signal will be turned on to power enable the differential amplifier such that the difference is computed by the differential amplifier and presented at the input of the switch ^^^^. The signal ^^2will then be turned on to present the new computed voltage to C3 through ^^^^and diode ^^3which in turn is connected to the fine control line of the RF-VCO. The output of the diff-amp ^^^^ ^^will be between ^^^^ ^^and ground around 0.8 V given the typical power supply voltage will be 1.2V. The diode-drop across ^^3will subtract from this voltage to store on ^^3. ^^^^is tuned on briefly to charge ^^3and then turned off for the next calibration cycle. The timing between ^^1, ^^2, ^^3, ^^4, ^^5, ^^^^ ^^ ^^, can be Page 19 of 28 18064335.v2-7 / 10 / 24controlled by inverters and RC delays to present the signals to enable the capturing and sampling the signals. Although the RC time constant may change over temperature, the changes will be small enough to allow the capturing of the reflecting pulses as long as the turn and off times are chosen with sufficient time buffers around the pulse times. The differential amplifier can be implemented such that the DC offsets due to mismatches in the transistors can be reduced by auto-zeroing bias capture circuits. The voltage drooping on C1 and C2 can be equalized by sizing the transistor M7 and M8 so that the two voltages on the diff-amp input when M6 is turned on are equal.

[0083] The ultrasonic carrier frequency generated by the RF VCO can be written as:Here ^^^^ ^^ ^^ ^^ ^^ ^^is the coarse voltage control coefficient, ^^^^ ^^ ^^ ^^is the fine control voltage, ^^^^ ^^ ^^ ^^ ^^ ^^is the input for controlling the VCO at coarse level potentially using a resistive voltage divider. The voltage ^^^^1 ^^2is the difference in voltage of the two ultrasonic reflections.

[0084] The ^^0is a base frequency of the VCO set primarily by transistor sizing and added or parasitic capacitances within the VCO. ^^^^ ^^ ^^ ^^ ^^ ^^is the VCO scale factor that can be set by a resistive divider (R3 / R4). These resistors (R3 / R4) could be resistors fabricated on top of the CMOS and piezoelectric stack such that the resistors can sbe laser trimmed to initialize the initial frequency to be at a desired value.

[0085] Due to the diffraction effect on the reflected pulse amplitudes on the receiving transducers, as the amplitude on one receiving electrode pulse rises, the amplitude of the second pulse can decrease or increase with a different frequency dependence, while still have a common frequency at which the two amplitudes are equal. In this case, the peak reflection of each pulse can be modeled as a linear function of frequency around the frequency where the two reflections are of equal amplitude. The two peak voltages of the devices can be modeled as:The corresponding values are sketched in FIG. 17. The two amplitudes will be equal when

[0086] There are several possibilities of the sign of ^^1and ^^2depending on the way the two reflections change in amplitude versus frequency. The signs for ^^1 and ^^2 can be the same or different depending on the way the curves intersect as seen in four cases of FIG.16. Page 20 of 28 18064335.v2-7 / 10 / 24

[0087] Every transmit / receive pulsing cycle will produce an output from the differential amplifier as ^^^^ ^^= ^^^^ ^^∗(^^1− ^^2)∗ Δf where ^^^^ ^^is the nominal diffamp gain. Each cycle will change the new operating frequency ^^^^. The incremental change in the frequency at the ^^ + 1th pulse-receive cycle will beFor the error in the frequency from the ideal frequency of equal amplitudes to converge to zero, each successive error should be smaller than the previous leading to the condition that ^^ < 1. This condition leads to ^^^^ ^^ ^^ ^^^^^^ ^^(^^1− ^^2)< 1. Depending on the signs of ^^1and ^^2^^^^ ^^ ^^ ^^can be chosen and designed into the RF-VCO to maintain a positive and less than unity value for ^^.

[0088] From experimental values, we have measuredand ^^2in order of 10 mV / MHz. ^^^^ ^^can be in the range of 10-20, and ^^^^ ^^ ^^ ^^can be in the range of MHz / V leading to ^^ in 0.1 to 0.2.

[0089] The cycles of using the transmit receive of pulses can be used to find the ideal carrier frequency ^^^^as described above after a certain number of cycles where the carrier frequency is locked. The lock condition can be detected by implementing a second differencing circuit that subtracts consequent ^^^^ ^^values to determine if the difference is below a threshold voltage through a comparator. However, if ^^ is sufficiently less than 1, convergence to the correct operating point will occur within a few frequency calibration cycles. Meanwhile, the ultrasonic T / R cycles to lock to the local oscillator can be implemented after the frequency is locked or interspersed between frequency correcting cycles (Fig. 18). The transistor circuit shown in Fig.16 show transmission gate ^^ ^^, ^^4and ^^4to gate the output of the RF amplifier from the receiving transducer into the comparator generating the digital signals corresponding to the chosen two receiver signals to lock to the local oscillator as described in sections above.

[0090] A device that consists of two oscillators connected to each other may be seen in FIG. 19. One oscillator consists of a low frequency oscillator which has high accuracy but higher phase noise, while a second oscillator that has high Q and low phase noise but lower accuracy. The first oscillator is a BAW pulse packet delay line oscillator (BPP-DLO), that relies on pulse transit time between top and bottom surfaces of a silicon chip. Various schemes have been developed to improve the temperature stability of the BPP-DLO. On the same chip an FBAR resonator-based oscillator (FBO) is created. A trench maybe needed (FIG. 20) Page 21 of 28 18064335.v2-7 / 10 / 24between the BPP-DLO and the FBAR device to prevent mechanical elastic waves to be coupled between the two, firas the FBAR oscillator can radiate some elastic waves through its anchors, which can reach the bulk transducers of the BPP-DLO. The frequency of this oscillator can be in the GHz range. For further isolation of the two components, an absorptive layer can be patterned on the back side of the clock chip to absorb all energy in areas other than where the reflection for the BAW delay line needs to occur (FIG.19 and FIG.20).

[0091] Recently CMOS integrated processes have been implemented that enable piezoelectric thin films integrated with CMOS. In particular, in these process flows the release layer enables both FBAR resonators and BAW transducers (FIG. 21). A very compact high frequency oscillator can therefore be fabricated where the BPP-DLO and FBO are intimately placed close to each other to reduce footprint on a CMOS chip. However, it is possible that the energy lost though the anchors of the base of the resonator can enter the bulk substrate and may affect the BPP-DLO. Hence, ultrasonic frequency of the BPP-DLO would be chosen to be different than the FBAR frequency by having different stacks for the piezoelectric stacks.

[0092] In order to lock the FBO to the BPP-DLO, the output of the FBO is then divided down and phase locked to the BPP-DLO using a phased locked circuit. The electronics needed to sustain the BPP-DLO and the FBO can be monolithically integrated on one substrate, per recent advances in integrating both released and unreleased piezoelectric devices on top of CMOS substrates as described above. Alternatively, the CMOS chips can be a separate chip with the MEMS chips with FBAR and BAW transducers are separately driven, where the BAW transducers and the FBAR devise can be on the same MEMS die or on two separate dies. The MEMS dies can be bonded to the CMOS chip by flip-chip bonding or by wire-bonding.

[0093] The effective Q of a BPP-DLO can be estimated as the number of wavelengths that can fit within the transmit path. This is because the pulses travel this distance. Given the typical wafer thickness of 600um and the wavelength ~4um at 1.87 GHz provides ~ 150*2 wavelengths from transmit to receive. This effective Q is ~300. In contrast the Q of FBAR resonators can be several thousand producing much lower phase noise. The error in frequency between the BAW delay-line oscillator and the FBAR oscillator will generate a voltage or current that can be used to adjust the frequency of the FBAR oscillator. This adjustment can be implemented by placing a series or parallel tunable capacitor with the FBAR oscillator or applying a DC bias on piezoelectric film (https: / / ieeexplore.ieee.org / document / 4389166). The PLL filter would be chosen such that the frequency variations due to phase noise of the BPP- DLO are reduced enough to center the FBAR oscillator frequency. Page 22 of 28 18064335.v2-7 / 10 / 24

[0094] The previous BPP-DLO that are patented use one transducer for transmitting and receiving. In the implementation described in this patent, the noise of the BPP-DLO would potentially need to be decreased further to decrease the jitter. In order to reduce the noise, the SNR of the receiver and transmitter of the RF pulses on the piezoelectric transducers needs to be increased. A higher SNR on the receiver leads to less noise compared to the signal, which improves the stability of the time at which a comparator is activated comparing the input signal and a threshold voltage. To increase the signal at the receive side, an array of transmit transducers will be driven simultaneously by an array of amplifiers, and the receive transducers piezoelectrically induced displacement currents would be added together into a single TIA as seen in FIG.22, to increase the current by N, while increasing the noise only by √N. While the noise from each channel would average out, to achieve higher signal and SNR, this gain would occur at the cost of higher power and chip area.

[0095] While various embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the teachings is / are used. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, embodiments may be practiced otherwise than as specifically described and claimed. Embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0096] The above-described embodiments of the described subject matter can be implemented in any of numerous ways. For example, some embodiments may be implemented using hardware, software or a combination thereof. When any aspect of an embodiment is implemented at least in part in software, the software code can be executed on any suitable Page 23 of 28 18064335.v2-7 / 10 / 24processor or collection of processors, whether provided in a single device or computer or distributed among multiple devices / computers. Page 24 of 28 18064335.v2-7 / 10 / 24

Claims

CLAIMS What is claimed is:

1. An oscillator having minimized dependence on temperature, comprising: a first piezoelectric transducer positioned on a substrate formed from a material having a first temperature coefficient of frequency; an RF voltage-controller oscillator having an output coupled to the first piezoelectric transducer; a local voltage-controlled oscillator configured to gate the output from the RF voltage-controlled oscillator to the first piezoelectric transducer so that a first plurality of short pulses are generated into the substrate; a second piezoelectric transducer positioned on the substrate and spaced apart from the first piezoelectric transducer to receive the plurality of short pulses after the plurality of short pulses have reflected through the substrate; and a detection circuit configured to generate a signal representing a time period between two of the plurality of short pulses received by the second piezoelectric transducer.

2. The oscillator of claim 1, further comprising a layer of a second material having a second temperature coefficient that is different than the first temperature coefficient positioned on the substrate.

3. The oscillator of claim 2, wherein the second material is selected from the group consisting of fused silica, highly doped silicon, sapphire, and glass compositions with positive temperature of coefficient for speed of sound.

4. The oscillator of claim 2, further comprising a counter that is incremented according to the receipt of the plurality of short pulses through one of the substrate and the at least one layer and that is decremented according to the receipt of the plurality of short pulses according to the passage of the plurality of short pulses of pulses through the other of the silicon wafer and the at least one layer.

5. The oscillator of claim 4, wherein the detection circuit comprises: an RF envelope detector coupled to the second piezoelectric transducer and configured to convert the plurality of short pulses to an amplified signal; and a comparator coupled to the RF envelop detector and configured to digitize the amplified signal and add temperature-dependent and programmed fixed delays.

6. The oscillator of claim 5, wherein the second layer has a thickness selected so that a first transit time of the series of pulses through the substrate will be compensated by a Page 25 of 28 18064335.v2-7 / 10 / 24second transit time of the series of pulses through the second material with the second temperature coefficient.

7. The oscillator of claim 6, wherein the second material is fused silica.

8. The oscillator of claim 7, wherein the layer is bonded to the substrate.

9. The oscillator of claim 8, wherein the layer is bonded to the substrate by an adhesive layer.

10. The oscillator of claim 9, wherein the adhesive layer is patterned so that the adhesive layer is not positioned in any location where the plurality of short pulses will be reflected.

11. The oscillator of claim 8, where the adhesive layer has a thickness selected to control the reflection and transmission of the plurality of pulses across the substrate and the layer of fused silica.

12. The oscillator of claim 5, wherein the first piezoelectric transducer is configured so that two or more of the reflections of the series of pulses traversing the silicon wafer and the layer will have equal amplitude.

13. The oscillator of claim 5, wherein the first piezoelectric transducer comprises an outer ring portion and the second piezoelectric transducer comprises an inner circular portion such that the amplitude of two or more of the short pulses are equal.

14. The oscillator of claim 5, wherein the RF voltage-controlled oscillator is configured to generate an RF frequency such that two or more of the reflections of the plurality of short pulses traversing the silicon wafer and the layer will have an equal amplitude.

15. The oscillator of claim 5, wherein the RF envelop detector includes a differential amplifier for amplifying a voltage of any reflections of the plurality of short pulses and for locking to a frequency where the amplitudes of two reflections of the plurality of short pulses are equal.

16. The oscillator of claim 5, further comprising a capacitor for storing an output of the differential amplifier and an initial voltage received from the RF voltage-controlled oscillator.

17. The oscillator of claim 16, wherein a nominal value of an output of the RF voltage-controlled oscillator is set by a voltage divider.

18. The oscillator of claim 17, wherein voltage divider is formed from a plurality of resistors that define an initial bias for the RF voltage-controlled oscillator. Page 26 of 28 18064335.v2-7 / 10 / 2419. An oscillator system, comprising: a first oscillator positioned on a substrate and having a first frequency, a first accuracy, a first phase noise; a second oscillator positioned on the substrate and having a second frequency, a second accuracy, a second phase noise; wherein the first frequency is lower than the second frequency, the first accuracy is higher than the second accuracy, and the first phase noise is higher than the second phase noise; and wherein the first oscillator is a BAW pulse packet delay line oscillator and the second oscillator is a FBAR resonator-based oscillator.

20. The oscillator system of claim 19, wherein second frequency is adjusted by phased-locked-loop locking of the second oscillator with the first oscillator.

21. The oscillator system of claim 20, wherein the first oscillator and the second oscillator are formed monolithically and phase-locked-loop locked using a plurality of CMOS transistors in the substrate.

22. The oscillator system of claim 21, wherein the first oscillator comprises an array of transmit transducers that are driven in parallel and an array of receive transducers having an array of outputs fed to a single amplifier. Page 27 of 28 18064335.v2-7 / 10 / 24

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