Size generalization of error codes for quantum error correction

Abstract

Methods, systems and apparatus for implementing quantum error correction codes based on offset-defined stabilizers. In one aspect, a number of n offsets are determined. Measure qubits are partitioned into odd columns and even columns. For measure qubits, and for each odd column measure qubit, a stabilizer over data qubits reached by adding each of the n offsets to the measure qubit position is measured. For each even column measure qubit, one or more of the n offsets are negated and a stabilizer over data qubits reached by adding each of the one or more negated n offsets to the measure qubit position is measured.

Description

[0001] SIZE GENERALIZATION OF ERROR CODES FOR QUANTUM ERROR CORRECTION

[0002] BACKGROUND

[0003] This specification relates to quantum computing.

[0004] Quantum computing provides a means to solve certain problems that cannot be solved in a reasonable period of time using conventional classical computers. These problems include factoring very large numbers into their primes and searching large, unstructured data sets. A number of physical systems are being explored for their use in quantum computing, including ions, spins in semiconductors, and superconducting circuits. However, these systems do not perform sufficiently well to serve directly as computational qubits. For example, single two-state physical systems, which can be used as physical qubits, cannot reliably encode and retain information for long enough to be useful, e.g., due to noise.

[0005] Quantum error correction is a technology that can enable a quantum computer to reliably execute a quantum algorithm despite noise afflicting its qubits. A decoder is a key component of quantum error correction schemes whose role is to identify errors faster than they accumulate in the quantum computer. The decoder takes as an input a syndrome, which is measurement data extracted from quantum parity check measurements, and returns as output an estimation of error. Given this estimation, the effect of the error can be reversed. Decoders should be implemented efficiently in order to scale to the regime of practical applications of quantum computing.

[0006] Certain error correcting codes have fixed sizes. The constructions are created by establishing polynomials over finite fields, which produce permutation matrices, which are mapped onto a toroidal surface. The codes that appear related but at different sizes can end up with very different polynomials. Such code schemes, accordingly, would be benefit from size generalization such that they could be scaled in size up or down, so that a family of codes could be used.

[0007] SUMMARY

[0008] This specification describes size generalization of error correcting codes, and in particular low-density parity check codes.

[0009] One innovative aspect of the subject matter described in this specification can be implemented in a method that includes determining a number of n offsets; for measure qubits, wherein the measure qubits are partitioned into odd columns and even columns: for each odd column measure qubit, measuring a stabilizer over data qubits reached by adding each of the n offsets to the measure qubit position, for each even column measure qubit, negating one or more of the n offsets and measuring a stabilizer over data qubits reached by adding offsets comprising each of the one or more negated n offsets to the measure qubit position.

[0010] Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical computers and quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0011] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination.

[0012] In some implementations the number of offsets comprises a first set of offsets and a second set of offsets, and the method further comprises for each odd column measure qubit, measuring a stabilizer over data qubits reached by adding each offset of the first set of offsets to the measure qubit position; and for each even column measure qubit, measuring a stabilizer over data qubits reached by adding each offset in a second set of offsets to the measure qubit position, wherein the second set of offsets comprises one or more of: negations of the first set of offsets, rotated versions, mirrored versions, or independently defined offsets based on stabilizer type or code geometry

[0013] In some implementations the method further includes generating, from the measurements, codes for error correction.

[0014] In some implementations the method further comprises determining, in a control circuit of a quantum processor implementing a quantum error correction code, a configuration of physical qubits using the n offsets, comprising determining qubit interaction patterns for stabilizer measurements for the quantum error correction code; and executing, by the quantum processor, the control circuit.

[0015] In some implementations the stabilizers are measured over the data qubits in parallel with a quantum computation executed on logical qubits encoded by the quantum error correction code.

[0016] In some implementations determining the number of n offsets comprises: in response to determining that at least one of: boundary conditions for the quantum error correction code differ to predetermined base boundary conditions; a connectivity graph of the quantum processor differs to abase connectivity graph associated with the predetermined base boundary conditions; and physical qubit spacing in the quantum processor differs to a base physical qubit spacing, modifying a set of base offsets stored in a memory accessible to the control circuit of the quantum processor, comprising mapping each offset to a valid data qubit position according to the predetermined base boundary’ conditions.

[0017] In some implementations modifying the set of base offsets compnses one or more of: applying modulo wrapping of offset coordinates; rotating or mirroring the offsets; scaling the offsets to match a physical qubit spacing; removing offsets exceeding a stabilizer weight limit; or remapping offsets to match a connectivity graph of the quantum processor.

[0018] In some implementations the predetermined base boundary conditions comprise: toroidal boundary conditions wherein qubit positions wrap around in at least one lattice dimension according to a modulo operation; or planar boundary’ conditions in which qubit positions at edges of a lattice are truncated or replaced to remain within valid lattice coordinates.

[0019] In some implementations determining the number of n offsets comprises retrieving a set of base offsets from a memory accessible to a control circuit of the quantum processor and using the base offsets without modification for lattice configurations of different sizes.

[0020] In some implementations the qubit interaction patterns comprise: a first set of interaction patterns for odd column measure qubits, wherein each first set interaction pattern specifies data qubits reached by adding n offsets to a position of a respective odd-column measure qubit; and a second set of interaction patterns for even column measure qubits, wherein each second set interaction pattern specifies data qubits reached by adding offsets comprising the one or more negated n offsets to a position of a respective even column measure qubit.

[0021] In some implementations the measure qubits are physical qubits arranged on a lattice that comprises integer coordinate positions (x. y), wherein the odd columns comprise columns in the lattice with an odd column index x and the even columns comprise columns in the lattice with an even column index x.

[0022] In some implementations the measure qubits are arranged with data qubits in a checkerboard pattern on the lattice, the data qubits comprising physical qubits, wherein measure qubits in odd columns are assigned to X-basis stabilizers and measure qubits in even columns are assigned to Z-basis stabilizers. In some implementations the method further comprises processing results of measuring the stabilizers in a quantum error correction decoder to identify error syndromes and determine, using the error syndromes, corresponding correction operations to be applied to physical qubits of a quantum processor performing the quantum error correction code or Pauli frames in control software of the quantum processor.

[0023] In some implementations the number n of offsets is equal to a quantum error correction code stabilizer weight, the stabilizer weight defining a number of data qubits entangled with each measure qubit during each stabilizer measurement.

[0024] In some implementations the n offsets comprise a combination of short-range offsets to nearest-neighbor data qubits and long-range offsets to non-nearest-neighbor data qubits.

[0025] In some implementations the n offsets comprise integer coordinate pairs, each coordinate pair identifying a relative position of a data qubit to be entangled with a given measure qubit.

[0026] In some implementations the quantum error correction code comprises a low-density parity check code.

[0027] The subject matter described in this specification can be implemented in particular ways so as to realize the following advantages.

[0028] Examples of the present disclosure provide technical improvements to the operation of quantum computing systems, particularly in implementing and scaling quantum error correction codes. These improvements address challenges in configuring, controlling, and decoding large-scale quantum systems with limited hardware resources and connectivity constraints.

[0029] For example, examples of the present disclosure define the stabilizer structure of the quantum error correction code is using a set of relative offsets between measure qubits and data qubits. Because these offsets define the interaction pattern based on relative positions rather than absolute coordinates or global algebraic structures, such as polynomial fields or parity check matrices over GF(2), the same set of offsets can be reused across different lattice sizes and topologies. This offset-based construction inherently supports scalable deployment of error correction codes across lattices of varying dimensions, which reduces the need for recalculating or recompiling the code structure for each physical hardware instance. This contrasts with conventional implementations that require customized stabilizer definitions or algebraic generator matrices for each code size, resulting in computational and memory overhead.

[0030] As another example, example of the present disclosure enable dynamic adaptation of stabilizer interaction patterns based on hardware constraints, such as qubit spacing, lattice boundary conditions, or limited qubit connectivity. In particular, stored set of base offsets can be modified to apply modulo-based coordinate wrapping (e.g.. for toroidal boundary conditions), apply geometric transformations (e.g., rotations or reflections) to match physical qubit layouts, or scale offset vectors to accommodate different physical qubit spacings. These capabilities allow the control circuitry of a quantum processor to generate valid stabilizer measurement patterns on irregular or resource-constrained topologies without requiring hardcoded gate sequences. The ability to remap offsets while preserving code distance and stabilizer weight enables error correction to be implemented on a broader class of physical quantum hardware.

[0031] As another example, examples of the present disclosure facilitate the automated execution of stabilizer measurements through control circuitry configured to apply interaction patterns derived from offsets. The system partitions measure qubits into odd and even columns, and applies the offsets (or their negation) accordingly. This enables uniform and parallelizable execution of stabilizer circuits by the quantum processor, reducing latency and synchronization complexity during quantum error correction cycles. Furthermore, the use of compact offset sets simplifies hardware instruction sets for qubit control and stabilizer scheduling.

[0032] As another example, the presently described offset-based representation of stabilizers naturally aligns with the detector graph model used in modem decoding algorithms, such as minimum-weight perfect matching (MWPM) and union-find decoding. The relative offset formulation directly corresponds to edges in a detector graph, enabling efficient compilation and streaming of syndrome information to a classical decoder. The system can thus reduce the latency between error detection and correction, improving fault-tolerance thresholds and logical qubit fidelity in practical devices.

[0033] The presently described methods and systems there improve the configurability, portability, and scalability of quantum error correction on real-world quantum computing hardware, In addition, the methods and systems enable more efficient use of classical control systems, reduced memory and computation requirements for code compilation, and lower- latency decoding during active quantum computation.

[0034] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example computing system for decoding a quantum error correcting code.

[0036] FIG. 2 is a flowchart of an example process for correcting errors in a quantum computation using a quantum error correction code, e.g., LDPC code.

[0037] FIG. 3 depicts an example quantum computer for performing the quantum operations described in this specification.

[0038] DETAILED DESCRIPTION

[0039] This specification describes systems and methods for implementing quantum error correction codes based on offset-defined stabilizers. The codes described in examples of the present disclosure are constructed from a set of n offsets, e.g., 1, -1, i, -i, -3+6i. and 6-3i. where n = 6. Other values of n and offsets can be used. These create a checkerboard pattern of data and measure qubits, with the odd-column measure qubits being X type and the evencolumn measure qubits being Z type. Each X type measure qubit measures a stabilizer over the data qubits reached by adding each of the n offsets to its position. The same principle applies for the Z type, except one or more of the offsets can be negated, rotated versions, mirrored versions, or independently defined offsets based on stabilizer type or code geometry'. This construction produces the same codes, but without involving the polynomials or the permutation matrices, and the same offsets are used for the codes that look like they should be related. By choosing some offsets, and growing the grid to larger and larger sizes, a family of codes is produced for that choice of offsets.

[0040] FIG. 1 is a block diagram of an example computing system 100. The example computing system 100 is an example of a system implemented as classical and quantum computer programs on one or more classical computers and quantum computing devices in one or more locations, in which the systems, components, and techniques described herein can be implemented.

[0041] The example computing system 100 includes a quantum computing device 102 and a classical processor 104. For illustrative purposes, the quantum computing device 102 and classical processor 104 shown in FIG. I are illustrated as separate entities, however in some implementations the classical processor 104 may be included in the quantum computing device 102. For example, in some implementations the quantum computing device 102 can be directly connected to the classical processor 104. In other implementations, the quantum computing system 102 can be connected to the classical processor 104 through a network, e.g., a local area network (LAN), wide area network (WAN), the Internet, or a combination thereof.

[0042] The quantum computing device 102 includes components for performing quantum computation. For example, the quantum computing device 102 can include a quantum data plane that, in turn, includes multiple physical qubits, a control and measurement plane that is configure to perform operations and measurements on the physical qubits, a control processor plane that is configured to determine sequences of operations and measurements that a quantum algorithm being performed by the quantum computing system requires, and a classical computer that is in data communication with the control processor and facilitates user interactions and access to networks or storage. The particular type of the quantum computing device 102 can depend on the type of qubit used. In some implementations the qubits can be superconducting qubits, semiconducting qubits, photonic qubits, or atom-based qubits. For example, the qubits can include Xmon qubits, flux qubits, phase qubits, CAT qubits, or qubits with frequency interactions.

[0043] Typically, quantum computations performed by the quantum computing device 102 will be noisy due to the unavoidable presence of errors caused by, e.g.. unwanted interactions between qubits, unwanted interactions with the environment (causing decoherence), faulty quantum gates or operations, or errors in the state preparation or measurement process. Example types of errors include coherent errors that act on single qubits, e.g., Pauli X-type errors called bit-flip errors that map the qubit basis states X|0) = | l)and X| 1) = |0) and Pauli-Z errors called phase-flip errors that map the qubit basis states Z|0) = |0) and Z| l) = — 11). Noise in a quantum computing device can be represented by an error model, e.g., independent error models as described in more detail below. Example sources of noise include crosstalk between neighboring qubits, thermal fluctuations, spontaneous emission, and pulse calibration errors. If left unchecked, errors can destroy quantum information and render quantum computations performed by the quantum computing device 102 useless.

[0044] Therefore, the quantum computing device 102 can be configured to execute a quantum error correcting code 106 when performing quantum computations, e.g., the quantum error correcting codes described in this specification. Quantum error correcting codes encode a first number k of qubits (a Hilbert space of dimension 2k) into a second number n of qubits (a Hilbert space of dimension 2n). w here the second number is larger than the first number, i.e.. n > k. The k qubits are data qubits that store logical information and are to be protected from error. The additional n ~ k qubits are ancilla or measure qubits that are used to detect and identify physical errors. In general, the size and overhead of the quantum error correction code (e.g.. the ratio n / k, the weight of stabilizers, and the code distance) can determine the error suppression capability and the physical qubit resources required.

[0045] Example quantum error correcting codes include stabilizer codes, e.g., Calderbank- Shor-Steane (CSS) codes, the surface code, and various types of low-density parity-check (LDPC) codes. LDPC codes include quantum analogs of classical LDPC codes where the parity-check matrices are sparse and can scale to support hundreds or thousands of physical qubits with relatively low stabilizer weight (e.g., 4 or 6). These codes include hypergraphproduct codes, lifted product codes, bicycle codes, and homological product codes, each using different algebraic constructions to define stabilizers.

[0046] In stabilizer codes implemented on lattices (such as surface codes or planar LDPC codes), the structure of each stabilizer can be defined by a set of offsets relative to a central measure qubit. Each offset specifies a relative coordinate (e.g., Ax, Ay) to a data qubit involved in the stabilizer. In some conventional approaches — particularly for algebraic LDPC constructions — the stabilizers and corresponding data qubit locations are implicitly defined over finite fields or polynomial rings, using algebraic relations to generate valid parity-check matrices. For example, the adjacency of qubits can be defined via cyclic shifts or multiplicative polynomials over GF(2m), which allows analytical specification of codes with specific girth and distance properties. However, such methods typically require fixed global lattice sizes and specialized decoder structures.

[0047] In contrast, the present disclosure describes systems and techniques in which stabilizers are constructed using explicit offset sets that define the relative position of data qubits entangled with each measure qubit. These offset sets can be stored in a base offset datastore 108 and reused across multiple lattice sizes, enabling scalable code families (e.g., distance-c / surface codes) without recalculating the stabilizer structure from scratch for each new size. This enables flexible deployment of quantum error correction codes on physical quantum processors with different topologies, spacings, and hardware constraints, including rotated or planar surface codes, Toric codes, and hybrid variants such as XZZX codes or heavy -hex / square configurations.

[0048] The surface code encodes a logical qubit into a patch of multiple physical qubits on a lattice, e.g., a square or hex grid. The lattice includes alternating data qubits and ancilla qubits, where a qubit is placed on each edge of the lattice. The code is defined to be the ground space of the Hamiltonian where V represents vertices of the lattice, F represents faces defined by edges connecting vertices of the lattice, the operator Xvis associated with vertex v and is a product of Pauli-X matrices acting on edges incident to v, and the operator Zf is associated with face f and is a product of Pauli-Z matrices acting on all edges of f. The code space is defined as the simultaneous “+1” eigenstate of the operators Xvand Zf. These operators (or products of these operators) are called the stabilizers of the code. When an error has affected the qubits of the code, any stabilizer that anti-commutes with the error returns a “-1” measurement outcome. A subset of vertices with -1 measurement outcomes is called a syndrome cr. The syndrome <J can be used to determine a correction operator that, when applied to the code, corrects the error up to a stabilizer.

[0049] During execution of the quantum error correcting code 106, the quantum computing device 102 is configured to provide measurement data 110 to the classical processor 104. The measurement data 110 can be received as a batch or stream of data. The measurement data 110 includes classical measurement outcome bits, e.g.. corresponding to stabilizer measurements. In the present disclosure, a detector is a parity of measurement outcome bits that is deterministic in the absence of errors. The outcome of a detector measurement is 1 if the observed parity differs from the expected parity for a noiseless computation, and is 0 otherwise. A Pauli-type error P is said to flip a detector D if including P in the circuit changes the outcome of D, and a detection event is a detector with outcome 1. A logical observable is a linear combination of measurement bits, whose outcome corresponds to the measurement of a logical Pauli operator.

[0050] The classical processor 104 includes components for performing classical computations. For example, the classical processor 104 can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0051] The classical processor 104 implements a decoder 112 that is configured to process measurement data 110 received from the quantum computing device 102 to decode the measurement data, i.e., predict which errors may have occurred during the quantum computation performed by the quantum computing device 102. To process the measurement data 110, the decoder 104 is configured to execute a decoding algorithm 114 (also referred to herein as a decoding process) that maps the decoding problem onto a graph problem using a graph-like error model for the quantum error correcting code 106.

[0052] A graph-like error model is an independent error model, i.e., a set of m independent error mechanisms, where error mechanism i occurs with probability p[i] (where p G Rmis a vector of priors), and flips a set of detectors and observables. In a graph-like error model, each error mechanism flips at most two detectors. Graph-like error models can be used to approximate common noise models for many important classes of quantum error correction codes including surface codes, for which X-type and Z-type Pauli errors are both graph-like.

[0053] A graph-like error model is represented by a detector graph of nodes and edges G = (V, E). e.g., detector graph 116. Each node v G V in the detector graph corresponds to a detector. Each edge e G E is a set of detector nodes of cardinality one or two representing an error mechanism that flips this set of detectors. The set of edges E can be decomposed as E - E1(J E2where for each edge e in E}. |e| = 1 and for each edge e in E2, |e| = 2. A regular edge e = (u, v) G E2flips a pair of detectors u, v G E, whereas a half-edge (u, ) G E, flips a single detector u G V. A half-edge can be connected to a boundary of the detector graph , in which case the edge can be defined as (u, vb) where vbis a virtual boundary' node (which does not correspond to any detector). In some implementations, e.g., when the graph problem is solved using minimum weight perfect matching, each edge can be assigned a weight that is determined by a respective error probability, e.g., w(e =1OgEach edge can also be labelled with a set of logical observables that are flipped by the error mechanism, which is denoted either by / (gj) or l(u, v) for e — (u,, v) G E. The distance D(u, v) between two nodes u and v in the detector graph is equal to the length of the shortest path between them.

[0054] Example decoding algorithms include minimum weight perfect matching (MWPM) and union find. MWPM decoding processes determine a most probable physical error consistent with syndromes in the measurement data. Detection events in measurement data are identified and labelled in the detector graph. A minimum weight embedded matching of the detection events in the detector graph is then determined, where an embedded matching of a set of detection events is a set of edges in the detector graph where each node corresponding to a detection event in the set of detection events is incident to an odd number of edges in the set of edges and each node that does not correspond to a detection event in the set of detection events is incident to an even number of edges in the set of edges. In conventional implementations of MWPM decoding processes, Edmond’s blossom algorithm is used to determine the embedded matching, e.g., by seeding clusters of nodes in the detector graph using the detection events and growing, shrinking, or freezing the clusters until the minimum weight embedded matching is obtained. The embedded matching is used to determine a prediction of which logical observable measurements were flipped, which can in turn be used to determine a correction operator that, when applied to the quantum error correcting code 106, corrects the errors.

[0055] Union find decoding processes can be viewed as an approximation of minimum weight perfect matching decoding processes. A union find decoding process identifies detection events in measurement data and seeds clusters of nodes in the detector graph using the detection events. The clusters are then iteratively grown in the detector graph until the parity of the cluster changes. A so-called peeling step is then performed. A spanning tree for each grown cluster is generated and estimations of error are computed by traversing the spanning trees in reverse order. A correction operator that, when applied to the quantum error correcting code 106, corrects the errors is then determined.

[0056] After the decoder 112 has completed decoding, the classical processor 104 is configured to output a correction operator 118. The correction operator 118 can be applied to the quantum error correcting code 106 to correct the errors identified by the decoder 112.

[0057] In combination, the quantum computing device 102 and classical processor 104 implement a full-stack architecture for fault-tolerant quantum computation, capable of detecting, decoding, and correcting errors in real time to maintain logical fidelity over extended quantum operations.

[0058] FIG. 2 is a flowchart of an example process 200 for correcting errors in a quantum computation using a quantum error correction code, e g., a LDPC code. For convenience, the process 200 will be described as being performed by a system of one or more classical computing devices and one or more quantum computing devices located in one or more locations. For example, system 100 of FIG. 1, appropriately programmed in accordance with this specification, can perform the process 200.

[0059] The system determines one or more requirements of the quantum computation to be performed (step 202). For example, the system can determine one or more target performance metrics, e.g., a target logical error rate, a number of logical qubits to be encoded, and a maximum allowable execution time for the computation. These performance metrics can be provided as input to the system, e.g., as user input. The system uses the target performance metrics to select a suitable code distance or lattice size for the quantum error correction code. The system then maps the quantum computation to available hardware resources of the quantum processor (step 204). The mapping is performed in view of the lattice size or code distance identified in step 202, ensuring that the selected quantum error correction code can meet the target performance metrics when implemented on the given hardware. For example, the system can determine a number of available physical qubits included in the quantum processor, identify a connectivity graph that specifies which physical qubits can be entangled, and select applicable boundary conditions for the lattice, e.g., toroidal or planar boundaries. The characteristics of the hardware constrain the geometries and sizes of the quantum error correction codes that can be implemented on the quantum processor, and can require adjustments to the lattice size or layout determined in step 202 to fit within limits of the hardware.

[0060] The system then selects an appropriate quantum error correction code for the computation (step 206). In some implementations, the selected code can be implemented on a checkerboard-pattern lattice of measure qubits and data qubits, e.g., a two dimensional or three dimensional lattice. The lattice can define integer coordinate positions (x, y), where odd columns of qubits in the lattice are columns in the lattice with an odd column index x and even columns in the lattice are columns in the lattice with an even column index x. In some implementations measure qubits in odd columns are assigned to specific ty pe of stabilizer, e.g., X-basis stabilizers and measure qubits in even columns are assigned to a different type of stabilizer, e.g., Z-basis stabilizers. This assignment ensures orthogonality of X- and Z- basis stabilizers in the lattice, and simplifies control sequencing by localizing measurement ty pes to alternating columns.

[0061] In some implementations the quantum error correction code can be a LDPC code, a surface code (planar or rotated), Toric code, or variants thereof (such as a XZZX surface code or a heavy -square or -hex surface code). In these codes, the stabilizer structure can be fully defined by a set of n offsets. The offsets are integer coordinate pairs that each identify a relative position of a data qubit to be entangled with a given measure qubit during a stabilizer measurement. The number of offsets in the set can be equal to a quantum error correction code stabilizer weight that defines the number of data qubits entangled with each measure qubit during each stabilizer measurement. The set of offsets can include short-range offsets to nearest-neighbor data qubits and long-range offsets to non-nearest-neighbor data qubits.

[0062] The system determines, based on the selected quantum error correction code and the available hardware configuration, a number of n offsets for the stabilizer structure of the quantum error correction code and uses the offsets to define qubit interaction patterns implemented by control circuitry of the quantum processor (step 208). In some implementations the qubit interaction patterns can include a first set of interaction patterns for odd column measure qubits, where each interaction pattern in the first set specifies data qubits reached by adding n offsets to a position of a respective odd-column measure qubit. The qubit interaction patterns can also include a second set of interaction patterns for even column measure qubits, where each interaction pattern in the second set specifies data qubits reached by adding a second set of offsets to a position of a respective even column measure qubit. In some implementations, the second set of offsets can include one or more of: negations of the first set of offsets, rotated versions, mirrored versions, or independently defined offsets based on stabilizer type or code geometry. The n offsets can include both nearest-neighbor data qubits and additional longer-range data qubits in specific directions.

[0063] For example, in some implementations each qubit can be located at a complex coordinate on a 2D lattice of size w x h, where the real part represents the x-coordinate and the imaginary' part represents the y-coordinate. Alternatively, the qubit positions can be represented using integer (x, y) coordinate tuples or multidimensional index vectors, depending on the lattice abstraction used by the control system. For a n a distance-5 surface code implemented on a checkerboard lattice, for Z-basis stabilizers defined at positions where x % 2 == 0 (even x) and y % 2 = 1 (odd y), the system can compute data qubit positions as:

[0064] |m + d for d in [1, Ij, -1. -Ij. -3 - 6j, +6 - 3j]].

[0065] This defines a set of 6 relative offsets including four nearest-neighbors and two longer-range connections. Similarly , for X-basis stabilizers, defined at positions where x % 2 == 1 and y % 2 == 0, the system can use the offsets:

[0066] [m + d for d in [1, Ij, -1, -Ij, +3 - 6j, +6 + 3j]].

[0067] These stabilizers likewise use both short- and long-range connections and wrap them to the lattice using a modulo-based function to implement toroidal boundary conditions.

[0068] Because the offsets define the stabilizer structure in terms of relative positions of data qubits with respect to each measure qubit, the set of offsets is not dependent on the absolute lattice dimensions. Therefore, the code construction inherently supports scaling of the lattice size and corresponding code distance without requiring recalculation of new offsets for each implementation of a quantum error correction code. This enables a single stored offset set to generate a family of related quantum error correction codes.

[0069] Therefore, in some implementations the system can retrieve a set of base offsets from a memory accessible to control circuitry of the quantum processor and use the base offsets without modification for lattice configurations of different sizes. For example, the system can use the base offsets in cases where it is determined that the qubit arrangement, connectivity, and boundary conditions (such as toroidal boundary conditions wherein qubit positions wrap around in at least one lattice dimension according to a modulo operation or planar boundary conditions in which qubit positions at edges of a lattice are truncated or replaced to remain within valid lattice coordinates) match those assumed by the base offset set. The base offset sets may be precomputed and stored during system design, or dynamically selected from a library of known configurations matching different code types and boundary conditions. In a Toric code example, offsets for a 5x5 lattice can be directly reused for a 7x7 or 9x9 lattice without modification, because the wrapping behavior and connectivity patterns remain consistent, which allows the system to modularly scale the lattice while preserving code properties.

[0070] In other implementations, the system modifies the set of base offsets stored in the memory accessible to the control circuit of the quantum processor, e.g., implementations where the system determines that at least one of the boundary conditions for the quantum error correction code differ to predetermined base boundary conditions, the connectivity graph of the quantum processor differs to a base connectivity graph associated w ith the predetermined base boundary conditions, or the physical qubit spacing in the quantum processor differs to a base physical qubit spacing.

[0071] To modify the set of base offsets, the system maps each offset to a valid data qubit position according to the predetermined base boundary conditions. For example, the system can apply modulo wrapping of offset coordinates to adapt a toroidal code to a smaller or resized lattice, e.g., if an offset points to a data qubit at position (25, 13) on a lattice of size 24x12, the system wraps the coordinates to (1, 1) using modulo operations. This ensures that stabilizer patterns wrap correctly around the edges of the lattice w hen toroidal boundary conditions are used. As another example, the system can rotate or mirror the offsets to match a rotated or mirrored hardware layout, e.g., if the quantum processor uses a mirrored layout due to hardware wiring constraints, an offset of (x, y) can be mirrored to (-x, y) or (x. -y). F or a 90-degree rotation, the system transforms an offset (x, y) into (-y, x). As another example, the system can scale the offsets to match a physical qubit spacing in hardware with a non-unit qubit separation, e.g., if the physical spacing between qubits is increased to reduce crosstalk or due to fabrication constraints, the offsets (±1. 0), (0, ±1) may be scaled to (±2. 0), (0, ±2) to maintain physical connectivity betw een measure and data qubits. As another example, the system can remove offsets exceeding a stabilizer weight limit imposed by decoder complexity or physical qubit connectivity, e.g., if the decoder or hardware only supports stabilizers involving up to 4 data qubits, but the base offset set includes 6 entries, the system truncates the list to the 4 nearest data qubits, e.g., removing long-range offsets such as (+6. -3) and (-3, -6). As another example, the system can re-map offsets to match a connectivity graph of the quantum processor, especially for irregular or sparse topologies, e.g., in superconducting qubit architectures where only certain nearest-neighbor couplings are available, the system may replace an unreachable offset like (+2, 0) with a reachable alternative such as (+1, +1), provided it maintains the code's distance and stabilizer structure. The remapping respects both the hardware constraints and the logical code properties.

[0072] The system executes the control circuitry (step 210). This includes, e.g., applying control pulses to implement the defined stabilizer measurements on the quantum processor. The control circuitry coordinates entangling operations between measure qubits and corresponding data qubits based on the determined qubit interaction patterns. In particular, for measure qubits, where the measure qubits are partitioned into odd columns and even columns, for each odd column measure qubit, the system measures a stabilizer, e.g., X stabilizer, over data qubits reached by adding each of the n offsets to the measure qubit position. For each even column measure qubit, the system measures a (different) stabilizer, e.g., a Z stabilizer, over data qubits reached by adding another set of n offsets to the measure qubit position. The other set of n offsets can be the same or different to the offsets added to the odd column measure qubits, e.g., can include negated, mirrored, or rotated offsets.

[0073] These stabilizer measurements generate syndrome data that indicate the presence and type of errors affecting the data qubits. In some implementations, the system performs these stabilizer measurements in parallel with the execution of logical quantum gate operations (that form the quantum computation) on logical qubits encoded by the quantum error correction code, thereby enabling continuous error detection during computation. The resulting measurement outputs are then transmitted to a classical decoder, which uses the syndrome information to identify error configurations and determine appropriate correction operations to maintain logical qubit fidelity.

[0074] The system processes results of measuring the stabilizers in a quantum error correction decoder to identify error syndromes and determine, using the error syndromes. corresponding correction operations (step 212). These operations can include single- or multi-qubit Pauli corrections determined by minimum-weight matching, belief propagation, or other decoding algorithms compatible with the selected code. The correction operations can be operations that are applied to physical qubits of a quantum processor performing the quantum error correction code or operations that are applied to Pauli frames in control software of the quantum processor.

[0075] FIG. 3 depicts an example quantum computer 300 for performing the quantum operations described in this specification. The example quantum computer 300 includes an example quantum computing device 302. The quantum computing device 302 is intended to represent various forms of quantum computing devices. The components shown here, their connections and relationships, and their functions, are exemplary only, and do not limit implementations of the inventions described and / or claimed in this document.

[0076] The example quantum computing device 302 includes a qubit assembly 352 and a control and measurement system 304. The qubit assembly includes multiple qubits, e.g., qubit 306, that are used to perform algorithmic operations or quantum computations. While the qubits shown in FIG. 3 are arranged in a rectangular array, this is a schematic depiction and is not intended to be limiting. The qubit assembly 352 also includes adjustable coupling elements, e.g., coupler 308, that allow for interactions between coupled qubits. In the schematic depiction of FIG. 3, each qubit is adjustably coupled to each of its four adjacent qubits by means of respective coupling elements. However, this is an example arrangement of qubits and couplers and other arrangements are possible, including arrangements that are non-rectangular, arrangements that allow for coupling between non-adjacent qubits, and arrangements that include adjustable coupling between more than two qubits.

[0077] Each qubit can be a physical two-level quantum system or device having levels representing logical values of 0 and 1. The specific physical realization of the multiple qubits and how they interact with one another is dependent on a variety of factors including the type of the quantum computing device 302 included in the example computer 300 or the ty pe of quantum computations that the quantum computing device is performing. For example, in an atomic quantum computer the qubits may be realized via atomic, molecular or solid-state quantum systems, e g., hyperfine atomic states. As another example, in a superconducting quantum computer the qubits may be realized via superconducting qubits or semi-conducting qubits, e.g., superconducting transmon states. As another example, in a NMR quantum computer the qubits may be realized via nuclear spin states. As another example, in a neutral atom quantum computer the qubits may be realized via an array of neural atoms, e.g.. rubidium or cesium, where Rydberg interactions allow for implementations of multi-qubit gates and facilitate connectivity between qubits in the array.

[0078] In some implementations a quantum computation can proceed by loading qubits, e.g., from a quantum memory. and applying a sequence of unitary operators to the qubits. Applying a unitary operator to the qubits can include applying a corresponding sequence of quantum logic gates to the qubits, e.g., to implement the surface code circuits described in this specification. Example quantum logic gates include single-qubit gates, e.g., Pauli-X, Pauli-Y, Pauli-Z (also referred to as X, Y, Z), Hadamard gates, S gates, rotations, two-qubit gates, e.g., controlled-X, controlled-Y, controlled-Z (also referred to as CX, CY, CZ), controlled NOT gates (also referred to as CNOT) controlled swap gates (also referred to as CSWAP), iSWAP gates, and gates involving three or more qubits, e.g.. Toffoli gates. The quantum logic gates can be implemented by applying control signals 310 generated by the control and measurement system 304 to the qubits and to the couplers.

[0079] For example, in some implementations the qubits in the qubit assembly 352 can be frequency tunable. In these examples, each qubit can have associated operating frequencies that can be adjusted through application of voltage pulses via one or more drive-lines coupled to the qubit. Example operating frequencies include qubit idling frequencies, qubit interaction frequencies, and qubit readout frequencies. Different frequencies correspond to different operations that the qubit can perform. For example, setting the operating frequency to a corresponding idling frequency may put the qubit into a state where it does not strongly interact with other qubits, and where it may be used to perform single-qubit gates. As another example, in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. In other cases, e.g., when the qubits interact via tunable couplers, qubits can be configured to interact with one another by setting the parameters of their respective couplers to enable interactions between the qubits and then by setting the qubit’s respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. Such interactions may be performed in order to perform multi-qubit gates.

[0080] The type of control signals 310 used depends on the physical realizations of the qubits. For example, the control signals may include RF or microwave pulses in an NMR or superconducting quantum computer system, or optical pulses in an atomic quantum computer svstem. A quantum computation can be completed by measuring the states of the qubits, e.g., using a quantum observable such as X or Z, using respective control signals 310. The measurements cause readout signals 312 representing measurement results to be communicated back to the measurement and control system 304. The readout signals 312 may include RF, microwave, or optical signals depending on the physical scheme for the quantum computing device and / or the qubits. For convenience, the control signals 310 and readout signals 312 shown in FIG. 3 are depicted as addressing only selected elements of the qubit assembly (i.e. the top and bottom rows), but during operation the control signals 310 and readout signals 312 can address each element in the qubit assembly 352.

[0081] The control and measurement system 304 is an example of a classical computer system that can be used to perform various operations on the qubit assembly 352, as described above, as well as other classical subroutines or computations. The control and measurement system 304 includes one or more classical processors, e.g., classical processor 314, one or more memories, e.g., memory 316, and one or more I / O units, e.g., I / O unit 318, connected by one or more data buses. The control and measurement system 304 can be programmed to send sequences of control signals 310 to the qubit assembly, e.g. to carry out a selected series of quantum gate operations, and to receive sequences of readout signals 312 from the qubit assembly, e.g. as part of performing measurement operations.

[0082] The processor 314 is configured to process instructions for execution within the control and measurement system 304. In some implementations, the processor 314 is a single-threaded processor. In other implementations, the processor 314 is a multi-threaded processor. The processor 314 is capable of processing instructions stored in the memory' 316.

[0083] The memory 316 stores information within the control and measurement system 304. In some implementations, the memory 316 includes a computer-readable medium, a volatile memory unit, and / or a non-volatile memory unit. In some cases, the memory 316 can include storage devices capable of providing mass storage for the system 304, e.g. a hard disk device, an optical disk device, a storage device that is shared over a network by multiple computing devices (e.g.. a cloud storage device), and / or some other large capacity storage device.

[0084] The input / output device 318 provides input / output operations for the control and measurement system 304. The input / output device 318 can include D / A converters, A / D converters, and RF / microwave / optical signal generators, transmitters, and receivers, whereby to send control signals 310 to and receive readout signals 312 from the qubit assembly, as appropriate for the physical scheme for the quantum computer. In some implementations, the input / output device 318 can also include one or more network interface devices, e.g., an Ethernet card, a serial communication device, e.g., an RS-232 port, and / or a wireless interface device, e.g., an 802.11 card. In some implementations, the input / output device 318 can include driver devices configured to receive input data and send output data to other external devices, e.g., keyboard, printer and display devices.

[0085] Although an example control and measurement system 304 has been depicted in FIG. 3, implementations of the subject matter and the functional operations described in this specification can be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

[0086] Embodiments and all of the functional operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments may be implemented as one or more computer program products, i. e. , one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of. data processing apparatus. The computer readable medium may be a machine- readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term ‘‘data processing apparatus'’ encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus may include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to suitable receiver apparatus.

[0087] A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program may be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0088] The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and apparatus may also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0089] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory' or both.

[0090] The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer may be embedded in another device, e.g. , a tablet computer, a mobile telephone, a personal digital assistant (PDA), a mobile audio player, a Global Positioning System (GPS) receiver, to name just a few. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memorydevices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory' may be supplemented by, or incorporated in, special purpose logic circuitry7.

[0091] To provide for interaction with a user, embodiments may be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user may provide input to the computer. Other kinds of devices may be used to provide for interaction with a user as well; for example, feedback provided to the user may be any form of sensory7feedback, e.g.. visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including acoustic, speech, or tactile input.

[0092] Embodiments may be implemented in a computing system that includes a back end component, e.g, as a data server, or that includes a middleware component, e.g., an application sen' er, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user may interact with an implementation, or any combination of one or more such back end. middleware, or front end components. The components of the system may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g. , the Internet.

[0093] The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0094] While this specification contains many specifics, these should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0095] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products.

[0096] In each instance where an HTML file is mentioned, other file types or formats may be substituted. For instance, an HTML file may be replaced by an XML, JSON, plain text, or other types of files. Moreover, where a table or hash table is mentioned, other data structures (such as spreadsheets, relational databases, or structured files) may be used.

[0097] Thus, particular embodiments have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still achieve desirable results. What is claimed is:

Claims

CLAIMS1. A computer implemented method comprising: determining a number of n offsets; for measure qubits, wherein the measure qubits are partitioned into odd columns and even columns: for each odd column measure qubit, measuring a stabilizer over data qubits reached by adding each of the n offsets to the measure qubit position; for each even column measure qubit, negating one or more of the n offsets and measuring a stabilizer over data qubits reached by adding each of the one or more negated n offsets to the measure qubit position.

2. The method of claim 1 , further comprising generating, from the measurements, codes for error correction.

3. The method of claim 1 or claim 2, further comprising: determining, in a control circuit of a quantum processor implementing a quantum error correction code, a configuration of physical qubits using the n offsets, comprising determining qubit interaction patterns for stabilizer measurements for the quantum error correction code; and executing, by the quantum processor, the control circuit.

4. The method of claim 3, wherein the stabilizers are measured over the data qubits in parallel with a quantum computation executed on logical qubits encoded by the quantum error correction code.

5. The method of claim 4, wherein determining the number of n offsets comprises: in response to determining that at least one of: boundary conditions for the quantum error correction code differ to predetermined base boundary conditions; a connectivity graph of the quantum processor differs to a base connectivity graph associated with the predetermined base boundary conditions; and physical qubit spacing in the quantum processor differs to a base physical qubit spacing,modifying a set of base offsets stored in a memory accessible to the control circuit of the quantum processor, comprising mapping each offset to a valid data qubit position according to the predetermined base boundary conditions.

6. The method of claim 5, wherein modifying the set of base offsets comprises one or more of: applying modulo wrapping of offset coordinates; rotating or mirroring the offsets; scaling the offsets to match a physical qubit spacing; removing offsets exceeding a stabilizer weight limit; or remapping offsets to match a connectivity graph of the quantum processor.

7. The method of claim 5 or claim 6, wherein the predetermined base boundary conditions comprise: toroidal boundary conditions wherein qubit positions wrap around in at least one lattice dimension according to a modulo operation; or planar boundary conditions in which qubit positions at edges of a lattice are truncated or replaced to remain within valid lattice coordinates.

8. The method of claim 4, wherein determining the number of n offsets comprises retrieving a set of base offsets from a memory accessible to a control circuit of the quantum processor and using the base offsets without modification for lattice configurations of different sizes.

9. The method of any of claims 3 to 8, wherein the qubit interaction patterns comprise: a first set of interaction patterns for odd column measure qubits, wherein each first set interaction pattern specifies data qubits reached by adding n offsets to a position of a respective odd-column measure qubit; and a second set of interaction patterns for even column measure qubits, wherein each second set interaction pattern specifies data qubits reached by adding offsets to a position of a respective even column measure qubit.

10. The method of any preceding claim, wherein the measure qubits are physical qubits arranged on a lattice that comprises integer coordinate positions (x, y), wherein the oddcolumns comprise columns in the lattice with an odd column index x and the even columns comprise columns in the lattice with an even column index x.

11. The method of claim 10, wherein the measure qubits are arranged with data qubits in a checkerboard pattern on the lattice, the data qubits comprising physical qubits, wherein measure qubits in odd columns are assigned to X-basis stabilizers and measure qubits in even columns are assigned to Z-basis stabilizers.

12. The method of any preceding claim, further comprising processing results of measuring the stabilizers in a quantum error correction decoder to identify error syndromes and determine, using the error syndromes, corresponding correction operations to be applied to physical qubits of a quantum processor performing the quantum error correction code or Pauli frames in control software of the quantum processor.

13. The method of any preceding claim, wherein one or more of: the number n of offsets is equal to a quantum error correction code stabilizer weight, the stabilizer weight defining a number of data qubits entangled with each measure qubit during each stabilizer measurement; the n offsets comprise a combination of short-range offsets to nearest-neighbor data qubits and long-range offsets to non-nearest-neighbor data qubits; and the n offsets comprise integer coordinate pairs, each coordinate pair identifying a relative position of a data qubit to be entangled with a given measure qubit.

14. The method of claim 3, wherein the quantum error correction code comprises a low- density parity check code.

15. The method of any preceding claim, wherein the number of offsets comprises a first set of offsets and a second set of offsets, and wherein the method further comprises: for each odd column measure qubit, measuring a stabilizer over data qubits reached by adding each offset of the first set of offsets to the measure qubit position; and for each even column measure qubit, measuring a stabilizer over data qubits reached by adding each offset in a second set of offsets to the measure qubit position, wherein the second set of offsets comprises one or more of: negations of the first set of offsets, rotatedversions, mirrored versions, or independently defined offsets based on stabilizer type or code geometry.

16. A quantum computing system comprising: a quantum processor comprising: a plurality of physical qubits: qubit couplers defining interactions between the plurality of qubits; and control electronics configured to operate the plurality of qubits and qubit couplers; and one or more data processing apparatuses configured to receive and process data received from the quantum computing hardware; wherein the quantum computing apparatus is configured to perform operations according to the method of any one of claims 1 to 15.

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