Distributed grounding for co-planar waveguide
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- IQM FINLAND OY
- Filing Date
- 2024-10-21
- Publication Date
- 2026-07-01
Smart Images
Figure FI2024050562_01052025_PF_FP_ABST
Abstract
Description
DISTRIBUTED GROUNDING FOR CO-PLANAR WAVEGUIDEFIELD OF THE INVENTION
[0001] The invention is generally related to the field of quantum computing. In particular, the invention is related to distributed grounding for a co-planar waveguide in an arrangement for a superconducting chip.BACKGROUND OF THE INVENTION
[0002] A quantum computing device, also referred to as a quantum computer, uses quantum mechanical phenomena, such as superposition and entanglement, to perform required quantum computing operations. Unlike a conventional computer that manipulates information in the form of bits (e.g., "1" or "0"), the quantum computer manipulates information using qubits. A qubit may refer not only to a basic unit of quantum information but also to a quantum device that is used to store one or more qubits of information (e.g., the superposition of "0" and "1").
[0003] Quantum computing devices are implemented by superconducting circuits that typically use frequency multiplexed qubit readout using one or more resonators per qubit, where multiple qubits are read out by a single shared probe line. The qubits may be coupled to the single shared probe line by a readout resonator and one or more Purcellfilter resonators. The resonators should be tuned relative to each to each other for accurate and reliable readout of the qubit states.
[0004] Resonators for superconducting circuits can be implemented as transmission line resonators. Transmission line resonators can be made from coplanar waveguides (CPW) or microstrip lines, which are widely used in superconducting circuits due to their compatibility with fabrication techniques and low loss characteristics at cryogenic temperatures. A transmission line resonator is a one-dimensional structure that consists of a transmission line with a specific length and termination conditions to create a resonant mode at a desired frequency. In a transmission line resonator, the transmission line serves as a waveguide for propagating electromagnetic waves. The resonant behavior of a transmission line resonator is determined by its length and termination conditions. By carefully designing the length and impedance of the transmission line, a standing wave pattern can be established, creating resonance at a specific frequency. Transmission line resonators can be coupled to other elements in a superconducting quantum circuit, such as qubits or other resonators, to enable interactions and perform desired quantum operations.
[0005] A coplanar waveguide (CPW) comprises a center conductor, which is typically a metal trace, and two ground planes on either side of the center conductor. The center conductor and the ground conductors are arranged in the same plane, whereby intensity of electric field can be high between the center conductor and the ground conductors.
[0006] In superconducting circuits, CPW can be used as a transmission line for carrying high-frequency signals and as a structure for implementing various circuit elements such as transmission line resonators. However, a high electric field between a center conductor and in-plane conductors of the CPW can cause drawbacks, examples of which are given below:• Breakdown of Superconductivity: Superconductivity relies on the absence of electrical resistance. However, when the electric current exceeds a critical value, it can cause the superconducting material to transition into a normal state, where resistance is present. This phenomenon is known as the quenching effect. High electric field intensity can induce localized heating and generate normal conducting regions, leading to a loss of superconductivity in those areas. This can disrupt the circuit's operation and potentially damage the superconducting components.• Flux Penetration and Trapped Magnetic Fields: Superconductors have the ability to expel magnetic fields from their interior, a property known as the Meissner effect. However, under high electric field intensity, magnetic flux lines can penetrate into the superconductor, leading to the formation of vortices. These vortices can trap magnetic fields and cause energy dissipation, which can limit the performance of the circuit.• Electric Field-Induced Phase Transitions: In certain types of superconductors, high electric field intensity can induce phase transitions that alter the material's superconducting properties. For example, some superconductors can undergo a transition from a superconducting state to a normal state under strong electric fields. This effect can be utilized in applications such as field-effect superconducting devices, where the electric field is used to control the superconducting behavior.SUMMARY
[0007] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is notintended to identify key features of the invention, nor is it intended to be used to limit the scope of the invention.
[0008] The objective of the invention is to provide a technical solution to improve distribution of electric field from a signal conductor of co-planar waveguide to the ground in an arrangement for a superconducting chip.
[0009] The objective above is achieved by the features of the independent claims in the appended claims. Further embodiments and examples are apparent from the dependent claims, the detailed description and the accompanying drawings.
[0010] According to a first aspect, there is provided an arrangement for a superconducting chip comprising:- a first substrate that comprises a first conductive surface layer,- a second substrate comprising at least one conductive surface layer, and- a co-planar waveguide comprising a signal line on the first substrate, wherein the first conductive surface layer of the first substrate and the at least one conductive surface layer of the second substrate are connected by bonding elements that extend in a direction that is perpendicular to a longitudinal direction of the signal line and the superconducting chip is configured to distribute coupling of the signal line to the ground via the at least one conductive surface layer of the second substrate, the bonding elements, and at least one of the following:- the first conductive surface layer of the first substrate which is separated by a dielectric material from the signal line above; or- a second conductive surface layer of the first substrate on an opposite side of the first substrate than the signal line.
[0011] According to a second aspect there is provided a superconducting chip comprising at least one arrangement according to an aspect.
[0012] According to a third aspect there is provided a quantum computing apparatus comprising at least one superconducting chip comprising at least one arrangement according to an aspect, wherein the co-planar waveguide is configured to operate as a readout resonator of at least one superconducting element coupled to the co-planar waveguide, and a control unit connected to the at least one superconducting chip, and the control unit is configured to perform quantum computing operations based on a readout of the at least one superconducting element coupled to the co-planar waveguide.
[0013] At least some aspects provide improved distribution of electric field from a signal line of a co-planar waveguide to the ground in a superconducting chip.BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The invention is explained below with reference to the accompanying drawings in which:Figs. 1 , 2, 3 and 4 illustrate examples of superconducting chips in accordance with at least some embodiments; andFIG. 5 shows a block diagram of a quantum computing apparatus in accordance with at least some embodiments.DETAILED DESCRIPTION
[0015] Various embodiments of the invention are further described in more detail with reference to the accompanying drawings. However, the invention may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description. In contrast, these embodiments are provided to make the description of the invention detailed and complete. According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the invention encompasses any embodiment thereof, which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the invention. For example, the chips and apparatus disclosed herein may be implemented in practice by using any numbers of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the invention may be implemented using one or more of the elements presented in the appended claims.
[0016] In the present application, similar or corresponding elements and components across different figures and embodiments are referred to using the same reference numbers. The use of consistent reference numbers is intended to denote their similarity or correspondence unless otherwise stated.
[0017] The word "exemplary" is used herein in the meaning of "used as an illustration". Unless otherwise stated, any embodiment described herein as "exemplary" should not be construed as preferable or having an advantage over other embodiments.
[0018] Any positioning terminology, such as "left", "right", "upper", "lower", etc., may be used herein for convenience to describe one element's or feature's relationship to one ormore other elements or features in accordance with the figures. It should be apparent that the positioning terminology is intended to encompass different orientations of the chip disclosed herein, in addition to the orientation (s) depicted in the figures. As an example, if one imaginatively rotates the chip in the figures 90 degrees clockwise, elements or features described as "left" and "right" relative to other elements or features would then be oriented, respectively, "above" and "below" the other elements or features. Therefore, the positioning terminology used herein should not be construed as any limitation of the invention.
[0019] Although the numeric terminology, such as "first", "second", etc., may be used herein to describe various embodiments and the features thereof, it should be understood that the embodiments and the features thereof should not be limited by this numerative terminology. This numerative terminology is used herein only to distinguish one embodiment or feature from another embodiment or feature. Thus, a first embodiment discussed below could be called a second embodiment and vice versa, without departing from the teachings of the invention.
[0020] The following embodiments are exemplary. Although the specification may refer to "an", "one", or "some" embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment. Single features of different embodiments may also be combined to provide other embodiments.
[0021] As used herein, “at least one of the following” and “at least one of ” and similar wording, where the list of two or more elements are joined by “and” or “or”, mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.
[0022] As used in the embodiments disclosed herein, a qubit may refer to a superconducting quantum device, or a superconducting element, configured to store one or more quantum bits of information (or qubits for short). In this sense, the qubit serves as a quantum information storage and processing device. The source of nonlinearity in the qubit may be represented by one or more Josephson junctions. The term "Josephson junction" is used herein in its ordinary meaning and may refer to a quantum mechanical device made of two superconducting electrodes which are separated by a barrier (e.g., a thin insulating tunnel barrier, normal metal, semiconductor, ferromagnet, etc.).
[0023] According to the embodiments disclosed herein, a quantum computing apparatus, also referred to as a quantum computer, may refer to an apparatus that comprises a superconducting chip comprising at least one superconducting chipcomprising a co-planar waveguide, wherein the co-planar waveguide is configured to operate as a readout resonator of at least one superconducting element coupled to the co-planar waveguide, and a control unit that connected to the at least one superconducting chip, said control unit is configured to perform quantum computing operations (e.g., qubit operations, such as reading the state of a qubit, initializing the state of the qubit, and entangling the state of the qubit with the states of other qubits in the quantum computing apparatus, etc.) based on a readout of the at least one superconducting element coupled to the co-planar waveguide. Existing implementation examples of such quantum computing apparatuses may include superconducting quantum computers, trapped ion quantum computers, quantum computers based on spins in semiconductors, quantum computers based on cavity quantum electrodynamics, optical photon quantum computers, quantum computers based on defect centers in diamond, etc. The readout may be a frequency-multiplexed readout of the qubits connected to a common feedline by resonator structures.
[0024] The exemplary embodiments disclosed herein provide a technical solution that allows mitigating or even eliminating the above-sounded drawbacks of the prior art.
[0025] There is provided improved distribution of electric field from a signal conductor of co-planar waveguide to the ground in a superconducting chip. The superconducting chip comprises a first substrate that comprises a first conductive surface layer, a second substrate comprising at least one conductive surface layer, and a co-planar waveguide comprising a signal line on the first substrate. The first conductive surface layer of the first substrate and the at least one conductive surface layer of the second substrate are connected by bonding elements that extend in a direction that is perpendicular to a longitudinal direction of the signal line and the superconducting chip is configured to distribute coupling of the signal line to the ground via the at least one conductive surface layer of the second substrate, the bonding elements, and at least one of the following: the first conductive surface layer of the first substrate which is separated by a dielectric material from the signal line above; or a second conductive surface layer of the first substrate on an opposite side of the first substrate than the signal line. A superconducting chip and a quantum computing apparatus comprising one or more superconducting chips may comprise one or more circuit elements that may be built using co-planar waveguides (CPWs). Examples of the circuit elements comprise at least:- Transmission Line: CPW provides a low-loss transmission line for propagating high-frequency signals with minimal attenuation and distortion. The central conductor of the CPW is typically made of a superconductingmaterial, such as niobium or aluminum, which offers excellent conductivity and low loss when operated at low temperatures. The ground planes on either side of the central conductor provide a return path for the signal, ensuring impedance matching and minimizing signal reflections.- Resonators: CPW is commonly used to create superconducting resonators, which are key elements in many superconducting circuits. By forming CPW in a loop or meandered configuration, the circuit can exhibit resonant behavior at specific frequencies. Resonators based on CPW, such as coplanar waveguide resonators or kinetic inductance resonators, are used in applications like quantum computing, qubit readout, and microwave photonics.- Couplers and Splitters: CPW structures can be designed to function as couplers and splitters, allowing for power division or coupling between different elements in the superconducting circuit. For example, a CPW directional coupler can be used to couple energy from one CPW line to another with controllable coupling strength.- Filters and Delay Lines: CPW can be employed to implement filters and delay lines in superconducting circuits. By designing the CPW with specific dimensions and incorporating additional circuit elements, such as resonators or capacitors, it is possible to create filters that selectively pass or reject certain frequencies. Similarly, CPW-based delay lines can introduce controlled delays in the propagation of signals.- Josephson Junctions: Josephson junctions are critical elements in many superconducting circuits, particularly in applications like superconducting qubits. CPW can be utilized to create the necessary structures for Josephson junctions, which consist of two superconducting electrodes separated by a thin insulating barrier. By incorporating Josephson junctions into CPW structures, it is possible to create quantum devices that exploit the unique properties of superconductivity.
[0026] Superconducting circuit refers to a collection of interconnected superconducting elements that work together to perform a specific function. These circuits are typically fabricated on a substrate using superconducting materials, such as niobium or aluminum, which exhibit zero electrical resistance at very low temperatures. Superconducting circuits can take various forms, such as transmission lines, transmission line resonators, co-planar waveguides, Josephson junctions, SQUIDs (Superconducting QuantumInterference Devices), or qubits used in quantum computing. They are designed to exploit the unique properties of superconductors, such as the ability to carry persistent currents and exhibit quantum effects. Superconducting circuits are used in applications like quantum computing, high-speed digital electronics, and ultra-sensitive detectors.
[0027] Superconducting chip refers to the physical implementation of a superconducting circuit on a chip-scale device. It involves fabricating the superconducting circuitry on a small semiconductor substrate, often made of silicon or sapphire, using advanced microfabrication techniques. The superconducting chip typically contains multiple superconducting elements, such as transmission lines, transmission line resonators, co-planar waveguides, Josephson junctions or SQUIDs, interconnected to form a functional circuit. The chip may also include control and readout electronics, cryogenic cooling infrastructure, and other components necessary for its operation. In the context of quantum computing multiple superconducting qubits may be integrated on a single chip. These qubits can be manipulated and measured collectively to perform quantum computations. Superconducting chips are also used in other applications like analog-to-digital converters, microwave amplifiers, and signal processing systems.
[0028] Flip-chip bonding is a packaging technique for electronic devices, particularly in microelectronics and semiconductor industries. It involves the attachment of an integrated circuit (IC) chip directly onto a substrate or another chip, typically using solder bumps or other conductive materials. The term "flip-chip" refers to the orientation of the IC chip during the bonding process. Instead of mounting the chip with its active surface facing up, as done in traditional packaging methods, the chip is flipped over so that its active surface, which contains the circuitry and contact pads, faces downward. This allows for direct electrical connections between the chip and the substrate or other chips. The bonding process involves aligning the solder bumps or conductive contacts on the chip with corresponding pads or traces on the substrate. The chip is then pressed onto the substrate, and the solder bumps are heated, melting the solder and creating electrical and mechanical connections between the chip and the substrate. Once the solder cools and solidifies, it forms a reliable and high-density interconnection between the chip and the substrate.
[0029] Fig. 1 , 2, 3 and 4 illustrate examples of superconducting chips in accordance with at least some embodiments. Each of the superconducting chips 100 comprises at least one arrangement that comprises substrates 102, 104, 204, or portions of the substrates, that are bonded together, and a co-planar waveguide on at least one of the substrates, said co-planar waveguide comprising a signal line 116. The arrangement isconfigured to encircle a signal line 116 with ground from all directions in the x-y plane to distribute the signal to ground coupling. Examples of the arrangement comprises at least a readout resonator that may be coupled to at least one superconducting element. The superconducting chips are illustrated by cross-sectional views in a plane defined by the X- and Y-axis of a cartesian coordinate system. Surfaces of the substrates extend in a plane defined by the X-axis and Z-axis (not shown) of the coordinate system. Each of the substrates may comprise one or more superconducting elements that are a part of a superconducting circuit on the substrate. In an example, the co-planar waveguide comprises a signal line 116, or a signal conductor, that extends longitudinally in a direction that is parallel to the plane defined by the X-axis and Z-axis. Accordingly, the signal line 116 has its longitudinal dimension in a transverse direction with respect to the X- and Y- axis. The substrates are bonded by bonding elements 112 that extend in a direction that is perpendicular to the longitudinal dimension of the signal line, thus parallel to the direction of the Y-axis, between the bonded substrates. In the superconducting chip of Fig. 1 , the signal line 116 is on the same plane with a first conductive surface layer 108 of a first substrate 104 and gapped with respect to the first conductive surface layer 108 and bonding elements 112. Figs 2, 3 and 3 illustrate superconducting chips, where the arrangements comprise at least one conductive surface layer 208 of the first substrate that is at least partially recessed into the first substrate 204 under the signal line. The first conductive surface layer 208 is at least partially formed in a recess at the first substrate 204 and the recess is at least partially filled with a dielectric material 218, 318. In an example, the dielectric material 318 partially fills the recess and the dielectric material 318 is laterally gapped towards edges of the recess. In this way, a part of the first conductive surface layer 208 of the first substrate at a bottom 214 of the recess may be left exposed. In this way the dielectric separates the signal line from the conductive surface layer, while the dielectric has a shape that controls the electric field distribution, whereby coupling through the dielectric to the conductive surface layer may be controlled. In an example, the dielectric material 218 fills, e.g. completely fills, the recess, when the dielectric material extends between lateral edges of the recess and covers the bottom 214 of the recess. In this way coupling of electric field from the signal line 116 to the ground via the bottom 214 of the recess may be controlled. In an example, the signal line may be trenched to the dielectric material 318. In this way, coupling of the electric field to the bonding elements that are laterally around the trenched signal line 116 is focused through the dielectric.
[0030] It should be noted that the bonding elements 112 of the substrates may be formed by a bonding process of the superconducting chips, for example by flip-chip bonding. The bonding elements may be bumps of electrically conductive material arranged in a series of bumps that run in a direction that is parallel to the longitudinal dimension of the signal linel 16. In this way distributed coupling of the signal line to the ground over the length of the signal line may be facilitated. Each of the substrates comprises at least one conductive surface layer 106, 108, 110, 208 and the bonding elements 112 may connect the substrates together at facing conductive layers.
[0031] It should be noted that at least one of the substrates 104 may have one or more conductive surface layers 108, 110 that have been arranged on opposite sides of the substrate, e.g. on opposite sides of the substrate in the direction of the Y-axis. The conductive surface layers on opposite sides of the substrate may be connected by one or more through-silicon vias (TSVs). The TSVs may be positioned to the substrate to extend between opposite sides of the substrate for connecting the conductive surface layers on the opposite sides. Accordingly, the TSVs may extend in a depth-direction, or direction of thickness, of the substrate. It should be noted that the TSVs may form a series of TSVs arranged to extend in a direction that is parallel to the longitudinal dimension of the signal line. In this way the connection between the conductive surface layers on opposite sides of the substrate may be provided in the longitudinal dimension of the signal line for supporting distributed coupling of the signal line to the ground over the length of the signal line. Preferably, the TSVs are provided on laterally opposite sides of the signal line 116 for facilitating distributed coupling of the signal line to the ground on both sides of the signal line. At first ends, the TSVs may be connected to the bonding elements 112 and / or conductive surface layer 108 of the substrate 104, and at other ends the TSVs may be connected to the conductive surface layers on the opposite side of the substrate.
[0032] It should be noted that a distributed coupling of the signal line 116 to the ground at the superconducting chips 100 may be designed based on a width, ai, of the signal line and distances of the signal line from conductive surface layers 106, 108, 110 of the substrates 104, 204, which are illustrated with respect to each superconducting chip 100. bi refers to a lateral distance between the signal line 116 and the first conductive surface layer 108, 208 and / or the bonding elements 112. du, d2i, dsi and d4i refer to vertical distances between the signal line 116 and the conductive surface layer 106 of the second substrate. di2 refers to a vertical distance between the signal line 116 and the second conductive surface layer 110 of the first substrate 104. d22, d32 and d42 refer to verticaldistances between the signal line 116 and the first conductive surface layer 108, 208 of the first substrate 104, 204.In an example in accordance with at least some embodiments, there is provided an arrangement for a superconducting chip 100 and a superconducting chip 100 comprising at least one said arrangement. The arrangement comprises a first substrate 104 that comprises at least one conductive surface layer 108, a second substrate 102 comprising at least one conductive surface layer 106, and a co-planar waveguide comprising a signal line 116 on the first substrate. The first conductive surface layer of the first substrate and the at least one conductive surface layer of the second substrate are connected by bonding elements 112 that extend in a direction that is perpendicular to a longitudinal direction of the signal line. The arrangement is configured to distribute coupling of the signal line to the ground via the at least one conductive surface layer of the second substrate, the bonding elements and at least one of the following: the first conductive surface layer 108 of the first substrate 104 which is separated by a dielectric material from the signal line 116 above; or a second conductive surface layer 110 of the first substrate 104 on an opposite side of the first substrate 104 than the signal line 116. In an example, the first conductive surface layer 108 of the first substrate 104 may be separated by from the signal line 116, when the dielectric material is positioned on the first conductive surface layer, whereby the first conductive surface layer is buried under the dielectric material. In an example, the distributed coupling of the signal line to the ground may be provided by positioning the signal line with respect to the at least one conductive surface layer 108 of the first substrate 104, the second conductive surface layer 110 of the first substrate 104, the at least one conductive surface layer 106 of the second substrate 102 and the bonding elements 112. Position of the signal line may be determined based on parameters defining a width of the signal line and distances of the signal line from conductive surface layers 106, 108, 110, 208 of the substrates 102, 104, 204. An example of the distances is a lateral distance / separation of the signal 116 line from the first conductive surface layer 108 of the first substrate and / or from the bonding elements 112. For example, the signal line may be laterally separated from the first conductive surface layer 108 of the first substrate 104 and / or the bonding elements 112. In an example, the lateral separation may be defined based on a gap between the signal line and the first conductive surface layer 108 of the first substrate and / or the bonding elements 112. Lateral dimension bi of the gap may be adapted for distributing the coupling of the signal line to the ground. In an example in accordance with at least some embodiments, the arrangement comprises that at least one conductive surface layer 106 of the secondsubstrate 102 is at least partially recessed into second substrate 102 above the signal line. The recessed part of the at least one conductive surface layer 106 facilitates controlling distributed coupling of electric field between the signal line and the conductive surface layer 106 of the second substrate. In an example, the at least one conductive surface layer 106 of the second substrate 102 is formed at least partially in a recess 119 at the second substrate 102. The recessed part of the at least one conductive surface layer 106 facilitates controlling distributed coupling of electric field between the signal line and the conductive surface layer 106 of the second substrate based on a distance du between the signal line 116 and a bottom 117 of the recess 119. In an example, the second substrate has a dominant thickness of X2, whereby at a recessed part of the at least one conductive surface layer 106, the thickness is less than X2.
[0033] In an example in accordance with at least some embodiments, the first substrate 104 comprises one or more through-silicon vias (TSVs) 118 which connect the first conductive surface layer 108 to the second conductive surface layer 110. In this way conductive surface layers on opposite sides of the first substrate may support coupling of the signal line to the ground. In an example, the first substrate has a thickness Xi and the TSVs extend through the first substrate. In an example, the first substrate comprises a recess 113 on the opposite side and the second conductive surface layer extends on a surface of the first substrate and over a bottom 114 of the recess 113 on the surface. Then, the lengths of the TSVs are less than Xi in thickness direction of the first substrate 104.
[0034] In an example in accordance with at least some embodiments, the arrangement comprises that the second conductive surface layer 110 of the first substrate 104 is at least partially recessed into first substrate 104 under the signal line. The recessed part of the second conductive surface layer decreases distance between the signal line and the second conductive surface layer 110 which facilitates coupling of electric field between the signal line and the second conductive surface layer through the first substrate. In an example, the first substrate has a dominant thickness of xi, whereby at a recessed part of the second conductive surface layer, the thickness is less than xi.
[0035] In an example in accordance with at least some embodiments, the arrangement comprises that the first conductive surface layer 208 of the first substrate 204 is at least partially recessed into the first substrate 204 under the signal line 116. In an example, the signal line is arranged on a dielectric material 218, 318 deposited on a recessed part of the first conductive surface layer, whereby a thickness of the dielectric material may beadapted for controlling coupling of electric field from the signal line to the first conductive surface layer 208 of the first substrate 204 under the signal line.
[0036] In an example in accordance with at least some embodiments, the arrangement comprises that the first conductive surface layer 208 of the first substrate 204 is at least partially formed in a recess at the first substrate 204 and the recess is at least partially filled with the dielectric material 218. In an example, the recess may be etched to the first substrate. In an example, the dielectric material may be deposited to a bottom 214 of the recess for filling the recess. It should be noted that a thickness of the dielectric material may be adapted for controlling coupling of electric field from the signal line 116 to the first conductive surface layer 208 of the first substrate 204 under the signal line.
[0037] In an example in accordance with at least some embodiments, the arrangement comprises that the first conductive surface layer 208 is at least partially formed in a recess at the first substrate 204 and the recess is at least partially filled with a dielectric material 318. In an example, the dielectric material 318 fills the recess, when the dielectric material extends between lateral edges of the recess and covers a bottom 214 of the recess. In this way, a part of the first conductive surface layer 208 of the first substrate at the bottom 214 of the recess may be left exposed by the dielectric material which allows coupling of electric field from the signal line to the ground. It should be noted that, the recess may be considered filled by the dielectric material, when an upper surface of the dielectric material 318 is at a level of the surface of the first substrate 204 around a mouth of the recess towards the second substrate 102.
[0038] It should be noted that a thickness of the dielectric material 318 may be adapted for controlling coupling of electric field from the signal line 116 to the first conductive surface layer 208 of the first substrate 104 under the signal line. In an example, height of the dielectric material 318 may exceed a surface level of the first substrate 204.
[0039] In an example in accordance with at least some embodiments, the arrangement comprises that the recess is filled by the dielectric material 318 and the signal line is trenched to the dielectric material. In this way, coupling of the electric field to the bonding elements that are laterally around the trenched signal line 116 may be controlled. In an example the trenching of the signal line may be provided by depositing dielectric material to the recess and etching the deposited dielectric material to form a trench, where a position for the signal line is formed. In an example of the trenched signal line, the dielectric material 318 comprises a position for the signal line between vertically extending portions of the dielectric material. The vertically extending portions of the dielectric material 318 are positioned on both sides of the signal line, thus on laterally oppositesides of the signal line. In this way, coupling of the electric field to the bonding elements from the signal line 116 may be controlled.
[0040] In an example, the trenched dielectric material 318 may extend from a bottom 214 of the recess inside the first substrate 204 towards the second substrate 102. In this way, a distance between the signal line 116 positioned on the dielectric material to the conductive surface layer at the second substrate may be adapted by the dielectric material. In an example, a top surface of the (trenched) dielectric material 318 may be positioned inside a recess 119 at the second substrate 102. The top surface inside the recess 119 at the second substrate 102 may have a gap to a bottom 117of the recess.
[0041] In an example in accordance with at least some embodiments, the dielectric material is laterally gapped towards edges of the recess 214. In this way, a part of the first conductive surface layer 208 of the first substrate at a bottom 214 of the recess may be exposed by the dielectric material which allows coupling of electric field from the signal line to the ground. In an example, the arrangement may have a gap, e.g. having a dimension bi , between the dielectric material and the first conductive surface layer and / or the bonding elements 112.
[0042] In an example in accordance with at least some embodiments, the arrangement for the superconducting chip 100 is a readout resonator coupled to at least one superconducting element. In this way the arrangement may support performing quantum operations by interaction of the readout resonator and the at least one superconducting element. In an example, the readout resonator is configured to detect and measure a state of the at least one superconducting element and act as a sensitive probe that interacts with the superconducting element for readout of a quantum state of the superconducting element. In an example, at least one superconducting element is a qubit, whereby a readout of the qubit may be performed via the readout resonator. In an example, the readout resonator is designed to have a well-defined resonant frequency that matches the frequency of the superconducting element. Then, when the superconducting element is coupled to the readout resonator, their interaction affects the resonator’s response. The quantum state of the superconducting element alters the resonant frequency, which can be detected through measurements of microwave signals transmitted or reflected by the readout resonator. To read out the state of the superconducting element, a microwave signal is applied to the readout resonator, typically at or near its resonant frequency. The interaction between the superconducting element and the resonator causes changes in the transmitted or reflected signal. Bymeasuring these changes, it is possible to infer the state of the superconducting element, such as whether it is in the ground state or an excited state.
[0043] Examples of materials for conductive layers, or conductive surface layers, comprise at least one of the following: copper; or copper oxide; or indium; or germanium; or niobium; aluminum; aluminum oxide; or alloys of one or more of the previous; or other materials that display superconducting behaviour in low temperatures. Examples of the other materials comprise organic engineered materials such as carbon nanotubes. Various engineered silicon-based / ceramic materials are also foreseeable, when made superconducting in chip substrate manufacturing process.
[0044] FIG. 5 shows a block diagram of a quantum computing apparatus 500 in accordance with at least some embodiments. The apparatus 500 comprises at least one superconducting chip 502 and a control unit 504. The chip 502 may comprises one or more arrangements for superconducting chips described with Figs. 1 to 4. The control unit 504 is configured to perform quantum computing operations by using the one or more arrangements. In an example in accordance with at least some embodiments quantum computing apparatus 500 comprises at least one superconducting chip 502 comprising at least one arrangement that comprises a co-planar waveguide configured to operate as a readout resonator of at least one superconducting element coupled to the co-planar waveguide. The quantum computing apparatus 500 further comprises a control unit 504 connected to the at least one superconducting chip and the control unit is configured to perform quantum computing operations based on a readout of the at least one superconducting element coupled to the co-planar waveguide. The apparatus 500 may further comprise a memory 506 storing executable instructions 508 which, when executed by the control unit 504, may cause the control unit 504 to perform the quantum computing operations. The control unit 504 may also store the result(s) of the quantum computing operations to the memory 506. It should be noted that the number, arrangement and interconnection of the constructive elements constituting the apparatus 500, which are shown in FIG. 5, are not intended to be any limitation of the present disclosure, but merely used to provide a general idea of how the constructive elements may be implemented within the apparatus 500. For example, the apparatus 500 may comprise two or more chips 502 each comprising one or more arrangements for superconducting chips 100 described with Figs. 1 to 4.
[0045] The control unit 504 may refer a central processing unit (CPU), general-purpose processor, single-purpose processor, microcontroller, microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signalprocessor (DSP), complex programmable logic device, etc. It should be also noted that the control unit 504 may be implemented as any combination of one or more of the aforesaid. As an example, the control unit 504 may be a combination of two or more microprocessors.
[0046] The memory 506 may be implemented as a classical nonvolatile or volatile memory used in the modern electronic computing machines. As an example, the nonvolatile memory may include Read-Only Memory (ROM), ferroelectric Random- Access Memory (RAM), Programmable ROM (PROM), Electrically Erasable PROM (EEPROM), solid state drive (SSD), flash memory, magnetic disk storage (such as hard drives and magnetic tapes), optical disc storage (such as CD, DVD and Blu-ray discs), etc. As for the volatile memory, examples thereof include Dynamic RAM, Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Static RAM, etc.
[0047] The executable instructions 508 stored in the memory 506 may be configured as a computer executable code which causes the control unit 504 to perform the quantum computing operations by using the chip 502. The computer executable code for carrying out the quantum computing operations may be written in any combination of one or more programming languages, such as Java, C++, or the like. In some examples, the computer executable code may be in the form of a high-level language or in a pre-compiled form, and be generated by an interpreter (also pre-stored in the memory 506) on the fly.
[0048] Electromagnetic couplings between components of superconducting circuit(s), may be, for example, capacitive, inductive, or both capacitive and inductive. In some embodiments, couplings between components are couplings through a space between two chips on which two components are respectively positioned. For example, in some implementations, a qubit positioned on a first substrate may be electromagnetically coupled to a readout resonator positioned on a second substrate that is bump bonded to and facing the first substrate. In some embodiments, couplings are in-plane, with a direction of a coupling electric field and / or magnetic field being substantially in a plane of a side of a chip on which both of two components are positioned. For example, in some implementations, a qubit on a first surface of a silicon substrate may be electromagnetically coupled to a readout resonator on the first surface of the silicon substrate.
[0049] Superconducting quantum circuits comprise components for performing computational operations based on quantum operations. Components of the superconducting quantum circuits, also referred to quantum circuit components, or quantum computing circuit components, disclosed herein include circuit components forperforming the quantum operations. That is, the superconducting quantum circuit components are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain superconducting quantum circuit components, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit components include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), readout resonators, readout transmission lines, co-planar waveguides, amplifiers, and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC SQUID), among others.
[0050] In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and / or input / output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements may be used to transmit data to and / or receive data from the quantum circuit components through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.
[0051] Any or all of the components mentioned in this disclosure, including the qubits, the readout resonators, the readout transmission lines, and the amplifiers, may be made of a superconductor material, such as aluminum, niobium, or titanium nitride, among other superconductor materials. The components may include both superconductor and nonsuperconductor material.
[0052] Fabrication of the electrical components disclosed herein may entail the deposition of one or more materials, such as superconductors, dielectrics and / or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating electrical components described herein may entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process may include, e.g., wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the electrical components described herein can be patterned using known lithographic techniques (e.g.,photolithography or e-beam lithography). It should be noted that the processes for fabricating the electrical components described herein may further entail flip-chip manufacturing, where a device is flipped upside down and directly attached to another device, allowing for more efficient and compact packaging.
[0053] During operation of a quantum computational system that uses circuit elements formed, in part, from superconductors, such as the circuit elements described herein, the circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (also referred to as superconducting) material may be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of 1.2 kelvin) and niobium (superconducting critical temperature of 9.3 kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.
[0054] In certain implementations, control signals for the quantum circuit components (e.g., qubits and qubit couplers) may be provided using classical circuit elements that are electrically and / or electromagnetically coupled to the quantum circuit components. The control signals may be provided in digital and / or analog form.
[0055] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable sub-combination.
[0056] Although the exemplary embodiments of the invention are described herein, it should be noted that various changes and modifications could be made in the embodiments of the invention, without departing from the scope of legal protection which is defined by the appended claims. In the appended claims, the word “comprising” does not exclude other elements or operations, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
[0057] Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.
[0058] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results.LIST OF REFERENCE SIGNS
Claims
CLAIMS1 . An arrangement for a superconducting (100) chip, comprising:- a first substrate (104) that comprises a first conductive surface layer (108),- a second substrate (102) comprising at least one conductive surface layer (106), and- a co-planar waveguide comprising a signal line (116) on the first substrate (104), wherein the first conductive surface layer (108) of the first substrate (104) and the at least one conductive surface layer (106) of the second substrate (102) are connected by bonding elements (112) that extend in a direction that is perpendicular to a longitudinal direction of the signal line and the arrangement is configured to distribute coupling of the signal line to the ground via the at least one conductive surface layer (106) of the second substrate (102), the bonding elements (112), and at least one of the following:- the first conductive surface layer (108) of the first substrate (104) which is separated by a dielectric material from the signal line (116) above; or- a second conductive surface layer (110) of the first substrate (104) on an opposite side of the first substrate (104) than the signal line (116).
2. The arrangement of claim 1 , wherein the at least one conductive surface layer (106) of the second substrate (102) is at least partially recessed into the second substrate (102) above the signal line (116).
3. The arrangement of claim 1 or 2, wherein the first substrate (104) comprises one or more through-silicon vias which connect the first conductive surface layer (108) to the second conductive surface layer (110).
4. The arrangement of any of the preceding claims, wherein the first conductive surface layer (108) of the first substrate (104) is at least partially recessed into the first substrate (104) under the signal line (116).
5. The arrangement of any of any of the preceding claims, wherein the second conductive surface layer (110) of the first substrate (104) is at least partially recessed into the first substrate (104) under the signal line (116).
6. The arrangement of any of the preceding claims, wherein the first conductive surface layer (108) is at least partially formed in a recess at the first substrate (104) and the recess is at least partially filled with the dielectric material.
7. The arrangement of claim 6, wherein the recess is filled by the dielectric material and the signal line (116) is trenched into the dielectric material.
8. The arrangement of any of the preceding claims, wherein the dielectric material is laterally gapped towards edges of the recess.
9. The arrangement according to any of the preceding claims, wherein the arrangement is a readout resonator coupled to at least one superconducting element.
10. A superconducting chip comprising at least one arrangement according to any of claims 1 to 9.11 . A quantum computing apparatus comprising at least one superconducting chip comprising at least one arrangement according to any of claims 1 to 9, wherein the co-planar waveguide is configured to operate as a readout resonator of at least one superconducting element coupled to the co-planar waveguide, and a control unit connected to the at least one superconducting chip, and the control unit is configured to perform quantum computing operations based on a readout of the at least one superconducting element coupled to the co-planar waveguide.