SEMICONDUCTOR DEVICE AND COMPUTER-IMPLEMENTED METHOD FOR DETERMINISTIC GOVERNANCE, STRUCTURAL INTEGRITY AUDIT (SIAEC), SEMANTIC-METRIC CONTROL (SIAEC), AND TOPOLOGICAL FORENSIC EXPLICABILITY OF NEURAL NETWORKS

ES3073249A1Undetermined Publication Date: 2026-07-09

Patent Information

Authority / Receiving Office
ES · ES
Patent Type
Applications
Filing Date
2026-04-19
Publication Date
2026-07-09

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Abstract

A semiconductor device (SoC) (1) and computer-implemented method for deterministic artificial intelligence supervision. It incorporates a secure port (8) in an inert state to ensure subordination by injecting a base truth. An AECM module (3) audits the integrity of physical memory using hash trees on the hot path, repairing tensors on the fly with no latency. An AECM module (4) vetoes semantic hallucinations by calculating spatial divergences in hardware and consolidating neuroplasticity in parallel search associative memories (4a) without retraining software. A forensic module (5) extracts the causal triad and cross-references it with a logical topological map, recording the exact node and layer responsible for the failure in immutable storage to provide full explainability.
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