LED LAYOUT STRUCTURES

Abstract

The present invention relates to an LED arrangement structure in which a plurality of LEDs are arranged in a lattice in the first and second directions to form a plurality of LED rows and a plurality of LED columns, each LED row comprising a plurality of LED groups, and each LED group comprising two adjacent LEDs. Two non-common electrode terminals in each of the LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB, such that when the LEDs are connected to the PCB, the two LEDs whose two non-common electrode terminals are connected to each other can be connected to the PCB via an interconnect hole, thus reducing the number of interconnect holes on the PCB, improving the PCB's efficiency, and reducing the PCB's production cost.

Description

Title of the invention: LED LAYOUT STRUCTURES technical field

[0001] The present invention relates to a field of LED (light-emitting diode) display technology, and more particularly, to LED arrangement structures. STATE OF THE ART

[0002] An LED display screen is a flat multimedia display terminal consisting of a light-emitting diode matrix module or a pixel unit, which has the characteristics of high brightness, wide viewing range, long life, low cost, etc.

[0003] Currently, during the design and production process of an LED display, it is generally necessary to punch holes in a printed circuit board (PCB), increase the width of the PCB, or increase the number of layers on the PCB. However, having too many holes on the PCB can easily increase the PCB defect rate, and increasing the width or number of layers can significantly increase material costs, thus considerably increasing the production cost of the LED display. Therefore, the question of how to improve PCB efficiency in order to reduce production costs has become a pressing technical issue that urgently needs to be addressed. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes an LED arrangement structure, which aims to solve the technical problem of the low efficiency of the prior art PCBs.

[0005] Resolution of the technical problem

[0006] To solve the aforementioned problems, an embodiment of the present invention provides an LED arrangement structure comprising:

[0007] a PCB, a plurality of data lines extending in a first direction, a plurality of scan lines extending in a second direction, and a plurality of interconnect holes being arranged in a display area of ​​the PCB; the plurality of data lines and the plurality of scan lines are located on different layers of the PCB, and the second direction intersects the first direction; and the plurality of interconnect holes comprise a plurality of first interconnect holes and a plurality of second holes interconnection;

[0008] a plurality of LEDs arranged on the PCB, the plurality of LEDs being arranged in a network in the first direction and the second direction to form a plurality of LED rows and a plurality of LED columns, the LED rows extending in the first direction, and the LED columns extending in the second direction; each of the LED rows comprises a plurality of LED groups, and each of the LED groups comprises two adjacent LEDs; a plurality of adjacent LEDs are arranged sequentially in the second direction to form a plurality of electroluminescent pixels; and each of the LEDs comprises a common electrode terminal and a non-common electrode terminal;

[0009] the common electrode terminals of all the LEDs in each of the LED columns are connected to one of the corresponding scan lines via one or more of the first interconnect holes among the first interconnect holes;

[0010] The non-common electrode terminals of all the LEDs in each of the LED rows are connected to one of the corresponding data lines; and

[0011] The non-common electrode terminals of two LEDs in each of the LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB board.

[0012] Preferably, in the LED arrangement structure, a plurality of non-common electrode connection lines extending in the first direction are also provided in the display area of ​​the PCB, the non-common electrode connection lines and the data lines are located at different layers of the PCB, and the non-common electrode connection lines and the scan lines are located at different layers of the PCB; and in each of the LED groups, the non-common electrode terminals of two LEDs are connected to one of the corresponding non-common electrode connection lines.

[0013] Preferably, in the LED arrangement structure, each of the non-common electrode connection lines is connected to one of the corresponding data lines via a second corresponding interconnect hole among the second interconnect holes.

[0014] Preferably, in the LED arrangement structure, in each of the LED groups, the corresponding non-common electrode connection lines is connected to one of the corresponding data lines via at least one second interconnecting hole.

[0015] More preferably, in the LED arrangement structure, the common electrode terminals of all the LEDs of each of the electroluminescent pixels are connected to one, corresponding, of the scanning lines via one, corresponding, of the first interconnection holes.

[0016] Preferably, in the LED arrangement structure, in each of the LED columns, the common electrode terminals of the entire set of LEDs of at least two adjacent electroluminescent pixels are connected to one of the corresponding scan lines via one of the corresponding first interconnect holes.

[0017] Furthermore, an embodiment of the present invention provides an LED arrangement structure comprising a PCB for mounting a plurality of LEDs, and the PCB comprises:

[0018] M lines of data extending in a first direction, where M>3 and is an integer;

[0019] N scanning lines extending in a second direction, where N>2 and is an integer; and the second direction intersects the first direction; and

[0020] a plurality of pairs of terminals, in which each of the pairs of terminals comprises a first terminal and a second terminal, the plurality of pairs of terminals form M rows of pairs of terminals and N columns of pairs of terminals, the first terminals of all the pairs of terminals in an i-th row of pairs of terminals are connected to an i-th data line, and the second terminals of all the pairs of terminals in a j-th column of pairs of terminals are connected to a j-th scan line;

[0021] in the i-th row of terminal pairs, a first terminal of an o-th terminal pair is connected to a first terminal of an (o+l)-th terminal pair on a surface layer of the PCB board, and o is an odd number or an even number.

[0022] More preferably, in the LED arrangement structure, the PCB further comprises M*N / 2 non-common electrode connection lines arranged in a network, and M*N / 2 is an integer; the non-common electrode connection lines extend in the first direction, the non-common electrode connection lines are located on the surface layer of the PCB, the scan lines are located on an inner or lower layer of the PCB, and the data lines are located on a film layer between the non-common electrode connection lines and the scan lines; in the i-th row of terminal pairs, the first terminal of the o-th terminal pair is connected to the first terminal of the (o+l)-th terminal pair via a p-th non-common electrode connection line in the i-th row;and in a case where o is an even number, p is equal to o / 2, and in a case where o is an odd number, p is equal to (o+l) / 2. ;

[0023] More preferably, in the arrangement structure of DEL, the p-th line of non-common electrode connection of the i-th row is connected to the i-th data line via at least one interconnect hole.

[0024] More preferably, in the LED arrangement structure, the PCB further comprises M*N / 3 common electrode connection lines arranged in a network, and M*N / 3 is an integer; the common electrode connection lines are located on the surface layer of the PCB; the j-th column of terminal pairs comprises a plurality of repeating units, and the second terminals of all the terminal pairs of the same repeating unit are connected to each other through one of the corresponding common electrode connection lines, and the corresponding common electrode connection line is connected to the j-th scan line through an interconnect hole.

[0025] By comparison to the prior art, embodiments of the present invention provide an LED arrangement structure in which the plurality of LEDs are arranged in a network in the first and second directions to form a plurality of LED rows and a plurality of LED columns, each of the LED rows comprises a plurality of LED groups, and each of the LED groups comprises two adjacent LEDs.Two non-common electrode terminals in each of the LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB board, so that when the LEDs are connected to the PCB board, the two LEDs whose two non-common electrode terminals are connected to each other can be connected to the PCB board via an interconnect hole, this reduces the number of interconnect holes on the PCB board, improving the yield of the PCB board and reducing the cost of producing the PCB board. Brief description of the drawings

[0026] In order to explain more clearly the technical solutions proposed in the embodiments of the present invention, the drawings necessary for describing the embodiments will be presented below. It is understood that the drawings presented in the following description constitute only some of the embodiments of the present invention. For those skilled in the art, other drawings can be obtained on the basis of these drawings, without the need for creative work.

[0027] [Fig. 1] represents a diagram of a prior art LED arrangement structure;

[0028] [Fig.2] represents another diagram of an art LED arrangement structure previous;

[0029] [Fig.3] represents a diagram of an LED arrangement structure according to an embodiment of the present invention;

[0030] [Fig.4] represents a diagram of an LED arrangement structure according to another method of embodiment of the present invention;

[0031] [Fig. 5] represents a diagram of an LED arrangement structure according to another method of embodiment of the present invention;

[0032] [Fig.6] represents a diagram of an LED arrangement structure according to another method of embodiment of the present invention;

[0033] [Fig.7] represents a diagram of an LED arrangement structure according to another method of embodiment of the present invention;

[0034] [Fig.8] represents a diagram of an LED arrangement structure according to another embodiment of the present invention; and

[0035] [Fig.9] represents an exploded view of various film layers of the structure LED arrangement of [Fig.8]. DETAILED DESCRIPTION

[0036] The technical solutions indicated in the embodiments of the present invention will be described below clearly and exhaustively with reference to the drawings of the embodiments of the present invention. It is understood that the embodiments described constitute only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by specialists in the art without creative work fall within the scope of protection of the present invention.

[0037] In the description of the present invention, it shall be understood that the orientations or positional relationships indicated by the terms "central," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," "column," "row," and others, are based on the orientations or positional relationships illustrated in the drawings. These terms are used to facilitate and simplify the description of the present invention, rather than to indicate or imply that the devices or elements mentioned herein must have particular orientations or be made or operate according to the particular orientations indicated. Therefore, these terms shall not be interpreted as limiting the present invention.

[0038] In this document, the expression "certain embodiments" shall be understood as meaning "by way of example, illustration, or explanation." Any embodiment described by way of example in this document shall not necessarily be interpreted as being more preferable or advantageous than other embodiments. The following description shall enable any specialist in the art to implement and use the present invention. In In the following description, the details are listed for explanatory purposes only. It should be noted that specialists in the field of normal competence will realize that the present invention can also be implemented without implementing these particular details. In other cases, well-known structures and processes will not be elaborated upon in order to avoid burdening the description of the present invention with unnecessary details. Therefore, the present invention should not be considered as limited to the embodiments illustrated, but as being compatible with the broadest possible scope that conforms to the principles disclosed in this document.

[0039] It should be noted that the first and second directions mentioned in the embodiments of the present invention are perpendicular to each other, and that the first direction can be a column direction or a row direction. Similarly, the second direction corresponds to the row direction or the column direction, and the first and second directions are interchangeable in a real application. When the first direction is an x ​​direction shown in Figures 1 to 7, the second direction is a y direction shown in Figures 1 to 7, the row of LEDs is a row shown in the drawings, the column of LEDs is a column shown in the drawings, the x direction shown in Figures 1 to 7 is a row direction, and the y direction is a column direction.

[0040] Referring to [Fig. 1], the latter illustrates a diagram of an LED arrangement structure of the technique. As shown in [Fig. 1], a plurality of electroluminescent pixels 20 of the same structure are arranged in an array on a PCB 10, and each of the electroluminescent pixels 20 comprises three LEDs of different electroluminescence colors, such as a red LED, a blue LED and a green LED, so that both the LEDs and the electroluminescent pixels 20 are arranged in an array on the PCB 10.The common electrode terminals of all the LEDs in each row of 20 LEDs are electrically connected to the surface layer of the PCB 10 to form a row scan line, and the non-common electrode terminals of the LEDs of the same color in each column of the 20 LEDs are electrically connected to the inner or lower layer of the PCB 10 via interconnect holes 101 on the PCB 10 to form a column data line. The stroboscopic chip performs a progressive scan of the pixels on the PCB 10 via scan lines 30, and the driver chip applies different currents via data lines 40 to obtain different colors in various LEDs 20, thus obtaining a complete image on the PCB 10.

[0041] As shown in [Fig.1], the number of interconnect holes 101 in the PCB 10 is determined by the number of LEDs, and three interconnect holes 101 are required for each electroluminescent pixel 20 in order to allow the data lines 40 to be routed to the inner or lower layer of the PCB 10.

[0042] Referring to [Fig. 2], [Fig. 2] represents a diagram of another LED arrangement structure of the technique. As shown in [Fig. 2], a plurality of light-emitting pixels 20 of the same structure are arranged in an array on a PCB 10, and each of the light-emitting pixels 20 comprises three LEDs of different electroluminescence colors, such as a red LED, a blue LED, and a green LED, so that the LEDs and the light-emitting pixels 20 are arranged in an array on the PCB 10.The common electrode terminals of all the LEDs in each row of electroluminescent pixels 20 are electrically connected to the inner or lower layer of the PCB 10 via interconnect holes 101 of the PCB 10 to form a row scan line, and the non-common electrode terminals of the LEDs of the same electroluminescent color in each column of electroluminescent pixels 20 are electrically connected to a surface layer of the PCB 10 to form a column data line 40.

[0043] As shown in [Fig. 2], in order to avoid the problem of conductor intersection on the PCB, in each column of LEDs 20, two data lines 40 must pass between the positive and negative electrodes of one or more LEDs. Although only one interconnect hole 101 is required for each LED 20 in [Fig. 2], due to the constraints related to the PCB wiring rules 10, the data line 40 passing between the positive and negative electrodes of the LEDs will inevitably lead to an increase in the size of the LEDs, thus resulting in a significant increase in costs.As an example of the classic 0408 COB chip (4 mil x 8 mil), the distance between the positive and negative electrodes of the COB chip is only 75 µm. Generally, the pad spacing on the PCB must be less than the pad spacing on the COB chip to avoid misalignment, so the pad spacing on the PCB is typically 70 µm. According to the PCB processing level, the line width and line spacing of the general wiring are both 100 µm. If two 40 data lines both pass between the positive and negative electrodes of the COB chip, the distance between the positive and negative electrodes of the COB chip is at least 500 µm. In this case, the COB chip must be much larger than the original 75µm diode design size, which will lead to a very large diode size and a sharp increase in manufacturing costs.

[0044] Referring to [Fig. 3], the latter represents a diagram of an LED arrangement structure according to an embodiment of the present invention. As shown in [Fig. 3], an LED arrangement structure comprises:

[0045] a PCB card 10;

[0046] a plurality of first LEDs 201 and a plurality of second LEDs 202 arranged on the PCB 10; the first LEDs 201 and the second LEDs 202 are arranged in a network in a first direction and a second direction;

[0047] the plurality of first LEDs 201 form a plurality of first rows of LEDs 210 along the second direction, the plurality of second LEDs 202 form a plurality of second rows of LEDs 220 along the second direction, and some of the plurality of first LEDs 201 and some of the plurality of second LEDs 202 form a plurality of third rows of LEDs 230 in the first direction;

[0048] the common electrode terminals of the respective first LEDs 201 in each of the first rows of LEDs 210 are electrically connected to form a scan line 30; the common electrode terminals of the respective second LEDs 202 in each of the second rows of LEDs 220 are electrically connected to form a scan line 30; the non-common electrode terminals of each of the first LEDs 201 and of each of the second LEDs 202 in each of the third rows of LEDs 23 are electrically connected to form a data line 40;

[0049] the common electrode or non-common electrode terminals of the first LED 201 and the second LED 202 adjacent to each other in each of the third rows of LEDs 230 are adjacent to each other; the scan lines 30 and the data lines 40 are located in different layers of the PCB 10.

[0050] In the case of the LED arrangement structure provided in the embodiment of the present invention, the plurality of first LEDs 201 and the plurality of second LEDs 202 are arranged on the PCB 10, the first LEDs 201 and the second LEDs 202 are arranged in a network in a first direction and a second direction, the plurality of first LEDs 201 form the plurality of first rows of LEDs 210 in the second direction, the plurality of second LEDs 202 form the plurality of second rows of LEDs 220 in the second direction, and the plurality of first LEDs 201 and the plurality of second LEDs 202 form the plurality of third rows of LEDs 230 in the first direction.Simultaneously, the common electrode terminals of the first LEDs 201 in each of the first rows of LEDs 210 are electrically connected to form a 30-scan line in the second direction, the common electrode terminals of the second LEDs 202 in each of the second rows of LEDs 220 are electrically connected to. forming a scan line 30 in the second direction, and the non-common electrode terminals of the second LEDs 202 and the first LEDs 201 in each of the third rows of LEDs 230 are electrically connected to form a data line 40 in the first direction. The common electrode terminals or the non-common electrode terminals of the first LED 201 and the second LED 202 adjacent to each other in each of the third rows of LEDs 230 are adjacent to each other, and the scan line 30 and the data line 40 are located in different layers of the PCB 10, this not only reduces the number of interconnect holes 101 in the PCB 10, but also does not require increasing the width or the number of layers of the PCB 10, and reduces the production cost of the LED display screen while increasing the yield of the PCB 10.

[0051] More specifically, in the embodiment illustrated in [Fig.3], three first adjacent LEDs 201 in the first row of LEDs 210 can form an electroluminescent pixel 20, and three second adjacent LEDs 202 in the second row of LEDs 220 can form an electroluminescent pixel 20. The first LEDs 201 in the electroluminescent pixel 20 are arranged vertically and the second LEDs 202 in the electroluminescent pixel 20 are also arranged vertically.The scan line 30 formed by electrically connecting the common electrode terminals of the first LEDs 201 in each of the first rows of LEDs 210 is a column scan line, the scan line 30 formed by electrically connecting the common electrode terminals of the second LEDs 202 in each of the second rows of LEDs 220 is also a column scan line, and the data line 40 formed by electrically connecting the non-common electrode terminals of the first LEDs 201 and the second LEDs 202 in each of the third rows of LEDs 230 is a row data line.Since the common electrode terminals or the non-common electrode terminals of the first LED 201 and the second LED 202 adjacent to each other in each of the third rows of LEDs 230 are adjacent to each other, the LEDs in at least the first rows of LEDs 210 or the second rows of LEDs 220 may not be provided with the interconnect holes 101 in the PCB 10, and it is not necessary for each of the LEDs to be provided with an interconnect hole 101 in the PCB 10. Therefore, the number of interconnect holes 101 in the PCB 10 is reduced without increasing the size of the LED and the width or thickness of the PCB 10, thus reducing the production cost of the LED display screen while improving the yield of the PCB 10.

[0052] In certain embodiments, each of the scan lines 30 is arranged on the surface layer of the PCB 10, and each of the data lines 40 is arranged on the lower or inner layer of the PCB 10. More specifically, the scan line 30 formed by electrically connecting the common electrode terminals of the first LEDs 201 in each of the first rows of LEDs 210 is arranged on the surface layer of the PCB 10, the scan line 30 formed by electrically connecting the common electrode terminals of the second LEDs 202 in each of the second rows of LEDs 220 is also arranged on the surface layer of the PCB 10, and the data line 40 formed by electrically connecting the non-common electrode terminals of the first LEDs 201 and the second LEDs 202 in each of the third rows of LEDs 230 is arranged on the lower or inner layer of the PCB 10.

[0053] In certain embodiments, several first LEDs 201 adjacent in each of the first rows of LEDs 210 constitute an electroluminescent pixel 20, and several second LEDs 202 adjacent in each of the second rows of LEDs 220 constitute an electroluminescent pixel 20. More specifically, an electroluminescent pixel 20 can be formed by a plurality of LEDs, one or more LEDs having identical or different electroluminescence colors may be present in said electroluminescent pixel 20, the two electroluminescent pixels 20 may or may not be entirely identical with respect to the size, number and color of the LEDs, and a particular arrangement can be configured according to a real application.

[0054] In some embodiments, the first LED 201 and the second LED 202 of each of the third rows of LEDs 230 are LEDs of the same electroluminescent color; the first LED 201 and the second LED 202 are LEDs of the same size; the first LED 201 and the second LED 202 are any red, blue, or green LEDs. However, the embodiments of the present invention are not limited to this, and the first LED 201 and the second LED 202 may be LEDs of different sizes.

[0055] More specifically, in the present embodiment, all the electroluminescent pixels 20 are identical to each other, and each of the electroluminescent pixels 20 is composed of a red LED, a blue LED, and a green LED. The red LED, the blue LED, and the green LED are arranged vertically sequentially from top to bottom in the second direction, so that the left and right viewing angles of the LED display screens are symmetrical and the left and right viewing angles of the LED display screens in the form of a finished product are maximized.

[0056] More specifically, each of the electroluminescent pixels 20 can be composed of a red LED, a blue LED, and a green LED. Similarly, the electroluminescent pixels 20 formed on the PCB 10 by the first LEDs 201 and the second LEDs 202 are arranged in a lattice on the PCB 10. The red LED, the blue LED, and The green LED of each of the 20 electroluminescent pixels can be arranged vertically sequentially from top to bottom.

[0057] It should be noted that the first LEDs 201 and the second LEDs 202 of the third row of LEDs 230 can be LEDs of the same size or of different sizes, provided that the left and right positions of the common electrode and non-common electrode terminals of the second LEDs 202 of the first row of LEDs 210 and of the second row of LEDs 220 which are adjacent are reversed, as illustrated in [Fig.3], so that the interconnect holes 101 in at least one column of the PCB 10 can be eliminated.

[0058] In certain embodiments, the non-common electrode terminals of the first LED 201 and the second LED 202 that are adjacent to each other in each of the third rows of LEDs 230 are electrically connected at the surface layer level of the PCB 10. More specifically, when the common electrode terminals of the first LED 201 and the second LED 202 that are adjacent to each other in each of the third rows of LEDs 230 are adjacent to each other, if there is only one corresponding first row of LEDs 210 on the PCB 10, the first row of LEDs 210 cannot be placed on the outermost edge of the array and must be arranged in the middle of the array; If there is only one second row of matching 220 LEDs on PCB 10, the second row of 220 LEDs cannot be placed on the outermost edge of the array and must be placed in the middle of the array.In this case, the electrical connection between the non-common electrode terminals of the first LED 201 and the second LED 202, which are adjacent to each other in the third row of LEDs 230 on the surface layer of the PCB 10, can be made, thus reducing the number of interconnect holes 101 on the PCB 10. When the non-common electrode terminals of the first LED 201 and the second LED 202, which are adjacent to each other in each of the third rows of LEDs 230, are adjacent to each other, the electrical connection between the non-common electrode terminals of the first LED 201 and the second LED 202, which are adjacent to each other in the third row of LEDs 230, can be made directly on the surface layer of the PCB 10, thus reducing the number of interconnect holes 101 on the PCB 10.

[0059] In certain embodiments, as shown in Figures 3 to 5, the number of first rows of LEDs 210 and the number of second rows of LEDs 220 on the PCB 10 may be equal or not, the first rows of LEDs 210 and the second rows of LEDs 220 may be arranged alternately or not on the PCB 10, and the number of interconnect holes 101 on the PCB 10 may be reduced only if the common electrode or non-common electrode terminals of the first LED 201 and the second LED 202 which are adjacent to each other in each of the third rows of LEDs 230 are adjacent to each other. In [Fig. 3], the number of first rows of LEDs 210 is equal to the number of second rows of LEDs 220, and the first rows of LEDs 210 and the second rows of LEDs 220 are arranged alternately on the PCB 10, so that half of the interconnect holes 101 on the PCB 10 can be omitted compared to [Fig. 1]. The number of first rows of LEDs 210 in [Fig. 4] is less than the number of second rows of LEDs 220. If the number of first rows of LEDs 210 is equal to a and the number of second rows of LEDs 220 is equal to b, the interconnect holes 101 of the a rows can be omitted from the PCB 10 of [Fig. 1]. In [Fig. 5], the number of first rows of LEDs 210 is greater than the number of second rows of LEDs 220.If the number of the first rows of LEDs 210 is equal to a and if the number of the second rows of LEDs 220 is equal to b, the interconnect holes 101 of the b rows can be omitted from the PCB 10 of [Fig.l]. .

[0060] In certain embodiments, the non-common electrode terminals of all the first LEDs 201 in each of the third rows of LEDs 230 are electrically connected to each other via interconnect holes 101 on the PCB 10. More specifically, as shown in [Fig. 3], when the non-common electrode terminals of all the first LEDs 201 in the third row of LEDs 230 are electrically connected to each other via the interconnect holes 101 on the PCB 10, it is sufficient to electrically connect the non-common electrode terminal of the second LED 202 adjacent to the first LED 201 to the non-common electrode terminal of the first LED 201 on the surface layer of the PCB 10, so as to reduce the number of interconnect holes 101 on the PCB 10.

[0061] In certain embodiments, the non-common electrode terminals of all the second LEDs 202 in each of the third rows of LEDs 230 are electrically connected to each other via the interconnect holes 101 on the PCB 10. More specifically, as shown in [Fig. 6], when the non-common electrode terminals of all the second LEDs 202 in a third row of LEDs 230 are electrically connected to each other via the interconnect holes 101 on the PCB 10, it is sufficient to electrically connect one non-common electrode terminal of a first LED 201 adjacent to a second LED 202 to one non-common electrode terminal of the second LED 202 on the surface layer of the PCB 10, so as to reduce the number of interconnect holes 101 in the PCB 10.

[0062] In certain embodiments, the non-common electrode terminals of the The first LED 201 and the second LED 202 in each of the third rows of LEDs 230 are electrically connected to each other via the interconnect hole 101 on the PCB 10. More specifically, as shown in [Fig.[7] when the non-common electrode terminals of a first LED 201 and a second LED 202 in a third row of LEDs 230 are electrically connected to each other through an interconnect hole 101 on the PCB 10, a non-common electrode terminal of a second LED 202 adjacent to the first LED 201 is electrically connected to the non-common electrode terminal of the first LED 201 on the surface layer of the PCB 10, and a non-common electrode terminal of a first LED 201 adjacent to the second LED 202 is electrically connected to the non-common electrode terminal of the second LED 202 on the surface layer of the PCB 10, thus reducing the number of interconnect holes 101 on the PCB 10.

[0063] It should be noted that a first LED 201 in the third row of LEDs 230 corresponds to a single first row of LEDs 210, and that a second LED 202 corresponds to a single second row of LEDs 220. The first rows of LEDs 210 and the second rows of LEDs 220 are arranged in the first direction, and the third rows of LEDs 230 are arranged in the second direction.

[0064] It should also be noted that the arrangement of the LEDs in Figures 3 to 7 can be rotated 90 degrees in practical applications, i.e. that the column scan lines formed in Figures 3 to 7 become row scan lines, the row data lines become column data lines, and that the LEDs of each of the electroluminescent pixels 20 are arranged horizontally.

[0065] It should also be noted that the LEDs 201 of the LED lamp panel structure provided in the embodiments of the present invention can be packaged on the PCB 10 in the manner of a COB chip, or can be packaged on the PCB 10 in the manner of an SMD, the choice being able to be made according to the specific situation in the actual application, and not being particularly limited in accordance with the present invention.

[0066] Based on the description given above, it should be noted that the scan line 30 necessarily includes a portion located on the PCB 10 and a portion located on the LED. The data line 40 necessarily includes a portion located on the PCB 10. The interconnect hole 101 is used to connect respective portions of different film layers. In relation to the description given above, the structure of the PCB 10 can be determined, and Figures 8 and 9 illustrate the structure of the PCB 10. The LED arrangement structure provided in the embodiments of the present invention will be described in more detail. in relation to the structure of PCB board 10.

[0067] Figure (a) of [Fig. 9] is an exploded view of the film layer in which the scan lines are located in the LED arrangement structure of [Fig. 8] (B). Figure (b) of [Fig. 9] is an exploded view of the film layer in which the data lines are located in the LED arrangement structure of [Fig. 8]. Figure (c) of [Fig. 9] is an exploded view of the film layer in which the non-common electrode connection conductors are located in the LED arrangement structure of [Fig. 8].

[0068] It should be noted that, in Figures 8 and 9, the non-common electrode connection line 511 and the common electrode connection line 512 are located in the same film layer, and that the scan line 30, the data line 40, and the non-common electrode connection line 511 are located in different film layers. However, the embodiment of the present invention is not limited to this, the non-common electrode connection line and the common electrode connection line being, for example, located in different film layers.

[0069] As shown in Figures 3 to 9, one embodiment of the present invention provides an LED arrangement structure comprising a PCB 10 and a plurality of LEDs arranged on the PCB 10.

[0070] The PCB 10 is provided with a plurality of data lines 40 extending in a first direction, a plurality of scan lines 30 extending in a second direction, and a plurality of interconnect holes 101 in a display area of ​​the PCB 10. The data lines 40 and the scan lines 30 are located at different layers of the PCB 10, and the second direction intersects the first direction. The plurality of interconnect holes 101 comprises a plurality of first interconnect holes 101a and a plurality of second interconnect holes 101b.

[0071] A plurality of LEDs (for example, a first LED 201) are arranged on the PCB. The plurality of LEDs are arranged in a lattice in the first and second directions, so as to form a plurality of LED rows (for example, a third row of LEDs 230) and a plurality of LED columns (for example, a first row of LEDs 210). The LED rows extend in the first direction and the LED columns extend in the second direction. Each LED row comprises a plurality of LED groups (for example, as illustrated in [Fig. 3], the first LED 201 and the second LED 202 form one LED group), and each LED group comprises two adjacent LEDs. A plurality of adjacent LEDs are arranged sequentially in the second direction to form a plurality of light-emitting pixels. The LED comprises a common electrode terminal and a non-common electrode terminal.

[0072] In each of the LED columns, the common electrode terminals of all the LEDs are connected to one of the scan lines 30 via first interconnection holes 101a.

[0073] In each of the LED rows, the non-common electrode terminals of all the LEDs are connected to one of the data lines 40.

[0074] In at least one of the LED rows, the non-common electrode terminals of the two LEDs in each group of LEDs are connected to each other on the surface layer of the PCB board 10.

[0075] According to the embodiment of the present invention, two non-common electrode terminals in each of the LED groups are connected to each other on the surface layer of the PCB in at least one row of LEDs, so that when the LEDs are connected to the PCB, the two LEDs whose non-common electrode terminals are connected to each other can be connected to the PCB via an interconnect hole, thus reducing the number of interconnect holes on the PCB, improving the efficiency of the PCB and reducing the cost of producing the PCB.

[0076] More specifically, compared to a case where each of the non-common electrode terminals of the prior art LED lamp conductors is connected to the PCB via the interconnect hole, in the embodiments of the present invention, the non-common electrode terminals of the two LEDs in each group of LEDs are connected to each other on the surface layer of the PCB, so that when interconnect holes are present, the number of interconnect holes can be reduced, and the connection positions between the non-common electrode terminals and the data lines can be reduced, thereby reducing the risk of connection failure, improving the yield of the PCB, and reducing the cost of PCB production.

[0077] In certain embodiments, as shown in Figures 8 and 9, a plurality of non-common electrode connection lines 511 extending in the first direction are further provided in the display area of ​​the PCB 10. The non-common electrode connection lines 511 and the data lines 40 are located at different layers of the PCB 10, and the non-common electrode connection lines 511 and the scan lines 30 are located at different layers of the PCB 10. In each of the LED groups, the non-common electrode terminals of two LEDs are connected to one of the non-common electrode connection lines 511. By arranging the non-common electrode connection lines so that they are located at different layers from the data and scan lines, it is possible to reduce the size of a single line, thus reducing... the pixel size. Consequently, the resolution of the LED arrangement structure can be improved. By connecting the non-common electrode terminals of the two LEDs to a non-common electrode connection line, it is possible to reduce the number of interconnect holes in the PCB and the number of interconnect holes in the LED arrangement structure, thus improving the efficiency of the LED arrangement structure.

[0078] More specifically, as shown in Figures 3 and 8, it can be seen that in one of the LED groups, the non-common electrode terminals of two LEDs (for example, the first LED 201 and the second LED 202 in [Fig.3]) are connected to each other, so that the non-common electrode terminals of the two LEDs can be connected to a non-common electrode connection line 511, thereby reducing the number of interconnection holes and increasing the efficiency of the LED arrangement structure.

[0079] In certain embodiments, as shown in Figures 8 and 9, the non-common electrode connection line 511 is connected to the data line 40 via the second interconnect hole 101b. By connecting the non-common electrode connection line to the data line via the second interconnect hole, the data line can be used to drive the LEDs via the non-common electrode connection line, thus enabling normal operation of the LED arrangement structure.

[0080] In certain embodiments, in each of the LED groups, the non-common electrode connection line is connected to one of the data lines via at least one second interconnect hole. More specifically, the non-common electrode connection line may be connected to one of the data lines via one second interconnect hole, the non-common electrode connection line may be connected to one of the data lines via two second interconnect holes, or the non-common electrode connection line may be connected to one of the data lines via three interconnect holes.

[0081] In certain embodiments, as shown in Figures 8 and 9, in each of the LED groups, the non-common electrode connection line 511 is connected to one of the data lines 40 via at least one, and at most two, second interconnect holes 101b. The number of second interconnect holes in the PCB is relatively low by connecting the non-common electrode connection line to a data line via a second interconnect hole, so that the space occupied by a single pixel is reduced, the resolution of the LED arrangement structure is improved, and the number of interconnect holes is reduced to minimize damage to each The film layer on the PCB is applied during a process, thus preventing the effects of moisture and oxygen penetration, electrical modifications, and other factors, and improving the PCB's efficiency. By connecting the non-common electrode connection line to a data line via two secondary interconnect holes, if the wiring in one of the secondary interconnect holes is broken, the wiring in the other secondary interconnect hole can still activate two LEDs, thereby increasing the PCB's efficiency.

[0082] More specifically, as shown in [Fig.8], in each of the LED groups, the non-common electrode connection line 511 is connected to one of the data lines via a second interconnect hole 101b.

[0083] The common electrode terminal of each LED is connected to the scanning line via an interconnect hole, resulting in an excessive number of interconnect holes, an increased pixel size, and a decreased efficiency of the LED arrangement structure. Considering the aforementioned problems, in certain embodiments, as illustrated in Figures 3 and 8, the common electrode terminals of all the LEDs in the electroluminescent pixel 20 are connected to the scanning line 30 via a first interconnect hole 101a.By connecting the common electrode terminals of all the LEDs in the light-emitting pixel to the scan line via an interconnect hole, the number of interconnect holes can be reduced, thereby reducing the pixel size, improving the resolution of the LED arrangement structure, and enhancing the efficiency of the LED arrangement structure. In some embodiments, as shown in Figures 3, 8, and 9, the common electrode terminals of all the LEDs in at least two adjacent light-emitting pixels 20 in each of the LED columns are connected to the scan line 30 via a first interconnect hole 101a.By connecting the common electrode terminals of all the LEDs in two electroluminescent pixels adjacent to the scan line via a first interconnect hole, the number of interconnect holes on the PCB can be reduced, so the pixel size can be reduced, the resolution of the LED arrangement structure can be improved, and the efficiency of the LED arrangement structure can be improved.

[0084] It should be noted that, in Figures 8 and 9, although only a first terminal 513a or a second terminal 513b is shown in some of the pairs of terminals 513, it can be understood that there may be a second terminal 513b corresponding to the first terminal 513a to form a pair of terminals 513, and that there may be a first terminal constituting the terminal 513a corresponding to the second terminal 513b to form a pair of terminals 513. Therefore, in the following embodiment, the first terminal 513a or the second terminal 513b is still described as being part of a pair of terminals 513. Consequently, the pair of terminals 513 shown in Figures 8 and 9 is a third pair of column terminals and a fourth pair of column terminals, and the sweep lines shown in Figures 8 and 9 are a second sweep line, a third sweep line, a fourth sweep line and a fifth sweep line.

[0085] It should be noted that, in [Fig.9], the third pair of terminals and the fourth pair of terminals in the second row are used by way of example for the purposes of description, and therefore, that o is equal to 3. However, the embodiment of the present invention is not limited to this, and o may have a corresponding value which depends on the position of the pair of terminals.

[0086] Furthermore, as shown in Figures 3 to 9, an embodiment of the present invention provides an LED arrangement structure comprising a PCB 10 for mounting a plurality of LEDs. The PCB 10 comprises M data lines 40, N scan lines 30, and a plurality of terminal pairs 513.

[0087] The M (where M>3 and is an integer) 40 data lines extend in the first direction.

[0088] The N (where N>2 and is an integer) 30 scanning lines extend in the second direction. The second direction intersects the first direction.

[0089] The plurality of terminal pairs 513 are arranged on a surface layer of the PCB 10. Each terminal pair 513 comprises a first terminal 513a and a second terminal 513b. The plurality of terminal pairs 513 form M rows of terminal pairs 513 and N columns of terminal pairs 513. The first terminals 513a of all the terminal pairs 513 in an i-th row of terminal pairs 513 are connected to an i-th data line 40, and the second terminals 513b of all the terminal pairs 513 in a j-th column of terminal pairs 513 are connected to a j-th scan line 30.As an example, in Figures 8 and 9, the first 513a terminals of all 513 terminal pairs in a second row of 513 terminal pairs are connected to a second data line, and the second 513b terminals of all 513 terminal pairs in a third column of 513 terminal pairs are connected to a third scan line.

[0090] In the i-th row of terminal pairs 513, the first terminal 513a of an o-th (o is an odd or even number) pair of terminals 513 is connected to the first terminal 513a of an (o+l)-th pair of terminals 513 on the surface layer of the PCB. By way of example, in Figures 8 and 9, in the second row of terminal pairs, the first terminal 513a of a third pair of terminals 513 is connected to the first terminal 513a of a fourth pair of terminals 513 on the surface layer of the board. PCB 10.

[0091] Certain embodiments of the present invention provide an LED arrangement structure, in which, in a row of terminal pairs, a first terminal of a previous terminal pair is connected to a first terminal of a subsequent terminal pair, so that two LEDs can be connected via the first terminals of two terminal pairs, and the two LEDs can be connected to the PCB via an interconnect hole, thereby reducing the number of interconnect holes on the PCB, improving the efficiency of the PCB, and reducing the cost of producing the PCB.

[0092] In some embodiments, as shown in Figures 8 and 9, the PCB 10 further comprises M*N / 2 non-common electrode connection lines 511 arranged in a network, and M*N / 2 is an integer. The non-common electrode connection lines 511 extend in a first direction, the non-common electrode connection lines 511 are located on a surface layer of the PCB 10, the scan lines 30 are located on an inner or lower layer of the PCB 10, and the data lines 40 are located on a film layer between the non-common electrode connection lines 511 and the scan lines 30. In the i-th row of terminal pairs 513, the first terminal 513a of the o-th terminal pair 513 is connected to the first terminal 513a of the (o+l)-th terminal pair via the p-th non-common electrode connection line 511 in the i-th row.When o is an even number, p is equal to o / 2, and when o is an odd number, p is equal to (o+l) / 2. By connecting the first terminals of the two pairs of terminals via the non-common electrode connection line, the two LEDs can be connected via the first terminals of the two pairs of terminals, and the two LEDs can be connected to the PCB via an interconnect hole, thus reducing the number of interconnect holes on the PCB, thereby improving the PCB's efficiency and reducing its production cost. However, the present invention is not limited to this, and the scan line can be located on the film layer between the non-common electrode connection line and the data line.

[0093] More specifically, by way of example, the third pair of terminals and the fourth pair of terminals are illustrated in Figures 8 and 9, a first terminal 513a of the third pair of terminals 513 in a second row is connected to a first terminal 513a of the fourth pair of terminals 513 via a second non-common electrode connection line 511 (a first non-common electrode connection line is not shown in [Fig.8]) in the second row.

[0094] In certain embodiments, as shown in Figures 8 and 9, a p-th A non-common electrode connection line 511 in an i-th row is connected to an i-th data line 40 via at least one and at most two interconnect holes. The non-common electrode connection line is connected to the data line via an interconnect hole, so that the number of interconnect holes in the PCB is low, the space occupied by a single pixel is reduced, the resolution of the LED arrangement structure is improved, the reduction in the number of interconnect holes reduces damage to each film layer of the PCB during the process, the influences of moisture and oxygen penetration, electrical and other changes are avoided, and the efficiency of the PCB is improved.By connecting the non-common electrode connection lines to a data line via two interconnect holes, when the wiring in one of the two interconnect holes is broken, the wiring in the other of the two interconnect holes can still activate two LEDs, thus improving the efficiency of the PCB board.

[0095] More specifically, as shown in Figures 8 and 9, the second non-common electrode connection line 511 of the second row is connected to the second data line 40 via a second interconnect hole 101b. However, the present invention is not limited to this, and it is possible to connect the data line via a plurality of interconnect holes to the non-common electrode connection line.

[0096] In certain embodiments, as shown in Figures 8 and 9, the PCB 10 further comprises M*N / 3 common electrode connection lines 512 arranged in a lattice, and M*N / 3 is an integer. The common electrode connection lines 512 are located on a surface layer of the PCB 10. The j-th column of terminal pairs 513 comprises a plurality of repeating units, and the second terminals 513b of all the terminal pairs 513 in the same repeating unit are connected via one of the common electrode connection lines 512. The common electrode connection line 512 is connected to the j-th scanning line 30 by an interconnect hole.The second terminals of all the terminal pairs of the repeating unit are connected to each other via a common electrode connection line, and the common electrode connection line is connected to the scan line via the interconnect hole, so that the common electrode terminals of all the LEDs of the electroluminescent pixel are connected to the scan line via an interconnect hole, this reduces the number of interconnect holes, reduces the pixel size, and improves the resolution and efficiency of the LED arrangement structure.

[0097] More specifically, two common electrode connection lines in two adjacent repeating units can be connected to the scanning line through the same interconnecting hole.

[0098] In this particular implementation, each of the aforementioned units or structures can be implemented as a separate object, or can be implemented in any combination as the same object or as several objects. For a particular implementation of each of the aforementioned units or structures, reference may be made to the embodiments presented above, as the details are not described here.

[0099] The arrangement of LEDs according to an embodiment of the present invention has been described in detail. The principles and embodiments of the present invention have been described with reference to particular embodiments, and the description of the embodiments provided above is intended simply to facilitate understanding of the process of the present invention and its central concept. Furthermore, specialists in the art may make modifications to both the particular implementations and the scope in accordance with the teachings of the present invention. In view of the foregoing, the content of this document should not be construed as limiting the invention.

Claims

Demands

1. Light-emitting diode (LED) arrangement structure comprising: a printed circuit board (PCB) wherein a plurality of data lines extending in a first direction, a plurality of scan lines extending in a second direction, and a plurality of interconnect holes are arranged in a display area of ​​the PCB; the plurality of data lines and the plurality of scan lines are located on different layers of the PCB, and the second direction intersects the first direction; and the plurality of interconnect holes comprise a plurality of first interconnect holes and a plurality of second interconnect holes; and a plurality of LEDs arranged on the PCB, wherein the plurality of LEDs are arranged in a network in the first direction and the second direction to form a plurality of LED rows and a plurality of LED columns, the LED rows extending in the first direction, and the LED columns extending in the second direction; each of the LED rows comprises a plurality of LED groups, and each of the LED groups comprises two adjacent LEDs; a plurality of adjacent LEDs are arranged sequentially in the second direction to form a plurality of electroluminescent pixels; and each of the LEDs comprises a common electrode terminal and a non-common electrode terminal, wherein the common electrode terminals of all the LEDs in each of the LED columns are connected to one of the scan lines via one or more of the first interconnect holes among the first interconnect holes; The non-common electrode terminals of all the LEDs in each of the LED rows are connected to one of the data lines; and the non-common electrode terminals of two LEDs in each of the LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB board.

2. LED arrangement structure according to claim 1, wherein a plurality of non-common electrode connection lines extending in the first direction are also provided in the display area of ​​the PCB, the electrode connection lines non-common and data lines are located at different layers of the PCB, and non-common electrode connection lines and scan lines are located at different layers of the PCB; and the non-common electrode terminals of the two LEDs in each of the LED groups are connected to one of the non-common electrode connection lines.

3. LED arrangement structure according to claim 2, wherein each of the non-common electrode connection lines is connected to one of the data lines via a second interconnect hole.

4. LED arrangement structure according to claim 3, wherein, in each of the LED groups, said one of the non-common electrode connection lines is connected to one of the data lines via at least one second interconnect hole.

5. LED arrangement structure according to claim 1, wherein the common electrode terminals of all the LEDs in each of the light-emitting pixels are connected to one of the scanning lines via one of the first interconnect holes.

6. LED arrangement structure according to claim 1, wherein, in each of the LED columns, the common electrode terminals of the entire set of LEDs of at least two adjacent light-emitting pixels are connected to one of the scan lines via one of the first interconnect holes.

7. A light-emitting diode (LED) arrangement structure comprising a PCB for mounting a plurality of LEDs, wherein the PCB comprises: M data lines extending in a first direction, where M > 3 and is an integer; N scan lines extending in a second direction, where N > 2 and is an integer; and the second direction intersects the first direction; and a plurality of terminal pairs, wherein each terminal pair comprises a first terminal and a second terminal, the plurality of terminal pairs forming M rows of terminal pairs and N columns of terminal pairs, the first terminals of all terminal pairs in an i-th row of terminal pairs are connected to an i-th data line, and the second terminals of all terminal pairs in a j-th column of terminal pairs are connected to a j-th scan line; wherein, in the i-th row of terminal pairs, a first terminal of an o-th terminal pair is connected to a first terminal of an (o+l)-th terminal pair on a surface layer of the PCB board, and o is an odd number or an even number.

8. LED arrangement structure according to claim 7, wherein the PCB further comprises M*N / 2 non-common electrode connection lines arranged in a lattice, and M*N / 2 is an integer; the non-common electrode connection lines extend in the first direction, the non-common electrode connection lines are located on the surface layer of the PCB, the scan lines are located on an inner or lower layer of the PCB, and the data lines are located on a film layer between the non-common electrode connection lines and the scan lines; in the i-th row of terminal pairs, the first terminal of the o-th terminal pair is connected to the first terminal of the (o+l)-th terminal pair via a p-th non-common electrode connection line in the i-th row;and in a case where o is an even number, p is equal to o / 2, and in a case where o is an odd number, p is equal to (o+l) / 2.;

9. LED arrangement structure according to claim 8, wherein the p-th non-common electrode connection line in the i-th row is connected to the i-th data line via at least one interconnect hole.

10. LED arrangement structure according to claim 7, wherein the PCB further comprises M*N / 3 common electrode connection lines arranged in a lattice, and M*N / 3 is an integer; the common electrode connection lines are located on the surface layer of the PCB; the j-th column of terminal pairs comprises a plurality of repeating units, and the second terminals of all the terminal pairs in a single repeating unit are connected to each other via one of the common electrode connection lines, and said one of the common electrode connection lines is connected to the j-th scan line via an interconnect hole.

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