Control circuit, light-emitting device, display device, and method for driving control circuit

Abstract

Provided is a control circuit that is connected to a current control object and that includes a drive transistor. The control circuit comprises: a first electrode; a first insulating layer positioned above the first electrode; a second electrode overlapping the first electrode with the first insulating layer interposed therebetween; a second insulating layer positioned above the second electrode; and a third electrode overlapping the second electrode with the second insulating layer interposed therebetween. The second electrode is connected to one conduction terminal of the drive transistor.

Description

Control Circuit, Light-Emitting Device, Display Device, and Driving Method of Control Circuit

[0001] The present disclosure relates to a control device.

[0002] Patent Document 1 discloses a pixel circuit in which two parallel capacitive elements are connected to one conduction terminal of a driving transistor.

[0003] Japanese Patent Application Laid-Open No. 2008-39893

[0004] In a conventional current control circuit using a capacitive element, there is a problem that the accuracy of current control decreases due to manufacturing variations of the capacitive element.

[0005] A control circuit according to an aspect of the present disclosure is a control circuit including a driving transistor and connected to a current control object, and includes a first electrode, a first insulating layer located above the first electrode, a second electrode overlapping the first electrode through the first insulating layer, a second insulating layer located above the second electrode, and a third electrode overlapping the second electrode through the second insulating layer, and the second electrode is connected to one conduction terminal of the driving transistor.

[0006] According to this control circuit, even if there are manufacturing variations (variations in capacitance values) of the capacitive element, the influence on current control is reduced, and a predetermined current can be passed through the current control object.

[0007] This is a cross-sectional view showing an example of the configuration of capacitive elements in this control circuit. This is a circuit diagram showing an example of the configuration of this control circuit. This is a plan view showing an example of the configuration of capacitive elements in this control circuit. This is a cross-sectional view showing an example of the configuration of capacitive elements in this control circuit. This is a circuit diagram showing an example of the configuration of this control circuit. This is a plan view showing an example of the configuration of capacitive elements in this control circuit. This is a plan view showing the effect of capacitive elements in this control circuit. This is a circuit diagram showing the configuration of a light-emitting device including this control circuit. This is a circuit diagram showing the configuration of a light-emitting device including this control circuit. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Ka. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kb. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kc. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kd. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Ke. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kf. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kg. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Kh. This is a timing chart showing the operation of the light-emitting device. This is a circuit diagram showing the state during period Ki.

[0008] Figure 1 is a cross-sectional view showing an example configuration of a capacitive element in this control circuit. Figure 2 is a circuit diagram showing an example configuration of this control circuit. Figure 3 is a plan view showing an example configuration of a capacitive element in this control circuit. As shown in Figures 1 to 3, this control circuit 10 is a control circuit that includes a drive transistor Td and is connected to a current-controlled object 5, and includes a first electrode 11, a first insulating layer Z1 located above the first electrode 11, a second electrode 12 overlapping the first electrode 11 via the first insulating layer Z1, a second insulating layer Z2 located above the second electrode 12, and a third electrode 13 overlapping the second electrode 12 via the second insulating layer Z2, wherein the second electrode 12 is connected to one conductive terminal of the drive transistor Td. In this case, a first capacitive element C1 is formed between the first electrode 11 and the second electrode 12, and a second capacitive element C2 is formed between the second electrode 12 and the third electrode 13.

[0009] In the control circuit 10 shown in Figure 2, the first electrode 11 (node ​​N1) is connected to the gate terminal of the drive transistor Td, the second electrode 12 (node ​​N2) is connected to one conductive terminal of the drive transistor Td and the object to be current controlled 5, and the other conductive terminal of the drive transistor Td is connected to the power line PL (for example, the high-potential side power line). The object to be current controlled 5 may be a light-emitting element (for example, an organic light-emitting diode, a quantum dot light-emitting diode) used in display devices, printer heads, photolithography exposure equipment, etc.

[0010] In this case, if the potential of node N1 (first electrode 11) is set to a predetermined potential, the gate-source voltage Vgs of the drive transistor Td will be a value corresponding to the capacitance ratio of the first capacitance element C1 and the second capacitance element C2 and the potential of the third electrode 13 (node ​​N3), and a current corresponding to the gate-source voltage Vgs will flow through the current-controlled object 5.

[0011] As shown in Figure 3, the second electrode 12 includes a main body HT and a lead-out portion H1 extending from the main body HT, and in a plan view, the entire main body HT may overlap with the first electrode 11. The main body HT may be a rectangle having sides parallel to a first direction D1 and sides parallel to a second direction D2 perpendicular to the first direction. The first electrode 11 includes a side E1 parallel to the first direction D1, and the third electrode 13 includes a side E3 parallel to the first direction D1, and sides E1 and E3 may overlap (align) in a plan view. The lead-out portion H1 has a width in the first direction D1 smaller than the main body HT, and the lead-out portion H1 may overlap with sides E1 and E3 in a plan view.

[0012] In the control circuit 10, as shown in Figure 3, even if there are variations in the alignment or shape of the first electrode 11, the second electrode 12, and the third electrode 13, the capacitance ratio of the first capacitance element C1 and the second capacitance element C2, and consequently the gate-source voltage Vgs, are less likely to change. Therefore, even if there are manufacturing variations in each capacitance element (C1 and C2), the accuracy of current control is less likely to decrease.

[0013] Figure 4 is a cross-sectional view showing an example of the configuration of capacitive elements in this control circuit. Figure 5 is a circuit diagram showing an example of the configuration of this control circuit. As shown in Figure 4, in a configuration including a first electrode 11, a first insulating layer Z1 located above the first electrode 11, a second electrode 12 overlapping the first electrode 11 via the first insulating layer Z1, a second insulating layer Z2 located above the second electrode 12, and a third electrode 13 overlapping the second electrode 12 via the second insulating layer Z2, a first capacitive element C1 may be formed between the first electrode 11 and the second electrode 12, a second capacitive element C2 may be formed between the second electrode 12 and the third electrode 13, and a third capacitive element C3 may be formed between the first electrode 11 and the third electrode 13. The capacitance of the third capacitive element C3 may be smaller than that of the first capacitive element C1 and the second capacitive element C2.

[0014] The control circuit 10 in Figure 5 includes a first transistor T1, a second transistor T2, a drive transistor Td, an initialization transistor Ti, and first to third capacitance elements C1 to C3 as shown in Figure 4, and the light-emitting element ED (current-controlled object 5) may be connected to the power line PL via the drive transistor Td. The first electrode 11 (node ​​N1) may be connected to the gate terminal of the drive transistor Td, and the second electrode 12 (node ​​N2) may be connected to one conductive terminal of the drive transistor Td and the anode of the light-emitting element ED (light-emitting diode). One conductive terminal of the first transistor T1 may be connected to the first electrode 11 (node ​​N1), one conductive terminal of the second transistor T1 may be connected to the third electrode 13 (node ​​N3), and one conductive terminal of the initialization transistor Ti may be connected to the second electrode 12 (node ​​N2).

[0015] In the control circuit 10, while an initialization potential Vi is supplied to the second electrode 12 (node ​​N2) via the initialization transistor Ti, the reference potential Vr is supplied to the first electrode 11 and the third electrode 13 via the first and second transistors T1 and T2, thereby initializing the potential of the second electrode 12.

[0016] With the power supply potential supplied from the power line PL to the other conductive terminal of the drive transistor Td, threshold compensation of the drive transistor Td may be performed by supplying a reference potential Vr to the first electrode 11 and the third electrode 13.

[0017] With the second electrode 12 electrically floating, a reference potential Vr is supplied to the first electrode 11 via the first transistor T1, and a data potential Vd is supplied to the third electrode 13 via the second transistor T2, thereby charging the first capacitor 11 according to the data potential. The drive transistor Td may supply a current to the light-emitting element ED (current-controlled object 5) according to the voltage Vgs held in the first capacitor C1. The voltage Vgs can be expressed by the following formula: Vgs = Vi + {(capacitance of C2) / (capacitance of C1 + capacitance of C2)} × (Vr - Vd). Here, the voltage Vgs is determined independently of the capacitance of the third capacitor element C3, and since the amount of charge held in C3 does not change when the first electrode 11 and the third electrode 13 are electrically floating, control (current control of the light-emitting element ED) that is not affected by the third capacitor element C3 which is formed parasitically is possible.

[0018] Furthermore, in the control circuit 10 shown in Figures 4 and 5, even if the finished size of the second electrode 12 (common electrode) varies slightly, the capacitance of the first capacitance element C1 and the second capacitance element C2 are proportional to the area of ​​the second electrode 12 (common electrode), so the capacitance ratio of C1 and C2 remains unchanged. Also, since the first and third electrodes 11 and 13 are sized to enclose the main body of the second electrode 12 (common electrode), slight variations in the finished size of the main body do not affect the capacitance of C1 and C2.

[0019] Figure 6 is a plan view showing an example configuration of a capacitive element in this control circuit. Figure 7 is a plan view showing the effect of the capacitive element in this control circuit. As shown in Figure 6, the first electrode 11 includes opposing first and second edges E1 and E2, the third electrode 13 includes opposing third and fourth edges E3 and E4, and the first lead-out portion H1 may intersect with the first and third edges E1 and E3. In plan view, the first and third edges E1 and E3 may overlap.

[0020] The second electrode 12 is connected to the main body HT and includes a second extension H2 that is extended in the opposite direction to the first extension H1, and the second extension H2 may intersect with the second and fourth edges E2 and E4. The distance between the first and second edges E1 and E2 may be equal to the distance between the third and fourth edges E3 and E4, and the widths of the first and second extensions H1 and H2 may be equal. In a plan view, the second and fourth edges E2 and E4 may overlap.

[0021] In Figure 6, for example, even if the first electrode 11 is shifted in the second direction D2 and the shape of the capacitance formation regions of the first and second capacitance elements C1 and C2 changes, the capacitance (capacitance value) of C1 and C2 themselves does not change. Furthermore, by forming the first to third electrodes 11 to 13 as shown in Figure 6, it can be seen that even if the first electrode 11 is shifted as shown in Figure 7, it does not affect the capacitance of the first and second capacitance elements C1 and C2. The same applies when the third electrode 13 is shifted.

[0022] Figures 8A and 8B are circuit diagrams showing the configuration of a light-emitting device including this control circuit. As shown in Figures 8A and 8B, the light-emitting device 20 comprises a light-emitting element ED (5) and one or more control circuits 10. When the light-emitting device 20 includes multiple control circuits 10, even if there are manufacturing variations in the capacitive elements in the multiple control circuits 10, current variations between control circuits 10 when the same data signal is input are less likely to occur. The light-emitting device 20 can be applied to display devices, printer heads, photolithography exposure devices, etc.

[0023] The light-emitting device 20 includes a power line PL, an initialization potential line IL, a reference potential line RL, a data line DL, a first scan line S1, a second scan line S2, and a third scan line S3. The control circuit 10 includes a first transistor T1 whose gate terminal is connected to the first scan line S1, a second transistor T2 whose gate terminal is connected to the second scan line S2, a third transistor T3 whose gate terminal is connected to the third scan line S3, a fourth transistor T4 (Td) which is a driving transistor, a first node N1 (first electrode 11) connected to the gate terminal of the fourth transistor T4, a second node N2 (second electrode 12) connected to one of the conductive terminals of the fourth transistor T4, and a third node N3 (third electrode 13).

[0024] The potential (Vr) of the reference potential line RL can be set higher than the potential (Vi) of the initialization potential line IL, and the potential of the power line PL can be set higher than the potential (Vr) of the reference potential line RL.

[0025] In the control circuit 10, the first node N1 is connected to the second node N2 via the first capacitance element C1 and to the reference potential line RL via the first transistor T1. The second node N2 is connected to the third node N3 via the second capacitance element C2, and the third node N3 is connected to the data line DL via the second transistor T2, to the reference potential line RL via the third transistor T3, and to the first node N1 via the third capacitance element C3.

[0026] The light-emitting device 20 includes a first light-emitting control line E1 and a second light-emitting control line E2. The control circuit 10 includes a fifth transistor T5 whose gate terminal is connected to the first light-emitting control line E1, a sixth transistor T6 whose gate terminal is connected to the second light-emitting control line E2, and a seventh transistor T7 (initialization transistor) whose gate terminal is connected to the third scan line S3.

[0027] The power line PL is connected to the second node N2 via the fifth transistor T5 and the fourth transistor T4 (drive transistor), and the second node N2 is connected to the anode of the light-emitting element ED via the sixth transistor T6. The anode of the light-emitting element ED is connected to the initialization potential line IL via the seventh transistor T7. The gate terminal of the seventh transistor T7 is not limited to being connected to the third scan line S3, but may also be connected to the first scan line S1.

[0028] In the light-emitting device 20, when potential is supplied to two or more of the first to third electrodes 11 to 13 (first to third nodes N1 to N3), the charge state of the first to third capacitive elements changes. After charging the first capacitive element C1 according to the data potential, during the lighting period from one charge according to the data potential to the next charge according to the data potential, two or more of the first to third electrodes 11 to 13 (first to third nodes N1 to N3) are driven without potential supply from other wiring (DL, RL, PL, IL).

[0029] Figure 9 is a timing chart showing the operation of the light-emitting device. Figure 10 is a circuit diagram showing the state during period Ka. During period Ka, transistors T3, T6, and T7 are in the ON state, the second node N2 (second electrode 12) is initialized to the initialization potential Vi by the initialization potential line IL, and the third node N3 (third electrode 13) is reset to the reference potential Vr by the reference potential line RL.

[0030] Figure 11 is a timing chart showing the operation of the light-emitting device. Figure 12 is a circuit diagram showing the state during period Kb. During period Kb, transistors T1, T3, T6, and T7 are in the ON state, and the first node N1 (first electrode 11) is reset to the reference potential Vr by the reference potential line RL.

[0031] Figure 13 is a timing chart showing the operation of the light-emitting device. Figure 14 is a circuit diagram showing the state during period Kc. During period Kc, transistors T1, T3, and T7 are ON, transistor T6 is OFF, and the second node N2 (second electrode 12) is floating.

[0032] Figure 15 is a timing chart showing the operation of the light-emitting device. Figure 16 is a circuit diagram showing the state during period Kd. During period Kd, transistors T1, T3, T5, and T7 are in the ON state. If the potential at the first node N1 is V1, the potential at the second node N2 is V2, and the threshold voltage of the fourth transistor is Vth, then V1 - V2 = Vth. Here, since V1 = Vr, V2 = Vr - Vth, and the threshold voltage of the fourth transistor T4 is compensated.

[0033] Immediately after the start of period Kd, the gate-source voltage Vgs of the fourth transistor T4 is high, causing current to flow between the source and drain of the fourth transistor T4, and charging the first and second capacitor elements C1 and C2 so that the potential of the second node N2 rises. As the potential of the second node N2 rises, the voltage Vgs decreases and it becomes more difficult for current to flow, but as long as current flows, the potential of the second node N2 continues to rise, and charging of the first and second capacitor elements C1 and C2 continues. Finally, when the voltage Vgs becomes equal to the threshold voltage Vth of the fourth transistor T4, current stops flowing, and charging ends. In other words, by setting the required time as period Kd, the threshold voltage Vth can be charged into the first capacitor element C1.

[0034] Figure 17 is a timing chart showing the operation of the light-emitting device. Figure 18 is a circuit diagram showing the state during period Ke. During period Ke, transistor T1 is ON, transistors T3, T5, and T7 are OFF, and the second node N2 (second electrode 12) and the third node N3 (third electrode 13) are floating.

[0035] Figure 19 is a timing chart showing the operation of the light-emitting device. Figure 20 is a circuit diagram showing the state during period Kf. During period Kf, transistors T1 and T2 are ON, and charging occurs via the data line DL according to the data potential. Letting the potential of the data line DL (data potential) be Vd, (V1 - V2) = Vgs can be expressed as follows: Vgs = V1 - V2 = Vth + {(Capacitance of C2) / (Capacitance of C1 + Capacitance of C2)} × (Vr - Vd) As a result, the voltage Vgs is maintained in the first capacitance element C1.

[0036] Figure 21 is a timing chart showing the operation of the light-emitting device. Figure 22 is a circuit diagram showing the state during period Kg. During period Kg, transistor T1 is in the ON state, transistor T2 is in the OFF state, and the third node N3 (third electrode 13) is floating.

[0037] Figure 23 is a timing chart showing the operation of the light-emitting device. Figure 24 is a circuit diagram showing the state during period Kh. During period Kh, all transistors T1 to T7 are in the OFF state, and the first node N1 (first electrode 11) is also floating.

[0038] Figure 25 is a timing chart showing the operation of the light-emitting device. Figure 26 is a circuit diagram showing the state during period Ki. During period Ki, transistors T5 and T6 are ON, a current Id corresponding to the data potential Vd flows through transistor T4, and the brightness of the light-emitting element ED is controlled according to the data potential Vd. During period Ki, the voltage Vgs does not change.

[0039] Thus, with the light-emitting device shown in Figures 8 to 26, the voltage Vgs is determined independently of the capacitance of the third capacitance element C3, enabling control (current control of the light-emitting element ED) that is not affected by the parasitic capacitance of the third capacitance element C3. During period Ks, the potential of the second node N2 (second electrode 12) is initialized, and during period Kr, the anode potential is reset.

[0040] The embodiments described above are for illustrative and explanatory purposes only, and not limiting purposes. It will be apparent to those skilled in the art that many variations are possible based on these examples and descriptions. The gist of this embodiment is described below. The term "described above" below includes the configurations disclosed in Figures 1 to 26.

[0041] [Summary] A control circuit connected to an object to be current controlled, including a drive transistor, comprising: a first electrode; a first insulating layer located above the first electrode; a second electrode overlapping the first electrode via the first insulating layer; a second insulating layer located above the second electrode; and a third electrode overlapping the second electrode via the second insulating layer, wherein the second electrode is connected to one conductive terminal of the drive transistor.

[0042] The control circuit described above, wherein the second electrode includes a main body and a first extension portion drawn out from the main body, and in a plan view, the entire main body overlaps with the first electrode.

[0043] The control circuit described above, wherein the entire body portion overlaps with the third electrode in a plan view.

[0044] The control circuit described above, wherein a first capacitor element is formed between the first electrode and the second electrode, a second capacitor element is formed between the second electrode and the third electrode, and a third capacitor element is formed between the first electrode and the third electrode.

[0045] The control circuit described above, wherein the first electrode or the third electrode is connected to the gate terminal of the driving transistor.

[0046] The control circuit described above, wherein the first electrode is connected to the gate terminal of the driving transistor.

[0047] The control circuit described above, wherein the third capacitor element has a smaller capacitance than the first capacitor element and the second capacitor element.

[0048] The control circuit described above, wherein the potential of the second electrode is initialized by supplying a reference potential to the first electrode and the third electrode while an initialization potential is supplied to the second electrode.

[0049] The control circuit described above, wherein the threshold voltage of the driving transistor is compensated by supplying a reference potential to the first electrode and the third electrode while a power supply potential is supplied to the other conduction terminal of the driving transistor.

[0050] The control circuit described above, wherein the first capacitor element is charged according to the data potential by supplying a reference potential to the first electrode and a data potential to the third electrode while the second electrode is electrically floating.

[0051] The control circuit described above, wherein the driving transistor supplies a current corresponding to the voltage held in the first capacitor element to the current control object.

[0052] The control circuit described above, wherein the first electrode includes opposing first and second edges, the third electrode includes opposing third and fourth edges, and the first lead portion intersects the first and third edges.

[0053] The control circuit described above, wherein the first and third edges overlap in a plan view.

[0054] The control circuit described above, wherein the second electrode is connected to the main body and includes a second lead-out portion that is drawn out in the opposite direction to the first lead-out portion, and the second lead-out portion intersects with the second and fourth edges.

[0055] The control circuit described above, wherein the distance between the first and second edges is equal to the distance between the third and fourth edges.

[0056] The control circuit described above, wherein the widths of the first and second drawer sections are equal.

[0057] The control circuit described above, wherein the second and fourth edges overlap in a plan view.

[0058] The control circuit described above controls a light-emitting element as the object to be controlled by current.

[0059] A light-emitting device comprising a light-emitting element and the control circuit described above.

[0060] The light-emitting device comprises a power line, an initialization potential line, a reference potential line, a data line, a first scan line, a second scan line, and a third scan line, wherein the control circuit includes a first transistor whose gate terminal is connected to the first scan line, a second transistor whose gate terminal is connected to the second scan line, a third transistor whose gate terminal is connected to the third scan line, a fourth transistor which is the drive transistor, a first node connected to the gate terminal of the fourth transistor, a second node connected to one of the conductive terminals of the fourth transistor, and a third node, wherein the first node is connected to the second node via the first capacitance element and to the reference potential line via the first transistor, the second node is connected to the third node via the second capacitance element, and the third node is connected to the data line via the second transistor, to the reference potential line via the third transistor, and to the first node via the third capacitance element.

[0061] The above-described light-emitting device comprises a first light-emitting control line and a second light-emitting control line, wherein the control circuit includes a fifth transistor whose gate terminal is connected to the first light-emitting control line, a sixth transistor whose gate terminal is connected to the second light-emitting control line, and a seventh transistor whose gate terminal is connected to the third scan line, the power line is connected to the second node via the fifth transistor and the fourth transistor, the second node is connected to the anode of the light-emitting element via the sixth transistor, and the anode of the light-emitting element is connected to the initialization potential line via the seventh transistor.

[0062] The above-described light-emitting device, wherein the potential of the second node is initialized during the period when the first transistor, the third transistor, the sixth transistor, and the seventh transistor are ON and the other transistors are OFF.

[0063] The above-described light-emitting device, wherein threshold compensation of the fourth transistor is performed during the period when the first transistor, the third transistor, the fifth transistor, and the seventh transistor are ON and the other transistors are OFF.

[0064] The above-described light-emitting device, wherein data is written to the first capacitive element during a period when the first transistor and the second transistor are ON and the other transistors are OFF.

[0065] The above-described light-emitting device, wherein, during the period when the fifth transistor and the sixth transistor are ON and the other transistors are OFF, the fourth transistor supplies a current to the light-emitting element corresponding to the voltage held in the first capacitive element.

[0066] The above-described light-emitting device, wherein the potential of the anode of the light-emitting element is reset during the period in which threshold compensation of the fourth transistor is performed.

[0067] A display device including the light-emitting device described above.

[0068] A method for driving the control circuit described above, wherein, after charging the first capacitive element with a predetermined voltage by supplying voltage to the first electrode and the third electrode, two or more electrodes among the first electrode, second electrode, and third electrode are not simultaneously connected to other wiring, thereby preventing the predetermined voltage from changing even when the third capacitive element is formed.

[0069] 11 First electrode 12 Second electrode 13 Third electrode Td T4 Driving transistor N1 First node N2 Second node N3 Third node C1 First capacitance element C2 Second capacitance element C3 Third capacitance element H1 First lead section H2 Second lead section HT Main body

Claims

1. A control circuit connected to an object to be current controlled, including a drive transistor, comprising: a first electrode; a first insulating layer located above the first electrode; a second electrode overlapping the first electrode via the first insulating layer; a second insulating layer located above the second electrode; and a third electrode overlapping the second electrode via the second insulating layer, wherein the second electrode is connected to one conductive terminal of the drive transistor.

2. The control circuit according to claim 1, wherein the second electrode includes a main body and a first extension portion drawn out from the main body, and in a plan view, the entire main body overlaps with the first electrode.

3. The control circuit according to claim 2, wherein, in a plan view, the entire main body overlaps with the third electrode.

4. The control circuit according to any one of claims 1 to 3, wherein a first capacitive element is formed between the first electrode and the second electrode, a second capacitive element is formed between the second electrode and the third electrode, and a third capacitive element is formed between the first electrode and the third electrode.

5. The control circuit according to claim 4, wherein the first electrode or the third electrode is connected to the gate terminal of the drive transistor.

6. The control circuit according to claim 5, wherein the first electrode is connected to the gate terminal of the drive transistor.

7. The control circuit according to claim 5, wherein the third capacitance element has a smaller capacitance than the first capacitance element and the second capacitance element.

8. The control circuit according to claim 6, wherein the potential of the second electrode is initialized by supplying a reference potential to the first electrode and the third electrode while an initialization potential is supplied to the second electrode.

9. The control circuit according to claim 6, wherein threshold compensation of the drive transistor is performed by supplying a reference potential to the first electrode and the third electrode while the power supply potential is supplied to the other conductive terminal of the drive transistor.

10. The control circuit according to claim 6, wherein, with the second electrode electrically floating, a reference potential is supplied to the first electrode and a data potential is supplied to the third electrode, thereby charging the first capacitive element according to the data potential.

11. The control circuit according to claim 10, wherein the drive transistor supplies a current to the current-controlled object corresponding to the voltage held in the first capacitive element.

12. The control circuit according to claim 3, wherein the first electrode includes opposing first and second edges, the third electrode includes opposing third and fourth edges, and the first lead portion intersects with the first and third edges.

13. The control circuit according to claim 12, wherein the first and third edges overlap in a plan view.

14. The control circuit according to claim 12 or 13, wherein the second electrode includes a second lead portion connected to the main body and extended in the opposite direction to the first lead portion, and the second lead portion intersects the second and fourth edges.

15. The control circuit according to claim 14, wherein the distance between the first and second edges is equal to the distance between the third and fourth edges.

16. The control circuit according to claim 14, wherein the widths of the first and second drawer portions are equal.

17. The control circuit according to claim 14, wherein the second and fourth edges overlap in a plan view.

18. The control circuit according to any one of claims 1 to 17, wherein the object to be controlled by current is a light-emitting element.

19. A light-emitting device comprising a light-emitting element and a control circuit according to claim 4.

20. A light-emitting device according to claim 19, comprising a power line, an initialization potential line, a reference potential line, a data line, a first scan line, a second scan line, and a third scan line, wherein the control circuit includes a first transistor whose gate terminal is connected to the first scan line, a second transistor whose gate terminal is connected to the second scan line, a third transistor whose gate terminal is connected to the third scan line, a fourth transistor which is the drive transistor, a first node connected to the gate terminal of the fourth transistor, a second node connected to one of the conductive terminals of the fourth transistor, and a third node, wherein the first node is connected to the second node via the first capacitance element and to the reference potential line via the first transistor, the second node is connected to the third node via the second capacitance element, and the third node is connected to the data line via the second transistor, to the reference potential line via the third transistor, and to the first node via the third capacitance element.

21. The light-emitting device according to claim 20, comprising a first light-emitting control line and a second light-emitting control line, wherein the control circuit includes a fifth transistor whose gate terminal is connected to the first light-emitting control line, a sixth transistor whose gate terminal is connected to the second light-emitting control line, and a seventh transistor whose gate terminal is connected to the first scan line or the third scan line, wherein the power line is connected to the second node via the fifth transistor and the fourth transistor, the second node is connected to the anode of the light-emitting element via the sixth transistor, and the anode of the light-emitting element is connected to the initialization potential line via the seventh transistor.

22. The light-emitting device according to claim 21, wherein the potential of the second node is initialized during the period when the first transistor, the third transistor, the sixth transistor, and the seventh transistor are ON and the other transistors are OFF.

23. The light-emitting device according to claim 21, wherein threshold compensation of the fourth transistor is performed during the period when the first transistor, the third transistor, the fifth transistor, and the seventh transistor are ON and the other transistors are OFF.

24. The light-emitting device according to claim 21, wherein the first capacitor element is charged according to the data potential during the period when the first transistor and the second transistor are ON and the other transistors are OFF.

25. The light-emitting device according to claim 21, wherein during the period when the fifth transistor and the sixth transistor are ON and the other transistors are OFF, the fourth transistor supplies a current to the light-emitting element corresponding to the voltage held in the first capacitive element.

26. The light-emitting device according to claim 23, wherein the potential of the anode of the light-emitting element is reset during the period in which threshold compensation of the fourth transistor is performed.

27. A display device comprising a light-emitting device according to any one of claims 20 to 26.

28. A method for driving a control circuit according to claim 10, wherein, after charging the first capacitive element with a predetermined voltage by supplying voltage to the first electrode and the third electrode, two or more electrodes among the first electrode, the second electrode and the third electrode are not simultaneously connected to other wiring, thereby preventing the predetermined voltage from changing even when the third capacitive element is formed.

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