Display panel

Abstract

The display panel comprises a substrate, a plurality of pixel islands and a trace. The substrate comprises a first substrate layer and a second substrate layer which are stacked. The plurality of pixel islands are located on a side of the second substrate layer away from the first substrate layer, and each pixel island comprises at least one light emitting device. The trace is connected with the pixel islands and is located between the first substrate layer and the second substrate layer. By arranging the trace between the first substrate layer and the second substrate layer in the substrate, the trace can be prevented from being broken due to the difference in height of the trace at the edges of the pixel islands.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel. Background Technology

[0002] Stretchable electronic display products, capable of stretching and deforming in one or multiple directions, are favored by users. However, due to limitations in their design structure, the reliability of the encapsulation layer in stretchable display panels still needs improvement. Summary of the Invention

[0003] This disclosure provides a display panel that solves the problem of insufficient reliability of pixel island packaging by setting the traces connecting the pixel islands in the display panel in a flexible substrate.

[0004] This disclosure provides a display panel including a substrate, a plurality of pixel islands, and traces. The substrate includes a first substrate layer and a second substrate layer stacked thereon. The plurality of pixel islands are located on the side of the second substrate layer opposite to the first substrate layer, and each pixel island includes at least one light-emitting device. The traces are connected to the pixel islands and are located between the first substrate layer and the second substrate layer.

[0005] In the above scheme, placing the traces between the first and second substrate layers can reduce the risk of trace breakage, that is, this design can improve the reliability of the traces; in addition, the packaging of the pixel islands is no longer restricted by the traces, which makes the packaging layer formed in subsequent processes more flexible and can remove the restriction of the trace position on the packaging layer.

[0006] In one specific embodiment of this disclosure, the substrate further includes a first buffer layer. The first buffer layer is disposed between the trace and the first substrate layer.

[0007] For example, optionally, the first buffer layer is an inorganic material, and the first base layer and the second base layer are organic materials.

[0008] In the above scheme, the first buffer layer (inorganic layer) has a strong bond with the trace, thereby reducing the risk of interface separation on both sides of the trace.

[0009] In one specific embodiment of this disclosure, the pixel island further includes a driving circuit layer. The driving circuit layer is located between the substrate and the light-emitting device, and includes pixel driving circuitry and multiple dielectric layers. The pixel driving circuitry is connected to traces.

[0010] Optionally, at least one dielectric layer has a via, through which the traces are connected to the pixel driving circuit.

[0011] For example, the pixel driving circuit may optionally include at least one of a thin-film transistor and a capacitor.

[0012] In one specific embodiment of this disclosure, the display panel further includes an encapsulation layer. The encapsulation layer covers the pixel islands and is in contact with a first buffer layer and / or at least one dielectric layer.

[0013] For example, optionally, the encapsulation layer includes a first inorganic encapsulation layer, the edge of which contacts at least one of a first buffer layer and a plurality of dielectric layers.

[0014] In one specific embodiment of this disclosure, the plurality of dielectric layers include at least one of a gate insulating layer, a capacitor dielectric layer, and a passivation layer.

[0015] In one specific embodiment of this disclosure, the encapsulation layer further includes a second inorganic encapsulation layer, with the first inorganic encapsulation layer located between the second inorganic encapsulation layer and the substrate. The orthographic projection of the first inorganic encapsulation layer onto the substrate lies within the orthographic projection of the second inorganic encapsulation layer onto the substrate.

[0016] For example, optionally, the edges of the first inorganic encapsulation layer and the second inorganic encapsulation layer face the substrate and are in contact with different dielectric layers.

[0017] For example, the display panel may optionally include a second buffer layer. The second buffer layer is located between the pixel islands and the second base layer.

[0018] Optionally, the edge of the first inorganic encapsulation layer contacts at least one of the plurality of dielectric layers, the first buffer layer, and the second buffer layer on the surface of the first substrate layer.

[0019] Optionally, the edge of the second inorganic encapsulation layer contacts at least one of the first buffer layer, the second buffer layer, and the plurality of dielectric layers on the surface facing the first substrate layer.

[0020] Optionally, the surface of the first inorganic encapsulation layer facing the first substrate layer and the surface of the second inorganic encapsulation layer facing the first substrate layer are in contact with the same film layer in the first buffer layer, the second buffer layer, and the plurality of dielectric layers; or, the surface of the first inorganic encapsulation layer facing the substrate and the surface of the second inorganic encapsulation layer facing the substrate are in contact with different film layers in the first buffer layer, the second buffer layer, and the plurality of dielectric layers, respectively.

[0021] Optionally, among the first buffer layer, the second buffer layer, and the plurality of dielectric layers, the film layer whose edge of the first inorganic encapsulation layer is in contact with the surface of the first substrate layer facing the first substrate layer is further away from the first substrate layer than the film layer whose edge of the second inorganic encapsulation layer is in contact with the surface of the first substrate layer facing the first substrate layer.

[0022] For example, optionally, the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact at the edge of the pixel island.

[0023] For example, optionally, the encapsulation layer may further include at least one organic encapsulation layer and / or at least one inorganic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0024] For example, optionally, the material of at least one dielectric layer in contact with the encapsulation layer is an inorganic material.

[0025] In one specific embodiment of this disclosure, the display panel further includes a first recess. The first recess is disposed in the driving circuit layer and the second substrate layer, and the encapsulation layer covers the first recess.

[0026] For example, optionally, the orthographic projection of the first groove on the substrate surrounds the orthographic projection of the pixel driving circuit and the light-emitting device on the substrate.

[0027] In the above embodiment, the first groove surrounds the light-emitting device, which can block water, air and impurities from entering from the gap at the junction of the encapsulation layer and the dielectric layer from eroding the light-emitting device and circuit elements, thereby improving the reliability of the encapsulation.

[0028] In one specific embodiment of this disclosure, a through hole is located in a first groove, a contact pad is provided in the through hole, and the wiring is connected to the pixel driving circuit through the contact pad.

[0029] In one specific embodiment of this disclosure, the contact pad fills the through hole.

[0030] In one specific embodiment of this disclosure, the contact pad conforms to the first groove.

[0031] For example, the display panel may optionally include a barrier layer that covers the first recess and the portion of the barrier layer that covers the first recess is conformal to the first recess.

[0032] For example, optionally, a blocking layer covers the pixel islands.

[0033] For example, the material of the barrier layer may optionally include metal oxides.

[0034] For example, the metal compound material may optionally include aluminum oxide or titanium nitride. Attached Figure Description

[0035] Figure 1 This is a top view of a display panel according to an embodiment of the present disclosure.

[0036] Figure 2 This is a partially enlarged schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0037] Figure 3 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0038] Figure 4This is a partial cross-sectional schematic diagram of a pixel island of a display panel provided in an embodiment of the present disclosure.

[0039] Figure 5 This is a schematic diagram of the through-holes and light-emitting devices of a display panel as an embodiment of the present disclosure, projected onto a substrate.

[0040] Figure 6 This is a partial cross-sectional schematic diagram of a pixel island of a display panel provided in an embodiment of the present disclosure.

[0041] Figure 7 This is a partial cross-sectional schematic diagram of pixel islands in another display panel provided in an embodiment of the present disclosure.

[0042] Figure 8 This is a partial cross-sectional schematic diagram of pixel islands in another display panel provided in an embodiment of the present disclosure.

[0043] Figure 9 This is a partial cross-sectional schematic diagram of a pixel island of a display panel provided in an embodiment of the present disclosure.

[0044] Figure 10 This is a partial cross-sectional schematic diagram of pixel islands in another display panel provided in an embodiment of the present disclosure.

[0045] Figure 11 This is a schematic diagram of a through hole, a first groove, a second groove, and a light-emitting device projected onto a substrate in an embodiment of this disclosure.

[0046] Figure 12 This is a partial cross-sectional schematic diagram of pixel islands in another display panel provided in an embodiment of the present disclosure.

[0047] Figure 13 This is a partial cross-sectional schematic diagram of another display panel provided in an embodiment of the present disclosure.

[0048] Figure label:

[0049] 100 - Display panel; 101 - Display area; 102 - Non-display area; 10 - Substrate; 11 - Island area; 12 - Flexible connection area; 13 - First substrate layer; 14 - Second substrate layer; 15 - First buffer layer; 20 - Pixel island; 21 - Light-emitting device; 211 - Anode; 212 - Light-emitting functional layer; 213 - Light-emitting layer; 214 - Cathode; 22 - Pixel defining layer; 23 - Driving circuit layer; 231 - Thin-film transistor; 232 - Capacitor ; 233-Second buffer layer; 234-Capacitor dielectric layer; 235-Gate insulating layer; 236-Passivation layer; 237-Planarization layer; 30-Trace; 40-Through hole; 41-Contact pad; 50-Encapsulation layer; 51-First inorganic encapsulation layer; 52-Organic encapsulation layer; 53-Second inorganic encapsulation layer; 60-First groove; 61-Second groove; 70-Barrier layer; 2311-Gate layer; 2321-First electrode plate; 2322-Second electrode plate. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] Currently, stretchable display panels have gained widespread attention. They generally consist of multiple pixel islands, each containing at least one sub-pixel. The pixel islands are connected by elastic connection areas. Because the connection areas are elastic, stretchable display panels can be stretched or twisted in various directions. However, since stretchable display panels are constantly stretched and twisted, higher requirements are placed on the reliability of the pixel island packaging.

[0052] In view of this, at least one embodiment of the present disclosure provides a display panel to solve the problem of insufficient packaging reliability of pixel islands.

[0053] The specific structure of the display panel in at least one embodiment of this disclosure will now be described with reference to the accompanying drawings. In these drawings, a spatial Cartesian coordinate system is established with the plane of the display panel in a flat state as a reference to illustrate the position of each structure within the display panel. In this spatial Cartesian coordinate system, the X-axis and Y-axis are parallel to the plane of the display panel, and the Z-axis is perpendicular to the plane of the display panel.

[0054] Figure 1 This is a top view of a display panel 100 provided in an embodiment of the present disclosure. Figure 1As shown, the display panel 100 may include a display area 101 and a non-display area 102. The display panel 100 may be a flexible display panel, such as a stretchable display panel. Figure 2 for Figure 1 An enlarged schematic diagram of region S1. (See attached image.) Figure 2 As shown, the substrate 10 located in the display area 101 includes a plurality of island areas 11 spaced apart, and an elastic connection area 12 between adjacent island areas 11. Pixel islands 20 are disposed on the island areas 11, and each pixel island 20 includes at least one light-emitting device.

[0055] Specifically, the shape of the pixel islands can be adaptively adjusted as needed, and is not limited to... Figure 2 The square shown can also be a rectangle, hexagon, or circle, etc.

[0056] Figure 3 For along Figure 2 A cross-sectional view of line AB in the middle. (See diagram below.) Figure 3 As shown, one embodiment of this disclosure provides a display panel 100, which includes a substrate 10, a plurality of pixel islands 20 and traces 30.

[0057] Specifically, the substrate 10 includes a first substrate layer 13 and a second substrate layer 14 stacked together. The first substrate layer 13 and the second substrate layer 14 may be flexible substrate layers. The materials of the first substrate layer 13 and the second substrate layer 14 may be organic materials, respectively. For example, the first substrate layer 13 and the second substrate layer 14 may be made of one or more of the following materials: polyimide, silicone rubber, polyurethane elastomers, and acrylic elastomers.

[0058] Optionally, the island region 11 and the elastic connection region 12 of the substrate 10 can be made of the same or different materials. For example, the substrate 10 in the island region 11 can be made of a non-elastic material to ensure the reliability of the pixel island 20 encapsulation; or the substrate 10 in the elastic connection region 12 can be made of a highly elastic material to ensure tensile performance.

[0059] Pixel islands 20 are located on the side of the second substrate layer 14 opposite to the first substrate layer 13, and each pixel island 20 includes at least one light-emitting device 21. Optionally, each pixel island 20 may also include a driving circuit layer 23. Specifically, the light-emitting device 21 may be an OLED light-emitting device. For example, the light-emitting device 21 may include an anode 211, a light-emitting functional layer 212, a light-emitting layer 213, and a cathode 214 stacked on the substrate 10. Optionally, the light-emitting device 21 is specifically disposed in a pixel opening of the pixel defining layer 22. Optionally, the light-emitting functional layer 212 may include one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. Optionally, one or more of an electron injection layer, an electron transport layer, and a hole blocking layer may also be included between the light-emitting layer 213 and the cathode 214.

[0060] The trace 30 is connected to the pixel island 20, and the trace 30 is located between the first substrate layer 13 and the second substrate layer 14. Multiple pixel islands 20 can be connected via the trace 30. Part or all of a trace 30 is located between the first substrate layer 13 and the second substrate layer 14. Optionally, the portion of the trace 30 located in the island region 11 is located between the first substrate layer 13 and the second substrate layer 14, and the portion of the trace 30 located in the elastic connection region 12 is also located between the first substrate layer 13 and the second substrate layer 14. The portion of the trace 30 in the island region 11 and the portion in the elastic connection region 12 are located on the same layer. This method can shorten the distance between the start and end of the voltage input of the trace 30, thereby reducing the voltage drop effect.

[0061] In at least one embodiment of this disclosure, the substrate and traces can be formed using the following process. Optionally, polyimide (PI) is first coated and cured to form a first substrate layer 13; a metal trace layer is formed using processes such as physical vapor deposition (PVD), screen printing, or slit coating, and a predetermined pattern is formed by exposure etching or laser etching to form traces 30; finally, polyimide is coated and cured to form a second substrate layer 14 on traces 30.

[0062] The trace 30 can be a signal line that connects to the corresponding pixel island 20 and provides a signal to the corresponding pixel island 20. For example, the trace 30 may include one or more of the following: a reference voltage signal line REF, a power supply signal line VDD, a scan signal line Scan, an illumination control signal line EM, and a data line Data.

[0063] In this embodiment, the trace 30 is sandwiched between the two substrate layers, preventing easy separation from them. Furthermore, when the display panel undergoes stretching, bending, or other deformations, the stress on the trace 30 is dispersed into the substrate 10, reducing the risk of trace 30 breakage. This design improves the reliability of the trace 30. Additionally, this design prevents the trace 30 from being exposed on the substrate or even the encapsulation surface of the pixel island 20. This avoids the problem of trace 30 breaking due to discontinuities at the edges of the pixel island when it is placed in the driving circuit layer. Placing the trace 30 within the substrate 10 also frees the encapsulation layer of the pixel island 20 from the constraints of the trace, improving the encapsulation quality of the pixel island 20. Therefore, placing the trace 30 between the first substrate layer 13 and the second substrate layer 14 avoids the poor encapsulation reliability issues caused by placing the trace 30 between the substrate 10 and the encapsulation layer 50, thus improving encapsulation reliability.

[0064] like Figure 4 As shown, in one embodiment of this disclosure, in order to better protect the trace 30 and ensure the reliability of the display panel 100 packaging, optionally, the display panel 100 further includes a first buffer layer 15. The first buffer layer 15 is disposed between the trace 30 and the first base layer 13. The first buffer layer 15 plays the role of protecting the pixel island 20 and preventing external ions, water vapor and oxygen from entering the pixel island, thereby preventing the trace 30 and the electronic components in the driving circuit layer from being corroded.

[0065] Optionally, the first buffer layer 15 is made of an inorganic material. Optionally, the first base layer 13 and the second base layer 14 are organic layers. The material of the first buffer layer 15 may include one or more of silicon oxide, silicon nitride, etc. In this way, the trace 30 is isolated from the external environment by multiple layers of materials such as organic and inorganic layers, effectively preventing the trace 30 from being corroded by external water vapor and protecting the trace 30.

[0066] Optionally, before forming the trace 30, a first buffer layer 15 is formed on the first substrate layer 13 using a chemical vapor deposition (CVD) process.

[0067] The first buffer layer 15 has a strong bond with the trace 30, thus preventing the trace 30 from separating from the first base layer 13 and the second base layer 14 and moving within the substrate 10, thereby fixing the trace and improving its reliability. The first buffer layer 15 also has good bonding strength with the first base layer 13 and the second base layer 14 on both sides, which can avoid the risk of interface separation.

[0068] like Figure 3 and Figure 4 As shown, in one embodiment of this disclosure, the display panel 100 may optionally include a driving circuit layer 23. Optionally, the driving circuit layer 23 is located between the light-emitting device 21 and the substrate 10 in the island area 11. Optionally, the driving circuit layer 23 includes a pixel driving circuit and multiple dielectric layers. The multiple dielectric layers can be used to define circuit elements in the pixel driving circuit. The dielectric layers may be insulating dielectric layers, having an insulating function. The traces 30 may be connected to the pixel driving circuit. Optionally, at least one dielectric layer has a via 40, and the traces 30 are connected to the pixel driving circuit through the via 40.

[0069] For example, optionally, the pixel driving circuit includes at least one circuit element selected from thin-film transistor 231 and capacitor 232. Optionally, the plurality of dielectric layers in the driving circuit layer 23 include one or more of capacitor dielectric layer 234, gate insulating layer 235, and passivation layer 236 stacked on the substrate 10. Thin-film transistor 231 may include an active layer, gate layer 2311, and source / drain layers; the active layer may include source / drain regions and channels of different doping types. Capacitor 232 may include a first electrode 2321 and a second electrode 2322 located on both sides of capacitor dielectric layer 234. The materials of capacitor dielectric layer 234, gate insulating layer 235, and passivation layer 236 may be insulating materials, while the materials of gate layer 2311, source / drain layers, first electrode 2321, and second electrode 2322 are conductive materials, specifically metallic materials. Gate insulating layer 235 may be located between the active layer and gate layer 2311. The capacitor dielectric layer 234 and passivation layer 236 may be located between the gate layer 2311 and the source / drain layers. The source / drain layers can be electrically connected to the source and drain regions of the active layer through vias. Optionally, the gate layer 2311 and the first electrode 2321 of the capacitor 232 may be disposed in the same layer. Optionally, the gate layer 2311 and the first electrode 2321 of the capacitor 232 may be fabricated by patterning the same conductive layer in the same process. Forming the gate layer 2311 and the first electrode 2321 of the capacitor 232 in this way can improve the formation efficiency of the display panel.

[0070] Optionally, the display panel further includes a second buffer layer 233. The second buffer layer 233 is located between the pixel island 20 and the second substrate layer 14. Optionally, the second buffer layer 233 is located between the second substrate layer 14 and the active layer. The second buffer layer 233 can serve as a dielectric layer in the driving circuit layer 23, or it can be disposed in the substrate 10. The second buffer layer 233 can be an inorganic buffer layer. The material of the second buffer layer 233 may include at least one of silicon oxide and silicon nitride.

[0071] Optionally, to improve the packaging reliability of the display panel 100, the through-hole 40 penetrates the driving circuit layer 23 and the second substrate layer 14 to expose the trace 30. A contact pad 41 is filled in the through-hole 40, and the trace 30 is connected to the pixel driving circuit through the contact pad 41. Alternatively, as... Figure 5As shown, the orthographic projection of the via 40 onto the substrate 10 surrounds the pixel driving circuit (not shown) and the orthographic projection of the light-emitting device 21 onto the substrate 10. That is, the via 40 forms a closed annular groove, and the contact pad 41 is made of a conductive material, including metal (e.g., copper), and fills the via 40. Because metal has excellent density, it can further block water, gas, and impurities, thereby improving packaging reliability. Specifically, the shape of the orthographic projection of the via 40 onto the substrate 10 can be a polygonal annulus, specifically adjusted according to the shape of the pixel island 20, for example, it can be a rectangular, circular, or elliptical annulus. The contact pad 41 can also contact the first buffer layer 15 to improve the packaging effect.

[0072] like Figure 6 As shown, in one embodiment of this disclosure, optionally, the display panel 100 further includes an encapsulation layer 50. Optionally, the encapsulation layer 50 covers the pixel islands 20. Optionally, the orthographic projection of the encapsulation layer 50 onto the substrate 10 is located in the island region 11. Optionally, the island region 11 is located within the orthographic projection of the encapsulation layer 50 onto the substrate 10.

[0073] Optionally, the encapsulation layer 50 may contact the first buffer layer 15 to cover the second base layer 14, the circuit elements and light-emitting devices in the pixel driving circuit, forming a blocking structure to improve the encapsulation effect.

[0074] Optionally, the encapsulation layer 50 may contact the second buffer layer 233 to cover the circuit elements and light-emitting devices in the pixel driving circuit, forming a blocking structure to improve the encapsulation effect.

[0075] Specifically, the dielectric layer furthest from the substrate 10 among the plurality of dielectric layers is the first dielectric layer. Optionally, the encapsulation layer 50 contacts at least one of the plurality of dielectric layers to cover at least a portion of the circuit elements and light-emitting devices in the pixel driving circuit, forming a barrier structure to improve the encapsulation effect. Optionally, the edge of the encapsulation layer 50 contacts at least one of the plurality of dielectric layers, and the dielectric layer in contact with the encapsulation layer 50 is located between the first dielectric layer and the substrate 10. Optionally, in an optional embodiment, the first dielectric layer is a passivation layer 236.

[0076] Optionally, to further improve the reliability of the pixel island 20 packaging, the dielectric layer in contact with the packaging layer 50 includes the dielectric layer closest to the substrate 10 among multiple dielectric layers. The closer the dielectric layer connected to the packaging layer 50 is to the substrate 10, the lower the probability that water, gas, and impurities can enter the pixel island 20. Therefore, this approach further improves the reliability of the packaging.

[0077] In this embodiment, since the trace 30 is disposed in the substrate 10, compared to the arrangement of the trace 30 in the driving circuit layer 23 or between the driving circuit layer 23 and the substrate 10, the encapsulation layer 50 is not limited by the position of the trace 30 and can be connected to any dielectric layer in the driving circuit layer. Therefore, by disposing the trace 30 between the two substrate layers and connecting the encapsulation layer 50 to the dielectric layer located below the first dielectric layer, the reliability of the encapsulation can be ensured.

[0078] Optionally, the encapsulation layer 50 may include at least one inorganic encapsulation layer. The material of the inorganic encapsulation layer may include at least one of silicon oxide and silicon nitride. Optionally, at least a portion of the edge of the inorganic encapsulation layer in the encapsulation layer 50 may contact the first buffer layer 15 to cover the second substrate layer 14, the circuit elements and light-emitting devices in the pixel driving circuit, forming a barrier structure to improve the encapsulation effect. Optionally, at least a portion of the edge of the inorganic encapsulation layer in the encapsulation layer 50 may contact the second buffer layer 233 to cover the circuit elements and light-emitting devices in the pixel driving circuit, forming a barrier structure to improve the encapsulation effect. Optionally, at least a portion of the edge of the inorganic encapsulation layer in the encapsulation layer 50 may contact at least one dielectric layer to cover at least a portion of the circuit elements and light-emitting devices in the pixel driving circuit, forming a barrier structure.

[0079] Optionally, the encapsulation layer 50 may include multiple inorganic encapsulation layers stacked along the thickness direction Z of the substrate 10. Optionally, the edges of at least two inorganic encapsulation layers in the encapsulation layer 50 contact the same dielectric layer. Optionally, the edges of at least two inorganic encapsulation layers in the encapsulation layer 50 contact different dielectric layers. Optionally, the edges of the multiple dielectric layers may be stepped. Optionally, the edges of at least two inorganic encapsulation layers in the encapsulation layer 50 have different heights relative to the substrate 10 (or the first substrate layer 13). The edges of the same inorganic encapsulation layer may have the same or different heights relative to the substrate 10 (or the first substrate layer 13). Optionally, in the encapsulation layer 50, the inorganic encapsulation layers farther from the substrate 10 (or the first substrate layer 13) contact the dielectric layers closer to the substrate 10 (or the first substrate layer 13), so that their inner and outer layers encapsulate at least a portion of the circuit elements and light-emitting devices in the pixel driving circuit, forming an inner and outer layer blocking structure. Optionally, in the encapsulation layer 50, the orthographic projection of the inorganic encapsulation layer near the substrate 10 (or the first substrate layer 13) onto the substrate 10 lies within the orthographic projection of the inorganic encapsulation layer away from the substrate 10 (or the first substrate layer 13) onto the substrate 10.

[0080] Optionally, the encapsulation layer 50 may include multiple inorganic encapsulation layers and at least one organic encapsulation layer stacked along the thickness direction Z of the substrate. Optionally, the inorganic and organic encapsulation layers may be stacked alternately. The organic encapsulation layer may buffer stress generated between the inorganic encapsulation layers. The material of the inorganic encapsulation layer may include alumina, tantalum oxide, hafnium oxide, zinc oxide, SiOx, SiNx, and / or SiON. The organic encapsulation layer may include polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, PI, polyethylene, etc.

[0081] like Figure 7 As shown, in one embodiment of this disclosure, to further improve the reliability of the pixel island 20 packaging, optionally, the packaging layer 50 includes a first inorganic packaging layer 51. Optionally, the edge of the first inorganic packaging layer 51 contacts at least one of the plurality of dielectric layers in the driving circuit layer 23. Optionally, the edge of the first inorganic packaging layer 51 contacts at least one of the plurality of dielectric layers in the driving circuit layer 23, excluding the passivation layer 236. For example, the side of the edge of the first inorganic packaging layer 51 facing the first base layer 13 is connected to the capacitor dielectric layer 234 or the gate insulating layer 235. Optionally, the surface of the edge of the first inorganic packaging layer 51 facing the first base layer 13 may also contact the second buffer layer 233 or the first buffer layer 15. Optionally, the surface of the edge of the first inorganic packaging layer 51 facing the first base layer 13 may contact the first buffer layer 15 and at least one of the plurality of dielectric layers. Optionally, the surface of the edge of the first inorganic packaging layer 51 facing the first base layer 13 may contact the second buffer layer 233 and at least one of the plurality of dielectric layers. Optionally, the edge of the first inorganic encapsulation layer 51 facing the surface of the first base layer 13 contacts at least one of the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers.

[0082] Optional, such as Figure 7 As shown, the encapsulation layer 50 further includes a second inorganic encapsulation layer 53. The first inorganic encapsulation layer 51 is located between the second inorganic encapsulation layer 53 and the substrate 10 (or the first substrate layer 13). Optionally, the orthographic projection of the first inorganic encapsulation layer 51 on the substrate 10 lies within the orthographic projection of the second inorganic encapsulation layer 53 on the substrate 10.

[0083] Optionally, the edges of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 facing the surface of the first substrate layer 13 are in contact with the same dielectric layer. Optionally, the edges of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 facing the surface of the first substrate layer 13 are in contact with different dielectric layers to form an inner and outer layer barrier structure.

[0084] Optionally, at least one of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 has its edge facing the surface of the first base layer 13 and contacting the first buffer layer 15, so that the coverage area is larger and deeper, and a portion of the second base layer 14 is wrapped in it, further improving the encapsulation effect.

[0085] Optional, such as Figure 7 As shown, at the edge of pixel island 20, the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 are in contact. The outer second inorganic encapsulation layer 53 itself covers the inner first inorganic encapsulation layer 51. The edge of the first inorganic encapsulation layer 51 faces the surface of the first base layer 13 and contacts the first buffer layer 15. The first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 are in contact, and the relationship between the two can be used to cover them again, further improving the encapsulation effect.

[0086] Optionally, the surface of the edge of the second inorganic encapsulation layer 53 facing the first base layer 13 contacts at least one of the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers. Optionally, the surface of the edge of the second inorganic encapsulation layer 53 facing the first base layer 13 contacts at least one of the first buffer layer 15 and the plurality of dielectric layers. Optionally, the surface of the edge of the second inorganic encapsulation layer 53 facing the first base layer 13 contacts at least one of the second buffer layer 233 and the plurality of dielectric layers.

[0087] Optionally, the edges of the first inorganic encapsulation layer 51 facing the surface of the first base layer 13 and the edges of the second inorganic encapsulation layer 53 facing the surface of the first base layer 13 are in contact with the same film layer among the first buffer layer 15, the second buffer layer 233 and the plurality of dielectric layers.

[0088] Optionally, the surface of the first inorganic encapsulation layer 51 facing the substrate 10 and the surface of the second inorganic encapsulation layer 53 facing the substrate 10 are respectively in contact with different films among the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers. For example, the side of the first inorganic encapsulation layer 51 facing the substrate 10 is connected to one of the passivation layer 236, the capacitor dielectric layer 234, the gate insulating layer 235, the first buffer layer 15, or the second buffer layer 233; the side of the second inorganic encapsulation layer 53 facing the substrate 10 is connected to another of the passivation layer 236, the capacitor dielectric layer 234, the gate insulating layer 235, the first buffer layer 15, or the second buffer layer 233.

[0089] Optionally, the edge of one of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53, facing the surface of the first base layer 13, contacts the first buffer layer 15, and the edge of the other, facing the surface of the first base layer 13, contacts the second buffer layer 233.

[0090] Optionally, among the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers, the film layer that contacts the surface of the first inorganic encapsulation layer 51 with its edge facing the first base layer 13 is further away from the first base layer 13 than the film layer that contacts the surface of the second inorganic encapsulation layer 53 with its edge facing the first base layer 13.

[0091] Optional, such as Figure 8 As shown, the display panel 100 also includes a second recess 61. The second recess 61 extends through the second substrate layer 14 and the second buffer layer 233 to expose the first buffer layer 15. The edges of the first inorganic encapsulation layer 51 and / or the second inorganic encapsulation layer 53, facing the first substrate layer 13, contact (or connect) the first buffer layer 15. Specifically, the edge of the first inorganic encapsulation layer 51, facing the first substrate layer 13, covers the first buffer layer 15 exposed from the second recess 61 and the trace 30. Optionally, the orthographic projection of the second recess 61 on the substrate 10 surrounds the orthographic projection of the pixel driving circuit and the light-emitting device 21 on the substrate 10.

[0092] Optionally, the material of the dielectric layer in contact with the encapsulation layer 50 is an inorganic material.

[0093] Optionally, the encapsulation layer 50 may further include at least one organic encapsulation layer and / or at least one inorganic encapsulation layer located between the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53.

[0094] Optional, such as Figure 7 As shown, a first inorganic encapsulation layer 51, an organic encapsulation layer 52, and a second inorganic encapsulation layer 53 are sequentially stacked on the pixel island 20. At the edge of the pixel island 20, the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 are in contact with each other and with the dielectric layer. Specifically, the encapsulation layers 50 are all approximately trapezoidal in shape. At the top base of the trapezoid, the first inorganic encapsulation layer 51, the organic encapsulation layer 52, and the second inorganic encapsulation layer 53 are sequentially stacked along the Z-axis direction, and at the waist of the trapezoid, the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 are sequentially stacked along the X-axis direction. The bottom end of the first inorganic encapsulation layer 51 and the bottom end of the second inorganic encapsulation layer 53 are respectively connected to at least one layer of the dielectric layer or the second buffer layer 233. This encapsulation structure, consisting of a first inorganic encapsulation layer 51, an organic encapsulation layer 52, and a second inorganic encapsulation layer 53, is formed above the pixel island 20. This structure can prevent water, gas, or impurities from entering the pixel island 20 from the Z-axis direction. Similarly, the encapsulation structure consisting of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 is formed on the side of the pixel island 20. This structure can effectively prevent water, gas, or impurities from entering the pixel island 20 from the direction perpendicular to the Z-axis.

[0095] Optionally, to further improve the reliability of the pixel island 20 package, the dielectric layer in contact with the package layer 50 may be made of an inorganic material. That is, the end of the inorganic package layer in the package layer 50 is connected to the upper surface of at least one dielectric layer. Since both the inorganic package layer in the package layer 50 and the dielectric layer connected to it are made of inorganic materials, the interfacial stress at the connection point can be reduced. Therefore, this method can ensure the reliability of the pixel island 20 package. Optionally, the inorganic package layer in the package layer 50 and the dielectric layer connected to the inorganic package layer in the package layer 50 may be made of the same material, resulting in better bonding performance at the connection point and improved package reliability.

[0096] Optionally, to further improve the reliability of the pixel island 20 package, one of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 is in contact with one of the plurality of dielectric layers, and the other is connected to at least one dielectric layer located between the first dielectric layer and the substrate 10. Optionally, the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 are respectively connected to different dielectric layers to reduce the interface stress at the connection and further improve the reliability of the package. In one embodiment, optionally, as... Figure 7 As shown, the first inorganic encapsulation layer 51 is connected to the capacitor dielectric layer 234, and the second inorganic encapsulation layer 53 is connected to the gate insulating layer 235 or the second buffer layer 233, forming an inorganic connection, which is an inner and outer encapsulation, forming a barrier structure that prevents water and oxygen from intruding.

[0097] Optional, such as Figure 8 As shown, the first inorganic encapsulation layer 51 is connected to the first buffer layer 15, and the second inorganic encapsulation layer 53 is connected to the second buffer layer 233, forming an inorganic connection, which is an inner and outer encapsulation, forming a barrier structure.

[0098] like Figure 9 and Figure 10 As shown, to further improve the reliability of the pixel island 20 packaging, in one embodiment of this disclosure, the display panel 100 further includes a first recess 60. Optionally, the first recess 60 is disposed in the pixel defining layer 22, the planarization layer 237, and the driving circuit layer 23, and the orthographic projection of the first recess 60 onto the substrate 10 and the orthographic projection of the via 40 onto the substrate at least partially overlap. Optionally, the encapsulation layer 50 covers the first recess 60. Optionally, as... Figure 11 As shown, the orthographic projection of the first groove 60 on the substrate 10 surrounds the orthographic projection of the pixel driving circuit and the light-emitting device 21 on the substrate 10. Optionally, the first inorganic encapsulation layer 51 fills the first groove 60 to further form a protective structure on the outer periphery of the pixel island 20, such that the side of the pixel island 20 forms a three-layer protective structure of the first inorganic encapsulation layer 51-the second inorganic encapsulation layer 53.

[0099] Optional, such as Figure 11As shown, the orthographic projection of the second groove 61 on the base 10 surrounds the outside of the orthographic projection of the first groove 60 on the base 10.

[0100] The position of the first groove 60 can be adaptively adjusted as needed. In one embodiment, the first groove 60 is disposed in the driving circuit layer 23 and the second base layer 14. Optionally, the first groove 60 penetrates the second base layer 14, the second buffer layer 233, the gate insulating layer 235, the capacitor dielectric layer 234, and the passivation layer 236. Optionally, the orthographic projection of the first groove 60 on the substrate 10 surrounds the outside of the orthographic projection of the via 40 on the substrate 10.

[0101] like Figure 12 As shown, to further improve the reliability of the pixel island 20 package, in one embodiment of this disclosure, the via 40 is located in the first groove 60. At least a portion of the first groove 60 can serve as the via 40. A contact pad 41 is provided in the via 40, and the trace 30 is connected to the pixel driving circuit through the contact pad 41. The contact pad 41 is conformal to the first groove 60. The portion of the contact pad 41 located within the first groove 60 is recessed away from the bottom of the first groove 60. Specifically, after forming the first groove 60, a conductive layer can be formed as the contact pad 41 at the bottom and sidewalls of the first groove 60, as well as at the location of the passivation layer 236 extending to the driving circuit layer 23, using processes such as electroplating or chemical vapor deposition. The first inorganic encapsulation layer 51 can fill the first groove 60 and the recess of the contact pad 41. This creates a multi-layer encapsulation structure in the region where the driving circuit layer 23 is located at the edge of the pixel island, extending from the outer wall of the pixel island 20 towards its interior. This structure consists of a second inorganic encapsulation layer 53, a first inorganic encapsulation layer 51, and a contact pad 41. This further improves the reliability of the encapsulation. The contact pad 41 can be disposed in the same layer as the source and drain layers and made of the same material, i.e., it can be fabricated by patterning the same conductive layer in the same process.

[0102] like Figure 13 As shown, to further improve the reliability of the pixel island 20 encapsulation, in one embodiment of this disclosure, the display panel 100 further includes a barrier layer 70. Optionally, the barrier layer 70 is located between the encapsulation layer 50 and the pixel island 20. Optionally, the impedance layer 70 may be disposed in the encapsulation layer 50, and the impedance layer 70 may be an inorganic encapsulation layer. Optionally, the barrier layer 70 covers the first groove 60, and the portion covering the first groove 60 is conformal to the first groove 60. The portion of the barrier layer 70 located within the first groove 60 is away from the surface recess at the bottom of the first groove 60. Optionally, the first inorganic encapsulation layer 51 may fill the recess of the barrier layer 70 in the first groove 60. Optionally, the barrier layer 70 may cover the contact pad 41. Optionally, the barrier layer 70 covers the pixel island 20 to prevent water and oxygen intrusion.

[0103] Optionally, the barrier layer 70 is an inorganic layer. Optionally, the material of the barrier layer 70 includes dense materials with good barrier properties such as metal oxides; optionally, the material of the barrier layer 70 includes aluminum oxide or titanium nitride.

[0104] Optionally, the barrier layer 70 may be located between the first inorganic encapsulation layer 51 and the pixel island. The orthographic projection of the barrier layer 70 onto the substrate 10 lies within the orthographic projection of the first inorganic encapsulation layer 51 onto the substrate 10. Optionally, the edge of the barrier layer 70 facing the surface of the first substrate layer 13 contacts at least one of the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers.

[0105] Optionally, the surfaces of the first inorganic encapsulation layer 51 and the barrier layer 70 facing the first base layer 13 are in contact with the same film layer among the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers; or, the surfaces of the first inorganic encapsulation layer 51 and the barrier layer 70 facing the first base layer 13 are in contact with different film layers among the first buffer layer 15, the second buffer layer 233, and the plurality of dielectric layers, respectively. Optionally, the film layer in contact with the surface of the first inorganic encapsulation layer 51 facing the first base layer 13 is further away from the first base layer 13 than the film layer in contact with the surface of the barrier layer 70 facing the first base layer 13. Optionally, the edge of the barrier layer 70 facing the first base layer 13 contacts the capacitor dielectric layer 234 or the gate insulating layer 235; the edge of the first inorganic encapsulation layer 51 facing the first base layer 13 contacts the first buffer layer 15 and / or the second buffer layer 233; and the edge of the second inorganic encapsulation layer 53 facing the first base layer 13 contacts at least one of the first buffer layer 15, the second buffer layer 233, and multiple dielectric layers. Alternatively, as... Figure 13 As shown, at the edge of pixel island 20, barrier layer 70 and first inorganic encapsulation layer 51 are in contact.

[0106] Optionally, the first inorganic encapsulation layer 51, the second inorganic encapsulation layer 53, and the barrier layer 70 are in contact with the same or different film layers among the first buffer layer 15, the second buffer layer 233, and multiple dielectric layers to form an inorganic connection, thereby forming a three-layer barrier structure that covers the entire structure from the inside out, in order to improve the encapsulation effect.

[0107] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized in that, include: The substrate includes a first substrate layer and a second substrate layer stacked together; Multiple pixel islands are located on the side of the second substrate layer opposite to the first substrate layer. Each pixel island includes a driving circuit layer and at least one light-emitting device. The driving circuit layer is located between the substrate and the light-emitting device. The driving circuit layer includes a pixel driving circuit and multiple dielectric layers. At least one dielectric layer has a via. The orthographic projection of the via onto the substrate surrounds the orthographic projections of the pixel driving circuit and the light-emitting device onto the substrate. The via is filled with a contact pad. The trace is electrically connected to the pixel driving circuit through the contact pad and is located between the first substrate layer and the second substrate layer.

2. The display panel according to claim 1, characterized in that, The substrate also includes: A first buffer layer is disposed between the trace and the first base layer.

3. The display panel according to claim 2, characterized in that, The first buffer layer is an inorganic material, while the first base layer and the second base layer are organic materials.

4. The display panel according to claim 2, characterized in that, The pixel driving circuit includes at least one of a thin-film transistor and a capacitor.

5. The display panel according to claim 4, characterized in that, Also includes: An encapsulation layer covers the pixel islands and is in contact with at least one of the dielectric layers.

6. The display panel according to claim 5, characterized in that, The encapsulation layer includes a first inorganic encapsulation layer, the edge of which contacts at least one of the plurality of dielectric layers.

7. The display panel according to claim 5, characterized in that, The plurality of dielectric layers include at least one of a gate insulating layer, a capacitor dielectric layer, and a passivation layer.

8. The display panel according to claim 6, characterized in that, The encapsulation layer further includes a second inorganic encapsulation layer, and the first inorganic encapsulation layer is located between the second inorganic encapsulation layer and the substrate; The orthographic projection of the first inorganic encapsulation layer on the substrate lies within the orthographic projection of the second inorganic encapsulation layer on the substrate.

9. The display panel according to claim 8, characterized in that, The display panel further includes: a second buffer layer located between the pixel island and the second base layer; the surface of the first inorganic encapsulation layer facing the first base layer contacts at least one of the first buffer layer, the second buffer layer, and the plurality of dielectric layers; the surface of the second inorganic encapsulation layer facing the first base layer contacts at least one of the first buffer layer, the second buffer layer, and the plurality of dielectric layers.

10. The display panel according to claim 9, characterized in that, The edges of the first inorganic encapsulation layer facing the surface of the first substrate layer and the edges of the second inorganic encapsulation layer facing the surface of the first substrate layer are respectively in contact with different film layers in the first buffer layer, the second buffer layer and the plurality of dielectric layers.

11. The display panel according to claim 8, characterized in that, At the edge of the pixel island, the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact.

12. The display panel according to claim 8, characterized in that, The material of at least one dielectric layer in contact with the encapsulation layer is an inorganic material.

13. The display panel according to claim 8, characterized in that, The encapsulation layer further includes at least one organic encapsulation layer and / or at least one inorganic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

14. The display panel according to claim 5, characterized in that, It also includes, A first groove is disposed in the driving circuit layer and the second base layer, and the encapsulation layer covers the first groove.

15. The display panel according to claim 14, characterized in that, The orthographic projection of the first groove on the substrate surrounds the orthographic projection of the pixel driving circuit and the light-emitting device on the substrate.

16. The display panel according to claim 14, characterized in that, The through hole is located in the first groove.

17. The display panel according to claim 16, characterized in that, The contact pad conforms to the first groove.

18. The display panel according to claim 17, characterized in that, The display panel further includes a barrier layer that covers the first groove and the portion of the barrier layer that covers the first groove is conformal to the first groove.

19. The display panel according to claim 18, characterized in that, The barrier layer covers the pixel island; and / or the material of the barrier layer includes a metal compound.

20. The display panel according to claim 19, characterized in that, The metal compound includes at least one of aluminum oxide and titanium nitride.

21. The display panel according to claim 1, characterized in that, The through hole is formed into a closed annular groove.

22. The display panel according to claim 21, characterized in that, The orthographic projection of the through hole onto the substrate is a polygonal annular shape.

23. The display panel according to claim 21, characterized in that, The orthographic projection of the through hole onto the substrate is rectangular, circular, or elliptical.

24. The display panel according to claim 2, characterized in that, The contact pad is in contact with the first buffer layer.

25. The display panel according to claim 1, characterized in that, The display panel also includes a second recess that extends through the second substrate layer, and the orthographic projection of the second recess on the substrate surrounds the orthographic projection of the pixel driving circuit and the light-emitting device on the substrate.

26. The display panel according to claim 25, characterized in that, The substrate further includes a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed between the trace and the first substrate layer, and the second buffer layer is located between the pixel island and the second substrate layer; The second groove extends through the second base layer and the second buffer layer to expose the first buffer layer and the trace.

27. The display panel according to claim 26, characterized in that, The display panel further includes an encapsulation layer that covers the pixel islands; The edge of the encapsulation layer is in contact with or connected to the first buffer layer on the side facing the first base layer.

28. The display panel according to claim 27, characterized in that, The encapsulation layer includes a first inorganic encapsulation layer, the edge of which covers the first buffer layer exposed from the second groove and the wiring on the side facing the first substrate layer.

Images