SEMICONDUCTIVE STRUCTURE AND MANUFACTURING METHOD FOR MONOLITHIC INTEGRATION OF FUNCTIONALITIES

Abstract

The invention relates to a semiconductor structure (1) comprising: − a silicon-on-insulator substrate (100) comprising: o a base layer (103) comprising silicon; o an intermediate layer (102) above the base layer; and o a first silicon layer (101) above the intermediate layer (102), the first silicon layer (101) having a lattice orientation (1,0,0); − a second silicon layer (200) above the first silicon layer (101), the second silicon layer (200) having a lattice orientation (1,1,1); and − an interface layer (300) between the first silicon layer (101) and the second silicon layer (200). Figure to be published with the abstract: Fig. 1

Description

Title of the invention: SEMICONDUCTIVE STRUCTURE AND MANUFACTURING METHOD FOR THE MONOLITHIC INTEGRATION OF FUNCTIONALITIES

[0001] The present invention relates generally, among other things, to a semiconductor structure and its growth process. More particularly, it relates to a semiconductor structure and a process for its fabrication, the semiconductor structure comprising nitride-based active layers and silicon-based materials, thus enabling the monolithic integration of different functionalities in a semiconductor structure and obtaining exceptional performance for both high-power / high-frequency and radio-frequency applications.

[0002] In a radio receiver circuit, an RF front end, short for radio frequency front end, is a generic term for circuits located between the antenna input, for example, of a receiver and extending to and including, for example, a mixer stage. An RF front end comprises components that process a signal at an original radio frequency and convert it to a lower intermediate frequency. An RF front end module, abbreviated as an RFFE module, typically comprises four circuit elements: a power amplifier, a low-noise amplifier, an RF switch, and an antenna. A power amplifier is designed to increase the power of a given input signal. An RF amplifier, often referred to as a low-noise amplifier or LNA, increases the receiver's sensitivity to the front end by amplifying weak signals without introducing noise. An LNA must have a very low noise figure.

[0003] Semiconductor devices comprising, for example, gallium nitride, also known as GaN, and / or Group III nitride-based heterostructures, such as InAlGaN / GaN heterostructures, allow the transport of high currents and support high voltages. This makes them increasingly desirable for power semiconductor devices, particularly for the fabrication of power amplifiers for RFFE modules and / or for the fabrication of RF switches for RFFE modules.In general, devices manufactured for high-power / high-frequency applications are based on device structures that exhibit high electron mobility and a high critical electric field, and are designated, for example, as heterojunction field-effect transistors (HFETs), high-electron-mobility transistors (HEMTs), or modulated field-effect transistors (MODFETs). HEMTs are by... Examples are useful in analog circuit applications, such as RF / microwave power amplifiers or power switches. These devices can typically accept high voltages, for example up to 1000 volts, or operate at high frequencies, for example from 100 kHz to 100 GHz.

[0004] Silicon-on-Insulator (SOI) substrates for radio frequencies, also known as RF-SOI substrates, enable high RF performance on silicon films compatible with standard CMOS processes, RF isolation and high linearity power signals, low RF loss, digital processing, and power management integration. This makes them ideal candidates for the fabrication of low-noise amplifiers and / or RF switchers for RFFE modules.

[0005] Each of these circuit elements, namely a power amplifier, a low-noise amplifier, and an RF switch, is typically manufactured, processed, implemented, and / or packaged individually and / or separately, either from semiconductor devices comprising Group III nitride-based heterostructures or from RF-SOI substrates. RFFE modules are therefore assembled by combining at least one power amplifier and / or an RF switch manufactured from semiconductor devices comprising Group III nitride-based heterostructures with a low-noise amplifier and / or an RF switch manufactured from RF-SOI substrates.

[0006] Solutions exist for combining group III nitride heterostructures with RF-SOI substrates. However, integrating the two platforms and their various functionalities remains a challenge. Indeed, growing semiconductor devices comprising group III nitride heterostructures on RF-SOI substrates is not straightforward. The high density of through-dislocations formed in group III nitride layers when grown on an RF-SOI substrate must be compensated for. Thick buffer layers, such as GaN buffer layers several micrometers thick, are required to regulate the through-dislocation density and grow between the active group III nitride layers and the substrate.These thick buffer layers create a thermal impedance between the active layers and the substrate, leading to performance degradation and compromising the reliability of the fabricated devices. Devices resulting from this integration are also subject to trapping effects, both from the surface of the Group III nitride heterostructures and from the buffer / bulk layers. The traps present in the buffer / bulk layers result from intentional impurities, such as carbon or iron, which are introduced into the buffer / bulk layers to make them more resistive. Furthermore, during the growth of semiconductor devices... In devices comprising group III nitride heterostructures on a silicon layer, a strain management buffer must be increased to compensate for lattice mismatches between the group III nitride layers and the silicon. The total thickness of the layer stack can thus reach several micrometers, further increasing the already significant thermal impedance of the fabricated devices.

[0007] Due to the ever-increasing need for high-power and high-frequency solutions, the telecommunications industry faces the challenge of making Group III nitride-based active devices compatible with existing technologies, thereby enabling the continued miniaturization of microelectronic devices and the continuous improvement of their performance.

[0008] The embodiments of the present invention therefore aim to provide a semiconductor structure and a manufacturing process that do not present the drawbacks inherent in the prior art. More specifically, the embodiments of the present invention aim to provide a semiconductor structure with improved performance and reliability at high power and high frequency, as well as a process for its manufacture. More particularly, the embodiments of the present invention aim to provide a semiconductor structure that allows the monolithic integration of several functionalities and that can be used for both high-power / high-frequency and radio-frequency applications.

[0009] The extent of protection sought for various embodiments of the invention is set out in the independent claims.

[0010] The embodiments and characteristic elements described in this document which do not fall within the scope of the independent claims shall be interpreted as useful examples for understanding the various embodiments of the invention.

[0011] A semiconductor structure is required from which several devices performing different functions can be manufactured, thus enabling the monolithic integration of multiple functionalities for different applications through a single semiconductor structure. For example, a semiconductor structure is required from which power amplifiers, low-noise amplifiers, and RF switches can be manufactured, thus enabling the monolithic integration of multiple functionalities for different high-power / high-frequency and radio-frequency applications through a single semiconductor structure. For example, a semiconductor structure is required that allows the fabrication of an RF front-end module from a hybrid combination of materials in a unique semiconductor structure.

[0012] While allowing the monolithic integration of several functionalities, it is also necessary to have a semiconductor structure that ensures sufficient isolation between devices or systems having different functions, thus minimizing, or even avoiding, interference between the different devices or systems.

[0013] It is also necessary to have a semiconductor structure exhibiting improved resistivity and reducing power losses and linearity problems. Furthermore, it is necessary to have a semiconductor structure that, from a manufacturing standpoint, is compatible with existing technologies. It is also necessary to have a semiconductor structure that allows the growth of III-N semiconductor layers with minimal stress and minimal density of through-hole dislocations resulting from lattice and / or thermal mismatch.

[0014] It is necessary to have a semiconductor structure with low thermal impedance. It is also necessary to have a semiconductor structure whose properties and parameters can be controlled or modified via the substrate on which the high-electron-mobility transistor is grown. Finally, it is necessary to have a high-electron-mobility transistor in which trapping effects are minimized or even eliminated.

[0015] This objective is achieved, according to a first aspect of the present invention, by a semiconductor structure comprising: - a Silicon-on-Insulator substrate comprising: o a base layer comprising silicon; an intermediate layer above the base layer; and o a first silicon layer above the intermediate layer, the first silicon layer having a lattice orientation (1,0,0); - a second silicon layer above the first silicon layer, the second silicon layer having a lattice orientation (1,1,1); and - an interface layer between the first silicon layer and the second silicon layer.

[0016] By means of the semiconductor structure according to the present invention, it becomes possible to fabricate several devices performing different functions from the same semiconductor structure, thus achieving the monolithic integration of several functionalities for different applications through a single semiconductor structure. Indeed, with the semiconductor structure according to According to the present invention, power amplifiers, low-noise amplifiers, and RF switches can be manufactured from similar and / or different materials, thus achieving the monolithic integration of several devices for various high-power / high-frequency and radio frequency applications through a single semiconductor structure. In other words, it becomes possible to fabricate an RF front-end module from a hybrid combination of materials within the single platform of the semiconductor structure according to the present invention.

[0017] Due to its low cost and large wafer size, (1,0,0) lattice-oriented silicon could be considered a promising substrate for the growth of an epitaxial stack of III-N semiconductor layers. Unfortunately, due to the large differences in lattice parameter, crystal structure, and coefficients of thermal expansion between (1,0,0) lattice-oriented silicon and III-N semiconductor layers, such as GaN, the growth of an epitaxial stack of III-N semiconductor layers on top of (1,0,0) lattice-oriented silicon remains extremely difficult and compromises the performance of the fabricated devices. Indeed, the lattice mismatch between (1,0,0) lattice-oriented silicon and, for example, GaN is nearly 16%, while the thermal mismatch between (1,0,0) lattice-oriented silicon and, for example, GaN is nearly 54%.Thermal and lattice mismatches lead to stresses and a high density of through-hole dislocations in III-N semiconductor layers epitaxially grown on (1,0,0) lattice-oriented silicon. Therefore, it is not possible to obtain epitaxially grown layers of thick III-N semiconductors for the fabrication of devices on (1,0,0) lattice-oriented silicon without cracks.

[0018] (1,1,1) lattice-oriented silicon constitutes the most promising stepping stone for the growth of an epitaxial stack of III-N semiconductor layers on silicon. The semiconductor structure according to the present invention allows the growth of III-N semiconductor layers above the second (1,1,1) lattice-oriented silicon layer, the III-N semiconductor layers exhibiting better lattice and thermal mismatch with the underlying second silicon layer than with (1,0,0) lattice-oriented silicon, thus exhibiting less stress and a lower density of through-dislocations than if the III-N semiconductor layers were grown on a (1,0,0) lattice-oriented silicon layer.The density of through-dislocations in an epitaxial stack of III-N semiconductor layers grown above the second silicon layer is thus minimized and the quality of growth. epitaxial of an epitaxial stack of III-N semiconductor layers grown above the second silicon layer is improved.

[0019] In this way, one or more power amplifiers and / or one or more RF switches can be fabricated from an epitaxial stack of III-N semiconductor layers grown above the second (1,1,1) lattice-oriented silicon layer. In parallel, and from the same semiconductor structure, one or more low-noise amplifiers and / or one or more RF switches can be fabricated from the Silicon-on-Insulator substrate. The semiconductor structure according to the present invention corresponds to a hybrid multilayer structure combining and integrating different material platforms from which one or more devices for high-power / high-frequency applications and one or more devices for radio-frequency applications can be fabricated side by side.In other words, for example, a power amplifier prepared from the epitaxial stacking of III-N semiconductor layers can be adjacent to a low-noise amplifier prepared from the Silicon-on-Insulator substrate.

[0020] By means of the semiconductor structure according to the present invention, the first silicon layer and the second silicon layer are separated from each other by an interface layer. In other words, the interface layer is formed between the first silicon layer and the second silicon layer. The interface layer electrically isolates the two silicon layers from each other, that is, the second silicon layer from the first silicon layer and vice versa. This ensures sufficient isolation between devices or systems made from and / or on each of the two silicon layers and having different functions, thereby minimizing, or even preventing, interference between the different devices or systems.Furthermore, according to an optional embodiment of the semiconductor structure according to the present invention, other functionalities can be integrated into high-power / high-frequency and / or radio-frequency applications, such as a trap-rich layer that reduces, or even minimizes, the RF losses of devices made from the semiconductor structure according to the present invention.

[0021] In the context of the present invention, the Silicon-on-Insulator substrate comprises a base layer of silicon, such as bulk silicon. The resistivity of the base layer of the Silicon-on-Insulator substrate is typically between 3 and 5 kOhm·cm and is preferably greater than 1 kOhm·cm. In this way, the resistivity of the underlying Silicon-on-Insulator substrate, for example, an epitaxial stack of III-N semiconductor layers, is reduced. being grown above the second silicon layer, is maximized for high power and high frequency applications.

[0022] In the context of the present invention, Silicon-on-Insulator (SOI) technology refers to the fabrication of semiconductor devices in a layered Silicon-on-Insulator substrate. The choice of insulator depends largely on the intended application of the semiconductor devices. Several types of Silicon-on-Insulator substrates can be used within the scope of the present invention.

[0023] Silicon on Insulator substrates for radio frequencies, also referred to as RF-SOI substrates, enable high RF performance on silicon films compatible with standard CMOS processes, RF isolation and high linearity power signals, low RF losses, digital processing and power management integration.

[0024] By way of example, an RF substrate with improved signal integrity comprises a base layer made of high-resistivity silicon, a trap-rich intermediate layer forming part of the intermediate layer and formed above the base layer, a buried insulator forming part of the intermediate layer and formed above the trap-rich layer, and a first silicon layer formed above the buried insulator, the first silicon layer comprising a single crystal. The resistivity of the base layer is typically greater than 3 kOhm·cm. The thickness of the first silicon layer is typically between 50 and 200 nm. The addition of a trap-rich layer enables exceptional RF performance. Such a substrate is particularly well-suited for devices with stringent linearity specifications.Applications typically target LTE-Advanced and 5G standards and meet different performance requirements. Compared to a high-resistivity SOI substrate, a signal integrity-enhanced substrate exhibits better linearity, lower RF losses, lower crosstalk, improved quality factors for passive components, smaller chip sizes, and better thermal conductivity. Furthermore, signal integrity-enhanced substrates typically have a total harmonic quality factor below -80 dBm.

[0025] Another example of RF-SOI comprises a base layer including silicon with intermediate resistivity, a trap-rich intermediate layer forming part of the intermediate layer and formed above the base layer, a buried insulator forming part of the intermediate layer and formed above the trap-rich layer, and a first silicon layer comprising a thin single crystal. Such a substrate is particularly well suited, for example, to highly integrated cost-sensitive, and is particularly well suited for example to the specifications of Wi-Fi, IoT and other consumer applications.

[0026] Another example of RF-SOI, called high-resistivity SOI, is intended, for example, for devices with lower linearity specifications. Such a substrate comprises a base layer including high-resistivity silicon, a buried insulator formed above the base layer, and a first silicon layer comprising a thin single crystal.

[0027] Power Silicon-on-Insulator (SOI) substrates meet the integration requirements, for example, of high-voltage and analog functions in intelligent, energy-efficient, and highly reliable power integrated circuits for the automotive and industrial markets. They offer excellent electrical insulation and are ideally suited for integrating devices operating at various voltages, from a few volts to several hundred volts, while reducing chip size and improving reliability. These substrates are ideal for applications such as CAN / LIN transceivers, switched-mode power supplies, brushless motor driver circuits, LED driver circuits, and others. A power SOI comprises a base layer of silicon, a buried insulator formed above it of oxide, and a first silicon layer of silicon.The thickness of the buried insulation is typically between 0.4 pm and 1 pm and the thickness of the first silicon layer is typically between 0.1 pm and 1.5 pm.

[0028] Silicon-on-Insulator substrates for photonics meet the requirement for integrating optical functions, for example on a CMOS chip, for low-cost, high-speed optical transceivers. These substrates comprise a base layer of silicon, a buried insulator formed above the base layer and comprising oxide, and a first silicon layer formed on the buried insulator and comprising monocrystalline silicon. The thickness of the buried insulator is typically between 0.7 µm and 2 µm, and the thickness of the first silicon layer is typically between 0.1 µm and 0.5 µm. The crystalline silicon-on-insulator layer can be used to fabricate, for example, optical waveguides and other optical devices, whether passive or active, for example, through suitable implants.The buried insulation, for example, allows the propagation of infrared light within the silicon layer based on total internal reflection. The upper surface of the waveguides can either be left uncovered and exposed to the air, for example for sensing applications, or covered with a coating, for example made of silica.

[0029] From a manufacturing perspective, SOI substrates are compatible with most conventional manufacturing processes. Generally, an SOI-based process can be implemented without special equipment or significant re-equipping of an existing plant. Challenges specific to SOI include new metrological requirements to account for the buried insulator and concerns regarding differential stresses in the first silicon layer.

[0030] In the context of the present invention, alternatives to a Silicon on Insulator substrate are one or more of the following: a silicon substrate, a silicon carbide substrate, a sapphire substrate, a germanium substrate, a germanium on insulator substrate, or any other suitable alternative to the foregoing.

[0031] According to examples of embodiments, the interface layer comprises one or more insulating layers.

[0032] According to examples of embodiments, the interface layer further comprises one or more of the following elements: - one or more trap-rich layers; - materials with low permittivity.

[0033] The interface layer formed between the first silicon layer and the second silicon layer comprises one or more materials that electrically insulate the two silicon layers from each other, i.e., the second silicon layer from the first silicon layer and vice versa. This ensures sufficient isolation between devices or systems made from the two silicon layers and having different functions, thereby minimizing, or even preventing, interference between the different devices or systems. Other features can be integrated for high-power / high-frequency and / or radio frequency applications, such as a trap-rich layer that reduces, or even minimizes, RF losses in devices made from the semiconductor structure. A trap-rich layer comprises, for example, one or more layers of polycrystalline silicon containing oxygen.A layer rich in traps includes, for example, one or more layers of silicon carbide.

[0034] According to examples of embodiments, the second silicon layer has a thickness between 50 nm and 80 nm.

[0035] In this way, the thickness of the second silicon layer is kept as small as possible. This makes it possible to minimize the thickness of the second silicon layer on the Silicon-on-Insulator substrate after the bonding of a donor wafer onto which the second silicon layer is grown on a target wafer comprising the Silicon-on-Insulator substrate, improving thus the thermal impedance of devices such as high electronic mobility transistors made from the semiconductor structure according to the present invention.

[0036] The thickness of the second silicon layer is, for example, 50 nm, or 55 nm, or 60 nm, or 65 nm, or 70 nm, or 75 nm, or 80 nm. The second silicon layer should preferably be as thin as possible.

[0037] According to exemplary embodiments, the semiconductor structure further comprises an epitaxial stack of III-N semiconductor layers above the second silicon layer, the III-N epitaxial stack of semiconductor layers comprising an active epitaxial layer; the active epitaxial layer comprising: - a first active III-N layer formed above the second silicon layer; and - a second active IILN layer formed above the first active IILN layer; with a two-dimensional electron gas between the first active IILN shell and the second active IILN shell.

[0038] Due to the insulation of the Silicon-on-Insulator (SOI) substrate's base layer from the bulk silicon, the parasitic capacitance within semiconductor devices fabricated from the Group III nitride heterostructure is reduced, thus improving their power consumption and performance. SOI-fabricated semiconductor devices also exhibit better lock resistance and better equivalent VDD performance than semiconductor devices integrated on other types of substrates. The temperature dependence of SOI-fabricated semiconductor devices is reduced compared to semiconductor devices integrated on other types of substrates. Due to the insulation, SOI-fabricated semiconductor devices exhibit lower leakage currents and, consequently, better energy efficiency.

[0039] A two-dimensional electron gas, also designated 2DEG, is a gas of electrons free to move in two dimensions, but tightly confined in the first. This tight confinement leads to quantized energy levels for movement in that direction. The electrons appear as a 2D sheet embedded in a 3D world. Group III nitride-based heterostructures comprising a first active IILN layer and a second active IILN layer, such as AlGaN / GaN heterostructures, are very well suited to high-power and high-frequency applications due to their high electron velocity and high critical electric field. In this heterostructure, a two-dimensional electron gas, also designated 2DEG, is generated by the spontaneous and piezoelectric polarization between the first active III-N layer and the second active III-N layer, i.e. for example between AlGaN and GaN.

[0040] In the context of the present invention, the term Group III nitride refers to semiconductor compounds formed between elements of Group III of the periodic table, for example boron, also designated B, aluminum, also designated Al, gallium, also designated Ga, indium, also designated In, and nitrogen, also designated N. Examples of binary Group III nitride compounds include GaN, AIN, BN, etc. The term Group III nitride also refers to ternary and quaternary compounds such as AlGaN and InAlGaN.

[0041] In the context of the present invention, the first active III-N layer comprises one or more elements from N, P, As, and one or more elements from B, Al, Ga, In, Tl, Sc, Y, and series of lanthanides and actinides. The first active III-N layer comprises, for example, GaN. The second active III-N layer comprises one or more elements from N, P, As, and one or more elements from B, Al, Ga, In, and Tl. The second active III-N layer comprises, for example, AlGaN. The term AlGaN refers to a composition comprising Al, Ga, and N in any stoichiometric ratio (AlxGayN), where x is between 0 and 1 and y is between 0 and 1. Alternatively, the second active III-N layer comprises, for example, AlN. Alternatively, the second active III-N layer comprises InAlGaN. A composition such as InAlGaN includes In in any appropriate amount.Alternatively, the first active III-N layer and the second active III-N layer both comprise InAlGaN, and the second active III-N layer has a wider band gap than the first active III-N layer, with the second active III-N layer exhibiting a higher polarization than the first active III-N layer. Alternatively, the first active III-N layer and the second active III-N layer both comprise BInAlGaN, and the second active III-N layer has a wider band gap than the first active III-N layer, with the second active III-N layer exhibiting a higher polarization than the first active III-N layer. The compositions of the active layer can be chosen according to the desired characteristics, and the compositions can therefore vary accordingly.

[0042] A III-N buffer may be provided between the second silicon layer and the epitaxial stack of IIILN semiconductor layers. The III-N buffer may be of a different nature than the Silicon-on-Insulator substrate, in that, for example, the band gap of the sacrificial substrate and that of the III-N buffer are relatively far apart, for example by 1.1 eV and 6.2 eV respectively, in that the IIILN buffer has a high band gap, so as to obtain the following characteristics, such as a high breakdown voltage, for example greater than 250 V, preferably greater than 500 V, preferably even greater than 1000 V, for example greater than 2000 V, or even much higher. The IILN buffer is, for example, a wide bandgap IILN buffer.

[0043] According to examples of embodiments, the first active IILN layer comprises GaN and the second active IILN layer comprises AlGaN.

[0044] The first active IILN layer comprises gallium nitride and the thickness of the first active IILN layer is equal to or greater than 50 nm. Preferably, the first active IILN layer is formed by epitaxial growth and comprises pure gallium nitride, preferably several layers of gallium nitride, preferably a single layer of gallium nitride.

[0045] According to examples of embodiments, the first active IILN layer comprises InAlGaN, and the second active IILV layer comprises InAlGaN, and the second active IILN layer has a wider band gap than a band gap of the first active IILN layer and the second active IILN layer has a higher polarization than the polarization of the first active IILN layer.

[0046] Thus, the use of different materials in the first active IILN layer and the second IILN layer adjacent to each other causes a polarization which contributes to a 2DEG conductive region near the junction between the first active IILN layer and the second active IILN layer, in particular in the first active IILN layer which has a narrower band gap than the band gap of the second active IILN layer.

[0047] The second active IILN layer comprises indium aluminum gallium nitride. The second active IILN layer has, for example, a thickness of between 10 and 100 nm, preferably between 20 and 50 nm. Such a combination of thicknesses makes it possible to obtain good characteristics for the active layer, for example with regard to the 2DEG obtained.

[0048] According to examples of embodiments, the semiconductor structure further comprises: - a grid above the epitaxial stack of IIIN semiconductor layers and within a grid region; and - a passivation stacking between the epitaxial stacking of IILN semiconductor layers and the gate.

[0049] In the context of the present invention, a gate contact, such as a gate electrode, is provided in a gate region of a transistor, for example, a high-electron-mobility transistor. The formation of a gate contact in the gate region comprises a plurality of processing steps. By way of example, this This step includes the deposition of a photosensitive resin and a lithography step that defines the base of the gate contact, for example, by completely removing potential passivation layers from a passivation stack above the second active III-N layer, such as oxide or one or more dielectric layers. Alternatively, this step includes the deposition of a photosensitive resin and a lithography step that defines the base of the gate contact by, for example, partially removing passivation layers present above the second active III-N layer, such as oxide or one or more dielectric layers. In this way, some layers of the passivation stack remain below the gate of the high-electron-mobility transistor and form a gate dielectric to further reduce trapping effects and leakage current.The grid electrode of the grid contact is, for example, a Metal-Oxide-Semiconductor grid, also known as a MOS grid, and can be made by depositing stacks of metals, such as Ni, Pt, W, WN, or TiN, coated with Al, Au, or Cu. Metal patterns are defined successively by peeling the metal over the photoresist. Alternatively, the grid metal stack, such as Ni, Pt, W, WN, or TiN, is deposited and coated with Al, Au, or Cu. The photoresist application and lithography steps are then performed, and the resulting photoresist patterns act as a mask for dry etching the metal stacks in areas where they are undesirable. The photoresist is then removed.

[0050] According to exemplary embodiments, the epitaxial stacking of III-N semiconductor layers is adapted to accommodate an electronic channel between a source region and a drain region when a negative bias voltage is applied to the gate contact.

[0051] Thus, once a bias voltage greater than the threshold voltage of the high electronic mobility transistor has been applied to the gate contact, electrons flow in the electronic channel under the gate between the source and the drain of the high electronic mobility transistor.

[0052] According to examples of embodiments, a passivation stack is provided above the second active III-N layer.

[0053] The presence of the passivation stack above said epitaxial stack of III-N semiconductor layers corresponds to the epitaxial growth of the passivation stack above the epitaxial stack of IIIN semiconductor layers.

[0054] The passivation stack is formed, for example, in situ in association with the formation of the epitaxial stack of IILN semiconductor layers. The passivation stack is formed, for example, above the second active IILN layer. Thus, a fully crystalline passivation stack is formed by epitaxial growth on top of the epitaxial stack of III-N semiconductor layers. Alternatively, a partially crystalline passivation stack is formed by epitaxial growth on top of the epitaxial stack of III-N semiconductor layers. The passivation stack can also be formed by ex-situ deposition using epitaxial tools such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). Alternatively, the passivation stack can be formed by in-situ deposition in a MOCVD or MBE chamber. Alternatively, the passivation stack can be formed by depositing an amorphous film of the same material and recrystallizing it by thermal annealing.The passivation stack above the second active IILN layer includes, for example, silicon nitride. Alternatively, the passivation stack above the second active IILN layer includes, for example, gallium nitride. Alternatively, the passivation stack above the second active IILN layer includes both gallium nitride and silicon nitride.

[0055] A passivation stack is formed between the epitaxial stack of IILN semiconductor layers and, for example, a transistor gate. The passivation stack may be formed solely beneath the gate and may also serve as a gate dielectric. Alternatively, the passivation stack may be formed above the epitaxial stack of IILN semiconductor layers and may completely cover the epitaxial stack of IILN semiconductor layers. Alternatively, the passivation stack can be formed on top of the epitaxial stack of IILN semiconductor layers and partially cover the surface of the epitaxial stack of IILN semiconductor layers, and can for example be formed in the gate-free area between the source and drain of a high-electron-mobility transistor, where it serves as passivation and prevents depletion of the underlying 2DEG.

[0056] According to examples of embodiments, the passivation stack further comprises a layer of oxide and / or silicon nitride.

[0057] Thus, the passivation stack comprises silicon nitride and / or an oxide layer that acts as a passivation layer. The oxide layer has an electrically clean interface with the second active IILN layer, a high dielectric constant to maximize the electrostatic coupling between the electrical contacts formed on the semiconductor structure and the 2DEG, leading, for example, to an increase in the transconductance of high-electron-mobility transistors fabricated using the semiconductor structure, and a thickness sufficient to avoid dielectric breakdown and quantum tunneling leakage.

[0058] The passivation stack comprises, for example, high-density SiN, deposited in situ in a MOCVD reactor. The SiN may be stoichiometric or non-stoichiometric. It has been demonstrated experimentally by the applicant, for example, that a HEMT structure coated with SiN in situ is not affected by the processing steps, even those with a high temperature balance. Alternatively, the passivation stack comprises, for example, AlSiN. Al doping increases the band gap of the dielectric material. Alternatively, the electron-donating dielectric layer comprises one or more of Si, Al, O, and N. The passivation stack has, for example, a thickness of 1 to 500 nm, preferably 30 to 400 nm, more preferably 50 to 300 nm, for example 100 to 200 nm.In situ SiN can be externally thickened with SiN or SiOx by PECVD or LPCVD, for example, for thicknesses greater than 500 nm, before any further processing. A thin passivation stack allows the formation of low-resistance ohmic contacts. Furthermore, the passivation stack may include, for example, Si, which can diffuse into the AlGaN where it acts as a donor. Introducing a donor type into the AlGaN layer facilitates the formation of ohmic contacts, thus reducing contact resistance. The passivation stack is formed at temperatures between 700°C and 1300°C, between 700°C and 1250°C, and between 700°C and 1100°C. It is important to understand that SiN refers to a compound made up of Si and N. SiN can include Si3N4, but other formulas are also included, such as, but not limited to, the SixNy formula, in different stoichiometric or non-stoichiometric ratios.In the SixNy formula, x and y can be defined as real numbers, with 0 <x<100 et 0<y<100. Lorsque l'empilement épitaxial de couches semi-conductrices IILN est amené à croître, du NH3 est maintenu en circulation dans la chambre réactionnelle et la conduite de SiH4 est ouverte, cela permettant la croissance du SiN à haute température. Après la croissance de SiN, le flux de SiH4 est interrompu et la structure est refroidie à la température ambiante tout en maintenant le flux de NH3 , afin d'éviter une désorption d'avec la couche supérieure. .

[0059] According to examples of embodiments, the passivation stack is formed by epitaxial growth above the second active IIIN layer.

[0060] Advantageously, the crystallinity of the SiN grown in situ is preserved by doping it or by adding a species such as Al or B. When grown above the second active IIIN layer, the in situ SiN deforms to adapt to the stress resulting from the lattice mismatch between the materials. It is well known that a significant lattice mismatch is a trigger that reverts the epitaxial growth mode from a layer-by-layer growth mode. from a two-dimensional Franck-Van der Merwe growth mode to a three-dimensional Volker-Weber growth mode, which is more likely to transform into an amorphous growth mode. A smaller atom than Si can therefore be incorporated into the SiN, for example Al or B, to reduce the lattice parameter of the SiN in the beta phase and better match it to the lattice parameter of the second active III-N layer. An additional advantage of including Al in the SiN lattice is improved resistance to dry etching in fluorine-based plasmas, due to the interaction between Al and F that yields highly non-volatile AlF. The passivation stack is fully crystalline. Alternatively, the passivation stack is partially crystalline and includes at least a small number of crystalline monolayers.

[0061] According to examples of embodiments, the passivation stack includes a recess in a source region and a recess in a drain region; and the semiconductor structure further includes an ohmic contact respectively in the source region and in the drain region.

[0062] Preferably, the source contact and / or the drain contact are ohmic contacts formed respectively in a source region and / or in a drain region.

[0063] The source and drain contacts are ohmic contacts with the 2DEG and can be made by depositing stacks of metals, such as Ti / Al / Ni / Au, Ti / Al / Mo / Au, Ti / Al / Ti / Au, Ti / Al / Ti / W, Ti / Al / W, Ti / Al / W / Cr, Ta / Al / Ta, V / Al / Ni / Au, etc., in contact with the second active IILN layer of the epitaxial stack of IILN semiconductor layers. The second active IILN layer can be hollowed out before the metal is deposited. The contact properties can be further improved by thermal annealing, typically at a temperature between 800°C and 900°C, such as 850°C, in a nitrogen atmosphere or a forming gas atmosphere. Alternatively, additional metallic interconnection layers are defined using methods known to those skilled in the art, to allow the establishment of current paths with low resistivity to the gate, source and drain currents.

[0064] The formation of an ohmic contact in the source region and the formation of an ohmic contact in the drain region comprise a plurality of processing steps. By way of example, this is carried out by first depositing a photosensitive resin and defining the respective areas of the ohmic contacts by a lithography step. Potential passivation layers are then partially or totally removed respectively in a source region and / or in a drain region. Alternatively, potential passivation layers are completely removed in a source region and / or in a drain region. Once the areas of the ohmic contacts have been defined, i.e., when the Once the source and drain regions have been defined, a metallic layer or stack of metallic layers can be deposited, for example, by thermal evaporation, sputtering, or electron beam evaporation. Metallic patterns are defined consecutively by creating a metal deposition layer above the photoresist and without contact with the second active III-N layer. Alternatively, the photoresist is first removed, and the metallic stack, comprising, for example, Ti and Ai, is deposited. Then, a second deposition of photoresist is performed, followed by photolithography steps to dry-etch the metallic stack in areas where it is undesirable and to remove the photoresist.The defined ohmic contacts can then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere, such as hydrogen or forming gas or nitrogen gas, at a temperature for example between 800°C and 900°C.

[0065] The passivation stack is preferably eliminated by etching in a source region and a drain region, thereby exposing the second active IILN layer in a source region and a drain region.

[0066] Thus, openings are defined in the electron-donating dielectric layers to expose a source region and a drain region, respectively, in which the device terminals are to be formed. For example, a photolithography step can be performed, and the electron-donating dielectric layers can be removed by etching in a source region and a drain region, respectively. For example, the passivation stack can be removed by wet etching in HF or buffered HF, or by dry etching in an RIE or ICP plasma tool, depending on the fluorine chemistry.

[0067] Dry and wet etching of the passivation stack using fluorine chemistry will stop at the second active IILN layer, which acts as an etch-stop with very high selectivity. For example, etching of the electron-donating dielectric layers is carried out in a dry etching system based on fluorine chemistry, such as an inductively coupled plasma system using SF6 or CF4 as the etching gas and RF, or "platinum," and ICP, or "coil," etching powers of 10 W to 150 W, respectively. This allows for the complete removal of the remaining passivation stack without removing the second active IILN layer or any of the layers below it.Alternatively, the second active IILN layer is partially etched by wet etching, for example in an alkaline solution or in a developer for photosensitive resin, thus enabling the formation of respective ohmic contacts in a source region and in a drain region, partly in the active layer.

[0068] According to exemplary embodiments, the semiconductor structure includes, in a first functional region, a recess which extends through the epitaxial stacking of III-N semiconductor layers, through the second silicon layer and through the interface layer, thus exposing the first silicon layer.

[0069] In the first functional region, the first silicon layer is exposed. In this way, devices can be fabricated from and / or on top of the first silicon layer and / or one or more layers of the Silicon-on-Insulator substrate. For example, one or more low-noise amplifiers and / or one or more RF switches can be fabricated from the first silicon layer and / or one or more layers of the Silicon-on-Insulator substrate. One or more layers can, for example, be grown or deposited on top of the first silicon layer and / or one or more layers of the Silicon-on-Insulator substrate for the fabrication of one or more devices intended for RF applications.

[0070] An additional advantage of the first functional region is the use of the Silicon-on-Insulator substrate as a fourth terminal, for example, for a high-electron-mobility transistor fabricated from the semiconductor structure according to the present invention. In this way, a galvanic substrate contact with the Silicon-on-Insulator substrate can be used to impose a background voltage on the Silicon-on-Insulator substrate relative to a source contact of the high-electron-mobility transistor. Thanks to the recess formed in the first functional region, this galvanic substrate contact can be used to control or modify certain properties or parameters of the high-electron-mobility transistor, such as the threshold voltage and / or the off-state leakage of the high-electron-mobility transistor.Substrate galvanic contact can also be used to modulate, for example, the charge state of buffer or bulk traps present in the Silicon-on-Insulator (SOI) substrate, thereby minimizing or eliminating the trapping effects of the high-electron-mobility transistor (HEMT) and reducing memory effects within the HEMT. Substrate galvanic contact can be formed on the underside of the SOI substrate and substantially below a gate region of the HEMT fabricated on the SOI substrate after the bonding and / or epitaxial growth of the III-N semiconductor layer stack. Alternatively, substrate galvanic contact can be formed on the underside of the SOI substrate and substantially below the HEMT fabricated on the SOI substrate. after the bonding and / or epitaxial growth of the epitaxial stack of III-N semiconductor layers.

[0071] In the case of existing prior art solutions, when a high electron mobility transistor is fabricated, for example on a SiC substrate, given that SiC substrates used in RF applications typically exhibit very high resistivity, for example, a resistivity greater than 1.105 Ohm·cm, it is very difficult to achieve any impact on the properties of the active GaN HEMT through the substrate. When a high electron mobility transistor is fabricated, for example on a high-resistivity substrate in the case of existing prior art solutions, a very high bias voltage, for example, greater than 100 V, is required to achieve any impact on the active HEMT, due to the presence of the thick buffer stack between the active HEMT and the substrate.Unlike these prior art solutions, the semiconductor structure according to the present invention does not require the application of a very high voltage via the substrate galvanic contact to have an effect on the properties of active devices fabricated above the target substrate, because the total thickness of the layer stack between the substrate and the 2DEG is kept at a low value.

[0072] According to examples of embodiments, the semiconductor structure includes a second functional region comprising the epitaxial stacking of IILN semiconductor layers, the second silicon layer and the interface layer.

[0073] In the second functional region, the epitaxial stack of IILN semiconductor layers is epitaxially deposited on top of the second silicon layer. In this way, devices can be fabricated from and / or on top of the second silicon layer and / or one or more layers of the epitaxial stack of IILN semiconductor layers. For example, one or more power amplifiers and / or one or more RF switches can be fabricated from and / or on top of one or more layers of the epitaxial stack of IILN semiconductor layers. One or more layers can, for example, be grown or deposited on top of the second silicon layer and / or one or more layers of the epitaxial stack of IILN semiconductor layers for the fabrication of one or more devices intended for power applications.

[0074] According to examples of embodiments, the semiconductor structure further comprises a nucleation layer between the second silicon layer and the epitaxial stack of IILN semiconductor layers, the nucleation layer comprising AlN.

[0075] According to exemplary embodiments, the intermediate layer comprises: - an intermediate layer rich in traps; and - a buried insulator formed above the intermediate layer rich in traps.

[0076] According to a second aspect of the present invention, a method for manufacturing a semiconductor structure is proposed, the method comprising the steps of: - provide a Silicon on Insulator substrate, which consists of: o providing a base layer comprising silicon; o provide an intermediate layer above the base layer; and o provide a first silicon layer above the intermediate layer, the first silicon layer having a lattice orientation (1,0,0); and - provide a donor wafer comprising: o a donor substrate; o a sacrificial layer above the donor substrate; o a donor silicon layer having a lattice orientation (1,1,1) above the sacrificial layer; - provide a first interface layer above the first silicon layer; - provide a second interface layer above the donor silicon layer; - bond the second interface layer to the first interface layer, thus forming an interface layer between the first silicon layer and the donor silicon layer; and - separate the donor substrate and the Silicon on Insulator substrate by dividing the donor silicon layer, or by separating the donor substrate and the Silicon on Insulator substrate at an interface between the donor silicon layer and the sacrificial layer, thus forming above the interface layer a second silicon layer having a lattice orientation (1,1,1) and including at least partially the donor silicon layer bonded to the interface layer.

[0077] In this way, one or more power amplifiers and / or one or more RF switches can be fabricated from an epitaxial stack of III-N semiconductor layers grown above the second (1,1,1) lattice-oriented silicon layer. In parallel, and from the same semiconductor structure, one or more low-noise amplifiers and / or one or more RF switches can be fabricated from the Silicon-on-Insulator substrate. The process according to the present invention makes it possible to fabricate a hybrid multilayer structure combining and integrating different material platforms from which one or more devices for high-power / high-frequency applications and one or more devices for radio-frequency applications can be fabricated side by side. In other words, at As an example, a power amplifier processed from the epitaxial stacking of III-N semiconductor layers can be adjacent to a low-noise amplifier processed from the Silicon on Insulator substrate.

[0078] By means of the process according to the present invention, the first silicon layer and the second silicon layer are separated from each other by an interface layer. In other words, the interface layer is formed between the first silicon layer and the second silicon layer. The interface layer electrically isolates the two silicon layers from each other, that is, the second silicon layer from the first silicon layer and vice versa. This ensures sufficient isolation between devices or systems made from and / or on each of the two silicon layers and having different functions, thereby minimizing, or even preventing, interference between the different devices or systems.Furthermore, according to an optional embodiment of the method according to the present invention, other functionalities can be integrated into high-power / high-frequency and / or radio-frequency applications, such as a trap-rich layer that reduces, or even minimizes, RF losses in devices made from the semiconductor structure according to the present invention.

[0079] In the context of the present invention, the sacrificial layer comprises, for example, one or more of the following elements: silicon dioxide, a trap-rich layer, a buried insulator. Alternatively, the sacrificial layer is, for example, a buried brittle plane, induced by the implantation of ions in the donor wafer, more particularly in the donor substrate of the donor wafer.

[0080] The donor wafer and the Silicon-on-Insulator substrate are separated from each other by smart-cutting the donor silicon layer. In the context of the present invention, an interface layer is formed between the first silicon layer and the donor silicon layer, with the first silicon layer and the donor silicon layer coming into contact with each other. The separation of the donor wafer from the Silicon-on-Insulator substrate by smart-cutting the donor silicon layer occurs by causing the donor silicon layer to break at the interface between the donor silicon layer and the sacrificial layer. In other words, the donor silicon layer is cut at the interface between the donor silicon layer and the sacrificial layer.This separation forms a second silicon layer on the Silicon-on-Insulator substrate, comprising the donor silicon layer initially grown on the donor wafer and bonded to the Silicon-on-Insulator substrate. The thickness of this second silicon layer on the Silicon-on-Insulator substrate corresponds approximately to the thickness of the donor silicon layer grown on the donor wafer. Alternatively, the donor wafer can be separated. The bonding process with the Silicon-on-Insulator substrate by intelligent cutting at the donor silicon layer occurs by causing the donor silicon layer to split, leaving a first remaining portion of the donor silicon layer on the donor wafer separated from the Silicon-on-Insulator substrate, which will subsequently be referred to as the sacrificial silicon layer, and also leaving a second remaining portion of the donor silicon layer on the Silicon-on-Insulator substrate, which will subsequently be referred to as the second silicon layer. The sum of the thickness of the first remaining portion and the thickness of the second remaining portion corresponds approximately to the total thickness of the donor silicon layer that would have grown on the donor wafer before bonding. In other words, the donor silicon layer is divided in its thickness.This separation forms on the Silicon on Insulator substrate a second layer of silicon comprising at least partially the donor silicon layer initially grown on the donor wafer and bonded to the Silicon on Insulator substrate, the thickness of the second silicon layer on the Silicon on Insulator substrate being between 50 nm and 80 nm.

[0081] In the context of the present invention, the second interface layer is bonded directly to the first interface layer. In other words, in the case of direct bonding, the second interface layer is in direct contact with the first interface layer. Alternatively, in the context of the present invention, a target dielectric layer is provided above the first interface layer. The target dielectric layer comprises, for example, silicon dioxide, also referred to as SiO2. By way of example, the target dielectric layer is a buried oxide layer, also referred to as BOX. The thickness of the target dielectric layer is, for example, equal to or less than 50 nm, for example, 20 nm, 10 nm, 5 nm, etc. The thickness of the target dielectric layer is thus kept as small as possible. The target dielectric layer is used to facilitate the bonding of the second interface layer above the first interface layer..

[0082] In the context of the present invention, a donor wafer is, for example, a wafer having a diameter of 125 mm, 150 mm, 200 mm, or 300 mm. Alternatively, in the context of the present invention, a donor wafer comprises, for example, a plurality of chips or blocks of a few mm² or a few cm² of the donor silicon layer material. In the context of the present invention, a Silicon-on-Insulator substrate is provided on a target wafer, which is, for example, a wafer having a diameter of 125 mm, 150 mm, 200 mm, or 300 mm, the diameter of the target wafer being, for example, greater than a diameter of the donor wafer. Thus, by way of example, a donor wafer may be bonded to a target wafer. Alternatively, for example, several donor wafers can be bonded to a target wafer, thus increasing manufacturing yield.

[0083] The manufacturing process for a high-electron-mobility device according to the present invention is compatible with existing manufacturing techniques developed for complementary metal-oxide-semiconductor (CMOS) technology and processes. In other words, the fabrication of devices such as a high-electron-mobility transistor is compatible with the CMOS system, since the features and steps of the present process can be integrated into it without significant additional effort. This reduces the complexity and costs associated with manufacturing such a transistor.

[0084] In the context of the present invention, a (1,0,0) lattice-oriented silicon layer is a silicon layer <100> In the context of the present invention, a (1,1,1) lattice-oriented silicon layer is a silicon layer <111> .

[0085] According to exemplary embodiments, the method further comprises the step of epitaxial growth of a stack of III-N semiconductor layers above the second silicon layer, the epitaxial stack of III-N semiconductor layers comprising an active epitaxial layer; the active epitaxial layer comprising: - a first active III-N layer formed above the second silicon layer; and - a second active III-N layer formed above the first active III-N layer; with a two-dimensional electron gas between the first active III-N shell and the second active III-N shell.

[0086] The method according to the present invention makes it possible to grow a high-electron-mobility transistor on any substrate, for example even on foreign substrates. The method according to the present invention makes it possible to fabricate a high-electron-mobility transistor from an epitaxial stack of III-N semiconductor layers grown on a second bonded silicon layer, i.e., transferred by intelligent cutting, for example on a silicon substrate, such as a high-resistivity silicon substrate, or a SiC substrate, such as a semi-insulating SiC substrate, or a Silicon-on-Insulator substrate, or a germanium substrate, or a germanium-on-insulator substrate, or a sapphire substrate, etc.

[0087] Furthermore, the method according to the present invention makes it possible to bond the second silicon layer to the first silicon layer without having to provide a layer A buffer layer is placed on the Silicon-on-Insulator (SOI) substrate between the first and second silicon layers before bonding. In other words, a buffer layer should not be grown on the SOI substrate before bonding the donor silicon layer to the SOI substrate. A high-electron-mobility transistor (HEMT) fabricated according to the method of the present invention above the second silicon layer is therefore less susceptible to trapping effects than prior art HEMTs grown, for example, on semi-insulating SiC substrates or on high-resistivity Si substrates.

[0088] Another advantage of the process according to the present invention is the improved thermal impedance of the manufactured high-electron-mobility transistors. Thanks to a minimally thick buffer layer between the epitaxial stack of III-N semiconductor layers and the Silicon-on-Insulator substrate, and thanks to the limited thickness of the total stack of hybrid layers formed on the Silicon-on-Insulator substrate, it is possible to obtain low thermal resistivity for the high-electron-mobility transistor. In other words, there is less thermal impedance between the heat sink located at the bottom of the Silicon-on-Insulator substrate and the active device such as, for example, the high-electron-mobility transistor manufactured by the process according to the present invention.

[0089] In the context of the present invention, the growth of the epitaxial stack of III-N semiconductor layers includes the epitaxial growth of the epitaxial stack of III-N semiconductor layers above the second silicon layer, for example by MOCVD or by MBE.

[0090] According to exemplary embodiments, the method further comprises the step of forming a recess in a first functional region of the semiconductor structure, the recess extending through the epitaxial stack of III-N semiconductor layers, through the second silicon layer and through the interface layer, thus exposing the first silicon layer.

[0091] According to examples of embodiments, the process further comprises the steps of: - after separation of the donor wafer and the Silicon-on-Insulator substrate, and before the epitaxial growth of the III-N semiconductor layer epitaxial stack, place the Silicon-on-Insulator substrate, the interface layer, and the second silicon layer in an epitaxial chamber; and - desorb the second layer of silicon in situ in the epitaxial chamber.

[0092] The Silicon-on-Insulator substrate comprising the second silicon layer is prepared for epitaxy, for example by subjecting the Silicon-on-Insulator substrate comprising the second silicon layer to a mechano-chemical polishing for Prepare the second silicon layer for epitaxy. The Silicon-on-Insulator substrate, including the second silicon layer, is placed in an epitaxial chamber to grow the epitaxial stack of III-N semiconductor layers. The surface of the second silicon layer is cleaned by an in-situ desorption step, thus eliminating any surface or implantation damage. In this way, the surface of the second silicon layer is in perfect condition for the epitaxial growth of the III-N semiconductor stack above the second silicon layer in situ, within the epitaxial chamber. This improves the quality of epitaxial growth of active layers in devices such as high electron mobility transistors, thereby enhancing the electrical and thermal characteristics of these transistors. In the context of the present invention, epitaxial growth is achieved using MOCVD or MBE, or any other suitable epitaxial chamber. The first active IILN layer and the second active IILN layer can be formed in situ by epitaxial growth within a MOCVD or MBE epitaxial chamber.

[0093] According to examples of embodiments, the process further comprises the steps of: - in the first functional region, remove by etching the first layer of silicon in one or more regions; - in said one or more regions, form one or more recesses extending through the first silicon layer and through the intermediate layer and up, at least partially, into the base layer, thus defining one or more electrically insulated regions; - provide a dielectric layer in one or more of the recesses; and - to form a contact in said one or more regions of electrical insulation above the dielectric layer, thus forming one or more electrical insulations.

[0094] Said one or more recesses extending through the first silicon layer and through the intermediate layer and at least partially into the base layer allow a combination between a target SOI substrate and deep trench etching of the electrical insulations described above to create electrically isolated islands in association with a variable polarization of the substrate.

[0095] The invention notably includes a semiconductor structure comprising: - a Silicon-on-Insulator substrate comprising: o a base layer comprising silicon; an intermediate layer above the base layer; and o a first silicon layer above the intermediate layer, the first silicon layer having a lattice orientation (1,0,0); - a second silicon layer above the first silicon layer, the second silicon layer having a lattice orientation (1,1,1); and - an interface layer between the first silicon layer and the second silicon layer.

[0096] According to one variant, the interface layer comprises one or more insulating layers.

[0097] According to yet another variant, the interface layer further comprises one or more of the following elements: - one or more layers rich in traps; - materials with low permittivity.

[0098] According to another variant, the second silicon layer has a thickness between 50 nm and 80 nm.

[0099] According to yet another embodiment, the semiconductor structure further comprises an epitaxial stack of III-N semiconductor layers above the second silicon layer, the epitaxial stack of III-N semiconductor layers comprising an active epitaxial layer; the active epitaxial layer comprising: - a first active III-N layer formed above the second silicon layer; and - a second active III-N layer formed above the first active III-N layer; with a two-dimensional electron gas between the first active III-N shell and the second active III-N shell.

[0100] According to one variant, the first active III-N layer comprises GaN and the second active III-N layer comprises AlGaN.

[0101] According to yet another variant, the semiconductor structure further comprises: - a grid above the epitaxial stack of III-N semiconductor layers and within a grid region; and - a passivation stacking between the epitaxial stacking of III-N semiconductor layers and the gate.

[0102] According to another embodiment, the passivation stack includes a recess in a source region and a recess in a drain region; and the semiconductor structure further includes an ohmic contact respectively in the source region and in the drain region.

[0103] According to yet another variant, the semiconductor structure comprises: - in a first functional region, a recess extending through the epitaxial stack of III-N semiconductor layers, through the second silicon layer and through the interface layer, thus exposing the first silicon layer.

[0104] According to yet another variant, the semiconductor structure includes a second functional region comprising the epitaxial stacking of III-N semiconductor layers, the second silicon layer and the interface layer.

[0105] According to one variant, the semiconductor structure further comprises a nucleation layer between the second silicon layer and the epitaxial stack of III-N semiconductor layers, the nucleation layer comprising AlN.

[0106] According to another variant, the intermediate layer comprises: - an intermediate layer rich in traps; and - a buried insulator formed above the intermediate layer rich in traps.

[0107] The invention also relates to a method for manufacturing a semiconductor structure, comprising the steps of: - provide a Silicon-on-Insulator substrate, comprising: o the supply of a base layer comprising silicon; o the provision of an intermediate layer above the base layer; and o the provision of a first silicon layer above the intermediate layer, the first silicon layer having a lattice orientation (1,0,0); and - provide a donor platelet including: o a donor substrate; o a sacrificial layer above the donor substrate; o a donor silicon layer having a lattice orientation (1,1,1) above the sacrificial layer; - provide a first interface layer above the first silicon layer; - provide a second interface layer above the donor silicon layer; - bond the second interface layer to the first interface layer, thus forming an interface layer between the first silicon layer and the donor silicon layer; and - separate the donor wafer and the Silicon on Insulator substrate by dividing the donor silicon layer, or by separating the donor wafer and the Silicon on Insulator substrate at an interface between the donor silicon layer and the sacrificial layer, thus forming above the interface layer a second silicon layer having a lattice orientation (1,1,1) and including at least partially the donor silicon layer bonded to the interface layer.

[0108] According to one embodiment, the method further comprises the step of epitaxial growth of an epitaxial stack of III-N semiconductor layers above the second silicon layer, the epitaxial stack of III-N semiconductor layers comprising an active epitaxial layer; the active epitaxial layer comprising: - a first active III-N layer formed above the second silicon layer; and - a second active III-N layer formed above the first active III-N layer; with a two-dimensional electron gas between the first active III-N shell and the second active III-N shell.

[0109] According to yet another variant, the process further comprises the step of forming a recess in a first functional region of the semiconductor structure, the recess extending through the epitaxial stack of III-N semiconductor layers, through the second silicon layer and through the interface layer, thus exposing the first silicon layer.

[0110] Brief description of the drawings Some examples of embodiments will now be described with reference to the accompanying drawings. For clarity, the drawings represent cross-sections of layers and / or wafers and / or devices, such as, for example, high-electron-mobility transistors according to the present invention. It is clear that the layers and / or wafers and / or devices, such as, for example, high-electron-mobility transistors shown in the accompanying drawings, can have any shape and extend in any direction along the longitudinal direction 3 and / or the transverse direction 4, and / or in a third direction 5 transverse to the longitudinal direction 3 and transverse to the transverse direction 4. The above directions are not shown in all the accompanying drawings in order to preserve the simplicity of the drawings.

[0111] [Fig. 1] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention.

[0112] [Fig.2] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention.

[0113] [Fig.3] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention.

[0114] [Fig.4] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention, on which a gate contact is provided.

[0115] [Fig.5] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention.

[0116] [Fig.6] schematically represents a cross-section of an example of a mode of realization of a semiconductor structure according to the present invention.

[0117] [Fig.7] schematically represents a cross-section of an example embodiment of a semiconductor structure according to the present invention, on which a gate contact is provided.

[0118] [Fig.8A], [Fig.8B], [Fig.9A], [Fig.9B], [Fig.10], [Fig.ll], [Fig.12], [Fig.l3A], [Fig.l3B] schematically represent, in cross-section, examples of embodiments of the steps of the manufacturing process of a semiconductor structure according to the present invention.

[0119] Figure 8A schematically represents a cross-section of an example embodiment of a target wafer, the target wafer comprising a silicon-on-insulator substrate according to the present invention. Figure 8B schematically represents a cross-section of an example embodiment of a donor wafer according to the present invention.

[0120] Figure 9A schematically represents a cross-section of an example embodiment of a target wafer, the target wafer comprising a Silicon-on-Insulator substrate according to the present invention, and the Silicon-on-Insulator substrate comprising a first interface layer. Figure 9B schematically represents a cross-section of an example embodiment of a donor wafer according to the present invention, the donor wafer comprising a second interface layer.

[0121] Fig. 10 schematically represents, in cross-section, the flipping of a donor wafer according to the present invention, the donor wafer comprising a second interface layer over an example embodiment of a target wafer, the target wafer comprising a Silicon on Insulator substrate according to the present invention, and the Silicon on Insulator substrate comprising a first interface layer.

[0122] Fig. 11 schematically represents, in cross-section, the bonding of a donor wafer according to the present invention, the donor wafer comprising a second interface layer on an example embodiment of a target wafer, the target wafer comprising a Silicon on Insulator substrate according to the present invention, and the Silicon on Insulator substrate comprising a first interface layer.

[0123] Fig. 12 schematically represents, in cross-section, the structure resulting from the bonding of a donor wafer according to the present invention, the donor wafer comprising a second interface layer on an example embodiment of a target wafer, the target wafer comprising a Silicon on Insulator substrate according to the present invention, and the Silicon on Insulator substrate comprising a first interface layer.

[0124] Figure 13A schematically represents, in cross-section, the separation of a donor wafer according to the present invention, the donor wafer comprising a second interface layer with respect to an example embodiment of a target wafer, the target wafer comprising a Silicon-on-Insulator substrate according to the present invention, and the Silicon-on-Insulator substrate comprising a first interface layer. Figure 13B schematically represents a cross-section of an example embodiment of a semiconductor structure according to the present invention resulting from this separation.

[0125] [Fig. 14] schematically represents a cross-section of an example embodiment of a high electronic mobility transistor according to the present invention, with a source contact and a drain contact and with electrical insulations.

[0126] Detailed description of embodiments Figure 1 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. As an example, the interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon comprising oxygen.As an example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104.

[0127] Figure 2 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose reference numerals are identical to those of Figure 1 perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. For example, the interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon containing oxygen. For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further comprises an epitaxial stack of HL N 20 semiconductor layers above the second silicon layer 200.A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of IILN semiconductor layers 20. The epitaxial stack of IILN semiconductor layers 20 comprises a buffer layer 24 formed above the second silicon layer 200. The epitaxial stack of IILN semiconductor layers 20 comprises an active epitaxial layer 220 formed above the buffer layer 24. The active epitaxial layer 220 comprises a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further comprises a second active IILN layer 22 formed above the first active IILN layer 101. An Electron Gas two-dimensional 50 is formed between the first active IILN layer 21 and the second active IILN layer 22.The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN.

[0128] Figure 3 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose reference numerals are identical to those in Figures 1 and 2 perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.For example, interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon comprising oxygen. For example... For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further comprises an epitaxial stack of IILN semiconductor layers 20 above the second silicon layer 200. A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of IILN semiconductor layers 20.The hybrid stack 110 further includes a nucleation layer 600 planned between the second silicon layer 200 and the epitaxial stack of semiconductor layers IILN 20. The nucleation layer 600 includes, for example, AlN. The epitaxial stacking of IILN semiconductor layers 20 includes a buffer layer 24 formed above the nucleation layer 600. The epitaxial stacking of IILN semiconductor layers 20 includes an active epitaxial layer 220 formed above the buffer layer 24. The active epitaxial layer 220 includes a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further includes a second active IILN layer 22 formed above the first active IILN layer 101. A two-dimensional electron gas 50 is formed between the first active IILN layer 21 and the second active IILN layer 22.The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN.

[0129] Figure 4 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose reference numerals are identical to those in Figures 1, 2, and 3 perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.For example, interface layer 300 comprises one or more layers of polycrystalline silicon, such as polycrystalline silicon containing oxygen. For example, interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second... silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 includes, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further includes an epitaxial stack of IILN semiconductor layers 20 above the second silicon layer 200. A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of IILN semiconductor layers 20. The epitaxial stack of IILN semiconductor layers 20 includes a buffer layer 24 formed above the second silicon layer 200. The epitaxial stack of IILN semiconductor layers 20 includes an active epitaxial layer 220 formed above buffer layer 24.The active epitaxial layer 220 comprises a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further comprises a second active IILN layer 22 formed above the first active IILN layer 101. A two-dimensional electron gas 50 is formed between the first active IILN layer 21 and the second active IILN layer 22. The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN. Semiconductor structure 1 further includes a passivation stack 500 provided above the epitaxial stack of III-N semiconductor layers 20, more particularly above the second active IIIN layer 22. Semiconductor structure 1 further includes a gate 400 provided above the passivation stack 500 and in a gate region 40.Optionally, the semiconductor structure 1 may further include a nucleation layer provided between the second silicon layer 200 and the epitaxial stack of semiconductor layers IILN 20, the nucleation layer being made of AlN.

[0130] Figure 5 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose reference numerals are identical to those in Figures 1, 2, 3, and 4 perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.As an example, interface layer 300 includes one or more . layers comprising polycrystalline silicon, such as polycrystalline silicon containing oxygen. For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 includes, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further includes an epitaxial stack of HL N 20 semiconductor layers above the second silicon layer 200. A hybrid stack 110 is thus formed above the Silicon on Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200 and the epitaxial stack of HL N 20 semiconductor layers.The epitaxial stacking of IILN semiconductor layers 20 includes a buffer layer 24 formed above the second silicon layer 200. The epitaxial stacking of IILN semiconductor layers 20 includes an active epitaxial layer 220 formed above the buffer layer 24. The active epitaxial layer 220 includes a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further includes a second active IILN layer 22 formed above the first active IILN layer 101. A two-dimensional electron gas 50 is formed between the first active IILN layer 21 and the second active IILN layer 22. The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN. The semiconductor structure 1 comprises a first functional region 11 and a second functional region 12.In the first functionality region 11, a recess 111 extends through the epitaxial stack of IILN semiconductor layers 20, through the second silicon layer 200 and through the interface layer 300, thus exposing the first silicon layer 300. The semiconductor structure 1 further includes a second functionality region 12, the second functionality region 12 comprising the epitaxial stack of IILN semiconductor layers 20, the second silicon layer 200 and the interface layer 300.

[0131] Figure 6 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose reference numerals are identical to those in Figures 1, 2, 3, 4, and 5 perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having an orientation of network (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. For example, the interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon containing oxygen. For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104.The semiconductor structure 1 further comprises an epitaxial stack of IILN semiconductor layers 20 above the second silicon layer 200. A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of IILN semiconductor layers 20. The hybrid stack 110 further comprises a nucleation layer 600 located between the second silicon layer 200 and the epitaxial stack of IILN semiconductor layers 20. The nucleation layer 600 comprises, for example, AlN. The epitaxial stacking of IILN 20 semiconductor layers includes a buffer layer 24 formed above the nucleation layer 600. The epitaxial stacking of IILN 20 semiconductor layers includes an active epitaxial layer 220 formed above the buffer layer 24.The active epitaxial layer 220 comprises a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further comprises a second active IILN layer 22 formed above the first active IILN layer 101. A two-dimensional electron gas 50 is formed between the first active IILN layer 21 and the second active IILN layer 22. The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN. The semiconductor structure 1 comprises a first functionality region 11 and a second functionality region 12. In the first functionality region 11, a recess 111 extends through the epitaxial stack of semiconductor layers IILN 20, through the second silicon layer 200 and through the interface layer 300, thus exposing the first silicon layer 300.The semiconductor structure 1 further includes a second functionality region 12, the second functionality region 12 comprising the epitaxial stacking of IIL N semiconductor layers 20, the second silicon layer 200 and the interface layer 300.

[0132] Figure 7 schematically represents a cross-section of an example embodiment of a semiconductor structure 1 according to the present invention. The elements whose numerical references are identical to those in Figures 1, 2, 3, 4, 5, and 6 fulfill the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers. The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. As an example, the interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon comprising oxygen.For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further comprises an epitaxial stack of IILN semiconductor layers 20 above the second silicon layer 200. A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of IILN semiconductor layers 20.The hybrid stack 110 further includes a nucleation layer 600 provided between the second silicon layer 200 and the epitaxial stack of semiconductor layers IIIN 20. The nucleation layer 600 comprises, for example, AlN. It is clear that the presence of the nucleation layer 600 is optional according to the present invention. The epitaxial stacking of IILN 20 semiconductor layers includes a buffer layer 24 formed above the nucleation layer 600. The epitaxial stacking of IILN 20 semiconductor layers includes an active epitaxial layer 220 formed above the buffer layer 24. The active epitaxial layer 220 includes a first active IILN layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further includes a second active IILN layer 22 formed above the first active IILN layer 101.A two-dimensional electron gas 50 is formed between the first active IILN layer 21 and the second active IILN layer 22. The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN. The semiconductor structure 1 comprises a first functionality region 11 and a second functionality region 12. In the first functionality region 11, a hollow 111 extends through the stack. epitaxial stacking of III-N semiconductor layers 20, through the second silicon layer 200 and through the interface layer 300, thus exposing the first silicon layer 300. Semiconductor structure 1 further includes a second functionality region 12, the second functionality region 12 comprising the epitaxial stacking of III-N semiconductor layers 20, the second silicon layer 200 and the interface layer 300. Semiconductor structure 1 further includes a passivation stacking 500 provided above the epitaxial stacking of III-N semiconductor layers 20 in the second functionality region 12, more specifically above the second active III-N layer 22 in the second functionality region 12. Semiconductor structure 1 further includes a gate 400 provided above the passivation stacking 500 and in a grid region 40 in the second functionality region 12.

[0133] Figures 8A, 8B, 9A, 9B, 10, 11, 12, 13A and 13B schematically represent, in cross-section, examples of embodiments of the steps in the process of manufacturing a semiconductor structure according to the present invention. The elements whose numerical references are identical to those in Figures 1, 2, 3, 4, 5, 6 and 7 perform the same function.

[0134] Figure 8A schematically represents a cross-section of an example embodiment of a target wafer, the target wafer comprising a Silicon-on-Insulator substrate 100 according to the present invention. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102. The first silicon layer 101 has a lattice orientation (1,0,0). The intermediate layer 102 comprises a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104.

[0135] Figure 8B schematically represents a cross-section of an example embodiment of a donor wafer 700 according to the present invention. The donor wafer 700 comprises a donor substrate 701, a sacrificial layer 702 above the donor substrate 701, and a donor silicon layer 703 having a lattice orientation (1,1,1) above the sacrificial layer 702.

[0136] Figure 9A schematically represents a cross-section of an example embodiment of a target wafer, the target wafer comprising a Silicon on Insulator 100 substrate according to the present invention. The Silicon on Insulator 100 substrate comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102. The first silicon layer 101 has a lattice orientation (1,0,0). The intermediate layer 102 comprises a The Silicon-on-Insulator substrate 100 comprises a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The substrate further comprises a first interface layer 603. The first interface layer 603 includes one or more insulating layers. The first interface layer 603 may further include one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.

[0137] Figure 9B schematically represents a cross-section of an exemplary embodiment of a donor wafer 700 according to the present invention. The donor wafer 700 comprises a donor substrate 701, a sacrificial layer 702 above the donor substrate 701, and a donor silicon layer 703 having a lattice orientation (1,1,1) above the sacrificial layer 702. The donor wafer 700 further comprises a second interface layer 604 above the donor silicon layer 703. The second interface layer 604 comprises one or more insulating layers. The second interface layer 604 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.

[0138] Figure 10 schematically represents, in cross-section, the inversion of a donor wafer 700 according to the present invention onto a target wafer comprising a Silicon-on-Insulator substrate 100 according to the present invention. The donor wafer 700 comprises a donor substrate 701, a sacrificial layer 702 above the donor substrate 701, and a donor silicon layer 703 having a lattice orientation (1,1,1) above the sacrificial layer 702. The donor wafer 700 further comprises a second interface layer 604 above the donor silicon layer 703. The second interface layer 604 comprises one or more insulating layers. The second interface layer 604 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.The Silicon on Insulator substrate 100 comprises a base layer 103 of silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102. The first silicon layer 101 has a lattice orientation (1,0,0). The intermediate layer 102 comprises a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The Silicon on Insulator substrate 100 further comprises a first interface layer 603. The first interface layer 603 comprises one or more insulating layers. The first interface layer 603 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. The donor wafer 700 must be inverted relative to the target wafer and by . relative to its original orientation, as shown in [Fig.9A], so that the first interface layer 603 and the second interface layer 604 are facing each other.

[0139] Figure 11 schematically represents, in cross-section, the inversion of a donor wafer 700 according to the present invention onto a target wafer comprising a Silicon-on-Insulator substrate 100 according to the present invention. The donor wafer 700 comprises a donor substrate 701, a sacrificial layer 702 above the donor substrate 701, and a donor silicon layer 703 having a lattice orientation (1,1,1) above the sacrificial layer 702. The donor wafer 700 further comprises a second interface layer 604 above the donor silicon layer 703. The second interface layer 604 comprises one or more insulating layers. The second interface layer 604 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials.The Silicon-on-Insulator substrate 100 comprises a base layer 103 of silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102. The first silicon layer 101 has a lattice orientation of (1,0,0). The intermediate layer 102 comprises a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The Silicon-on-Insulator substrate 100 further comprises a first interface layer 603. The first interface layer 603 comprises one or more insulating layers. The first interface layer 603 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. The donor wafer 700 must be flipped relative to the target wafer and relative to its original orientation, as shown in [Fig.9A], so that the first interface layer 603 and the second interface layer 604 are facing each other. The donor wafer 700 is positioned above the Silicon on Insulator substrate 100 so that the first interface layer 603 and the second interface layer 604 are facing each other. The donor wafer 700 is lowered towards the Silicon on Insulator substrate 100 until the second interface layer 604 comes into contact with the first interface layer 603. Correspondingly, the target wafer is raised towards the donor wafer 700 until the first interface layer 603 comes into contact with the second interface layer 604.

[0140] Figure 12 schematically represents, in cross-section, the structure resulting from the bonding of a donor wafer 700 according to the present invention onto an example of an embodiment of a target wafer comprising a silicon substrate on Insulator 100 according to the present invention. The donor wafer 700 comprises a donor substrate 701, a sacrificial layer 702 above the donor substrate 701, and a donor silicon layer 703 having a lattice orientation (1,1,1) above the sacrificial layer 702. The donor wafer 700 further comprises a second interface layer 604 above the donor silicon layer 703. The second interface layer 604 comprises one or more insulating layers. The second interface layer 604 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. The Silicon on Insulator 100 substrate comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103 and a first silicon layer 101 above the intermediate layer 102. The first silicon layer 101 has a lattice orientation (1,0,0).The intermediate layer 102 comprises a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The Silicon-on-Insulator substrate 100 further comprises a first interface layer 603. The first interface layer 603 comprises one or more insulating layers. The first interface layer 603 may further comprise one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. The donor wafer 700 must be flipped relative to the target wafer and its original orientation, as shown in [Fig. 9A], so that the first interface layer 603 and the second interface layer 604 are facing each other.The donor wafer 700 is positioned above the Silicon substrate on Insulator 100 so that the first interface layer 603 and the second interface layer 604 are opposite each other. The donor wafer 700 is lowered towards the Silicon on Insulator substrate 100 until the second interface layer 604 comes into contact with the first interface layer 603. Correspondingly, the target wafer is raised towards the donor wafer 700 until the first interface layer 603 comes into contact with the second interface layer 604. The second interface layer 604 is then bonded to the first interface layer 603, thus forming an interface layer 300 between the first silicon layer 101 and the donor silicon layer 703. The donor wafer 700 and the target wafer are then bonded to each other.

[0141] Figure 13A schematically represents, in cross-section, the separation of a donor wafer according to the present invention from a target wafer comprising a Silicon on Insulator 100 substrate according to the present invention. The donor wafer 700 and the target wafer are separated from each other by intelligent cutting of the donor silicon layer 703. In the context of the present invention, a An interface layer 300 is formed between the first silicon layer 101 and the donor silicon layer 703, with the first interface layer 603 and the second interface layer 604 coming into contact with each other. Separation of the donor wafer 700 from the target substrate by intelligent cutting at the level of the donor silicon layer 703 occurs by causing the rupture of the donor silicon layer 703 at the interface between the donor silicon layer 703 and the sacrificial layer 702 of the donor wafer 700. In other words,The donor silicon layer 703 is cut at the interface between the donor silicon layer 703 and the sacrificial layer 702 of the donor wafer 700. This separation forms a second silicon layer 200 on the Silicon-on-Insulator substrate 100. This second layer comprises the donor silicon layer 703, which was initially grown on the donor wafer 700, and is now bonded to the target wafer containing the Silicon-on-Insulator substrate 100. The thickness of this second silicon layer 200 on the target wafer containing the Silicon-on-Insulator substrate 100 corresponds approximately to the thickness of the donor silicon layer 703 that was grown on the donor substrate 700. Alternatively, the separation of the donor wafer 700 from the target wafer containing the Silicon-on-Insulator substrate 100 by intelligent cutting of the donor silicon layer 703 occurs in causing the splitting of the donor silicon layer 703,thus leaving a first remaining portion of the donor silicon layer 703 on the donor wafer 700, separated from the target wafer comprising the Silicon on Insulator substrate 100, which will subsequently be referred to as the sacrificial silicon layer, and also leaving a second remaining portion of the donor silicon layer 703 on the target wafer comprising the Silicon on Insulator substrate 100, which will subsequently be referred to as the second silicon layer 200, the sum of the thickness of the first remaining portion and the thickness of the second remaining portion corresponding substantially to the total thickness of the donor silicon layer 703 that grows on the sacrificial substrate before bonding. In other words,The donor silicon layer 703 is split across its thickness. This split forms, on the target wafer comprising the Silicon on Insulator substrate 100, a second silicon layer 200 comprising at least partially the donor silicon layer 703 initially grown on the donor wafer 700 and bonded to the target wafer comprising the Silicon on Insulator substrate 100 according to the present invention, the thickness of the second silicon layer 200 on the Silicon on Insulator substrate 100 being between 50 nm and 80 nm. Figure 13B schematically represents a cross-section of an example embodiment of a semiconductor structure according to the present invention resulting from this split.

[0142] Figure 14 schematically represents a cross-section of an example embodiment of a high-electron-mobility transistor according to the present invention, having a gate, a source contact, and a drain contact, and having electrical insulation. The elements whose reference numerals are identical to those in Figures 1 to 13B perform the same function. The semiconductor structure 1 comprises a Silicon-on-Insulator substrate 100. The Silicon-on-Insulator substrate 100 comprises a base layer 103 comprising silicon, an intermediate layer 102 above the base layer 103, and a first silicon layer 101 above the intermediate layer 102, the first silicon layer 101 having a lattice orientation (1,0,0). The interface layer 300 comprises one or more insulating layers.The interface layer 300 optionally comprises one or more trap-rich layers and / or one or more layers comprising low-permittivity materials. For example, the interface layer 300 comprises one or more layers comprising polycrystalline silicon, such as polycrystalline silicon containing oxygen. For example, the interface layer 300 comprises one or more layers of silicon carbide, such as polycrystalline silicon carbide. The second silicon layer 200 preferably has a thickness between 50 and 80 nm. The intermediate layer 102 comprises, for example, a trap-rich intermediate layer 104 and a buried insulator 105 formed above the trap-rich intermediate layer 104. The semiconductor structure 1 further comprises an epitaxial stack of semiconductor layers IIIN 20 above the second silicon layer 200.A hybrid stack 110 is thus formed above the Silicon-on-Insulator substrate 100, the hybrid stack 110 comprising the interface layer 300, the second silicon layer 200, and the epitaxial stack of III-N semiconductor layers 20. The epitaxial stack of III-N semiconductor layers 20 comprises a buffer layer 24 formed above the second silicon layer 200. The epitaxial stack of III-N semiconductor layers 20 comprises an active epitaxial layer 220 formed above the buffer layer 24. The active epitaxial layer 220 comprises a first active III-N layer 21 formed above the buffer layer 24. The active epitaxial layer 220 further comprises a second active III-N layer 22 formed above the first active III-N layer 101. An Electron Gas two-dimensional 50 is formed between the first active IILN layer 21 and the second active IILN layer 22.The first active IILN layer 21 comprises GaN and the second active IILN layer 22 comprises AlGaN. The semiconductor structure 1 comprises a first functionality region 11 and a second functionality region 12. In the first functionality region 11, a recess 111 extends through the epitaxial stacking of semiconductor layers. III-N 20, through the second silicon layer 200 and through the interface layer 300, thus exposing the first silicon layer 300. The semiconductor structure 1 further includes a second functionality region 12, the second functionality region 12 comprising the epitaxial stacking of III-N semiconductor layers 20, the second silicon layer 200 and the interface layer 300. The semiconductor structure 1 further includes a passivation stacking 500 provided above the epitaxial stacking of III-N semiconductor layers 20 in the second functionality region 12, more specifically above the second active III-N layer 22 in the second functionality region 12.The semiconductor structure 1 further comprises a grid 400 for a HEMT fabricated by the method according to the present invention, provided above the passivation stack 500 and in a grid region 40 in the second functional region 12. The passivation stack 500 comprises, for example, a recess in a source region 41 and a recess in a drain region 42. The semiconductor structure 1 further comprises an ohmic contact 800 for the source of the HEMT in the source region 41 and an ohmic contact 900 for the drain of the HEMT in the drain region 42. The method further comprises the step of removing, by etching, the epitaxial stack of semiconductor layers IIIN 300 in one or more electrically insulated regions.The method further comprises the step of forming one or more recesses 401 extending through the first silicon layer 101 and through the intermediate layer 102 into, at least partially, the base layer 103, said one or more recesses 401 not being positioned between the gate region 40 and the source region 41 or between the gate region 40 and the drain region 42, thus defining one or more electrically insulating regions for the HEMT. The method further comprises the step of providing a dielectric layer 406 along the side walls 404, 405 of one or more of the recesses 401.The method further comprises the step of forming a contact 402 in said one or more electrically insulated regions such that the contact 402 is in direct contact with the base layer 103 at the bottom 403 of each of the recesses 401 along the transverse direction 4 and such that the contact 402 is in contact with the dielectric layer 406 along the lateral walls 404; 405 of each of the recesses 401, thus enabling the formation of one or more electrical insulators.

[0143] Although the present invention has been illustrated with reference to specific embodiments, it will be apparent to specialists in the art that the invention is not limited to the details of the embodiments presented above by way of illustration, and that the present invention can be implemented by making various transformations and modifications without departing from its scope. The present embodiments should therefore be considered in all respects as presented by way of non-limiting illustration, the scope of the invention being indicated by the annexed claims rather than by the preceding description, and all modifications which fall within the scope of the claims are therefore intended to be incorporated therein.

[0144] The reader of this patent application will further understand that the words "comprising" or "include" do not exclude other elements or steps, and that a single element, such as a computer system, a processor, or other integrated unit, can perform the functions of several means cited in the claims. All reference symbols appearing in the claims are not to be interpreted as limiting the respective claims. The terms "first," "second," "third," "a," "b," "c," and others, when used in the description or in the claims, are introduced to distinguish similar elements or steps and do not necessarily describe a sequential or chronological order. Similarly, the terms "top," "bottom," "above," "below," and others are used for descriptive purposes and do not necessarily denote relative positions.It is understood that the terms thus used are interchangeable in the appropriate circumstances and that embodiments of the invention may operate in accordance with the present invention in other sequences, or in orientations different from that(s) described or illustrated above.

Claims

Demands

1. Semiconductor structure (1) comprising: - a Silicon on Insulator substrate (100) comprising: o a base layer (103) comprising silicon; o an intermediate layer (102) above the base layer; and o a first silicon layer (101) above the intermediate layer (102), the first silicon layer (101) having a lattice orientation (1,0,0); - a second silicon layer (200) above the first silicon layer (101), the second silicon layer (200) having a lattice orientation (1,1,1); and - an interface layer (300) between the first silicon layer (101) and the second silicon layer (200).

2. Semiconductor structure (1) according to claim 1, wherein the interface layer (300) comprises one or more insulating layers.

3. Semiconductor structure (1) according to claim 1 or claim 2, wherein the interface layer (300) further comprises one or more of the following: - one or more trap-rich layers; - low permittivity materials.

4. Semiconductor structure (1) according to any one of the preceding claims, wherein the second silicon layer (200) has a thickness between 50 nm and 80 nm.

5. Semiconductor structure (1) according to any one of the preceding claims, wherein the semiconductor structure (1) further comprises an epitaxial stack of III-N semiconductor layers (20) above the second silicon layer (200), the epitaxial stack of III-N semiconductor layers (20) comprising an active epitaxial layer (220); the active epitaxial layer (220) comprising: - a first active III-N layer (21) formed above the second silicon layer (200); and - a second active III-N layer (22) formed above the first active III-N layer (101); with a two-dimensional electron gas between the first active III-N layer (21) and the second active III-N layer (22).

6. Semiconductor structure (1) according to claim 5, wherein the first active III-N layer (21) comprises GaN and wherein the second active III-N layer (22) comprises AlGaN.

7. Semiconductor structure (1) according to claim 6, wherein the semiconductor structure (1) further comprises: - a grid (400) above the epitaxial stack of III-N semiconductor layers (20) and in a grid region (40); and - a passivation stack (500) between the epitaxial stack of III-N semiconductor layers (20) and the grid (400).

8. Semiconductor structure (1) according to claim 7, wherein the passivation stack (500) comprises a recess in a source region (41) and a recess in a drain region (42); and wherein the semiconductor structure further comprises an ohmic contact respectively in the source region (41) and in the drain region (42).

9. Semiconductor structure (1) according to any one of claims 5 to 8, wherein the semiconductor structure (1) comprises: - in a first functional region (11), a recess (111) extending through the epitaxial stack of III-N semiconductor layers (20), through the second silicon layer (200) and through the interface layer (300), thereby exposing the first silicon layer (101).

10. Semiconductor structure (1) according to any one of claims 5 to 9, wherein the semiconductor structure (1) comprises a second functional region (12) comprising the epitaxial stacking of III-N semiconductor layers (20), the second silicon layer (200) and the interface layer (300).

11. Semiconductor structure (1) according to any one of the preceding claims in combination with claim 5, wherein the semiconductor structure (1) further comprises a nucleation layer (600) between the second silicon layer (200) and the epitaxial stack of III-N semiconductor layers (20), the nucleation layer (600) comprising AlN.

12. Semiconductor structure (1) according to any one of the preceding claims, wherein the intermediate layer (102) comprises: - a trap-rich intermediate layer (104); and - a buried insulator (105) formed above the trap-rich intermediate layer (104).

13. A method for manufacturing a semiconductor structure (1), comprising the steps of: - providing a Silicon-on-Insulator substrate (100), comprising: o providing a base layer (103) comprising silicon; o providing an intermediate layer (102) above the base layer (103); and o providing a first silicon layer (101) above the intermediate layer (102), the first silicon layer (101) having a lattice orientation (1,0,0); and - providing a donor wafer (700) comprising: o a donor substrate (701); o a sacrificial layer (702) above the donor substrate (701); o a donor silicon layer (703) having a lattice orientation (1,1,1) above the sacrificial layer (702); - provide a first interface layer (603) above the first silicon layer (101); - provide a second interface layer (604) above the donor silicon layer (703);- to bond the second interface layer (604) to the first interface layer (603), thus forming an interface layer (300) between the first silicon layer (101) and the donor silicon layer (703); and - to separate the donor wafer (700) and the Silicon on Insulator substrate (100) by dividing the donor silicon layer (703), or by separating the donor wafer (700) and the Silicon on Insulator substrate (100) at an interface between the donor silicon layer (703) and the sacrificial layer (601), thus forming above the interface layer (300) a second silicon layer (200) having a lattice orientation (1,1,1) and comprising at least partially the donor silicon layer (703) bonded to the interface layer (300).

14. A method according to claim 13, wherein the method further comprises the epitaxial growth step of an epitaxial stack of III-N semiconductor layers (20) above the second silicon layer (200), the epitaxial stacking of semiconductor layers

15. conductive III-N (20) comprising an epitaxial active layer (220); the epitaxial active layer (220) comprising: - a first active III-N layer (21) formed above the second silicon layer (200); and - a second active III-N layer (22) formed above the first active III-N layer (101); with a two-dimensional electron gas between the first active III-N shell (21) and the second active III-N shell (22). Method according to claim 14, wherein the method further comprises the step of forming a recess (110) in a first functional region (11) of the semiconductor structure (1), the recess (110) extending through the epitaxial stack of III-N semiconductor layers (20), through the second silicon layer (200) and through the interface layer (300), thereby exposing the first silicon layer (101).

Images