Telecommunications processor including a reconfigurable interconnect device

Abstract

Telecommunications processor comprising a reconfigurable interconnect device. The invention relates to a telecommunications processor comprising a reconfigurable, non-blocking interconnect device configured to receive signals from one or more receiving antennas at its inputs and deliver said signals via outputs to one or more transmitting antennas. The interconnect device includes a crossover switch forming a two-dimensional array of rows and columns, and comprising fewer elementary switches than the number of row-column intersections of the two-dimensional array, for routing said signals from the inputs to the outputs.Elementary switches are arranged at row-column intersections to form at least one triangular matrix, such that all row-column intersections within the triangular matrix contain an activatable elementary switch, and such that some or all of the row-column intersections outside the triangular matrix do not contain an elementary switch. Figure 1 for the abbreviation.

Description

Title of the invention: Telecommunications processor comprising a reconfigurable interconnection device

[0001] The invention relates to a telecommunications processor comprising a reconfigurable interconnection device and a method for configuring the processor according to the invention.

[0002] Figure 1 illustrates an example of a telecommunications processor according to the prior art. Typically, a telecommunications processor 1000 includes input ports Rx and output ports Tx connected to radio frequency (RF) or optical receive or transmit chains.

[0003] The Rx (respectively Tx) ports are associated with receiving (respectively transmitting) antennas to establish a link with, on the one hand, fixed relay stations, known as "gateways" (GW), and on the other hand, users (fixed or mobile). The antennas providing transmission or reception to users can be of the active antenna type (antenna array, "phased array"), and consist of a set of elementary antennas whose signals can be combined according to a configurable beamforming law to flexibly form beams in the desired directions.

[0004] The transmitting or receiving chains are respectively connected to RF antennas or optical transmission devices. For example, the receiving or transmitting chains process optical signals when the telecommunications system, including the processor, uses free-space optical links.

[0005] At the input ports Rx and output ports Tx, signals can be received, respectively transmitted, simultaneously from, or to, a set of different directions, depending on the pattern of the antenna(s) associated with the port. The signals generally comprise frequency channels in which the transmitted information is encoded.

[0006] An RF signal can be received by an antenna or an antenna array. The received electrical signal is generally processed (in receiving chains) in an analog manner to pre-filter the frequency band, to amplify it, or to perform a frequency transposition in order to shift the useful band around an intermediate frequency. In particular, in a digital processor, the signal is then converted into a digital signal by analog-to-digital converters (ADCs). The received signal may also undergo additional digital processing such as frequency filtering. The received and digitized signals can be decomposed into their elementary frequency components by Dx demultiplexers. The frequency components produced by the demultiplexers can be processed by a DBF-RX beamforming unit.

[0007] RF signals can be spatially filtered along specific directions due to the specific geometry of the antenna(s) (such as RX / GW).

[0008] Alternatively, beams can be produced using an array of elementary antennas combined with associated signal processing. This beamforming processing can be carried out in an analog manner, particularly in an analog telecommunications processor, or in a digital manner, particularly in a digital telecommunications processor.

[0009] The shaped signals are then routed to the input ports of an interconnect device 110. The signals delivered by the interconnect device 110 may optionally be processed by a beamforming unit in transmit mode DBF-TX. Then, multiplexers Mx combine the signals either directly from the output of the interconnect device 110 or from the output of the beamforming unit DBF-TX.

[0010] The composite signals are converted into analog signals by digital-to-analog converters (DACs), before being amplified (in transmission chains) to be transmitted by transmitting antennas (TX.GW, antenna array).

[0011] The interconnect device 110 implements a routing function for signals received at its inputs to produce them at its outputs. The interconnect device is reconfigurable to select the output(s) associated with the various inputs. The interconnect device 110 thus provides flexible connectivity between upstream receiving channels and downstream transmitting channels, a channel being considered as a resource in terms of direction and frequency sub-bands, and associated with a useful signal (for a user or for a gateway station), in transmission or reception.

[0012] Due to its position at the heart of the processor, the interconnect device handles all data traffic. In particular, the digital throughput processed by the interconnect device 110 is proportional to the total aggregate bandwidth (which depends on the number of beams and the average bandwidth per beam, for example on the order of several hundred GHz) and the quantization used for the digital signals (for example 16 bits).

[0013] The interconnection device is typically arranged in routing rows and columns. Switches at the intersections of the rows and columns allow a signal to be routed from a row to a column or vice versa. Depending on its architecture, in other words, the arrangement of the switches, an interconnection device may be able to route a signal from any one of its inputs to any one or more of its outputs, regardless of already connected rows and columns. In particular, an interconnection device is said to be "blocking" if it does not possess this property. The interconnection device is said to be "conditionally non-blocking" if it can implement any new interconnection on the condition of reconfiguring existing row and column connections. Finally, the interconnection device is said to be "strictly non-blocking" if it can implement any interconnection without requiring a reconfiguration of existing rows and columns.

[0014] When an input delivers its signal to a single output, this is called a unicast connection. When an input delivers its signal to multiple outputs, this is called a multicast connection. In particular, in an application where the processor is embedded in a satellite, the multicast connection is used to simultaneously broadcast the same information to several recipients, who are, in particular, visible from various directions and / or use different frequency channels.

[0015] A reconfigurable interconnection device with a simple architecture is a crossbar switch, for example, as illustrated in [Fig. 2]. The crossbar switch example forms a two-dimensional square network (or matrix) of N rows and N columns. The crossbar switch includes elementary switches at the intersections of the rows and columns (not shown). A connection between a row and a column is obtained, in particular, by turning on the switch located at the intersection of that row and column.

[0016] More generally, a reconfigurable interconnection device of the type cross-bus switch has a rectangular architecture comprising N rows and P columns.

[0017] In the context of this application, for reasons of simplification of the description and not of limitation, a dimension of the network designates a direction along which either the rows or the columns are positioned.

[0018] The inputs of the crossbar switch are located along a first dimension, and the outputs of the crossbar switch are located along a second dimension. Thus, in the example illustrated in [Fig. 2], the first dimension is that along which the rows are positioned, and the second dimension is that along which the columns are positioned. However, the reverse is also possible.

[0019] In the simplified example of a square matrix in [Fig. 2], the inputs of the crossbar switch are located along one left side of the square array; and the outputs of the crossbar switch are located along one bottom side of the square network. However, the inputs and outputs could be positioned on other sides of the square network.

[0020] The elementary switches located at the row-column intersections can be 1X1 switches, for example as illustrated in [Fig. 3]. A 1X1 switch has one input and one output and selectively establishes the connection between its input and its output. In an integrated electronic circuit, the 1X1 switch can be implemented by a FET transistor. As is known per se, the configuration of the crossbar switch using 1X1 switches must guarantee the absence of signal contention, namely, the impossibility for several inputs to transmit their inputs to the same output. Thus, in particular, when several rows are driven at low impedance, each column of the crossbar switch has at most one closed 1X1 switch.

[0021] The elementary switches can be 2x1 switches, also known as multiplexers, for example as illustrated in [Fig. 4]. A 2x1 multiplexer has two inputs and one output and selectively establishes the connection between its first or second input and its output. For example, in [Fig. 4], each 2x1 multiplexer selects the signal present at its row input or the signal at its column input and propagates it to its column output. The 2x1 multiplexer notably avoids any risk of contention between the row inputs.

[0022] A crossbar switch is particularly advantageous because it is non-blocking for unicast or multicast connections. However, the implementation complexity and power consumption of a crossbar switch are quadratic with its number of inputs / outputs.

[0023] A rectangular "crossbar" switch of N rows and P columns, consisting of a full matrix network, i.e. with an elementary switch at each row-column intersection, has a complexity in terms of elementary switches of N*P.

[0024] In the case where the switch is a square matrix network (N=P), the number of elementary switches is N2.

[0025] However, the digital data rate and the number of input / output operations supported by current telecommunications processors tend to increase. This is particularly impactful in an application where the telecommunications processor is embedded in a satellite.

[0026] A solution is therefore sought to address both the problem of implementation complexity and the power consumption of a reconfigurable interconnection device for a telecommunications processor.

[0027] To this end, the invention proposes a specific assembly of the elementary switches of the crossed bar switch combined with a permutation of the laws of signal beam formation upstream or downstream of the network, or combined with a permutation of signals upstream of the crossbar switch.

[0028] The assembly of elementary switches for a crossbar switch defines a partial square or rectangular matrix network, where no elementary switches are implemented within at least one triangular matrix so as to define at least one triangular matrix of active switches in the network.

[0029] The complexity in elementary switches is then reduced. The implementation by a permutation device of the beam formation laws upstream or downstream of the matrix network, or of permutation of the signals upstream of the matrix network, makes it possible to guarantee the establishment of any unicast and multicast connection by the reconfigurable interconnection device of the type of crossed bar switch having an architecture comprising N rows and P columns.

[0030] Thus, to configure the routing of signals, by applying specific permutations upstream or downstream of the crossbar switch, appropriately with a specific configuration of elementary switches organized according to at least one triangular matrix, the present invention makes it possible to reduce the complexity of the number of switches to be implemented.

[0031] In the case of a square matrix where N=P, the complexity in number of elementary commutators is reduced to N(N+l) / 2.

[0032] Due to the absence of elementary switches at row-column intersections which are not located within such at least one triangular matrix, the device of the invention allows a significant reduction in the consumption of the crossed bar switch.

[0033] To achieve the desired result, a telecommunications processor is proposed comprising a reconfigurable, non-blocking interconnect device configured to receive signals from one or more receiving antennas at its inputs and deliver said signals via outputs to one or more transmitting antennas. The interconnect device includes a crossbar switch forming a two-dimensional network of N rows and P columns, the inputs of the crossbar switch being located along a first dimension of the network, and the outputs of the crossbar switch being located along a second dimension of the network. The crossbar switch comprises a number of elementary switches less than the number of row-column intersections of the two-dimensional network, for routing said signals from the inputs to the outputs.The elementary switches are arranged on the network at row-column intersections to form at least one triangular matrix, such that all row-column intersections in said at least one triangular matrix. include an elementary switch that can be activated, and such that all or part of the row-column intersections outside said at least one triangular matrix do not include an elementary switch.

[0034] The device can be implemented according to alternative or combined embodiments.

[0035] In one embodiment, the interconnection device is coupled to a switching device allowing the input or output signals of said at least one triangular matrix to be switched.

[0036] In one embodiment, the telecommunications processor includes receive beamformers associated with beamforming laws, and the switching device is configured to switch one or more beamforming laws between the beamformers, so as to switch the upstream signals of said at least one triangular matrix, according to the routing requirement between the upstream and downstream signals of the configurable interconnect device.

[0037] In one embodiment, the telecommunications processor includes transmit beamformers associated with beamforming laws, and the switching device is configured to switch one or more beamforming laws between the beamformers, so as to switch said signals downstream of said at least one triangular matrix, according to the routing requirement between the upstream and downstream signals of the configurable interconnect device.

[0038] In one embodiment, the two-dimensional network of N rows and P columns forms a square matrix network with N=P or forms a rectangular matrix network with N 4P.

[0039] In one embodiment, the elementary switches forming at least one triangular matrix are 1x1 switches or 2x1 switches.

[0040] In one embodiment, the elementary switches forming at least one triangular matrix are 2X2 switches configured to selectively interconnect a first input along the first dimension or a second input along the second dimension with a first output along the first dimension and independently with a second output along the second dimension.

[0041] In one embodiment, the elementary switches on the diagonal of said at least one triangular matrix are connected successively to each other, by connecting the row output of each switch to the column input of the next switch on the diagonal.

[0042] In one embodiment, the switching device includes a switch connected upstream of the crossbar switch, said switch being configured to distribute said signals between the inputs of the crossbar switch according to the routing requirement between the upstream and downstream signals of the configurable interconnect device.

[0043] The invention also relates to methods.

[0044] In one embodiment, the invention relates to a method for configuring a telecommunications processor which comprises, for signal routing, steps consisting of:

[0045] determine a set of pairs (i, j) corresponding to a routing need between upstream and downstream signals of the interconnection device, considering all row-column intersections of the network of the crossbar switch;

[0046] determine elementary switches of said at least one triangular matrix to be activated for said routing, said step consisting of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, an extremum rank according to the second dimension; iii. order said rank groups according to their extreme rank along the second dimension; iv. allocate successively to each rank group, a rank following the first dimension of the network following the order obtained at the end of said scheduling, and starting with the rank following the first dimension forming a side of the triangular matrix; v. for each rank group, transpose each pair (i, j) into a pair (allocated rank, j), and activate the elementary switch of said pair (allocated rank, j); - swap the input signals of the crossbar switch, corresponding to the rank allocation.

[0047] In one embodiment, the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, a minimal rank according to the second dimension; iii. order said rank groups in ascending order of minimum rank according to the second dimension.

[0048] In one embodiment, the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, a maximum rank according to the second dimension; iii. order said rank groups in descending order of maximum rank according to the second dimension.

[0049] In one embodiment, the invention relates to a method for configuring a telecommunications processor which comprises, for signal routing, steps consisting of:

[0050] determine a set of pairs (i, j) corresponding to a routing need between upstream and downstream signals of the interconnection device, considering all row-column intersections of the network of the crossbar switch;

[0051] determine elementary switches of said at least one triangular matrix to be activated for said routing, said step consisting of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups according to their rank along the first dimension; iii. allocate successively to each rank group, a rank according to the second dimension of the network, and starting with the rank following the second dimension forming a side of the triangular matrix; iv. in each rank group, transpose for each pair, a pair (i, j) into a pair (i, allocated rank), activate the elementary switch of the pair (i, allocated rank), and store the rank j following the second dimension for the allocated rank; - sum the beam formation laws corresponding to the ranks according to the second dimension stored for the same allocated rank associated with a beam shaper in emission; - swap the output signals of the beamformers downstream of the crossbar switch, by swapping the assignment of laws on the beamformers, in correspondence with the rank allocation.

[0052] In one embodiment, the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups in ascending order of rank according to the first dimension.

[0053] In one embodiment, the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups in descending order of rank according to the first dimension.

[0054] Other features and advantages of the present invention will become more apparent upon reading the following description in relation to the following accompanying figures:

[0055] [Fig-1]: [Fig.1], already described, represents a telecommunications processor according to prior art;

[0056] [Fig.2]: [Fig.2], already described, represents a crossed bar switch according to prior art;

[0057] [Fig.3]: Fig.3, already described, represents a crossed bar switch according to prior art including 1X1 switches;

[0058] [Fig.4]: The [Fig.4] already described represents a crossed bar switch according to prior art including 2X1 switches;

[0059] [Fig.5]: [Fig.5] represents architectures of a crossed busbar switch of a reconfigurable interconnection device in a processor according to the invention;

[0060] [Fig.6]: [Fig.6] illustrates a first example of a configuration method for a telecommunications processor according to the invention;

[0061] [Fig.7]: [Fig.7] illustrates a second example of a method for configuring a telecommunications processor according to the invention;

[0062] [Fig.8]: [Fig.8] illustrates a third example of a configuration method for a telecommunications processor according to the invention;

[0063] [Fig.9]: [Fig.9] illustrates a fourth example of a method for configuring a telecommunications processor according to the invention;

[0064] [Fig. 10]: [Fig. 10] illustrates a fifth example of a method for configuring a telecommunications processor according to the invention;

[0065] [Fig. 11]: [Fig. 11] illustrates a sixth example of a method for configuring a telecommunications processor according to the invention;

[0066] [Fig. 12]: [Fig. 12] illustrates a seventh example of a method for configuring a telecommunications processor according to the invention;

[0067] [Fig. 13]: [Fig. 13] illustrates an eighth example of a method for configuring a telecommunications processor according to the invention;

[0068] [Fig. 14]: [Fig. 14] illustrates a ninth example of a method for configuring a telecommunications processor according to the invention;

[0069] [Fig. 15]: [Fig. 15] illustrates a tenth example of a method for configuring a telecommunications processor according to the invention;

[0070] [Fig. 16]: [Fig. 16] illustrates an eleventh example of a method for configuring a telecommunications processor according to the invention;

[0071] [Fig.17]: [Fig.17] illustrates a variant of a first embodiment of a telecommunications processor according to the invention;

[0072] [Fig. 18]: [Fig. 18] illustrates a second embodiment of a telecommunications processor according to the invention;

[0073] [Fig. 19]: [Fig. 19] details the second embodiment of a telecommunications processor according to the invention;

[0074] [Fig.20]: [Fig.20] illustrates an example of a Clos network in a third embodiment of a telecommunications processor according to the invention;

[0075] [Fig.21]: [Fig.21] illustrates another example of a Clos network in the third embodiment of a telecommunications processor according to the invention;

[0076] [Fig.22]: [Fig.22] illustrates an example of a telecommunications processor according to the invention;

[0077] [Fig.23]: [Fig.23] illustrates another example of a telecommunications processor according to the invention;

[0078] [Fig.24]: [Fig.24] illustrates yet another example of a telecommunications processor according to the invention;

[0079] [Fig. 25a]: [Fig. 25a] illustrates a general case of upstream permutations of the matrix network according to the invention;

[0080] [Fig. 25b]: [Fig. 25b] illustrates a general case of permutations downstream of the matrix network according to the invention;

[0081] [Fig.26]: [Fig.26] illustrates an example of permutations downstream of the matrix network according to the invention.

[0082] Figure 5 illustrates examples of crossbar switches (100a, 100b, 100c, or 100d) for a reconfigurable interconnect device of a telecommunications processor according to the invention, in a particular example of square matrix switches. The telecommunications processor is typically implemented, for example, with a set of interconnected electronic integrated circuits distributed across a set of printed circuit boards. The reconfigurable interconnect device receives signals corresponding to frequency sub-bands from one or more receiving antennas and delivers the signals to one or more transmitting antennas.

[0083] The crossbar switch (100a, 100b, 100c or 100d) forms a square network comprising rows and columns. Generically, a crossbar switch according to the invention will be referred to as 100. Elementary switches Located at row-column intersections of the network, they connect rows and columns. The arrangement of the elementary switches composing the crossbar switch according to the invention forms a triangular matrix.

[0084] A triangular matrix is ​​defined as an arrangement of elementary switches located, in particular, on a diagonal and a side of the diagonal of the network. The diagonal of the network can be that joining an upper left corner of the network with a lower right corner of the network (illustrated by 100a, 100d), also called the "main diagonal"; or that joining an upper right corner of the network with a lower right corner of the network (illustrated by 100b, 100c), also called the "anti-diagonal". Advantageously, according to the arrangement of the device of the invention, all the row-column intersections of the triangular matrix include an elementary switch that can be activated to route signals.

[0085] The inputs of the crossbar switch 100a, 100b, 100c, lOOd are located along a first dimension X of the row and column array. The outputs of the crossbar switch 100a, 100b, 100c, lOOd are located along a second dimension Y of the row and column array. In the figures illustrating the examples according to the invention, the first dimension X is the one along which the rows are positioned, and the second direction Y is the one along which the columns are positioned. In other words, the inputs are on the rows and the outputs are on the columns. However, the reverse is possible. Furthermore, in the figures, the inputs of the crossbar switch are located along a left side of the square array; and the outputs of the crossbar switch are located along a bottom side of the square array. However, the inputs and outputs could be positioned on other sides of the square array.The characteristics of other examples of the invention, in which, compared to the figures, the first dimension and the second dimension are different and / or the inputs and outputs are located on other sides of the network, can be easily deduced on the basis of the present description.

[0086] In a first architecture 100a illustrated in view a) of [Fig.5], the elementary switches form an upper triangular matrix along the main diagonal, with the inputs of the crossbar switch extending along the left side of the square network and the outputs of the crossbar switch extending along the lower side of the square network.

[0087] In a second architecture 100b illustrated in view b) of [Fig.5], the elementary switches form an upper triangular matrix along the antidiagonal, the inputs of the crossbar switch extending along a left side of the square network and the outputs of the crossbar switch extending along a lower side of the square network.

[0088] In a third architecture 100c illustrated in view c) of [Fig.5], the elementary switches form a lower triangular matrix along the antidiagonal, the inputs of the crossbar switch extending along one left side of the square network and the outputs of the crossbar switch extending along one lower side of the square network.

[0089] In a fourth architecture lOOd illustrated in view d) of [Fig.5], the elementary switches form a lower triangular matrix along the main diagonal, with the inputs of the crossbar switch extending along one left side of the square network and the outputs of the crossbar switch extending along one lower side of the square network.

[0090] In a connection between its inputs and outputs, the 100a, 100b, 100c, lOOd busbar switch uses only the elementary switches located at the row-column intersections of the network, forming a triangular matrix. The other intersections of the row and column network can then be devoid of elementary switches, which simplifies the implementation of the busbar switch. Furthermore, the reduction in the number of elementary switches compared to the prior art, and consequently the decrease in the number of communication links within the busbar switch, reduces its power consumption compared to the prior art.

[0091] In a first embodiment illustrated in Figures 6 to 17, the non-blocking nature of the crossbar switch is achieved by means of a switching device coupled to the switch 100. Depending on a given configuration of the connections to be made between the upstream and downstream signals of the crossbar switch, the switching device, generally denoted 600, allows the beam formation laws to be swapped. The swaps can be performed either upstream or downstream of the triangular matrix network. Thus, the switching device 600 makes it possible to adjust the routing requirements within the crossbar switch so as to use only elementary switches within a fixed triangular assembly, thereby reducing the required number of elementary switches.The arrangement of the elementary switches in a triangular matrix associated with the switching device ensures a non-blocking character of the crossed-bar switch according to the first embodiment, as well as the possibility for it to provide unicast and multicast connections.

[0092] In a first variant of the first embodiment illustrated in Figures 6 to 16, the switching device 600 includes DBF (Digital Beam Former) beam formers in the receive position. The DBF beam formers in the receive position are located upstream of the reconfigurable interconnect device, and therefore of the crossbar switch 100a, 100b, 100c, 100d. In a manner known in Each beamformer DBF1, DBF2, DBF3 produces one of the signals Rx-1, Rx-2, Rx-3 from the signals received from the elementary antennas of the receiving array, according to a beamforming law. The signals Rx-1, Rx-2, Rx-3 correspond to the radio frequency signals received in the beam directions defined by the beamforming laws Law No. 1, Law No. 2, Law No. 3, configured in the beamformers, which must then be transmitted by one or more transmitting antennas.

[0093] In this first variant of the first embodiment, the beamforming laws can be interchanged according to the configuration of the connections to be established between the signals upstream and downstream of the crossbar switch 100a, 100b, 100c, lOOd. Thus, routing of signals, particularly beams, through the crossbar switch 100a, 100b, 100c, lOOd can be achieved by activating the elementary switches in a configuration adapted to the constraints of the triangular arrangement of the elementary switches, and then interchanging the beamforming laws so as to modify the distribution of the Rx-1, Rx-2, Rx-3 signals between the inputs of the crossbar switch. According to this first variant, the receiving beamformers, which are also present in the telecommunications processor, are used as the interchange device.This allows for the optimization of switching resources in the telecommunications processor.

[0094] Figures 6 to 10 show examples of a method for configuring a processor according to the first variant of the first embodiment with the first architecture 100a. In particular, a first beamformer DBF1 is connected to a first input of the network of the crossbar switch 100a; a second beamformer DBF2 is connected to a second input of the network of the crossbar switch 100a; a third beamformer DBF3 is connected to a third input of the network of the crossbar switch 100a.

[0095] In a first example of the process illustrated in [Fig.6]:

[0096] - a first beam Rx-1 formed by a first formation law Law No. 1 must be routed to a second output of the 100a crossbar switch located on the second column;

[0097] - a second Rx-2 beam formed by a second formation law Law No. 2 must be routed to the third output located on the third column of the 100a crossbar switch;

[0098] - a third Rx-3 beam formed by a third law of formation Law No. 3 must be routed to a first output of the 100a crossbar switch located on the first column of the 100a crossbar switch.

[0099] In particular, initially and arbitrarily:

[0100] - the first law is assigned to the first beam former DBF1;

[0101] - the second law is assigned to the second beam former DBF2; and

[0102] - the third law is assigned to the third beam former DBF3.

[0103] In a first step, the method makes it possible to determine a set of (row, column) pairs that correspond to the routing requirements defined between the upstream and downstream signals of the interconnection device. In this step, all row-column intersections of the network 100 are considered. In other words, all network intersections are taken into account to identify the routing requirements for the bundles to be created, including network intersections that do not have an elementary switch.

[0104] Thus, in the example illustrated in [Fig.6]:

[0105] - the pair (1,2) designates a need for routing of the first Rx-1 beam to the second output of the 100a crossbar switch;

[0106] - the pair (2,3) designates a need for routing of the second Rx-2 beam to the third output of the 100a crossbar switch;

[0107] - the pair (3,1) designates a need for routing of the third Rx-3 beam to the first output of the 100a crossbar switch.

[0108] In a second step, the method determines the elementary switches to be activated, taking into account the constraints on the outputs. This step first involves organizing the (row, column) pairs into groups having the same rank along the first dimension X of the network, that is, along the dimension of the network along which the inputs are positioned. In particular, in the figures, the first dimension X is the one along which the input rows are positioned. Thus, the following row rank groups are identified:

[0109] - group 1 corresponding to row 1 rank: {(1,2)};

[0110] - group 2 corresponding to row 2 rank: {(2,3)};

[0111] - group 3 corresponding to row rank 3: {(3,1)}.

[0112] Then, in each group, the process makes it possible to determine a column rank extremum. The extremum rank is in particular an extreme rank, that is to say a minimum or maximum rank according to the 100a, 100b, 100c, lOOd architecture of the network.

[0113] In particular, for the crossbar switch according to the first architecture 100a, the extremum rank corresponds to the minimum rank. Thus, with reference to [Fig. 6], the minimum column rank for group 1 is column rank 2; the minimum column rank for group 2 is column rank 3; the minimum column rank for group 3 is column rank 1.

[0114] Then the row rank groups 1, 2, 3 are ordered according to their extremum column rank along the second dimension Y. In particular, for the crossed bar switch according to the first architecture 100a, the groups 1, 2, 3 are ordered in ascending order of minimum rank. Notably, with reference to [Fig. 6], the row rank groups 1, 2, 3 are ordered as follows {group 3, group 1, group 2], that is { { (3, 1)}, { (1, 2)}, { (2, 3)}}.

[0115] Next, for each row rank group 3, 1, 2, the process successively allocates a rank (allocated rank) along the first dimension X, starting with the rank following the first dimension X that forms a side of the triangular matrix. In [Fig. 6], the rank following the first dimension X that forms a side of the triangular matrix is ​​the row rank 1 located on the top side of the triangular matrix.

[0116] Thus, in general, for permutations upstream of the crossed bar switch, for the assembly type according to a 100a triangular matrix, the ranking of the first-dimensional rank groups X (row) is done in descending order of the extremum rank of the second dimension Y; the extremum rank of the second dimension Y (column) is minimal and the allocation of first-dimensional rank X (row) is increasing.

[0117] According to the same principles, a person skilled in the art may adapt the classifications for other types of assembly as follows:

[0118] For an assembly type according to a 100b triangular matrix, the ranking of first-dimensional rank groups X (row) is carried out in descending order of the extremum rank of the second dimension Y; the extremum rank of the second dimension Y (column) is maximal and the allocation of first-dimensional rank X (row) is then increasing.

[0119] For an assembly type according to a 100c triangular matrix, the ranking of first-dimensional rank groups X (row) is carried out in ascending order of the extremum rank of the second dimension Y; the extremum rank of the second dimension Y (column) is minimal and the allocation of first-dimensional rank X (row) is then decreasing.

[0120] For an assembly type according to a triangular matrix lOOd, the ranking of first-dimensional rank groups X (row) is carried out in descending order of the extremum rank of the second dimension Y; the extremum rank of the second dimension Y (column) is maximal and the allocation of first-dimensional rank X (row) is then decreasing.

[0121] In one embodiment, for the case of a 100a triangular matrix, a counter i of rank following the first dimension X is initialized to 1, then incremented progressively at each group allocation of rank 3, 1, 2. In particular, a first table stores the correspondences between the indices of the beamforming laws and the indices of the DBF beamformers. A second table stores the activation of the elementary switches for the set of connections to be established. Both tables are initialized empty at the beginning of the calculation of any new configuration of the interconnection device.

[0122] Thus, in [Fig. 6], for i=l, the first row of the switch is allocated to the rank 3 group, which is intended to route the third RX-3 beam. In parallel, the first table stores a correspondence between the third beamforming law and the beamformer connected to the first row, namely the first beamformer DBF1. The second switch activation table is updated for the rank 3 group by substituting i=l for the row rank 3: {(3,1)} becoming {(1,1)} is recorded in the second table.

[0123] For i=2, the second row of the switch is allocated to the rank 1 group, which is intended to route the first RX-1 beam. In parallel, the first table stores a correspondence between the first beamforming law and the beamformer connected to the second row, namely the second beamformer DBF2. The second switch activation table is updated for the rank 1 group by substituting i=2 for the row rank 1: {(1,2)} becoming {(2,2)} is recorded in the second table.

[0124] For i=3, the third row of the switch is allocated to the rank 2 group, which is intended to route the second RX-2 beam. In parallel, the first table stores a correspondence between the second beamforming law and the beamformer connected to the third row, namely the third beamformer DBF3. The second switch activation table is updated for the rank 2 group by substituting i=3 for the row rank 2: {(2,3)} becoming {(3,3)} is recorded in the second table.

[0125] In a third step, the method allows the signals, representing the beams Rx-1, Rx-2, Rx-3, to be permuted in accordance with the previous rank allocation. In particular, the correspondences between beam-forming laws and beam-formers stored in the first table are used to permute the beam-forming laws assigned to the beam-formers.

[0126] Thus, in [Fig.6], the first beamforming law Law No. 1 is assigned to the second beamformer DBF2; the second beamforming law Law No. 2 is assigned to the third beamformer DBF3; the third beamforming law Law No. 3 is assigned to the first beamformer DBF1.

[0127] In [Fig.6], following the previous steps, the elementary switches located at the intersections corresponding to the pairs (row, column) (1,1), (2,2), (3,3) were identified in the second activation table to implement the desired routing of the Rx-1, Rx-2, Rx-3 beams through the crossbar switch.

[0128] The elementary switches corresponding to the pairs (allocated rank, column) can then be activated, i.e. put in a conducting state, in order to route the beams Rx-1, Rx-2, Rx-3 to respectively the second output, the third output and the first output.

[0129] Figure 7 represents a second example of a method for configuring a processor according to the first variant of the first embodiment with the first architecture 100a. The second example of the method is identical to the first example illustrated in Figure 6, except for the routing of the beams to be obtained.

[0130] Thus, in the second example illustrated in [Fig.7]:

[0131] - the first Rx-1 beam formed by the first law of formation Law No. 1 must be routed to the third output of the 100a crossbar switch located on the third column;

[0132] - the second Rx-2 beam formed by the second law of formation Law No. 2 must be routed to the second output located on the second column of the 100a crossbar switch;

[0133] - the third Rx-3 beam formed by the third law of formation Law No. 3 must be routed to the first output of the 100a crossbar switch located on the first column of the 100a crossbar switch.

[0134] At the end of the first step, the set of (row, column) pairs that correspond to routing needs between upstream and downstream signals of the switch, considering all row-column intersections of the network, is determined as follows:

[0135] - the pair (1,3) designates a need for routing of the first Rx-1 beam to the third output of the 100a crossbar switch;

[0136] - the pair (2,2) designates a need for routing of the second Rx-2 beam to the second output of the 100a crossbar switch;

[0137] - the pair (3,1) designates a need for routing of the third Rx-3 beam to the first output of the 100a crossbar switch.

[0138] In the second step, the process allows the pairs (row, column) having the same rank along the first dimension X of the network to be organized into groups of rank X or row rank, and for the example of [Fig.7] as follows:

[0139] - group 1 corresponding to row 1 rank: {(1,3)};

[0140] - group 2 corresponding to row 2 rank: {(2,2)};

[0141] - group 3 corresponding to row rank 3: {(3,1)}.

[0142] Then, in each group, the process allows the next minimum rank to be second dimension Y is identified, and for the example as follows: the minimum rank for group 1 is the rank of column 3; the minimum rank for group 2 is the rank of column 2; the minimum rank for group 3 is the rank of column 1.

[0143] Then in the next step, the groups of rank 1, 2, 3 are ordered in ascending order of minimum column rank, and for the example of [Fig.7] as follows: {group 3, group 2, group 1}, that is { { (3, 1)}, { (2, 2)}, { (1, 3)}}.

[0144] Then, at each row rank group 3, 2, 1 the process allows successive allocation of a rank along the first dimension X, starting with the rank along the first dimension X forming a side of the triangular matrix.

[0145] In particular, in [Fig. 7], for i=l, the first row of the switch is allocated to group 3, which is intended to route the third RX-3 beam. In parallel, the first table stores a correspondence between the third beamforming law and the beamformer connected to the first row, namely the first beamformer DBF1. The second switch activation table is updated for group rank 3 by substituting i=l for row rank 3: {(3,1)} becoming {(1,1)} is recorded in the second table.

[0146] For i=2, the second row of the switch is allocated to group 2, which is intended to route the second RX-2 beam. In parallel, the first table stores a correspondence between the second beamforming law and the beamformer connected to the second row, namely the second beamformer DBF2. The second switch activation table is updated for group rank 2 by substituting i=2 for row rank 2: {(2,2)} becoming {(2,2)} is recorded in the second table.

[0147] For i=3, the third row of the switch is allocated to group 1, which is intended to route the first RX-1 beam. In parallel, the first table stores a correspondence between the first beamforming law and the beamformer connected to the third row, namely the third beamformer DBF3. The second switch activation table is updated for group rank 3 by substituting i=3 for row rank 1: {(1,3)} becoming {(3,3)} is recorded in the second table.

[0148] In the third step, the beams Rx-1, Rx-2, Rx-3 are swapped in accordance with the previous rank allocation. Thus, in [Fig. 7], the first beam-forming law is assigned to the third beam-former DBF3; the second beam-forming law remains assigned to the second beam-former DBF2; the third beam-forming law is assigned to the first beam-former DBF1.

[0149] Following the previous steps, the elementary switches located at the intersections corresponding to the pairs (row, column) (1,1), (2,2), (3,3) were identified in the second activation table to implement the desired routing of the Rx-1, Rx-2, Rx-3 beams through the crossbar switch.

[0150] Figure 8 illustrates a third example of a method for configuring a processor according to the first variant of the first embodiment with the first architecture 100a. The third example of the method is identical to the first example illustrated in Figure 6, except for the routing of the beams to be obtained.

[0151] Thus, in the third example illustrated in [Fig.8]:

[0152] - the first Rx-1 beam formed by the first law of formation Law No. 1 must be routed to the third output of the 100a crossbar switch located on the third column;

[0153] - the second Rx-2 beam formed by the second law of formation Law No. 2 must be routed to the first output located on the first column of the 100a crossbar switch;

[0154] - the third Rx-3 beam formed by the third law of formation Law No. 3 must be routed to the second output of the 100a crossbar switch located on the second column of the 100a crossbar switch.

[0155] At the end of the first step, the set of (row, column) pairs that correspond to the routing requirement between the upstream and downstream signals of the switch, considering all the row-column intersections of the network, is obtained and for the example of [Fig.8] is as follows:

[0156] - the pair (1,3) denoting a need for routing of the first Rx-1 beam to the third output of the 100a crossbar switch;

[0157] - the pair (2,1) denoting a need for routing of the second Rx-2 beam to the first output of the 100a crossbar switch;

[0158] - the pair (3,2) denoting a need for routing of the third Rx-3 beam to the second output of the 100a crossbar switch.

[0159] In the second step, the pairs (row, column) having the same rank according to the first dimension X of the network are grouped as follows:

[0160] - group 1 corresponding to row 1 rank: {(1,3)};

[0161] - group 2 corresponding to row rank 2: {(2,1)};

[0162] - group 3 corresponding to row rank 3: {(3,2)}.

[0163] Then, in each group, the minimum rank along the second dimension Y is identified as follows: the minimum rank for group 1 is the column rank 3; the minimum rank for group 2 is the column rank 1; the minimum rank for group 3 is the column rank 2.

[0164] Then groups 1, 2, 3 are ordered in ascending order of minimum column rank, as follows: {group 2, group 3, group 1}, that is { {(2,1)}, {(3,2)}, {(1,3)}}•

[0165] Then, to each group 2, 3, 1 is successively allocated a rank along the first dimension X, starting with the rank along the first dimension X forming a side of the triangular matrix.

[0166] In particular, in [Fig. 8], for i=l, the first row of the switch is allocated to group 2, which is intended to route the second RX-2 beam. In parallel, the first table stores a correspondence between the second beam-forming law and the beamformer connected to the first row, namely the first beamformer DBF1. The second switch activation table is updated for rank group 2 by substituting i=l for row rank 2: {(2,1)} becoming {(1,1)} is recorded in the second table.

[0167] For i=2, the second row of the switch is allocated to group 3, which is intended to route the third RX-3 beam. In parallel, the first table stores a correspondence between the third beamforming law and the beamformer connected to the second row, namely the second beamformer DBF2. The second switch activation table is updated for group rank 3 by substituting i=2 for row rank 3: {(3,2)} becomes {(2,2)} and is recorded in the second table.

[0168] For i=3, the third row of the switch is allocated to group 1, which is intended to route the first RX-1 beam. In parallel, the first table stores a correspondence between the first beamforming law and the beamformer connected to the third row, namely the third beamformer DBF3. The second switch activation table is updated for group rank 1 by substituting i=3 for row rank 1: {(1,3)} becoming {(3,3)} is recorded in the second table.

[0169] In the third step, the beam formation laws Rx-1, Rx-2, Rx-3 are permuted in accordance with the previous rank allocation. Thus, in [Fig. 8], the first beam formation law is assigned to the third beam former DBF3; the second beam formation law is assigned to the first beam former DBF1; the third beam formation law is assigned to the second beam former DBF2.

[0170] Following the previous steps, the elementary switches located at the intersections corresponding to the pairs of lines (1,1), (2,2), (3,3) were identified in the second activation table to implement the desired routing of the Rx-1, Rx-2, Rx-3 bundles through the crossbar switch.

[0171] Figure 9 represents a fourth example of a method for configuring a processor according to the first variant of the first embodiment with the first architecture 100a. The fourth example of the method is identical to the first example illustrated in Figure 6, except for the routing of the beams to be obtained.

[0172] Thus, in the fourth example illustrated in [Fig.9]:

[0173] - the first Rx-1 beam formed by the first law of formation Law No. 1 must be routed to the second output of the 100a crossbar switch located on the second column of the 100a crossbar switch;

[0174] - the second Rx-2 beam formed by the second law of formation Law No. 2 must be routed to the first output located on the first column of the busbar switch crossed 100a and to the third output of the 100a crossed busbar switch located on the third column;

[0175] At the end of the first step, the set of (row, column) pairs that correspond to routing needs between upstream and downstream signals of the switch, considering all row-column intersections of the network, is as follows:

[0176] - the pair (1,2) denoting a need for routing of the first Rx-1 beam to the second output of the 100a crossbar switch;

[0177] - the pair (2,1) denoting a need for routing of the second Rx-2 beam to the first output of the 100a crossbar switch;

[0178] - the pair (2,3) denoting a need for routing of the second Rx-2 beam to the third output of the 100a crossbar switch.

[0179] In the second step, the row and column pairs having the same rank along the first dimension X of the network are grouped as follows:

[0180] - group 1 corresponding to row 1 rank: { (1,2)};

[0181] - group 2 corresponding to row rank 2: { (2,1), (2,3)}.

[0182] Then, in each group, the minimum rank along the second dimension Y is identified as follows: the minimum rank for group 1 is the column rank 2; the minimum rank for group 2 is the column rank 1.

[0183] Then groups 1, 2 are ordered in ascending order of minimum rank, as follows: {group 2, group 1], that is { { (2,1), (2,3)}, {(1,2)}}.

[0184] Then, to each group 1, 2 is successively allocated a rank along the first dimension X, starting with the rank along the first dimension X forming a side of the triangular matrix.

[0185] In particular, in [Fig. 9], for i=l, the first row is allocated to group 2, which is intended to route the second RX-2 beam. In parallel, the first table stores a correspondence between the second beamforming law and the beamformer connected to the first row, namely the first beamformer DBF1. The second switch activation table is updated for group rank 2 by substituting i=l for row rank 2: {(2,1), (2,3)} becomes {(1,1), (1,3)} and is stored in the second table.

[0186] For i=2, the second row is allocated to group 1, which is intended to route the first RX-1 beam. In parallel, the first table stores a correspondence between the first beamforming law and the beamformer connected to the second row, namely the second beamformer DBF2. The second switch activation table is updated for group rank 1 by substituting i=2 for row rank 1: {(1,2)} becoming {(2,2)} is recorded in the second table.

[0187] In the third step, the beams Rx-1, Rx-2 are interchanged in accordance with the previous rank allocation. Thus, in [Fig.9], the first beam-forming law is assigned to the second beam-former DBF2; and the second beam-forming law is assigned to the first beam-former DBF1.

[0188] Following the previous steps, the elementary switches located at the intersections corresponding to the pairs (row, column) (1,1), (1,3), (2,2) were identified in the second activation table to implement the desired routing of the Rx-1, Rx-2 beams through the crossbar switch.

[0189] Figure 10 represents a fifth example of a method for configuring a processor according to the first variant of the first embodiment with the first architecture 100a. The fifth example method is identical to the first example shown in Figure 6, except for the routing of the beams to be obtained. Thus, in the fifth example shown in Figure 10, the third beam Rx-3 formed by the third law must be routed to the first, second, and third outputs of the crossbar switch 100a.

[0190] At the end of the first step, the set of (row, column) pairs that correspond to routing needs between upstream and downstream signals of the switch, considering all row-column intersections of the network, is as follows:

[0191] - the pair (3,1) denoting a need for routing of the third Rx-3 beam to the first output of the 100a crossbar switch;

[0192] - the pair (3,2) denoting a need for routing of the third Rx-3 beam to the second output of the 100a crossbar switch;

[0193] - the pair (3,3) denoting a need for routing of the third Rx-3 beam to the third output of the 100a crossbar switch.

[0194] In the second step, the pairs (row, column) having the same rank according to the first dimension X of the network are grouped as follows: group 3 corresponding to the rank of row 3: {(3,1), (3,2), (3,3)}.

[0195] Then, for i=l, the first row is allocated to group 3, which is intended to route the third RX-3 beam. In parallel, the first table stores a correspondence between the third beamforming law and the beamformer connected to the first row, namely the first beamformer DBF1. The second switch activation table is updated for group rank 3 by substituting i=l for row rank 3: {(3,1), (3,2), (3,3)} becoming {(1,1), (1,2), (1,3)} is stored in the second table. In the third step, in [Fig. 10], the third beamforming law is assigned to the first beamformer DBF1.

[0196] Following the previous steps, the elementary switches located at the intersections corresponding to the (row, column) pairs (1,1), (1,2), (1,3) were identified in the second activation table to implement the desired routing of the Rx-3 beam through the crossbar switch.

[0197] As illustrated in Figures 6 to 10, the reconfiguration method according to the invention thus makes it possible to obtain a unicast or multicast connection in a processor according to the first variant of the first embodiment with the first architecture 100a. The other architectures 100b, 100c, lOOd, similarly make it possible to obtain unicast or multicast connections, as explained below in relation to Figures 11 to 16.

[0198] In particular, in the first variant of the first embodiment, the permutation of the beam formation laws is a function of the initial distribution of the formation laws between the beam formers DBF1, DBF2, DBF3.

[0199] Figures 11 and 12 show examples of a processor configuration method according to the first variant of the first embodiment with the third architecture 100c. In the first variant of the first embodiment with the third architecture 100c, the configuration method is identical to that for the first variant of the first embodiment with the first architecture 100a, except that the row allocation order per group is carried out in descending order from the last row forming a side of the triangular matrix.

[0200] In particular, in a sixth method example illustrated in [Fig. 11], according to this first variant of the first embodiment with the third architecture 100c, the routing to be obtained is identical to that in the third example illustrated in [Fig. 8], as is the initial distribution of the beamforming laws in the beamformers. However, the elementary switches to be activated are not the same because the architectures 100a and 100c are different. Thus, in [Fig. 11], the elementary switches located at the intersections corresponding to the (row, column) pairs (1,3), (2,2), and (3,1) are identified to implement the desired routing of the beams Rx-1, Rx-2, and Rx-3 through the crossbar switch.The first beamforming law remains assigned to the first beamformer DBF1; the second beamforming law is assigned to the third beamformer DBF3; the third beamforming law is assigned to the second beamformer DBF2.

[0201] In a seventh method example illustrated in [Fig. 12], according to this first variant of the first embodiment with the third architecture 100c, the routing to be obtained is identical to that of the fifth example illustrated in [Fig. 10]; as is the initial distribution of the beamforming laws in the beamformers. However, the elementary switches to be activated are not the same because the architectures 100a and 100c are different. Thus, in [Fig. 12], the elementary switches located at the intersections corresponding to the (row, column) pairs (3,1), (3,2) and (3,3) are identified to implement the desired routing of the Rx-3 beam through the crossbar switch. The third beamforming law remains assigned to the third beamformer, DBF3.

[0202] Figures 13 and 14 show examples of a processor configuration method according to the first variant of the first embodiment with the second architecture 100b. In the first variant of the first embodiment with the second architecture 100b, the configuration method is identical to that for the first variant of the first embodiment with the first architecture 100a, except that the determination of an extremum rank along the second dimension Y in each group of pairs corresponds to the determination, in each group, of the maximum rank along the second dimension Y; and the ordering of the groups of pairs is carried out in descending order of the maximum rank along the second dimension Y.

[0203] In particular, in an eighth method example illustrated in [Fig. 13], according to this first variant of the first embodiment with the second architecture 100b, the routing to be obtained is identical to that in the third example illustrated in [Fig. 8]; as is the initial distribution of the beamforming laws in the beamformers. Furthermore, the steps for determining the (row, column) pairs corresponding to paths between the inputs and outputs, and the organization of the (row, column) pairs into rank groups having the same rank along the first dimension X, are identical.

[0204] In the eighth example of a method, the steps for determining an extremum rank along the second dimension Y and for ordering the groups of pairs are different as follows. In each group, the maximum rank along the second dimension Y is identified as follows: the maximum rank for group 1 is the rank in column 3; the maximum rank for group 2 is the rank in column 1; the maximum rank for group 3 is the rank in column 2. Then groups 1, 2, 3 are ordered in descending order of maximum rank, as follows: { group 1, group 3, group 2}, that is { {(1,3)}, {(3,2)}, {(2,1)}}.

[0205] Next, the step of successively allocating to each group a rank along the first dimension X remains identical to that of the third example illustrated in [Fig.8]. To each group 1, 3, 2 is successively allocated a rank along the first dimension X, starting with the rank along the first dimension X forming a side of the triangular matrix.

[0206] In particular, in [Fig. 13], for i=l, the first row is allocated to group 1 which is intended to route the first RX-1 beam. In parallel, the first table stores a correspondence between the first beam formation law and the beam shaper connected to the first row, namely the first beam shaper DBF1. The second switch activation table is updated for rank 1 group by substituting i=l for row rank 1: {(1,3}} remaining {(1,3)} is recorded in the second table.

[0207] For i=2, the second row is allocated to group 3, which is intended to route the third RX-3 beam. In parallel, the first table stores a correspondence between the third beamforming law and the beamformer connected to the second row, namely the second beamformer DBF2. The second switch activation table is updated for group rank 3 by substituting i=2 for row rank 3: {(3,2)} becoming {(2,2)} is recorded in the second table.

[0208] For i=3, the third row is allocated to group 2, which is intended to route the second RX-2 beam. In parallel, the first table stores a correspondence between the second beamforming law and the beamformer connected to the third row, namely the third beamformer DBF3. The second switch activation table is updated for group rank 2 by substituting i=3 for row rank 2: {(2,1)} becoming {(3,1)} is recorded in the second table.

[0209] In the third step, the beams Rx-1, Rx-2, Rx-3 are swapped in accordance with the previous rank allocation. Thus, in [Fig. 13], the first beam-forming law remains in the first beam-former DBF1; the second beam-forming law is assigned to the third beam-former DBF3; the third beam-forming law is assigned to the second beam-former DBF2.

[0210] Following the previous steps, the elementary switches located at the intersections corresponding to the pairs (row, column) (1,3), (2,2), (3,1) were identified in the second activation table to implement the desired routing of the Rx-1, Rx-2, Rx-3 beams through the crossbar switch.

[0211] A ninth method example according to the first variant of the first embodiment with the second architecture 100b is illustrated in [Fig. 14]. The ninth method example is identical to the eighth method example, except that the routing of the beams to be obtained is identical to that of the fifth example illustrated in [Fig. 10]. By applying the same steps as in the eighth method example, the elementary switches located at the intersections corresponding to the (row, column) pairs (1,1), (1,2), (1,3) are identified to implement the desired routing of the Rx-1, Rx-2, Rx-3 beams through the crossed bar switch. The third beamforming law is assigned to the first beamformer DBF1.

[0212] Figures 15 and 16 show examples of a method for configuring a processor according to the first variant of the first embodiment with the fourth lOOd architecture. In the first variant of the first embodiment with the fourth architecture lOOd, the configuration process is identical to that for the first variant of the first embodiment with the second architecture 100b, except that the allocation order of rows per group is carried out in descending order from the last row forming a side of the triangular matrix.

[0213] In particular, in a tenth method example illustrated in [Fig. 15], according to this first variant of the first embodiment with the fourth lOOd architecture, the routing to be obtained is identical to that in the third example illustrated in [Fig. 8]; as is the initial distribution of the beamforming laws in the beamformers. In this particular case, the elementary switches to be activated are the same. Thus, in [Fig. 15], the elementary switches located at the intersections corresponding to the (row, column) pairs (1,1), (2,2), (3,3) are identified to implement the desired routing of the Rx-1, Rx-2, Rx-3 beams through the crossed bar switch.Furthermore, the first beamforming law is assigned to the third beamformer DBF3; the second beamforming law is assigned to the first beamformer DBF1; the third beamforming law is assigned to the second beamformer DBF2.

[0214] In an eleventh method example illustrated in [Fig. 16], according to this first variant of the first embodiment with the fourth lOOd architecture, the routing to be obtained is identical to that of the fifth example illustrated in [Fig. 10]. However, the elementary switches to be activated are not the same because the 100a and lOOd architectures are different. Thus, in [Fig. 16], the elementary switches located at the row-column intersections corresponding to the (row, column) pairs (3,1), (3,2), (3,3) are identified to implement the desired routing of the Rx-3 beam through the crossbar switch. The third beamforming law remains assigned to the third beamformer DBF3.

[0215] In a second variant of the first embodiment, illustrated in [Fig. 17], the switching device comprises a switch 150 connected upstream of the crossbar switch 100a. The switch 150 is configured to optionally switch the signals from the receiving antenna(s) upstream of the inputs of the crossbar switch, depending on the connection configuration between the inputs and outputs of the crossbar switch.

[0216] In particular, the switch 150 includes inputs for receiving signals from the receiving antenna(s), and outputs that are connected to the inputs of the crossbar switch 100a (or 100b, 100c, or 100d). The switch 150 performs a permutation of the signals upstream of the inputs of the crossbar switch corresponding to the rank allocation step.

[0217] The 150 switch can be made using microelectromechanical systems or MEMS technology.

[0218] The 150 switch can, for example, be an optical unicast switch implementing a square array of the same dimensions as the crossbar switch (100a, 100b, 100c, or 100d). The 150 optical switch can then include a mirror array, which notably allows for negligible power dissipation. In particular, high-speed serial links over optical fiber can be used to propagate digital signals with high data rates and good power efficiency. Such links overcome limitations in the path lengths between the electronic units of the telecommunications processor, such as circuit boards or other equipment that may be embedded in a satellite.

[0219] The second variant of the first embodiment is advantageous when the telecommunications processor, which includes the reconfigurable interconnect device, is devoid of beamformers to perform upstream or downstream permutations of the reconfigurable interconnect device.

[0220] The configuration method for the reconfigurable interconnect device according to the second variant of the first embodiment is identical to that according to the first variant of the first embodiment, except that the signal switching is no longer achieved by switching the beamforming laws. In the second variant, the signal switching at the inputs of the crossbar switch (100a or 100b or 100c or lOOd) is achieved by changing the connection between the inputs and outputs of the switch 150. In particular, the configuration method varies with the 100a, 100b, 100c, lOOd architecture as described above. The configuration method makes it possible to obtain a unicast or multicast connection in the device according to the second variant of the first embodiment, in particular with one of the 100a, 100b, 100c, or lOOd architectures, illustrated in [Fig. 5].

[0221] In the first variant and the second variant of the first embodiment, the elementary switches are preferably 1X1 or 2X1 switches.

[0222] In a third variant of the first embodiment illustrated in Figures 25b and 26, the switching device includes transmitting DBF (Digital Beam Former) beamformers. The transmitting DBF beamformers are located downstream of the reconfigurable interconnect device, and therefore of the crossbar switch 100a, 100b, 100c, 100d. In a manner known per se, each beamformer DBF1, DBF2, DBF3 receives as input one of the signals Tx-1, Tx-2, Tx-3 and produces as output excitation signals for elementary antennas of the transmitting array antenna, according to a beamforming law. beam. The signals Tx-1, Tx-2, Tx-3 correspond to the radio frequency signals to be transmitted in beam directions defined by the training laws Law No. 1, Law No. 2, Law No. 3, configured in the formators, which must then be radiated by the transmitting antennas. For example, in [Fig. 26], the signal Tx-3 is routed and radiated on the TxBeam-1 beam corresponding to Law No. 1

[0223] In this third variant of the first embodiment, the beamforming laws can be interchanged and combined according to the configuration of the connections to be established between the inputs and outputs of the crossbar switch 100a, 100b, 100c, lOOd. Thus, routing of signals, in particular beams, through the crossbar switch 100a, 100b, 100c, lOOd can be achieved by activating the elementary switches according to a configuration adapted to the constraints of the triangular arrangement of the elementary switches, and then interchanging and possibly combining the beamforming laws so as to modify the distribution of the Tx-1, Tx-2, Tx-3 signals between the outputs of the crossbar switch. For example, in [Fig.

[26] , Law No. 1 for forming the TxBeam, initially and arbitrarily associated with the DBF1 formatter, is allocated by permutation to the DBF3 formatter; the output signals of the formatters, downstream of the crossed bar switch, are thus permuted due to the permutation of the laws on the formatters. According to this first variant, the transmitting beamformers, also present in the telecommunications processor, are used as a permutation device. This optimizes the switching resources in the telecommunications processor.

[0224] Figures 18 and 19 illustrate a second embodiment where the non-blocking character of the crossed bar switch is obtained by means of an elementary type of switch and a chaining of the particular architecture of the switch signals on the diagonal.

[0225] In this embodiment, the elementary switches are 2x2 switches. A 2x2 switch is illustrated, for example, in [Fig. 19]. The 2x2 switch referenced C22 makes two independent connections, between the two inputs and each output. Thus, it selectively makes a connection between, on the one hand, a first input EL along the first dimension X or a second input EC along the second dimension Y, and on the other hand, a first output SL along the first dimension X or a second output SC along the second dimension Y.

[0226] In particular, the first EL input is on a row; the second EC input is on a column; the first SL output is on a row; and the second SC output is on a column. However, the roles of the rows and columns could be reversed, depending on the choice of the first X dimension and the second Y dimension. The choice of the connection between the first EL input or the second Input EC, and the first output SL or the second output SC, can be configured using two 2:1 multiplexing functions. Selection can be achieved using independent controls that allow all combinations of input EC, EL, and output SC, SL. For example, a signal at one input can be simultaneously transmitted to the first output SL and the second output SC. By positioning themselves at row-column intersections of the triangular network of the crossbar switch, the 2x2 C22 switches can propagate a signal hop-by-hop along either rows or columns.

[0227] The 2x2 C22 switches form a lower triangular matrix along the main diagonal. In other words, the 2x2 C22 switches are arranged according to the fourth lOOd architecture illustrated in [Fig. 5]. However, the other arrangements 100a, 100b or 100c are also possible, with appropriate wiring.

[0228] An example of a method for configuring a processor according to the second embodiment is now described. The method seeks to perform the following routing:

[0229] - a first signal must be routed to a second output of the bar switch crossed lOOd located on the second column;

[0230] - a second signal must be routed to the third output located on the third crossbar switch column lOOd;

[0231] - a third signal must be routed to a first output of the bar switch crossed lOOd located on the first.

[0232] Initially:

[0233] - the first signal is delivered to a first input of the crossbar switch lOOd located on the first line;

[0234] - the second signal is delivered to a second input of the bar switch crossed lOOd located on the second line;

[0235] - the third signal is delivered to a third input of the bar switch crossed lOOd located on the third line.

[0236] This example of a method includes a first step of determining the (row, column) pairs that correspond to the routing requirements to be established between the inputs and outputs, which is identical to that described in relation to the first embodiment. Thus, in this example, the (row, column) pairs identified are the following: (1, 2), (2, 3), (3, 1).

[0237] The second step of determining the elementary switches to be activated is different. In particular, each pair of rows and columns corresponds to a set of 2X2 C22 switches to be activated.

[0238] If the row-column intersection corresponding to the pair (row, column) is located outside the triangular matrix, as is the case for pairs (1,2), (2,3), the following steps are carried out.

[0239] The 2X2 C22 switches located on the same row following the first dimension X as the pair's row (row, column) are configured so that the first input EL is connected with the first output SL. In particular, for the pair (1,2), the 2X2 C22 switch located on row 1 is activated, so that its first input EL is connected with its first output SL.

[0240] The 2X2 C22 switches located on the main diagonal between the row position following the first dimension X and the row position following the second dimension Y are configured to connect their second input EC with their first output SL. In particular, for the pair (1,2), there is no 2X2 C22 switch located on the main diagonal between row position 1 and column position 2. We then proceed to the next step.

[0241] The 2X2 C22 switches located on the same row along the second dimension Y as the column of the pair (row, column) are configured to connect their second input EC with their second output SC. Specifically, for the pair (1,2), the 2X2 C22 switches located on the row of column 2 are activated so that their second input EC is connected with their second output SC. Thus, the signal delivered at the first input is propagated to the second output.

[0242] The 2X2 C22 switches to be activated for pair (2,3) are determined similarly. The 2X2 C22 switches located in row 2 are activated so that their first input EL is connected to their first output SL. For pair (2,3), there is no 2X2 C22 switch located on the main diagonal between row 2 and column 3. The 2X2 C22 switches located in column 3 are activated so that their second input EC is connected to their second output SC.

[0243] Thus, the signal delivered on the second input is propagated to the third output.

[0244] If the intersection corresponding to the pair (row, column) is located in the triangular matrix, as is the case for the pair (3, 1), the following steps are carried out.

[0245] The 2X2 C22 switches located on the same row along the first dimension X as the row of the pair (row, column), and having a row along the second dimension Y lower than that of the row and column pair, are configured to connect their first input EL with their first output SL. In particular, for the pair (3,1), there is no 2X2 C22 switch located on the row rank 3, and having a column rank less than 1.

[0246] The 2X2 C22 switch located at the intersection corresponding to the row and column pair is configured to connect its first EL input with its second Sc output. In particular, for the pair (3, 1), the 2X2 C22 switch located at the intersection of row 3 and column 1 is activated, so that its first EL input is connected with its second Sc output.

[0247] The 2X2 C22 switches located on the same row along the second dimension Y as the column of the pair (row, column), and having a row along the first dimension X greater than that of the pair, are configured to connect their second input EC with their second output SC. In particular, for the pair (3,1), there is no 2X2 C22 switch located on the column row 1, and having a row row greater than 3.

[0248] Thus, the signal delivered at the third input is propagated to the first output.

[0249] The arrangement of the 2X2 C22 switches in the second embodiment ensures that the crossbar switch is non-blocking for unicast and multicast connections. The second embodiment is particularly advantageous when the telecommunications processor, which includes the reconfigurable interconnect device, lacks beamformers in the receive direction upstream of the reconfigurable interconnect device.

[0250] In particular, in the processor examples according to the invention, the implementation of the switches is primarily determined by the interfaces that perform signal transmission between the integrated circuits implementing the elementary switches. The second embodiment makes it possible to reduce the number of interface links within the crossbar switch, which leads to a reduction in power dissipation.

[0251] In the telecommunications processor examples, the reconfigurable interconnect device may be formed from the 100a, 100b, 100c or lOOd crossbar switch. Alternatively, the reconfigurable interconnect device may include other components.

[0252] In particular, in a third embodiment, the reconfigurable interconnect device is a known Clos network, with the 100a, 100b, 100c, 100d crossover switch forming a central stage of the Clos network. The Clos network forms a multi-stage architecture, including in particular an odd number of stages, greater than or equal to three. By routing signals across different stages, efficiency in terms of hardware resources and dissipation is improved compared to using a single stage comprising a crossover switch. The third embodiment is compatible with the first and second embodiments.

[0253] An example of a Clos 200 network in which all stages are implemented by crossover switch modules is shown in [Fig. 20]. The Clos 200 network comprises three stages, but it could comprise another odd number of stages. In particular, each stage takes the form of a column of modules of crossbar switches. In particular, each crossbar switch module on a floor is connected to each crossbar switch module on the floor above and to each module on the floor below.

[0254] In particular, the Clos 200 network comprises an input stage with r crossbar switch modules of dimensions n x m. A central stage comprises m crossbar switch modules of dimensions r x r. Each module of the central stage corresponds to the crossbar switch 100a, 100b, 100c, 100d forming a triangular matrix, described in relation to the preceding embodiments. An output stage comprises r crossbar switch modules of dimensions m x n. The Clos 200 network as a whole forms a square network of dimensions (rn) x (rn).

[0255] In particular, the non-blocking nature of the Clos 200 network depends on the number m of modules in the central stage. Thus, the network is strictly non-blocking if

[0256] m > II; + n0 -1

[0257] where neither is the number of inputs of a crossbar switch module of the input stage, and nO is the number of outputs of a crossbar switch module of the output stage.

[0258] The Clos network is non-blocking provided that previous connections are rearranged if

[0259] [Math 2] m > max(n? n0)-

[0260] In another example of a Clos 300 network illustrated in [Fig. 21], the input and output stages can be implemented with modules using time-division multiplexing. The central stage is implemented by a single spatial module connected to each module of the input and output stages. Routing operations in the input and output stages are performed in time-division (T), while routing operations in the central stage are performed in space-division (S). The Clos network is then said to be of the TST type (for "time-spatial-time"). Thanks to time-division multiplexing, the TST-type Clos 300 network performs, with a single module in the central stage, the routing operations for the m instances of modules in the central stage of the spatial-type Clos 200 network.For this purpose, preferably, the operating frequency of the central stage module is accelerated m times compared to that of the space-type Clos 200 array.

[0261] In particular, the input stage comprises several time-routing modules Ts, each having its output connected to an input of the crossover switch 100a, 100b, 100c, lOOd. Specifically, each time-routing module Ts comprises n inputs, a memory, and an output transmitting a frame. Each time slot in the frame corresponds to an input-output signal in the Clos 200 network. spatial type. The frame includes at least m time slices. In particular, signal routing is performed by writing the values ​​of the n input signals into memory in a first order, then reading the output from memory in a second order that defines the routing configuration, to produce the output frame. In particular, the output stage operates in a dual manner to the input stage.

[0262] Preferably, the signals are transmitted between the Ts modules of the input or output stage and the module of the central stage via high-speed serial links. In particular, such links are suitable for very high time frame rates with good energy efficiency. The links can be electrical links, for example coaxial cables, or optical links, for example optical fibers.

[0263] Thanks to the TST type Clos network, the reconfigurable interconnection device requires fewer module instances, interface links, and is therefore simpler to implement; notably through an acceleration of routing processing in the telecommunications processor and an increase in throughput on the interfaces.

[0264] Fig. 22 illustrates an example of a telecommunications processor 400 comprising a switching device formed by beam formers in receive, as described previously in relation to the first variant of the first embodiment, and a reconfigurable interconnecting device forming a Clos TST network.

[0265] The DBF beamformers are associated in groups with respective time-division routing modules Ts of the input stage. The example processor 400 may include Dx demultiplexers configured to decompose the signals from the receiving antenna(s) into their elementary frequency components. The frequency components produced by the Dx demultiplexers can then be processed by the DBF beamformers. The time-division modules Ts of the output stage may be associated in groups with Mx multiplexers that recombine the signals intended to be transmitted by the transmitting antenna(s).

[0266] Preferably, DBF beamformers are located downstream of filter banks that perform spectral decomposition of the signals from the receiving antenna(s). In particular, for digital beamformers, spectral decomposition of the useful bandwidth, notably into elementary bands, is performed for all signals from the receiving antenna(s). Each digital beamformer processes the useful elementary bands to form a beam in a direction specific to each elementary band. A digital beamformer can produce beams in different directions for different sub-bands by time-division multiplexing. For any routing needs of the signals, it is then possible to find a permutation of the beam formation laws for the sub-bands and directions, especially in association with a suitable configuration of the Ts modules of the input stage.

[0267] Figure 23 illustrates an example of a telecommunications processor 500 comprising a switching device consisting of a switch 150, as described previously in relation to the second variant of the first embodiment, and a reconfigurable interconnect device 100a forming a Clos TST network. The switch 150 is connected between the input stage and the central stage of the Clos network, so as to allow signal switching upstream of the inputs to the central stage. The telecommunications processor 500 is notably devoid of DBF beamformers in the receive stage. The example processor 500 may include Dx demultiplexers configured to decompose the signals from the receiving antenna(s) into their frequency components by elementary bands. The Dx demultiplexers are associated in groups with respective time-series routing modules Ts of the input stage.The time-division routing modules (Ts) of the output stage can be grouped with multiplexers (Mx) that reassemble the signals intended for transmission by the transmitting antenna(s). In this example, with switch 150 acting as a switching device, the switching is performed transparently downstream of the input stage Ts modules. This is also the case if the Clos network is spatial.

[0268] Figure 24 illustrates an example of a telecommunications processor 700 according to the second embodiment as described above, the reconfigurable interconnect device lOOd forming a Clos TST network. The telecommunications processor 700 is notably devoid of DBF beamformers in the receive stage. The example processor 700 may include Dx demultiplexers configured to decompose the signals from the antenna(s) into their elementary frequency components. The Dx demultiplexers are notably associated in groups with respective time modules Ts of the input stage. The time modules Ts of the output stage may be associated in groups with Mx multiplexers that shape the signals intended to be transmitted by the transmitting antenna(s).

[0269] In the case of a rectangular matrix network with a number of rows N greater than the number of columns P, N > P, the arrangement of the matrix network takes the form of a set of square matrix sub-networks implementing triangular assemblies of the elementary switches, possibly supplemented by a full or partial rectangular matrix network. Permutations can then be performed upstream or downstream of the matrix network.

[0270] Fig. 25a illustrates a general case of upstream permutations of the matrix network according to the invention, in the case N>P.

[0271] The optional rectangular matrix subnetwork enables unicast and multicast connections on input signals without upstream and downstream permutations. Its configuration is that of a full crossover switch.

[0272] In the case of a rectangular matrix network with a number of rows N less than the number of columns P, N < P, the arrangement of the matrix network takes the form of a set of square matrix sub-networks implementing triangular assemblies of the elementary switches, possibly supplemented by a full or partial rectangular matrix network. The permutations are then feasible downstream of the matrix network.

[0273] Fig. 25b illustrates a general case of downstream permutations of the matrix network according to the invention.

[0274] In the case of a telecommunications processor with beamforming in transmission, the permutations can be performed downstream of the triangular matrix network. With beamformers in transmission, it is then sufficient to permute and / or combine the formation laws. The downstream permutations with beamformers in transmission make it possible to establish all the connections (i, j) with the partial network of elementary switches.

[0275] Generally, for permutations downstream of the crossed bar switch, for the assembly type according to a 100a triangular matrix, the ranking of first-dimensional rank groups X (row) is done in descending order of first-dimensional rank X; and the second-dimensional rank allocation Y (column) is in descending order.

[0276] According to the same principles, a person skilled in the art can adapt the classifications for other types of assembly.

[0277] Thus, for a type of assembly according to a 100b triangular matrix, the ranking of first-dimensional rank groups X (row) is carried out in descending order of first-dimensional rank X; and the second-dimensional rank allocation Y (column) is then increasing.

[0278] For an assembly type according to a 100c triangular matrix, the ranking of first-dimensional rank groups X (row) is carried out in ascending order of first-dimensional rank X; and the second-dimensional rank allocation Y (column) is then descending.

[0279] For a type of assembly according to a triangular matrix lOOd, the ranking of the first-dimensional rank groups X (row) is carried out in increasing order of the first-dimensional rank X; and the second-dimensional rank allocation Y (column) is then increasing.

[0280] In an embodiment where the permutations are performed downstream of the matrix network of beam formation laws in emission, the method comprises steps consisting of: - determine a set of pairs (i, j) corresponding to a routing need between upstream and downstream signals of the interconnection device, considering all row-column intersections of the network of the crossed bus switch; i. determine elementary switches of said at least one triangular matrix to be activated for said routing, said step consisting of: ii. organize said pairs (i, j) into rank groups having the same rank according to the first dimension; iii. order said rank groups according to their rank along the first dimension; iv. allocate successively to each rank group, a rank according to the second dimension of the network, and starting with the rank following the second dimension forming a side of the triangular matrix; v. in each rank group, transpose for each pair, a pair (i, j) into a pair (i, allocated rank), activate the elementary switch of the pair (i, allocated rank), and store the column for the allocated rank;

[0281] - sum the sheaf formation laws corresponding to said column for each allocated rank associated with an emitting beamformer;

[0282] - swap the output signals of the beamformers downstream of the switch cross-bars, by permuting the assignment of laws on the sheaf-formers, in correspondence with the rank allocation.

[0283] In one variant, the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups in ascending order of rank according to the first dimension.

[0284] In an alternative variant, the step of determining the elementary switches to be activated consists of: i. organize said pairs (row, column) into groups of rank having the same rank according to the first dimension; ii. order said rank groups in descending order of rank according to the first dimension.

[0285] Figure 26 illustrates an example of downstream permutations of the matrix network of beam formation laws in emission according to a third variant of the first mode realization of the invention with an assembly of elementary switches according to a triangular matrix 100a.

[0286] The example is described to establish routing requirements for row-column pairs (1,2), (1,3) and (3,1).

[0287] In a first step, the method determines a set of row-column pairs that correspond to the routing requirements between the inputs and outputs of the interconnect device. In this step, all row-column intersections of the network are considered. In other words, all network intersections are taken into account to identify the routing requirements between the inputs of the crossover switch and the beams to be transmitted, including network intersections that lack an elementary switch.

[0288] Thus, in the example illustrated in [Fig.26]:

[0289] - the pair (1,2) designates a need to route the Tx-1 signal to the first input Input 1 of the 100a crossbar switch to the second TxBeam-2 beam corresponding to the law "Law No. 2";

[0290] - the pair (1,3) designates a need to route the Tx-1 signal to the first input Input from the 100a crossbar switch to the third beam TxBeam-3 corresponding to the law "Law No. 3";

[0291] - the pair (3,1) designates a need to route the Tx-3 signal to the third input Input 3 of the 100a crossbar switch to the first TxBeam-1 beam corresponding to the law "Law No. 1".

[0292] In a second step, the method determines the elementary switches to be activated. This step first involves organizing the (row, column) pairs into groups having the same rank along the first dimension X of the network, that is, along the dimension of the network along which the inputs are positioned. In particular, in [Fig. 26], the first dimension X is the one along which the input rows are positioned.

[0293] Thus, the following line rank groups are identified:

[0294] - group 1 corresponding to row 1 rank: {(1,2), (1,3)};

[0295] - group 3 corresponding to row rank 3: {(3,1)}.

[0296] Then the row rank groups 1 and 3 are ordered according to their row rank along the first dimension X. In particular, for the crossbar switch according to the first architecture 100a, groups 1 and 3 are ordered in descending order of row rank. Specifically, with reference to [Fig. 26], the row rank groups 1 and 3 are ordered as follows {group 3, group 1}, that is {{(3, 1)}, {(1, 2), (1, 3)}}.

[0297] Next, for each group of row ranks 3 and 1, the process allows a rank to be allocated successively along the second dimension Y, starting with rank following the second dimension Y forming a side of the triangular matrix containing the elementary commutators. In [Fig. 26], the rank following the second dimension Y forming a side of the triangular matrix is ​​the column rank 3 located on the right side of the triangular matrix. In this case, the allocation of ranks following the second dimension Y is then carried out in descending order.

[0298] In one embodiment, a counter k with rank following the second dimension Y is initialized to 3, then progressively decremented at each allocation for successive row rank groups 3 and 1. Each row rank group i is processed successively: for each connection (i, j) to be established, the association between the beam indices and the index k of the transmitting beamformers is stored in a first table. Each transmitting beamformer (k) is then configured with the sum of the beamforming laws (Law No., ...) corresponding to the directions of the beams TxBeam-j..., taking into account the first table of association between the beam indices j and the index k of the transmitting beamformers DBF. The summation of the laws is possible for the same source signal Tx-j, and applies to phase-shift beamforming laws (complex coefficients) or to true-time delay beamforming laws.A second table stores the activation of the elementary switches (i, k) for all the connections to be established.

[0299] For the example considered, column rank k=3 is allocated to row rank group 3 { (3, 1)}. For the connection (i=3, j=l), the association between the index j=l of the TxBeam-1 beam and the index k=3 of the DBF-3 beam shaper is stored in the first table. The DBF-3 beam shaper is configured with the sum of the single beamforming law Law No. l identified by j=l in the first table for k=3. The activation of the elementary switch (i=3, k=3) is also stored in the second table.

[0300] Next, column rank k=2 is allocated to row rank group 1 { (1, 2), (1, 3)}. For connection (i=l, j=2), the association between index j=2 of the TxBeam-2 beam and index k=2 of the DBF-2 beam shaper is stored in the first table. For connection (i=l, j=3), the association between index j=3 of the TxBeam-3 beam and index k=2 of the DBF-2 beam shaper is stored in the first table. The DBF-2 shaper is configured with the sum of the shaping laws Law No. 2 and Law No. 3 identified by j={2, 3} in the first table for k=2. The activation of the elementary switch (i=l, k=2) is also stored in the second table.

[0301] The elementary switches are thus activated taking into account the second activation table: { ( 3, 3), (1, 2)}.

[0302] Preferably, the steps of the method for reconfiguring the telecommunications processor according to the invention are implemented at least in part in a processor control unit, in particular in association with a memory unit.

[0303] By convention, the figures have been described taking the upper left corner as the origin of the row and column arrays. But another point in the row and column array can be chosen as the origin, and the descriptions of the examples can easily be adapted accordingly.

Claims

Demands

1. Telecommunications processor (1000) comprising a reconfigurable non-blocking interconnect device, configured to receive signals from one or more receiving antennas at inputs and deliver said signals via outputs to one or more transmitting antennas; the interconnect device comprising a crossbar switch (100) forming a two-dimensional network of N rows and P columns, the inputs of the crossbar switch being located along a first dimension of the network, the outputs of the crossbar switch being located along a second dimension of the network; the crossbar switch comprising a number of elementary switches less than the number of row-column intersections of the two-dimensional network, for routing said signals from the inputs to the outputs;the elementary switches being arranged on the network at row-column intersections to form at least one triangular matrix, such that all row-column intersections in said at least one triangular matrix have an elementary switch that can be activated, and such that all or part of the row-column intersections outside said at least one triangular matrix do not have an elementary switch.

2. Processor according to claim 1 wherein the interconnect device is coupled to a switching device enabling the input or output signals of said at least one triangular matrix to be switched.

3. Telecommunications processor according to claim 2, comprising receive beamformers associated with beamforming laws, and wherein said switching device is configured to switch one or more beamforming laws between the beamformers, so as to switch said upstream signals of said at least one triangular matrix, according to the routing requirement between upstream and downstream signals of the configurable interconnect device.

4. Telecommunications processor according to claim 2, comprising beamformers in emission associated with beamforming laws, and where said permutation device is configured to permute one or more beamforming laws between beamformers, so as to permute said signals downstream of said at least one triangular matrix, according to the routing requirement between upstream and downstream signals of the configurable interconnect device.

5. Telecommunications processor according to any one of the preceding claims, wherein the two-dimensional network of N rows and P columns forms a square matrix network with N=P or forms a rectangular matrix network with N ^P.

6. Telecommunications processor according to any one of the preceding claims, wherein said elementary switches forming at least one triangular matrix are 1x1 switches or 2x1 switches.

7. Telecommunications processor according to any one of claims 1 to 6, wherein said elementary switches forming at least one triangular matrix are 2X2 switches configured to selectively interconnect a first input along the first dimension or a second input along the second dimension with a first output along the first dimension and independently with a second output along the second dimension.

8. Telecommunications processor according to claim 7 wherein said elementary switches on the diagonal of said at least one triangular matrix are connected successively to each other, by connecting the row output of each switch to the column input of the next switch on the diagonal.

9. Telecommunications processor according to claim 2 wherein the switching device comprises a switch 150 connected upstream of the crossbar switch, said switch being configured to distribute said signals between the inputs of the crossbar switch according to the routing requirement between the upstream and downstream signals of the configurable interconnect device.

10. A method for configuring a telecommunications processor having characteristics according to any one of claims 3, 5, 6, 9, said method comprising, for signal routing, steps consisting of: determine a set of pairs (i, j) corresponding to a routing need between upstream and downstream signals of the interconnect device, considering all row-column intersections of the crossover network, determine elementary switches of said at least one triangular matrix to be activated for said routing, said step consisting of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, an extremum rank according to the second dimension; iii. order said rank groups according to their extreme rank along the second dimension; iv. allocate successively to each rank group, a rank following the first dimension of the network following the order obtained at the end of said scheduling, and starting with the rank following the first dimension forming a side of the triangular matrix; v. for each rank group, transpose each pair (i, j) into a pair (allocated rank, j), and activate the elementary switch of said pair (allocated rank, j); • swap the input signals of the crossbar switch, corresponding to the rank allocation.

11. A method according to claim 10, wherein the step of determining the elementary switches to be activated comprises: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, a minimal rank according to the second dimension; iii. order said rank groups in ascending order of minimum rank according to the second dimension.

12. A method according to claim 10, wherein the step of determining the elementary switches to be activated comprises: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. determine in each rank group, a maximum rank according to the second dimension; iii. order said rank groups in descending order of maximum rank according to the second dimension.

13. A method for configuring a telecommunications processor having characteristics according to any one of claims 4, 5, 6, said method comprising, for signal routing, steps consisting of: • determine a set of pairs (i, j) corresponding to a routing need between upstream and downstream signals of the interconnection device, considering all row-column intersections of the network of the crossed bus switch; • determine elementary switches of said at least one triangular matrix to be activated for said routing, said step consisting of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups according to their rank along the first dimension; iii. allocate successively to each rank group, a rank according to the second dimension of the network, and starting with the rank following the second dimension forming a side of the triangular matrix; iv. in each rank group, transpose for each pair, a pair (i, j) into a pair (i, allocated rank), activate the elementary switch of the pair (i, allocated rank), and store the rank j following the second dimension for the allocated rank; • sum the beam formation laws corresponding to the ranks according to the second dimension stored for the same allocated rank associated with a beam shaper in emission; • swap the output signals of the beamformers downstream of the crossbar switch, by swapping the assignment of laws on the beamformers, in correspondence with the rank allocation.

14. A method according to claim 13, wherein the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; ii. order said rank groups in ascending order of rank according to the first dimension.

15. A method according to claim 13, wherein the step of determining the elementary switches to be activated consists of: i. organize said pairs (i, j) into rank groups having the same rank along the first dimension; order said rank groups in descending order of rank according to the first dimension. ii.

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