Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate comprises: a plurality of sub-pixels (PX), comprising a first-type sub-pixel (C1) and a second-type sub-pixel (C2). The orthographic projection of a first anode structure (30A) on a base substrate (100) at least partially overlaps the orthographic projection of an occupied area of a first pixel driving circuit (10A) on the base substrate (100), so as to form a first overlapping region (OV1). The orthographic projection of a second anode structure (30B) on the base substrate (100) at least partially overlaps the orthographic projection of an occupied area of a second pixel driving circuit (10B) on the base substrate (100), so as to form a second overlapping region (OV2). The area of the first overlapping region (OV1) is smaller than the area of the second overlapping region (OV2). The orthographic projection of the first anode structure (30A) on the base substrate (100) at least partially overlaps the orthographic projection of a driving gate conductive portion of the first pixel driving circuit (10A) on the base substrate (100), so as to form a third overlapping region (OV3). The orthographic projection of the second anode structure (30B) on the base substrate (100) at least partially overlaps the orthographic projection of a driving gate conductive portion of the second pixel driving circuit (10B) on the base substrate (100), so as to form a fourth overlapping region (OV4). The ratio of the area of the third overlapping region (OV3) to the area of the fourth overlapping region (OV4) ranges from 0.8 to 1.2.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] OLEDs (Organic Light-Emitting Diodes) are current-type organic light-emitting devices (OLEDs). They emit light through the injection and recombination of charge carriers, with the intensity of the light being proportional to the injected current. Under the influence of an electric field, holes generated in the anode structure and electrons generated in the cathode structure migrate, injecting into the hole transport layer and electron transport layer, respectively, before migrating to the light-emitting layer. When these two molecules meet in the light-emitting layer, they generate energy excitons, which in turn excite the light-emitting molecules, ultimately producing visible light.

[0003] Brightness uniformity is a key quality indicator for display panels. In existing display panels, the openings of individual pixels are located in different locations, resulting in varying areas of overlap between the anode structure and the underlying pixel driver circuitry. This results in varying parasitic capacitance, which can lead to uneven brightness across the display panel.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, comprising a base substrate; and a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, wherein the plurality of sub-pixels comprise a first type of sub-pixels and a second type of sub-pixels, the first type of sub-pixels comprising a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit being electrically connected to the first light-emitting device for driving the first light-emitting device to emit light, the second type of sub-pixels comprising a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit being electrically connected to the second light-emitting device for driving the second light-emitting device to emit light; the first light-emitting device comprises a first anode structure, the second light-emitting device comprises a second anode structure, the orthographic projection of the first anode structure on the base substrate and the orthographic projection of the second anode structure on the base substrate are respectively arranged in different rows; the orthographic projection of the first anode structure on the base substrate at least partially overlaps with the orthographic projection of the occupied area of ​​the first pixel driving circuit on the base substrate to form a first overlapping area; the orthographic projection of the second anode structure on the base substrate overlaps with the orthographic projection of the second image structure on the base substrate The occupied area of ​​the pixel driving circuit at least partially overlaps with the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the substrate to form a second overlapping area; the area of ​​the first overlapping area is smaller than the area of ​​the second overlapping area; the first pixel driving circuit and the second pixel driving circuit both include a driving gate conductive portion, the driving gate conductive portion of the first pixel driving circuit includes a third gate of a third transistor used as a driving transistor of the first pixel driving circuit and a first connecting portion electrically connected to the third gate, and the driving gate conductive portion of the second pixel driving circuit includes a third gate of a third transistor used as a driving transistor of the second pixel driving circuit and a first connecting portion electrically connected to the third gate; the orthographic projection of the first anode structure on the substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the substrate to form a third overlapping area; the orthographic projection of the second anode structure on the substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the second pixel driving circuit on the substrate to form a fourth overlapping area; and the ratio of the area of ​​the third overlapping area to the area of ​​the fourth overlapping area is between 0.8 and 1.2.

[0007] According to some exemplary embodiments, an orthographic projection area of ​​the driving gate conductive portion of the first pixel driving circuit on the base substrate is larger than an orthographic projection area of ​​the driving gate conductive portion of the second pixel driving circuit on the base substrate.

[0008] According to some exemplary embodiments, an orthographic projection area of ​​the first connection portion of the first pixel driving circuit on the base substrate is larger than an orthographic projection area of ​​the first connection portion of the second pixel driving circuit on the base substrate.

[0009] According to some exemplary embodiments, a ratio of an area of ​​an orthographic projection of the third gate of the first pixel driving circuit on the substrate to an area of ​​an orthographic projection of the third gate of the second pixel driving circuit on the substrate is between 0.8 and 1.2.

[0010] According to some exemplary embodiments, the first anode structure includes an anode main portion and an anode extension portion, the anode extension portion extends from the anode main portion toward the first pixel driving circuit, and the orthographic projection of the third gate and the first connection portion of the first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the anode extension portion of the first anode structure on the substrate to form the third overlapping area.

[0011] According to some exemplary embodiments, an orthographic projection of the third gate and the first connection portion of the first pixel driving circuit on the base substrate is spaced apart from an orthographic projection of the anode main portion of the first anode structure on the base substrate.

[0012] According to some exemplary embodiments, the orthographic projections of the third gate and the first connection portion of the second pixel driving circuit on the base substrate at least partially overlap with the orthographic projection of the anode body portion of the second anode structure on the base substrate to form the fourth overlapping region.

[0013] According to some exemplary embodiments, the first pixel driving circuit and the second pixel driving circuit both include storage capacitors, the storage capacitors include a first storage capacitor electrode and a second storage capacitor electrode, the orthographic projections of the first storage capacitor electrode and the second storage capacitor electrode on the substrate at least partially overlap with each other, the first storage capacitor electrode includes the driving gate conductive portion; and the area of ​​the orthographic projection of the second storage capacitor electrode of the first pixel driving circuit on the substrate is smaller than the area of ​​the orthographic projection of the second storage capacitor electrode of the second pixel driving circuit on the substrate.

[0014] According to some exemplary embodiments, the area of ​​the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second storage capacitor electrode of the first pixel driving circuit on the substrate to form a fifth overlapping region; the area of ​​the orthographic projection of the driving gate conductive portion of the second pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second storage capacitor electrode of the second pixel driving circuit on the substrate to form a sixth overlapping region; and the ratio of the area of ​​the fifth overlapping region to the area of ​​the sixth overlapping region is between 0.8 and 1.2.

[0015] According to some exemplary embodiments, the display substrate includes: a semiconductor layer arranged on the base substrate; a first conductive layer located on a side of the semiconductor layer away from the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; a third conductive layer located on a side of the second conductive layer away from the base substrate; and a first electrode layer located on a side of the third conductive layer away from the base substrate, wherein the third gate is located in the first conductive layer, the second storage capacitor electrode is located in the second conductive layer, the first connecting portion is located in the third conductive layer, and the first anode structure and the second anode structure are located in the first electrode layer.

[0016] According to some exemplary embodiments, the second storage capacitor electrode includes a main body and a through hole located in the main body, the through hole exposing a portion of the third gate covered by the second storage capacitor electrode, and the first connection portion is electrically connected to the third gate through the through hole; and the first connection portion of the first pixel driving circuit includes a conductive plug, the orthographic projection of the conductive plug on the substrate falls within the orthographic projection of the through hole of the second storage capacitor electrode of the first pixel driving circuit on the substrate, and the area of ​​the orthographic projection of the conductive plug of the first pixel driving circuit on the substrate is larger than the area of ​​the orthographic projection of the conductive plug of the second pixel driving circuit on the substrate.

[0017] According to some exemplary embodiments, the first connection portion of the first pixel driving circuit further includes a first connection sub-portion and a second connection sub-portion, the first connection sub-portion, the conductive plug and the second connection sub-portion are an integral structure; and the orthographic projections of the first connection sub-portion and the second connection sub-portion on the base substrate are located on opposite sides of the orthographic projection of the through hole on the base substrate.

[0018] According to some exemplary embodiments, an orthographic projection area of ​​the through hole of the second storage capacitor electrode of the first pixel driving circuit on the substrate is larger than an orthographic projection area of ​​the through hole of the second storage capacitor electrode of the second pixel driving circuit on the substrate.

[0019] According to some exemplary embodiments, the multiple sub-pixels include adjacent n+1th row sub-pixels and nth row sub-pixels, the n+1th row sub-pixels include multiple first-type sub-pixels, and the nth row sub-pixels include multiple second-type sub-pixels, where n is a positive integer; and the first pixel driving circuits of the multiple first-type sub-pixels in the n+1th row sub-pixels and the second pixel driving circuits of the multiple second-type sub-pixels in the nth row sub-pixels have their orthographic projections on the substrate arranged side by side in the same row along a first direction.

[0020] According to some exemplary embodiments, the first anode structures of the multiple first-type sub-pixels in the n+1th row of sub-pixels and the second anode structures of the multiple second-type sub-pixels in the nth row of sub-pixels are respectively arranged in different rows as their orthographic projections on the substrate, and the first anode structures and the second anode structures are alternately arranged along a first direction.

[0021] According to some exemplary embodiments, the anode extension portion of the first anode structure of the plurality of first-type sub-pixels in the (n+1)th row of sub-pixels is located between the second anode structures of the two second-type sub-pixels in the (n)th row of sub-pixels in the first direction.

[0022] According to some exemplary embodiments, the display substrate includes a plurality of pixel units arranged on the base substrate, each of the pixel units including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; and at least one of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel of the same pixel unit is the first type of sub-pixel, and at least another one of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel of the same pixel unit is the second type of sub-pixel.

[0023] According to some exemplary embodiments, for any two pixel units adjacent to each other in the first direction, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel of one pixel unit is the first type of sub-pixel, and two of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel of the other pixel unit are the first type of sub-pixels.

[0024] According to some exemplary embodiments, for the first color sub-pixel, the second color sub-pixel and the third color sub-pixel belonging to the first category of sub-pixels, the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the third color sub-pixel on the substrate substrate is larger than the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the second color sub-pixel on the substrate substrate; and / or, for the first color sub-pixel, the second color sub-pixel and the third color sub-pixel belonging to the first category of sub-pixels, the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the second color sub-pixel on the substrate substrate is larger than the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the first color sub-pixel on the substrate substrate.

[0025] According to some exemplary embodiments, the display substrate further includes: a data signal line for transmitting a data signal; and a driving voltage line for transmitting a driving voltage; the data signal line, the driving voltage line and the first connecting portion are all located in the third conductive layer; and the data signal line, the driving voltage line and the first connecting portion all extend along the second direction.

[0026] According to some exemplary embodiments, for sub-pixels of the same color belonging to the first category of sub-pixels and the second category of sub-pixels, respectively, a ratio of an area of ​​an orthographic projection of the first connection portion of the first pixel driving circuit on the substrate to an area of ​​an orthographic projection of the first connection portion of the second pixel driving circuit on the substrate is between 1.1 and 1.8.

[0027] According to some exemplary embodiments, the width of the anode extension portion of the first anode structure in the first direction is smaller than the width of the anode body portion of the first anode structure in the first direction.

[0028] According to some exemplary embodiments, in adjacent sub-pixels in the (n+1)th row and sub-pixels in the (n)th row, the first anode structures of the first type of sub-pixels are electrically connected to the first pixel driving circuit through their respective anode connection holes, and the second anode structures of the second type of sub-pixels are electrically connected to the second pixel driving circuit through their respective anode connection holes; and in adjacent sub-pixels in the (n+1)th row and sub-pixels in the (n)th row, the anode connection holes of the first type of sub-pixels and the anode connection holes of the second type of sub-pixels are basically located on the same straight line.

[0029] According to some exemplary embodiments, the orthographic projection of the first anode structure on the base substrate covers the orthographic projection of its anode connection hole on the base substrate; and the anode body portion and the anode extension portion of the first anode structure are located on opposite sides of its anode connection hole in the second direction.

[0030] According to some exemplary embodiments, the orthographic projection of the first pixel driving circuit on the base substrate and the orthographic projection of the second pixel driving circuit on the base substrate are arranged side by side in the same row along a first direction.

[0031] According to some exemplary embodiments, the display substrate further includes a shielding portion located in the second conductive layer, the driving voltage line includes a bending portion, the bending portion bends in a direction away from the data signal line adjacent to the driving voltage line, and the orthographic projection of the bending portion of the driving voltage line on the base substrate at least partially overlaps with the orthographic projection of the shielding portion on the base substrate.

[0032] In yet another aspect, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0034] FIG1 is a schematic plan view of a display device according to some embodiments of the present disclosure;

[0035] 2A is a schematic plan view of a plurality of sub-pixels of a display substrate according to some exemplary embodiments of the present disclosure;

[0036] 2B is a schematic plan view of a plurality of sub-pixels of a display substrate and a pixel driving circuit thereof according to some exemplary embodiments of the present disclosure;

[0037] FIG3 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0038] 4 to 18 are partial plan views of a display substrate according to an embodiment of the present disclosure, which schematically illustrate plan views of several sub-pixels included in the display substrate, wherein FIG4 is a partial plan view of a semiconductor layer included in the display substrate according to an embodiment of the present disclosure, FIG5 is a partial plan view of a first conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG6 is a partial plan view of a combination of a semiconductor layer and a first conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG7A is a partial plan view of a second conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG7B is a partial plan view of a second conductive layer included in the display substrate according to some other exemplary embodiments of the present disclosure, FIG8 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, and a second conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG9 is a partial plan view of a first insulating layer included in the display substrate according to an embodiment of the present disclosure, FIG10 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer included in the display substrate according to an embodiment of the present disclosure, and FIG11 is a partial plan view of a display substrate included in FIG14 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, and a second insulating layer, included in a display substrate according to an embodiment of the present disclosure. FIG15 is a partial plan view of a first electrode layer included in a display substrate according to an embodiment of the present disclosure. FIG16 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, a second insulating layer, and a first electrode layer included in a display substrate according to an embodiment of the present disclosure. FIG17 is a partial plan view of a pixel defining layer included in a display substrate according to an embodiment of the present disclosure. FIG18 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, a second insulating layer, a first electrode layer, and a pixel defining layer included in a display substrate according to an embodiment of the present disclosure.

[0039] FIG19 is a cross-sectional view of a display substrate taken along line AA′ in FIG12 according to an embodiment of the present disclosure;

[0040] FIG. 20 is a cross-sectional view of a display substrate taken along line BB′ in FIG. 16 according to an embodiment of the present disclosure; and

[0041] FIG. 21 schematically illustrates capacitance between an anode structure and a gate of a driving transistor in a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0044] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0046] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0047] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0048] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0049] Those skilled in the art should understand that, herein, unless otherwise specified, the expressions "continuous extension", "integrated structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same patterning process during the manufacturing process. There are no spaces or breaks between these elements, components, structures and / or parts, but they are continuously extended structures.

[0050] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along the pixel region, for example, the longitudinal direction and the transverse direction of the pixel region. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0051] In this document, the term "row" is used to describe the positional relationship of components on a display substrate along a certain direction (e.g., a first direction). It should be noted that, unless otherwise specified, this positional relationship is described for components of the same type. For example, components such as pixel driver circuits, anode structures, and openings may be arranged on a display substrate. For pixel driver circuits, there may be rows of pixel driver circuits and their arrangement; for anode structures, there may be rows of anode structures and their arrangement.

[0052] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the thin film transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, the transistor may include a gate, a first electrode and a second electrode, wherein the first electrode can represent one of the source and the drain, and the second electrode can represent the other of the source and the drain. In the following examples, the case of a P-type thin film transistor used as a driving transistor is mainly described, and other transistors have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type thin film transistor.

[0053] Herein, the expression "PPI" (Pixels Per Inch) refers to pixel density, which represents the number of pixels set per inch. Generally, a higher PPI value represents that the display device can display images at a higher density.

[0054] The embodiments of the present disclosure provide at least one display substrate and a display device. The display substrate includes a base substrate; and a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, wherein the plurality of sub-pixels include a first type of sub-pixels and a second type of sub-pixels, the first type of sub-pixels including a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit being electrically connected to the first light-emitting device for driving the first light-emitting device to emit light, the second type of sub-pixels including a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit being electrically connected to the second light-emitting device for driving the second light-emitting device to emit light; the first light-emitting device includes a first anode structure, the second light-emitting device includes a second anode structure, the orthographic projection of the first anode structure on the base substrate and the orthographic projection of the second anode structure on the base substrate are respectively arranged in different rows; the orthographic projection of the first anode structure on the base substrate and the orthographic projection of the occupied area of ​​the first pixel driving circuit on the base substrate at least partially overlap to form a first overlapping area; the orthographic projection of the second anode structure on the base substrate and the occupied area of ​​the second pixel driving circuit overlap at least partially to form a first overlapping area The orthographic projections of the regions on the substrate at least partially overlap to form a second overlapping region; the area of ​​the first overlapping region is smaller than the area of ​​the second overlapping region; the first pixel driving circuit and the second pixel driving circuit both include a driving gate conductive portion, the driving gate conductive portion of the first pixel driving circuit includes a third gate of a third transistor used as a driving transistor of the first pixel driving circuit and a first connection portion electrically connected to the third gate, and the driving gate conductive portion of the second pixel driving circuit includes a third gate of a third transistor used as a driving transistor of the second pixel driving circuit and a first connection portion electrically connected to the third gate; the orthographic projection of the first anode structure on the substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the substrate to form a third overlapping region; the orthographic projection of the second anode structure on the substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the second pixel driving circuit on the substrate to form a fourth overlapping region; and the ratio of the area of ​​the third overlapping region to the area of ​​the fourth overlapping region is between 0.8 and 1.2. In the embodiment of the present disclosure, the first connection portion is designed so that the overlapping area of ​​the first connection portion and the gate of the third transistor in the two types of sub-pixels and the anode structure above is basically equal. In this way, the capacitive load between the node N4 and the node N1 is basically the same, which can at least reduce or eliminate the phenomenon of uneven brightness.

[0055] 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. Referring to FIG1 , the display substrate according to an embodiment of the present disclosure may include a base substrate 100 and a pixel unit PX disposed on the base substrate 100.

[0056] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel cells PX displaying an image are located. Each pixel cell PX will be described later. The non-display area NA is an area where pixel cells PX are not located, that is, an area where no image is displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel is determined based on the width of the non-display area NA.

[0057] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0058] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0059] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0060] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0061] That is, the plurality of pixel units PX are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.

[0062] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely, a first color sub-pixel SP1, a second color sub-pixel SP2, and a third color sub-pixel SP3. For example, the first color sub-pixel SP1 may be a red sub-pixel, the second color sub-pixel SP2 may be a green sub-pixel, and the third color sub-pixel SP3 may be a blue sub-pixel.

[0063] It should be noted that, in the embodiment of the present disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the above-mentioned three.

[0064] For example, in the exemplary embodiment shown in FIG1 , scan signal lines 61 and data lines 64 are schematically illustrated. Specifically, the display substrate may further include: a plurality of scan signal lines 61 and a plurality of data lines 64 disposed on the base substrate. The plurality of scan signal lines 61 supply scan signals to a plurality of rows of pixel units, and the plurality of data lines 64 supply data signals to a plurality of columns of pixel units. The scan signal lines 61 extend along a first direction X, and the plurality of scan signal lines 61 are arranged at intervals along a second direction Y. The data lines 64 extend along the second direction Y, and the plurality of data lines 64 are arranged at intervals along the first direction X.

[0065] For example, the scan signal line may be a representative of a horizontal line, and the data line may be a representative of a vertical line. It should be understood that the horizontal line may also include lines of other types or lines for supplying other signals, and the vertical line may also include lines of other types or lines for supplying other signals.

[0066] Each sub-pixel may include a light-emitting device and a pixel driving circuit for driving the light-emitting device. For example, in an OLED display substrate or display panel, the light-emitting device of a sub-pixel may include a stacked anode structure, a light-emitting material layer, and a cathode structure. The anode structures of the light-emitting devices of each sub-pixel are spaced apart and arranged in a matrix along rows extending in a first direction X and columns extending in a first direction Y.

[0067] Herein, for the convenience of description, in each plan view, the corresponding sub-pixel is represented by the orthographic projection of the anode structure of the light-emitting device of the sub-pixel on the substrate.

[0068] 2A is a schematic plan view of multiple sub-pixels of a display substrate according to some exemplary embodiments of the present disclosure, and FIG. 2B is a schematic plan view of multiple sub-pixels of a display substrate and a pixel driving circuit thereof according to some exemplary embodiments of the present disclosure.

[0069] 1 , 2A, and 2B , the display substrate may include a plurality of sub-pixels disposed on a base substrate 100 , wherein the plurality of sub-pixels are arranged in a matrix form (i.e., an array arrangement) along a first direction X and a second direction Y to form a plurality of rows of sub-pixels and a plurality of columns of sub-pixels.

[0070] For example, FIG2A schematically illustrates two adjacent pixel units PX, i.e., six sub-pixels, each arranged in different rows. Specifically, in the embodiments shown in FIG2A and FIG2B , two adjacent rows of sub-pixels are schematically illustrated, i.e., the n+1th row of sub-pixels PL1 and the nth row of sub-pixels PL2. These two rows of sub-pixels can be considered representative of adjacent odd-numbered and even-numbered rows of sub-pixels. As shown in FIG15 , the orthographic projections of the anode structures of the sub-pixels in the n+1th row of sub-pixels PL1 and the anode structures of the sub-pixels in the nth row of sub-pixels PL2 on the substrate 100 are arranged in different rows.

[0071] For example, each row of sub-pixels includes a first color sub-pixel SP1, a second color sub-pixel SP2, and a third color sub-pixel SP3 that are cyclically arranged. Two adjacent rows of sub-pixels are staggered, and within each of the two adjacent rows of sub-pixels, the second color sub-pixel SP2 in one row and the adjacent first color sub-pixel SP1 and third color sub-pixel SP3 in the other row form a pixel unit PX. Furthermore, within the pixel unit PX, the brightness centers of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 are located at the vertices of an equilateral triangle, respectively.

[0072] The first color sub-pixel SP1 may include a first light-emitting device located in a first light-emitting region and a pixel driving circuit SPC1 for driving the first light-emitting device. The first light-emitting device may emit red light. The second color sub-pixel SP2 may include a second light-emitting device located in a second light-emitting region and a pixel driving circuit SPC2 for driving the second light-emitting device. The second light-emitting device may emit green light. The third color sub-pixel SP3 may include a third light-emitting device located in a third light-emitting region and a pixel driving circuit SPC3 for driving the third light-emitting device. The third light-emitting device may emit blue light.

[0073] It should be noted that the light-emitting area of ​​a sub-pixel may be the area where the light-emitting device of the sub-pixel is located. For example, the light-emitting area of ​​a sub-pixel may be the area corresponding to the anode structure of the light-emitting device of the sub-pixel, or the light-emitting area of ​​a sub-pixel may be the area corresponding to the portion of the light-emitting material layer sandwiched between the anode structure and the cathode structure.

[0074] In an embodiment of the present disclosure, in the n+1th row of sub-pixels PL1 and the nth row of sub-pixels PL2, the pixel driving circuits of the respective sub-pixels SP1, SP2, and SP3, i.e., the pixel driving circuit SPC1, the pixel driving circuit SPC2, and the pixel driving circuit SPC3, are arranged side by side in the same row along the first direction X, i.e., arranged side by side horizontally.

[0075] In Figure 2B , the dashed box schematically illustrates an anode connection hole VHA. Through this anode connection hole VHA, the anode structure of the light-emitting device in each sub-pixel can be electrically connected to the underlying pixel driver circuit, thereby enabling the pixel driver circuit in each sub-pixel to drive its respective light-emitting device. In sub-pixels PL1 in the (n+1)th row and sub-pixels PL2 in the (n)th row, the anode connection holes VHA of each sub-pixel SP1, SP2, and SP3 are substantially aligned. In other words, the line connecting the geometric centers of the anode connection holes VHA of each sub-pixel SP1, SP2, and SP3 is substantially parallel to the first direction X.

[0076] It should be understood that when the anode connection hole VHA of each sub-pixel SP1, SP2, SP3 is rectangular, its geometric center is the intersection of the two diagonals of the rectangle; when the anode connection hole VHA of each sub-pixel SP1, SP2, SP3 is circular, its geometric center is the center of the circle.

[0077] In the examples shown in Figures 2A and 2B, in the n+1th row of sub-pixels PL1 and the nth row of sub-pixels PL2, the positive projections of the anode structures of the light-emitting devices of the sub-pixels SP1, SP2, and SP3 on the base substrate are arranged in two adjacent rows, and the pixel driving circuits of the sub-pixels SP1, SP2, and SP3 are arranged in the same row, that is, a horizontal side-by-side layout is adopted. Such a pixel arrangement is conducive to achieving a high PPI display substrate.

[0078] With reference to Figures 2B, 16, and 18, the relative positional relationship between the anode structure of some sub-pixels and the pixel driver circuitry thereunder is different from the relative positional relationship between the anode structure of some sub-pixels and the pixel driver circuitry thereunder. For example, the overlapping area between the orthographic projections of the anode structures of each sub-pixel in the n+1th row of sub-pixels PL1 and the orthographic projections of its pixel driver circuitry thereunder on the substrate substrate is smaller than the overlapping area between the orthographic projections of the anode structures of each sub-pixel in the nth row of sub-pixels PL2 and the orthographic projections of its pixel driver circuitry thereunder on the substrate substrate. The anode structures of each sub-pixel in the nth row of sub-pixels PL2 cover a majority of its pixel driver circuitry, while the anode structures of each sub-pixel in the n+1th row of sub-pixels PL1 cover only a small portion of its pixel driver circuitry. For ease of description, the plurality of sub-pixels are divided into a first category of sub-pixels C1 and a second category of sub-pixels C2.

[0079] Accordingly, the first-type sub-pixel C1 includes a first pixel driving circuit and a first light-emitting device, wherein the first pixel driving circuit is electrically connected to the first light-emitting device and is configured to drive the first light-emitting device to emit light. The second-type sub-pixel C2 includes a second pixel driving circuit and a second light-emitting device, wherein the second pixel driving circuit is electrically connected to the second light-emitting device and is configured to drive the second light-emitting device to emit light.

[0080] The first and second sub-pixels will be described in detail below with reference to the accompanying drawings. It should be noted that, although the first direction X and the second direction Y are perpendicular to each other in the illustrated embodiment, the embodiments of the present disclosure are not limited thereto. The structure of the pixel driver circuit for the sub-pixel will be described in detail below using a 7T1C pixel driver circuit as an example. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driver circuit. Other known pixel driver circuit structures may be applied to the embodiments of the present disclosure unless there is a conflict.

[0081] FIG. 3 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. 4 to 18 are partial plan views of a display substrate according to an embodiment of the present disclosure, which schematically illustrate plan views of several sub-pixels included in the display substrate, wherein FIG4 is a partial plan view of a semiconductor layer included in the display substrate according to an embodiment of the present disclosure, FIG5 is a partial plan view of a first conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG6 is a partial plan view of a combination of a semiconductor layer and a first conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG7A is a partial plan view of a second conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG7B is a partial plan view of a second conductive layer included in the display substrate according to some other exemplary embodiments of the present disclosure, FIG8 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, and a second conductive layer included in the display substrate according to an embodiment of the present disclosure, FIG9 is a partial plan view of a first insulating layer included in the display substrate according to an embodiment of the present disclosure, FIG10 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer included in the display substrate according to an embodiment of the present disclosure, and FIG11 is a partial plan view of a display substrate included in 14 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer and a second insulating layer included in the display substrate according to an embodiment of the present disclosure; FIG15 is a partial plan view of a first electrode layer included in the display substrate according to an embodiment of the present disclosure; FIG16 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, a second insulating layer and a first electrode layer included in the display substrate according to an embodiment of the present disclosure; FIG17 is a partial plan view of a pixel defining layer included in the display substrate according to an embodiment of the present disclosure; and FIG18 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, a second insulating layer, a first electrode layer and a pixel defining layer included in the display substrate according to an embodiment of the present disclosure. Figure 19 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure, taken along line AA' in Figure 12. Figure 20 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure, taken along line BB' in Figure 16. Figure 21 schematically illustrates capacitance between an anode structure and a gate of a driving transistor in a display substrate according to an embodiment of the present disclosure.

[0082] With reference to Figures 3 to 19, the pixel driving circuit may include: multiple thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (OLED). The multiple thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0083] It should be noted that, unless otherwise specified, in this document, the expression "the pixel driving circuit" includes the first pixel driving circuit and the second pixel driving circuit.

[0084] The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (i.e., a scanning signal of a previous row), a light-emitting control line 63 for transmitting a light-emitting control signal En, a data signal line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power line 67 for transmitting a reference voltage VSS.

[0085] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed along an active layer as shown in FIG8. The active layer may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0086] The active layer may include, for example, polysilicon and may include, for example, a channel region, a source region, and a drain region. The channel region may not be doped or may have a different doping type from the source and drain regions, and thus has semiconductor properties. The source and drain regions are located on either side of the channel region, respectively, and are doped with impurities, thereby having conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0087] It should be noted that, for the first insulating layer, the second insulating layer and the pixel defining layer, Figures 9, 13 and 17 schematically show the vias or openings therein, but do not show the main part of the insulating material layer. This is for the purpose of clearly showing the vias or openings in the insulating layer.

[0088] The first transistor T1 includes a first active layer 20a and a first gate G1. The first active layer 20a includes a first channel region 201a, a first source region 203a, and a first drain region 205a. The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. In addition, the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 (herein, for convenience of description, it may also be referred to as the third gate). As shown in Figure 3, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G3 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also called an initialization transistor.

[0089] The second transistor T2 includes a second active layer 20b and a second gate G2. The second active layer 20b includes a second channel region 201b, a second source region 203b, and a second drain region 205b. The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on in response to the scan signal Sn transmitted via the scan signal line 61 to electrically connect the gate G3 and drain D3 of the third transistor T3 to each other, thereby performing a diode connection of the third transistor T3.

[0090] The third transistor T3 includes a third active layer 20c and a gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in opposite directions relative to the third channel region 201c. The third source region 203c of the third transistor T3 is connected to the fourth drain region 205d and the fifth drain region 205e. The third drain region 205c is connected to the second source region 203b and the sixth source region 203f. The gate G3 of the third transistor T3 is electrically connected to the node N1 through vias VAH1 and VAH2 and the first connecting portion 71. The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also called a driving transistor.

[0091] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate electrode G4. The fourth active layer 20d includes a fourth channel region 201d, a fourth source region 203d, and a fourth drain region 205d. The fourth transistor T4 functions as a switching device for selecting a target sub-pixel for light emission. The fourth gate electrode G4 is connected to the scan signal line 61, the fourth source region 203d is connected to the data signal line 64 via a via VAH4, and the fourth drain region 205d is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on in response to the scan signal Sn transmitted via the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source electrode S3 of the third transistor T3.

[0092] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth channel region 201e, a fifth source region 203e, and a fifth drain region 205e. The fifth source region 203e can be connected to the driving voltage line 65 through a via VAH6. The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65. The drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0093] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f includes a sixth channel region 201f, a sixth source region 203f, and a sixth drain region 205f. The sixth drain region 205f can be connected to the anode structure of the OLED via a via VAH7. The gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, i.e., electrically connected to the anode structure of the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on in response to the light emission control signal En transmitted via the light emission control line 63 to transmit the drive voltage VDD to the OLED, thereby allowing the drive current Id to flow into the OLED.

[0094] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g. The seventh drain region 205g is connected to the first source region 203a of the first transistor T1. The seventh drain region 205g can be electrically connected to the initialization voltage line 66 through the via VAH8, the second connection portion 72, and the via VAH5. The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

[0095] One end (hereinafter referred to as a first storage capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second storage capacitor electrode) Cst2 is electrically connected to the driving voltage line 65 .

[0096] The anode structure of the OLED is electrically connected to the node N4, and the cathode structure is electrically connected to the power line 67 to receive the reference voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0097] It should be noted that, in FIG3 , each thin film transistor T1, T2, T3, T4, T5, T6, and T7 is a p-channel field effect transistor; however, the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be an n-channel field effect transistor.

[0098] In operation, during the initialization phase, a reset control signal RESET having a low level is supplied through the reset signal line 62. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the third transistor T3 through the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.

[0099] In the data programming phase, a scan signal Sn having a low level is supplied through the scan signal line 61. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode connection state through the turned-on second transistor T2 and is biased in the forward direction.

[0100] Subsequently, a compensation voltage Dm+Vth (for example, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via the data signal line 64 is applied to the gate G3 of the third transistor T3. Subsequently, the driving voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0101] In the light emitting period, the light emitting control signal En from the light emitting control line 63 changes from a high level to a low level. Subsequently, in the light emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emitting control signal En.

[0102] Then, a driving current is generated based on the difference between the voltage of the gate G3 of the third transistor T3 and the driving voltage VDD. A driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.

[0103] In the light-emitting phase, based on the current-voltage relationship of the third transistor T3, the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst. 2 Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the third transistor T3.

[0104] With reference to Figures 4 to 21 , the display substrate includes a base substrate 100 and a plurality of film layers disposed on the base substrate 100. In some embodiments, the plurality of film layers include at least a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23. The semiconductor layer 20, the first conductive layer 21, the second conductive layer 22, and the third conductive layer 23 are sequentially disposed away from the base substrate 100. The plurality of film layers further include at least a plurality of insulating film layers. For example, the plurality of insulating film layers may include a first gate insulating layer 24, a second gate insulating layer 25, and a first insulating layer 26. The first gate insulating layer 24 may be disposed between the semiconductor layer 20 and the first conductive layer 21, the second gate insulating layer 25 may be disposed between the first conductive layer 21 and the second conductive layer 22, and the first insulating layer 26 may be disposed between the second conductive layer 22 and the third conductive layer 23.

[0105] For example, the semiconductor layer 20 can be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness can be in the range of 400 to 800 angstroms, for example, 500 angstroms. The first conductive layer 21 and the second conductive layer 22 can be formed of a conductive material that forms the gate of a thin film transistor, for example, the conductive material can be Mo, and its film thickness can be in the range of 2000 to 4000 angstroms, for example, 3000 angstroms. The third conductive layer 23 can be formed of a conductive material that forms the source and drain of a thin film transistor, for example, the conductive material can include Ti, Al, etc. The third conductive layer 23 can have a stacked structure formed of Ti / Al / Ti, and its film thickness can be in the range of 6000 to 9000 angstroms. For example, when the third conductive layer 23 has a stacked structure formed of Ti / Al / Ti, the thickness of each Ti / Al / Ti layer can be approximately 500 angstroms, 6000 angstroms, and 500 angstroms, respectively. For example, the first gate insulating layer 24 and the second gate insulating layer 25 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and each layer may have a thickness of approximately 1000 to 2000 angstroms. For example, the first insulating layer 26 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and have a thickness of approximately 3000 to 6000 angstroms.

[0106] The display substrate includes a scan signal line 61, a reset signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged along a row direction to apply a scan signal Sn, a reset control signal RESET, a light emission control signal En, and an initialization voltage Vint to the sub-pixels SP1, SP2, and SP3, respectively. The display substrate may further include a data signal line 64 and a drive voltage line 65 that intersect the scan signal line 61, the reset signal line 62, the light emission control line 63, and the initialization voltage line 66 to apply a data signal Dm and a drive voltage VDD to the sub-pixels SP1, SP2, and SP3, respectively.

[0107] As shown in Figures 5 and 6, the scan signal line 61, reset signal line 62, and light emission control line 63 are all located in the first conductive layer 21. The gates G1 to G7 of the aforementioned transistors are also located in the first conductive layer 21. For example, the portions where the reset signal line 62 overlaps with the semiconductor layer 20 form the gates G1 of the first transistor T1 and G7 of the seventh transistor T7, respectively. The portions where the scan signal line 61 overlaps with the semiconductor layer 20 form the gates G2 of the second transistor T2 and G4 of the fourth transistor T4, respectively. The portions where the light emission control line 63 overlaps with the semiconductor layer 20 form the gates G6 of the sixth transistor T6 and G5 of the fifth transistor T5, respectively.

[0108] Continuing with Figures 5 and 6, the display substrate may further include a plurality of first storage capacitor electrodes Cst1. These plurality of first storage capacitor electrodes Cst1 are also located in the first conductive layer 21. The portion where the first storage capacitor electrode Cst1 overlaps with the semiconductor layer 20 forms the gate G3 of the third transistor T3. The first storage capacitor electrode Cst1 also forms one terminal of the storage capacitor Cst. In other words, the first storage capacitor electrode Cst1 serves both as the gate G3 of the third transistor T3 and as one electrode of the storage capacitor Cst.

[0109] The first storage capacitor electrode Cst1 has a first dimension W1 along the first direction X and a second dimension H1 along the second direction Y. For example, the orthographic projection of the first storage capacitor electrode Cst1 on the base substrate 100 may be substantially rectangular. "Substantially rectangular" herein may include shapes such as a rectangle, a rectangle with at least one rounded corner, or a rectangle with at least one chamfered corner. With reference to FIG5 , the first dimension W1 may represent the width of the first storage capacitor electrode Cst1, and the second dimension H1 may represent the height of the first storage capacitor electrode Cst1.

[0110] As shown in Figures 7A and 8, the initialization voltage line 66 is located in the second conductive layer 22. The display substrate may further include a plurality of second storage capacitor electrodes Cst2. The plurality of second storage capacitor electrodes Cst2 are also located in the second conductive layer 22. The plurality of second storage capacitor electrodes Cst2 are respectively arranged corresponding to the plurality of first storage capacitor electrodes Cst1. That is, the orthographic projections of the plurality of second storage capacitor electrodes Cst2 on the base substrate 100 at least partially overlap with the orthographic projections of the corresponding first storage capacitor electrodes Cst1 on the base substrate 100. The second storage capacitor electrodes Cst2 form another terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are arranged opposite each other, their orthographic projections on the base substrate 100 at least partially overlap, and a second gate insulating layer 25 is disposed therebetween. For example, the first storage capacitor electrode Cst1 can be electrically connected to the node N1 via vias VAH1 and VAH2 and the first connecting portion 71, and the second storage capacitor electrode Cst2 can be electrically connected to the drive voltage line 65 via via VAH9, i.e., the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are connected to different voltage signals. Thus, the portion where the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 overlap each other may form the storage capacitor Cst.

[0111] The second storage capacitor electrode Cst2 has a first size W2 along the first direction X and a second size H2 along the second direction Y.

[0112] 7A , 12 , and 20 , the second storage capacitor electrode Cst2 may include a through hole VH2 to facilitate electrical connection between the first storage capacitor electrode Cst1 located below the second storage capacitor electrode Cst2 and components located in the third conductive layer 23. For example, a portion of the first connection portion 71 is formed in the through hole VAH1 to form a conductive plug 711. The conductive plug 711 extends through the through hole VH2 and is electrically connected to the first storage capacitor electrode Cst1. In this manner, one end of the first connection portion 71 is electrically connected to one end Cst1 of the storage capacitor.

[0113] The through hole VH2 of the second storage capacitor electrode Cst2 has a first dimension W3 along the first direction X and a second dimension H3 along the second direction Y. For example, the orthographic projection of the through hole VH2 on the base substrate 100 may be substantially rectangular. "Substantially rectangular" herein may include shapes such as a rectangle or square, a rectangle or square with at least one rounded corner, or a rectangle or square with at least one chamfered corner. With reference to FIG. 7A , the first dimension W3 may represent the width of the through hole VH2, and the second dimension H3 may represent the height of the through hole VH2.

[0114] 11 , the data signal line 64 and the driving voltage line 65 are located in the third conductive layer 23. Furthermore, the first connecting portion 71, the second connecting portion 72, and the third connecting portion 73 are also located in the third conductive layer 23. The data signal line 64, the driving voltage line 65, and the first connecting portion 71 all extend along the second direction Y.

[0115] The display substrate may further include a plurality of film layers disposed on the base substrate 100. In some embodiments, the plurality of film layers include at least a second insulating layer 27, a first electrode layer 28, and a pixel defining layer 29. The first electrode layer 28 is disposed on a side of the third conductive layer 23 away from the base substrate, the second insulating layer 27 may be disposed between the third conductive layer 23 and the first electrode layer 28, and the pixel defining layer 29 is disposed on a side of the first electrode layer 28 away from the base substrate to define a plurality of openings 292 (see FIG. 17 ).

[0116] 15 and 16 , the display substrate includes a plurality of anode structures 30 located within the first electrode layer 28. Each subpixel includes one anode structure 30. The anode structure 30 is electrically connected to the underlying pixel driving circuitry via an anode connection hole VHA. Specifically, the anode structure 30 is electrically connected to one end of the third connection portion 73 via the anode connection hole VHA. The other end of the third connection portion 73 is electrically connected to the sixth drain region 205f of the sixth transistor T6 via a via VAH7. In this manner, the anode structure 30 is electrically connected to the drain of the sixth transistor T6.

[0117] With reference to Figures 7A to 14, the display substrate further includes a shielding portion 221 located in the second conductive layer, and the driving voltage line 65 includes a bend 651, which bends in a direction away from the data signal line 64 adjacent to the driving voltage line, and the orthographic projection of the bend 651 of the driving voltage line on the base substrate at least partially overlaps with the orthographic projection of the shielding portion 221 on the base substrate. For example, at the bend 651 of the driving voltage line, the driving voltage line 65 is electrically connected to the shielding portion 221 below through the via VH4. In this embodiment, the driving voltage line 65 forms a bend, and the bend overlaps with the shielding portion below, which not only facilitates the electrical connection between the driving voltage line 65 and the shielding portion 221 below, but also helps to improve the transmittance of the display substrate.

[0118] As described above, in an embodiment of the present disclosure, the plurality of sub-pixels are divided into two categories based on the relative positional relationship between the anode structure of the sub-pixel and the pixel driving circuit thereunder. The first category of sub-pixels C1 includes a first pixel driving circuit and a first light-emitting device, wherein the first pixel driving circuit is electrically connected to the first light-emitting device and is used to drive the first light-emitting device to emit light. The second category of sub-pixels C2 includes a second pixel driving circuit and a second light-emitting device, wherein the second pixel driving circuit is electrically connected to the second light-emitting device and is used to drive the second light-emitting device to emit light. For convenience of description, the first pixel driving circuit and the second pixel driving circuit are marked as 10A and 10B, respectively, the first light-emitting device and the second light-emitting device are marked as 20A and 20B, respectively, and the first anode structure and the second anode structure are marked as 30A and 30B, respectively.

[0119] The first-type sub-pixel C1 includes a first pixel driving circuit 10A and a first light-emitting device 20A. The first pixel driving circuit 10A is electrically connected to the first light-emitting device 20A and is used to drive the first light-emitting device 20A to emit light. The second-type sub-pixel C2 includes a second pixel driving circuit 10B and a second light-emitting device 20B. The second pixel driving circuit 10B is electrically connected to the second light-emitting device 20B and is used to drive the second light-emitting device 20B to emit light.

[0120] The orthographic projection of the first pixel driving circuit 10A on the base substrate 100 and the orthographic projection of the second pixel driving circuit 10B on the base substrate 100 are arranged side by side in the same row along the first direction X. For example, for adjacent odd-numbered rows of sub-pixels PL1 and even-numbered rows of sub-pixels PL2, the odd-numbered rows of sub-pixels PL1 include a plurality of first-type sub-pixels C1 arranged along the first direction X, and the even-numbered rows of sub-pixels PL2 include a plurality of second-type sub-pixels C2 arranged along the first direction X. The plurality of first pixel driving circuits 10A of the odd-numbered rows of sub-pixels PL1 and the plurality of second pixel driving circuits 10B of the even-numbered rows of sub-pixels PL2 are arranged side by side in the same row along the first direction X.

[0121] The first light-emitting device 20A includes a first anode structure 30A, and the second light-emitting device 20B includes a second anode structure 30B. The orthographic projections of the first anode structure 30A and the second anode structure 30B on the base substrate 100 are arranged in different rows. For example, the first anode structures 30A and the second anode structures 30B are alternately arranged along a first direction X.

[0122] The orthographic projection of the first anode structure 30A on the base substrate 100 at least partially overlaps with the orthographic projection of the area occupied by the first pixel driving circuit 10A on the base substrate 100, forming a first overlapping region OV1. The orthographic projection of the second anode structure 30B on the base substrate 100 at least partially overlaps with the orthographic projection of the area occupied by the second pixel driving circuit 10B on the base substrate 100, forming a second overlapping region OV2. In an embodiment of the present disclosure, the area of ​​the first overlapping region OV1 is smaller than the area of ​​the second overlapping region OV2.

[0123] It should be noted that, in this document, the expression "occupied area" refers to the maximum area covered by the orthographic projection of a pattern, layer structure, etc. on the substrate. Specifically, the orthographic projection of a pattern, layer structure, etc. on the substrate has two sides that are farthest apart in the first direction X and two sides that are farthest apart in the second direction Y. The extension lines of these four sides intersect to enclose an area, which is the occupied area of ​​the pattern, layer structure, etc. For example, with reference to FIG4 , for a pixel driver circuit of a sub-pixel, the occupied area of ​​its active layer has a rectangular or substantially rectangular shape. As shown in FIG4 , the occupied area of ​​the active layer of a sub-pixel is schematically shown using a dotted box. The occupied area has a dimension along the first direction X (i.e., width W4) and a dimension along the second direction Y (i.e., length H4), wherein the length H4 is greater than the width W4, or in other words, the length H4 is more than 1.2 times the width W4, that is, the occupied area has a rectangular shape. In this document, unless otherwise specified, the occupied area of ​​the active layer of a pixel driver circuit of a sub-pixel can be used to represent the occupied area of ​​the pixel driver circuit.

[0124] 16 , the orthographic projection of the second anode structure 30B on the substrate 100 overlaps with a majority of the orthographic projection of the area occupied by the second pixel driving circuit 10B on the substrate 100. The orthographic projection of the first anode structure 30A on the substrate 100 overlaps with only a small portion of the orthographic projection of the area occupied by the first pixel driving circuit 10A on the substrate 100. For example, the orthographic projection of the first anode structure 30A on the substrate 100 primarily overlaps with the orthographic projections of the initialization voltage line 66 and reset signal line 62 of the next row of sub-pixels on the substrate 100. In other words, the "topography" of the area where the first anode structure 30A of the first type of sub-pixel C1 and the second anode structure 30B of the second type of sub-pixel C2 are located is different.

[0125] Referring to Figures 3 and 16 , in each subpixel, the anode structure overlaps with the gate G3 of the third transistor T3 below, generating parasitic capacitance between them. This creates a capacitive load between node N4 and node N1. Because the first anode structure 30A of the first-type subpixel C1 and the second anode structure 30B of the second-type subpixel C2 are located in areas with different "topography," the capacitive load between node N4 and node N1 is inconsistent, resulting in uneven brightness.

[0126] In an embodiment of the present disclosure, one end of the first connection portion 71 is electrically connected to the gate G3 of the third transistor T3, and the gate G3 of the third transistor T3 and the first connection portion 71 constitute a driving gate conductive portion. That is, each of the first pixel driving circuit 10A and the second pixel driving circuit 10B includes a driving gate conductive portion, and the driving gate conductive portion of each of the first pixel driving circuit 10A and the second pixel driving circuit 10B includes the gate G3 of the respective third transistor T3 and the first connection portion 71. The orthographic projection of the first anode structure 30A on the substrate 100 at least partially overlaps with the orthographic projection of the driving gate conductive portion of the first pixel driving circuit 10A on the substrate 100, forming a third overlapping region OV3. The orthographic projection of the second anode structure 30B on the substrate 100 at least partially overlaps with the orthographic projection of the driving gate conductive portion of the second pixel driving circuit 10B on the substrate 100, forming a fourth overlapping region OV4.

[0127] In an embodiment of the present disclosure, the ratio of the area of ​​the third overlapping region OV3 to the area of ​​the fourth overlapping region OV4 is between 0.8 and 1.2, for example, between 0.85 and 1.15, between 0.9 and 1.1, or the area of ​​the third overlapping region OV3 is substantially equal to the area of ​​the fourth overlapping region OV4.

[0128] In the embodiment of the present disclosure, a first connection portion 71 located in the third conductive layer 23 is electrically connected to the gate G3 of the third transistor T3. By designing the first connection portion 71, the overlapping area of ​​the first connection portion 71 and the gate G3 of the third transistor T3 in the two types of sub-pixels and the anode structure above is substantially equal. In this way, the capacitive load between the node N4 and the node N1 is substantially consistent, thereby at least reducing or eliminating the phenomenon of uneven brightness.

[0129] In the embodiment of the present disclosure, the "topography" of the area where the first anode structure 30A of the first type of sub-pixel C1 and the second anode structure 30B of the second type of sub-pixel C2 are located is different. By increasing the area of ​​the driving gate conductive part of the first pixel driving circuit 10A of the first type of sub-pixel C1, the overlapping area between the driving gate conductive part of the first pixel driving circuit 10A of the first type of sub-pixel C1 and the first anode structure 30A is basically equal to the overlapping area between the driving gate conductive part of the second pixel driving circuit 10B of the second type of sub-pixel C2 and the second anode structure 30B.

[0130] 5 , the ratio of the area of ​​the orthographic projection of the gate G3 of the first pixel driving circuit 10A on the base substrate 100 to the area of ​​the orthographic projection of the gate G3 of the second pixel driving circuit 10B on the base substrate 100 is between 0.8 and 1.2, for example, between 0.85 and 1.15, or between 0.9 and 1.1, or the area of ​​the orthographic projection of the gate G3 of the first pixel driving circuit 10A on the base substrate 100 is substantially equal to the area of ​​the orthographic projection of the gate G3 of the second pixel driving circuit 10B on the base substrate 100.

[0131] 5, 11, and 12, the area of ​​the orthographic projection of the driving gate conductive portion of the first pixel driving circuit 10A on the substrate 100 is greater than the area of ​​the orthographic projection of the driving gate conductive portion of the second pixel driving circuit 10B on the substrate 100. For example, the area of ​​the orthographic projection of the first connection portion 71 of the first pixel driving circuit 10A on the substrate 100 is greater than the area of ​​the orthographic projection of the first connection portion 71 of the second pixel driving circuit 10B on the substrate 100. In the embodiment of the present disclosure, the area of ​​the driving gate conductive portion of the first pixel driving circuit 10A of the first-type sub-pixel C1 is increased by increasing the area of ​​the first connection portion 71 electrically connected to the gate G3 of the third transistor T3.

[0132] Referring to Figure 11 , as described above, a portion of the first connection portion 71 is formed in the via hole VAH1 to form a conductive plug 711. That is, the first connection portion 71 includes the conductive plug 711. For the first-type sub-pixel C1 and the second-type sub-pixel C2, the first connection portion 71 also includes a first connection sub-portion 712. For example, the first connection sub-portion 712 extends upward from the conductive plug 711 so that the other end of the first connection portion 71 is electrically connected to the via hole VAH2. The first connection sub-portion 712 and the conductive plug 711 are integrally formed. Furthermore, for the first-type sub-pixel C1, the first connection portion 71 also includes a second connection sub-portion 713. The first connection sub-portion 712, the conductive plug 711, and the second connection sub-portion 713 are integrally formed. The orthographic projections of the first connection sub-portion 712 and the second connection sub-portion 713 on the base substrate 100 are located on opposite sides of the orthographic projections of the via hole VH2 or the conductive plug 711 on the base substrate 100. That is, in the illustrated embodiment, the first connecting sub-portion 712 extends upward from the conductive plug 711, and the second connecting sub-portion 713 extends downward from the conductive plug 711. In the embodiment of the present disclosure, the first connecting portion 71 of the first-type sub-pixel C1 includes an additional second connecting sub-portion 713, thereby increasing the area of ​​the driving gate conductive portion of the first pixel driving circuit 10A of the first-type sub-pixel C1.

[0133] 15 and 16 , the first anode structure 30A includes an anode main portion 31A and an anode extension portion 32A, the anode extension portion 32A extending from the anode main portion 31A toward the first pixel driving circuit 10A, and the orthographic projection of each of the gate G3 and the first connection portion 71 of the first pixel driving circuit 10A on the base substrate 100 at least partially overlaps with the orthographic projection of the anode extension portion 32A of the first anode structure on the base substrate 100 to form the third overlapping area OV3.

[0134] For example, the anode extension portion 32A of the first anode structure of the plurality of first-type sub-pixels C1 in the n+1th row of sub-pixels PL1 is located in the first direction X between the second anode structures 30B of the two second-type sub-pixels C2 in the nth row of sub-pixels PL2.

[0135] The orthographic projection of each of the gate G3 and the first connecting portion 71 of the first pixel driving circuit 10A on the base substrate 100 is spaced apart from the orthographic projection of the anode main portion 31A of the first anode structure 30A on the base substrate 100. In other words, the orthographic projection of each of the gate G3 and the first connecting portion 71 of the first pixel driving circuit 10A on the base substrate 100 does not overlap with the orthographic projection of the anode main portion 31A of the first anode structure 30A on the base substrate 100.

[0136] The second anode structure 30B includes an anode main portion 31B, and the orthographic projection of each of the gate G3 and the first connection portion 71 of the second pixel driving circuit 10B on the base substrate 100 at least partially overlaps with the orthographic projection of the anode main portion 31B of the second anode structure on the base substrate 100 to form the fourth overlapping area OV4.

[0137] In the embodiment of the present disclosure, the driving gate conductive portion forms one end of the storage capacitor, that is, the combination of the first storage capacitor electrode (i.e., the gate G3 of the third transistor T3) Cst1 and the first connecting portion 71 forms one end of the storage capacitor. As described above, the area of ​​the orthographic projection of the driving gate conductive portion of the first pixel driving circuit 10A on the substrate 100 is larger than the area of ​​the orthographic projection of the driving gate conductive portion of the second pixel driving circuit 10B on the substrate 100. In order to make the values ​​of the storage capacitors of each sub-pixel substantially consistent, in the embodiment of the present disclosure, the area of ​​the second storage capacitor electrode Cst2 in the first pixel driving circuit 10A can be reduced. That is, the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A on the substrate 100 is smaller than the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of the second pixel driving circuit 10B on the substrate 100.

[0138] 15 , the width of the anode extension portion 32A of the first anode structure in the first direction X is smaller than the width of the anode main portion 31A of the first anode structure in the first direction X.

[0139] In the adjacent n+1th row of sub-pixels PL1 and nth row of sub-pixels PL2, the anode connection holes VHA of the first type of sub-pixel C1 and the anode connection holes VHA of the second type of sub-pixel C2 are substantially located on the same straight line. This design facilitates the formation of the anode connection holes through a patterning process.

[0140] The orthographic projection of the first anode structure 30A on the base substrate 100 covers the orthographic projection of the anode connection hole VHA on the base substrate 100. The anode body portion 31A and the anode extension portion 32A of the first anode structure are located on opposite sides of the anode connection hole VHA in the second direction Y.

[0141] 5, 7B, and 11, the orthographic projection of the driving gate conductive portion (including the gate G3 and the first connecting portion 71) of the first pixel driving circuit 10A on the substrate 100 at least partially overlaps with the orthographic projection of the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A on the substrate 100, forming a fifth overlapping region. The orthographic projection of the driving gate conductive portion (including the gate G3 and the first connecting portion 71) of the second pixel driving circuit 10B on the substrate 100 at least partially overlaps with the orthographic projection of the second storage capacitor electrode Cst2 of the second pixel driving circuit 10B on the substrate 100, forming a sixth overlapping region. The ratio of the area of ​​the fifth overlapping region to the area of ​​the sixth overlapping region is between 0.8 and 1.2, for example, between 0.85 and 1.15, or between 0.9 and 1.1, or the area of ​​the fifth overlapping region is substantially equal to the area of ​​the sixth overlapping region. In this way, the values ​​of the storage capacitors Cst of each sub-pixel can be substantially consistent.

[0142] 7B and 11 , the second storage capacitor electrode Cst2 includes a main body portion Cst20 and a through hole VH2 in the main body portion, wherein the through hole VH2 exposes a portion of the gate G3 covered by the second storage capacitor electrode, and the first connection portion 711 is electrically connected to the gate G3 through the through hole VH2.

[0143] The orthographic projection of the conductive plug 711 on the base substrate 100 falls within the orthographic projection of the through hole VH2 of the second storage capacitor electrode of the first pixel driving circuit on the base substrate 100. For example, the orthographic projection area of ​​the conductive plug 711 of the first pixel driving circuit 10A on the base substrate 100 is larger than the orthographic projection area of ​​the conductive plug 711 of the second pixel driving circuit 10B on the base substrate 100.

[0144] In an embodiment of the present disclosure, the orthographic projection area of ​​the through hole VH2 of the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A on the substrate 100 is larger than the orthographic projection area of ​​the through hole VH2 of the second storage capacitor electrode Cst2 of the second pixel driving circuit 10B on the substrate 100. For example, the through hole VH2 of the second storage capacitor electrode Cst2 has a first dimension W3 along the first direction X and a second dimension H3 along the second direction Y. The first dimension W3 of the through hole VH2 of the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A is substantially equal to the first dimension W3 of the through hole VH2 of the second storage capacitor electrode Cst2 of the second pixel driving circuit 10B. The second dimension H3 of the through hole VH2 of the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A is larger than the second dimension H3 of the through hole VH2 of the second storage capacitor electrode Cst2 of the second pixel driving circuit 10B. In this manner, the area of ​​the second storage capacitor electrode Cst2 of the first pixel driving circuit 10A can be reduced, which facilitates achieving consistency in the storage capacitance of each sub-pixel.

[0145] 1 and 15 to 18 , the display substrate includes a plurality of pixel units disposed on a base substrate 100, each of which includes a first color sub-pixel SP1, a second color sub-pixel SP2, and a third color sub-pixel SP3. At least one of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 of the same pixel unit is a sub-pixel C1 of the first type, and at least another of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 of the same pixel unit is a sub-pixel C2 of the second type. For example, for any two adjacent pixel units in a first direction, one of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 of one pixel unit is a sub-pixel C1 of the first type, and two of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 of the other pixel unit are sub-pixels C1 of the first type.

[0146] 11 , for the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 belonging to the first type of sub-pixel C1, the area of ​​the positive projection of the first connection portion 71 of the first pixel driving circuit of the third color sub-pixel SP3 on the base substrate is larger than the area of ​​the positive projection of the first connection portion 71 of the first pixel driving circuit of the second color sub-pixel SP2 on the base substrate 100.

[0147] For the first color sub-pixel SP1, the second color sub-pixel SP2 and the third color sub-pixel SP3 belonging to the first type of sub-pixel C1, the area of ​​the positive projection of the first connection portion 71 of the first pixel driving circuit of the second color sub-pixel SP2 on the substrate is larger than the area of ​​the positive projection of the first connection portion 71 of the first pixel driving circuit of the first color sub-pixel SP1 on the substrate.

[0148] For sub-pixels of the same color belonging to the first category of sub-pixels C1 and the second category of sub-pixels C2, respectively, the ratio of the area of ​​the positive projection of the first connection portion 71 of the first pixel driving circuit 10A on the substrate to the area of ​​the positive projection of the first connection portion 71 of the second pixel driving circuit 10B on the substrate is between 1.1 and 1.8.

[0149] That is, in the embodiment of the present disclosure, the area of ​​the first connection portion 71 in the first type of sub-pixel C1 is increased by approximately 10% to 80% relative to the first connection portion 71 in the second type of sub-pixel C2 of the same color. The inventors have found that through such a design, the capacitance inconsistency between the two types of sub-pixels can be better compensated.

[0150] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above. For example, the display panel may be an OLED display panel.

[0151] 1 , at least some embodiments of the present disclosure further provide a display device, which may include the display substrate described above.

[0152] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0153] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description and will not be repeated here.

[0154] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: a substrate; and A plurality of sub-pixels are provided on the substrate, and the sub-pixels are arranged in an array along a first direction and a second direction. The plurality of sub-pixels include a first type of sub-pixels and a second type of sub-pixels, the first type of sub-pixels include a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit is electrically connected to the first light-emitting device, and is used to drive the first light-emitting device to emit light, and the second type of sub-pixels include a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit is electrically connected to the second light-emitting device, and is used to drive the second light-emitting device to emit light; The first light emitting device includes a first anode structure, the second light emitting device includes a second anode structure, and the orthographic projection of the first anode structure on the base substrate and the orthographic projection of the second anode structure on the base substrate are respectively arranged in different rows; The orthographic projection of the first anode structure on the substrate at least partially overlaps with the orthographic projection of the area occupied by the first pixel driving circuit on the substrate to form a first overlapping area; the orthographic projection of the second anode structure on the substrate at least partially overlaps with the orthographic projection of the area occupied by the second pixel driving circuit on the substrate to form a second overlapping area; the area of ​​the first overlapping area is smaller than the area of ​​the second overlapping area; The first pixel driving circuit and the second pixel driving circuit each include a driving gate conductive portion, the driving gate conductive portion of the first pixel driving circuit including a third gate of a third transistor used as a driving transistor in the first pixel driving circuit and a first connection portion electrically connected to the third gate, and the driving gate conductive portion of the second pixel driving circuit including a third gate of a third transistor used as a driving transistor in the second pixel driving circuit and a first connection portion electrically connected to the third gate; The orthographic projection of the first anode structure on the base substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the base substrate to form a third overlapping area; The orthographic projection of the second anode structure on the base substrate at least partially overlaps with the orthographic projection of the driving gate conductive portion of the second pixel driving circuit on the base substrate to form a fourth overlapping area; and The ratio of the area of ​​the third overlapping region to the area of ​​the fourth overlapping region is between 0.8 and 1.

2.

2. The display substrate according to claim 1, wherein An orthographic projection area of ​​the driving gate conductive portion of the first pixel driving circuit on the base substrate is larger than an orthographic projection area of ​​the driving gate conductive portion of the second pixel driving circuit on the base substrate.

3. The display substrate according to claim 2, wherein: An orthographic projection area of ​​the first connection portion of the first pixel driving circuit on the base substrate is larger than an orthographic projection area of ​​the first connection portion of the second pixel driving circuit on the base substrate.

4. The display substrate according to claim 2 or 3, wherein: A ratio of an area of ​​an orthographic projection of the third gate of the first pixel driving circuit on the base substrate to an area of ​​an orthographic projection of the third gate of the second pixel driving circuit on the base substrate is between 0.8 and 1.

2.

5. The display substrate according to claim 4, wherein: The first anode structure includes an anode main portion and an anode extension portion, the anode extension portion extends from the anode main portion toward the first pixel driving circuit, and the positive projection of the third gate and the first connection portion of the first pixel driving circuit on the substrate at least partially overlaps with the positive projection of the anode extension portion of the first anode structure on the substrate to form the third overlapping area. The display substrate according to claim 5 , wherein: The orthographic projections of the third gate and the first connecting portion of the first pixel driving circuit on the base substrate are spaced apart from the orthographic projection of the anode main portion of the first anode structure on the base substrate.

7. The display substrate according to claim 6, wherein: The orthographic projections of the third gate and the first connecting portion of the second pixel driving circuit on the base substrate at least partially overlap with the orthographic projection of the anode main portion of the second anode structure on the base substrate to form the fourth overlapping region.

8. The display substrate according to claim 7, wherein: The first pixel driving circuit and the second pixel driving circuit each include a storage capacitor, the storage capacitor including a first storage capacitor electrode and a second storage capacitor electrode, the orthographic projections of the first storage capacitor electrode and the second storage capacitor electrode on the substrate at least partially overlap each other, and the first storage capacitor electrode includes the driving gate conductive portion; as well as An orthographic projection area of ​​the second storage capacitor electrode of the first pixel driving circuit on the base substrate is smaller than an orthographic projection area of ​​the second storage capacitor electrode of the second pixel driving circuit on the base substrate.

9. The display substrate according to claim 8, wherein: The area of ​​the orthographic projection of the driving gate conductive portion of the first pixel driving circuit on the base substrate at least partially overlaps with the orthographic projection of the second storage capacitor electrode of the first pixel driving circuit on the base substrate to form a fifth overlapping area; An orthographic projection of the driving gate conductive portion of the second pixel driving circuit on the base substrate at least partially overlaps with an orthographic projection of the second storage capacitor electrode of the second pixel driving circuit on the base substrate to form a sixth overlapping area; as well as The ratio of the area of ​​the fifth overlapping region to the area of ​​the sixth overlapping region is between 0.8 and 1.

2.

10. The display substrate according to claim 9, wherein: The display substrate comprises: A semiconductor layer disposed on the substrate; a first conductive layer located on a side of the semiconductor layer away from the substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; a third conductive layer located on a side of the second conductive layer away from the base substrate; and a first electrode layer located on a side of the third conductive layer away from the base substrate, The third gate is located in the first conductive layer, the second storage capacitor electrode is located in the second conductive layer, the first connecting portion is located in the third conductive layer, and the first anode structure and the second anode structure are located in the first electrode layer.

11. The display substrate according to claim 10, wherein: The second storage capacitor electrode includes a main body and a through hole in the main body, the through hole exposing a portion of the third gate covered by the second storage capacitor electrode, and the first connection portion is electrically connected to the third gate through the through hole; and The first connection portion of the first pixel driving circuit includes a conductive plug, the orthographic projection of the conductive plug on the base substrate falls within the orthographic projection of the through hole of the second storage capacitor electrode of the first pixel driving circuit on the base substrate, and the area of ​​the orthographic projection of the conductive plug of the first pixel driving circuit on the base substrate is greater than the area of ​​the orthographic projection of the conductive plug of the second pixel driving circuit on the base substrate.

12. The display substrate according to claim 11, wherein: The first connection portion of the first pixel driving circuit further includes a first connection sub-portion and a second connection sub-portion, the first connection sub-portion, the conductive plug and the second connection sub-portion forming an integrated structure; and The orthographic projections of the first connecting sub-portion and the second connecting sub-portion on the base substrate are located on opposite sides of the orthographic projection of the through hole on the base substrate.

13. The display substrate according to claim 12, wherein: An orthographic projection area of ​​the through hole of the second storage capacitor electrode of the first pixel driving circuit on the base substrate is larger than an orthographic projection area of ​​the through hole of the second storage capacitor electrode of the second pixel driving circuit on the base substrate.

14. The display substrate according to claim 4, wherein: The plurality of sub-pixels include adjacent sub-pixels in the (n+1)th row and sub-pixels in the (n)th row, the sub-pixels in the (n+1)th row include a plurality of sub-pixels of the first type, and the sub-pixels in the (n)th row include a plurality of sub-pixels of the second type, where n is a positive integer; as well as The orthographic projections of the first pixel driving circuits of the plurality of first-type sub-pixels in the n+1th row of sub-pixels and the second pixel driving circuits of the plurality of second-type sub-pixels in the nth row of sub-pixels on the substrate are arranged side by side in the same row along the first direction.

15. The display substrate according to claim 14, wherein: The first anode structures of the multiple first-type sub-pixels in the n+1th row of sub-pixels and the second anode structures of the multiple second-type sub-pixels in the nth row of sub-pixels are respectively arranged in different rows in their orthographic projections on the substrate, and the first anode structures and the second anode structures are alternately arranged along a first direction.

16. The display substrate according to claim 15, wherein: The anode extension portion of the first anode structure of the plurality of first-type sub-pixels in the (n+1)th row of sub-pixels is located in the first direction between the second anode structures of the two second-type sub-pixels in the (n)th row of sub-pixels.

17. The display substrate according to claim 16, wherein: The display substrate includes a plurality of pixel units arranged on the base substrate, each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; as well as At least one of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel of the same pixel unit is a sub-pixel of the first type, and at least another one of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel of the same pixel unit is a sub-pixel of the second type.

18. The display substrate according to claim 17, wherein: For any two pixel units adjacent to each other in the first direction, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel of one pixel unit is the first type of sub-pixel, and two of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel of the other pixel unit are the first type of sub-pixels.

19. The display substrate according to claim 17, wherein: For the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel belonging to the first type of sub-pixels, the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the third color sub-pixel on the substrate is larger than the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit of the second color sub-pixel on the substrate; and / or For the first color sub-pixel, the second color sub-pixel and the third color sub-pixel belonging to the first category of sub-pixels, the area of ​​the positive projection of the first connection part of the first pixel driving circuit of the second color sub-pixel on the base substrate is larger than the area of ​​the positive projection of the first connection part of the first pixel driving circuit of the first color sub-pixel on the base substrate.

20. The display substrate according to claim 4, wherein The display substrate further includes: a data signal line for transmitting a data signal; and a driving voltage line for transmitting a driving voltage; The data signal line, the driving voltage line and the first connection portion are all located in the third conductive layer; and The data signal line, the driving voltage line and the first connection portion all extend along a second direction.

21. The display substrate according to claim 4, wherein For sub-pixels of the same color belonging to the first category of sub-pixels and the second category of sub-pixels respectively, the ratio of the area of ​​the orthographic projection of the first connection portion of the first pixel driving circuit on the base substrate to the area of ​​the orthographic projection of the first connection portion of the second pixel driving circuit on the base substrate is between 1.1 and 1.

8.

22. The display substrate according to claim 5, wherein The width of the anode extension portion of the first anode structure in the first direction is smaller than the width of the anode main portion of the first anode structure in the first direction.

23. The display substrate according to claim 14, wherein: In adjacent sub-pixels in the (n+1)th row and the (n)th row, the first anode structures of the first-type sub-pixels are electrically connected to the first pixel driving circuit through their respective anode connection holes, and the second anode structures of the second-type sub-pixels are electrically connected to the second pixel driving circuit through their respective anode connection holes; as well as In the adjacent (n+1)th row of sub-pixels and (n)th row of sub-pixels, the anode connection holes of the first type of sub-pixels and the anode connection holes of the second type of sub-pixels are substantially located on the same straight line.

24. The display substrate according to claim 23, wherein: The orthographic projection of the first anode structure on the base substrate covers the orthographic projection of the anode connection hole thereof on the base substrate; and The anode main portion and the anode extension portion of the first anode structure are located on opposite sides of the anode connection hole in the second direction.

25. The display substrate according to claim 1, wherein The orthographic projection of the first pixel driving circuit on the base substrate and the orthographic projection of the second pixel driving circuit on the base substrate are arranged side by side in the same row along a first direction.

26. The display substrate according to claim 20, wherein The display substrate also includes a blocking portion located in the second conductive layer, the driving voltage line includes a bending portion, the bending portion bends in a direction away from the data signal line adjacent to the driving voltage line, and the orthographic projection of the bending portion of the driving voltage line on the base substrate at least partially overlaps with the orthographic projection of the blocking portion on the base substrate.

27. A display device comprising the display substrate according to any one of claims 1 to 26.