Display substrate and manufacturing method therefor, and display apparatus

Abstract

The present disclosure provides a display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises: a plurality of first gate driving circuits and a plurality of second gate driving circuits, wherein timings of first gate driving signals output by the first gate driving circuits and second gate driving signals output by the second gate driving circuits are different, and the first gate driving circuits and the second gate driving circuits share at least one signal line.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the rapid development of intelligent technology, market demand and expectations for smart terminal display devices are increasing. Smart terminal display devices such as mobile phones and tablets are becoming increasingly important in people's lives. In addition, more diverse application scenarios have led people to pursue full-screen displays while also hoping to enjoy larger sizes and higher resolutions. In order to optimize display effects, low-frequency display to reduce power consumption has become a key focus.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a method for manufacturing the same, and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a plurality of first gate driving circuits and a plurality of second gate driving circuits, wherein the first gate driving signals output by the first gate driving circuits and the second gate driving signals output by the second gate driving circuits have different timings; and the first gate driving circuits and the second gate driving circuits share at least one signal line.

[0007] Optionally, the display substrate includes a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits and the plurality of second gate driving circuits are both located in the peripheral area;

[0008] In a peripheral area close to a same side of the display area, at least a portion of the first gate driving circuit and at least a portion of the second gate driving circuit are arranged in a mirror image.

[0009] Optionally, the first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal with a first level.

[0010] Optionally, at least a portion of the orthographic projection of the first level signal line on the base substrate of the display substrate is located between the orthographic projection of the first gate driving circuit on the base substrate and the orthographic projection of the second gate driving circuit on the base substrate.

[0011] Optionally, the orthographic projection of the first-level signal line on the base substrate at least partially overlaps with the orthographic projection of the first gate drive circuit on the base substrate; and / or the orthographic projection of the first-level signal line on the base substrate at least partially overlaps with the orthographic projection of the second gate drive circuit on the base substrate.

[0012] Optionally, the first gate drive circuit and the second gate drive circuit share a first clock signal line and / or a second clock signal line, and the first clock signal transmitted by the first clock signal line and the second clock signal transmitted by the second clock signal line have opposite phases.

[0013] Optionally, at least part of the first gate drive circuit and at least part of the second gate drive circuit are mirror-symmetrical about a first symmetry axis; the first symmetry axis at least partially overlaps with the first clock signal line, or the first symmetry axis at least partially overlaps with the second clock signal line, or the first symmetry axis at least partially overlaps with the first level signal line.

[0014] Optionally, the orthographic projection of the first level signal line on the base substrate is located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate.

[0015] Optionally, the orthographic projection of the first clock signal line on the substrate at least partially overlaps with the orthographic projection of one of the first gate drive circuit and the second gate drive circuit on the substrate; the orthographic projection of the second clock signal line on the substrate at least partially overlaps with the orthographic projection of the other of the first gate drive circuit and the second gate drive circuit on the substrate.

[0016] Optionally, the first gate driving circuit is coupled to a first frame start signal line, and the second gate driving circuit is coupled to a second frame start signal line.

[0017] Optionally, the orthographic projection of the first level signal line on the base substrate is located between the orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate.

[0018] Optionally, the orthographic projection of the first frame start signal line on the substrate at least partially overlaps with the orthographic projection of the first gate drive circuit on the substrate; the orthographic projection of the second frame start signal line on the substrate at least partially overlaps with the orthographic projection of the second gate drive circuit on the substrate.

[0019] Optionally, the orthographic projection of the first frame start signal line on the substrate and the orthographic projection of the second frame start signal line on the substrate are located between the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate.

[0020] Optionally, at least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line is made of the second source and drain metal layer in the display substrate.

[0021] Optionally, at least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line includes two stacked conductive layers, one conductive layer is made of the second source and drain metal layer, and the other conductive layer is made of the third source and drain metal layer in the display substrate.

[0022] Optionally, the channel width-to-length ratio of the output transistor included in the first gate drive circuit is equal to the channel width-to-length ratio of the output transistor included in the second gate drive circuit.

[0023] Optionally, the channel width-to-length ratio of the output transistor included in the first gate drive circuit is greater than the channel width-to-length ratio of the output transistor included in the second gate drive circuit.

[0024] Optionally, at least some target devices having the same function in the first gate driving circuit and the second gate driving circuit are coupled.

[0025] Optionally, the display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines, a plurality of second initialization signal lines, and a plurality of third initialization signal lines, wherein the first sub-pixel driving circuit includes a first driving transistor, a first data writing transistor, a first compensation transistor, a second reset transistor, and a third reset transistor;

[0026] The gate of the first data writing transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the first data writing transistor is coupled to the corresponding data line, and the second electrode of the first data writing transistor is coupled to the first electrode of the first driving transistor;

[0027] The gate of the first compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the first compensation transistor is coupled to the second electrode of the first driving transistor, and the second electrode of the first compensation transistor is coupled to the gate of the first driving transistor;

[0028] The gate of the second reset transistor is coupled to the output terminal of the corresponding second gate driving circuit, the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the second reset transistor is coupled to the corresponding light emitting element;

[0029] The gate of the third reset transistor is coupled to the output end of the corresponding second gate driving circuit, the first electrode of the third reset transistor is coupled to the corresponding third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the first driving transistor.

[0030] Optionally, the display substrate further includes a plurality of second sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines and a plurality of second initialization signal lines, wherein the second sub-pixel driving circuit includes a second driving transistor, a second data writing transistor, a second compensation transistor and a second reset transistor;

[0031] The gate of the second data writing transistor is coupled to the output terminal of the corresponding second gate driving circuit, the first electrode of the second data writing transistor is coupled to the corresponding data line, and the second electrode of the second data writing transistor is coupled to the first electrode of the second driving transistor;

[0032] The gate of the second compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the second compensation transistor is coupled to the second electrode of the second driving transistor, and the second electrode of the second compensation transistor is coupled to the gate of the second driving transistor;

[0033] A gate of the second reset transistor is coupled to an output terminal of the corresponding second gate driving circuit, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to a corresponding light-emitting element.

[0034] Optionally, the display substrate further includes:

[0035] a first electrostatic discharge circuit coupled to the first gate driving circuit;

[0036] a second electrostatic discharge circuit coupled to the second gate drive circuit;

[0037] The first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged in a mirror image, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line.

[0038] Optionally, the surrounding area also includes:

[0039] Multiple light-emitting control driving circuits are divided into multiple groups of light-emitting control driving circuits, each group of light-emitting control driving circuits includes two light-emitting control driving circuits arranged in a mirror image, and the two light-emitting control driving circuits share at least one signal line.

[0040] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0041] Based on the technical solution of the above display substrate, a third aspect of the present disclosure provides a method for manufacturing a display substrate, which is used to manufacture the above display substrate. The manufacturing method includes:

[0042] A plurality of first gate drive circuits and a plurality of second gate drive circuits are manufactured, wherein the first gate drive signal output by the first gate drive circuit and the second gate drive signal output by the second gate drive circuit have different timings; the first gate drive circuit and the second gate drive circuit share at least one signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0044] FIG1 is a schematic diagram showing how the display brightness of a display substrate changes over time according to an embodiment of the present disclosure;

[0045] FIG2 is a schematic diagram of the circuit structure of an 8T1C provided in an embodiment of the present disclosure;

[0046] FIG3 is a timing diagram of the operation of the display substrate during image refresh and image retention according to an embodiment of the present disclosure;

[0047] FIG4 is a timing diagram of a gate drive circuit driving an 8T1C circuit structure according to an embodiment of the present disclosure;

[0048] FIG5 is a schematic diagram of the circuit structure of a 7T1C provided in an embodiment of the present disclosure;

[0049] FIG6 is a timing diagram of a gate drive circuit driving a 7T1C circuit structure according to an embodiment of the present disclosure;

[0050] FIG7 is a schematic diagram of a first layout of a gate driving circuit provided in an embodiment of the present disclosure;

[0051] FIG8 is a schematic diagram of a first layout of a first gate driving circuit and a second gate driving circuit provided in an embodiment of the present disclosure;

[0052] FIG9 is a schematic diagram of the layout of the active layer and the first gate metal layer in FIG7 ;

[0053] FIG10 is a schematic diagram of the layout of the second gate metal layer in FIG7 ;

[0054] FIG11 is a schematic diagram of a via hole formed on the interlayer insulating layer in FIG7 ;

[0055] FIG12 is a schematic diagram of the layout of the first source and drain metal layer in FIG7 ;

[0056] FIG13 is a schematic diagram of the layout of a gate driving circuit and an electrostatic discharge circuit provided in an embodiment of the present disclosure;

[0057] FIG14 is a schematic diagram of the circuit structure of an electrostatic discharge circuit provided in an embodiment of the present disclosure;

[0058] FIG15 is a schematic diagram of the layout of the active layer and the first gate metal layer in FIG13;

[0059] FIG16 is a schematic diagram of a via hole formed on the interlayer insulating layer in FIG13;

[0060] FIG17 is a schematic diagram of the layout of the first source and drain metal layer in FIG13;

[0061] FIG18 is a second schematic layout diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0062] FIG19 is a schematic diagram of the layout of the active layer and the first gate metal layer in FIG18;

[0063] FIG20 is a schematic diagram of a via hole formed on the interlayer insulating layer in FIG18;

[0064] FIG21 is a schematic diagram of the layout of the first source / drain metal layer in FIG18 ;

[0065] FIG22 is a schematic diagram of a via hole formed on the first passivation layer in FIG18 ;

[0066] FIG23 is a schematic diagram of a via hole formed on the first planar layer in FIG18;

[0067] FIG24 is a schematic diagram of the layout of the second source / drain metal layer in FIG18 ;

[0068] FIG25 is a schematic diagram of a third layout of a gate driving circuit provided in an embodiment of the present disclosure;

[0069] FIG26 is a fourth schematic diagram of a layout of a gate driving circuit provided in an embodiment of the present disclosure;

[0070] FIG27 is a circuit structure diagram of the light emitting control driving circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0072] Referring to Table 1, Figures 2 and 3, in the sub-pixel driving circuit, the voltages of the T2M and T1M nodes around the N1 node cause leakage on the N1 node, causing the voltage of the N1 node to be continuously high within a frame (e.g., △N1 = 0.0713 V), making it impossible to maintain stability. This results in dimming of the brightness (e.g., a potential change of △N4 = 0.064 V at the N4 node). As shown in Figure 1, the human eye can clearly observe the change in brightness and observe flickering on the screen.

[0073]

[0074] Table 1

[0075] Since the main factor causing screen flicker is the voltage change of the N1 node within a frame, in order to improve the problem of low-frequency flicker, a set of gate drive circuits is added for driving.

[0076] As shown in Figures 2 and 3, during low-frequency display, the longV mode is used for driving the display. That is, the light-emitting control signal EM has multiple pulses within one frame. The first pulse of the light-emitting control signal EM is the screen refresh frame, which implements data signal writing; the second and third pulses of the light-emitting control signal EM (not shown in the figure) are the screen hold frames, which reset the anode of the light-emitting element.

[0077] In more detail, a sub-pixel driving circuit including an 8T1C (ie, 8 transistors and 1 capacitor) circuit structure is taken as an example.

[0078] In the screen refresh frame, there are three voltage writing stages. The first stage is that the reset signal (transmitted by the reset signal line Reset) and the second gate drive signal (transmitted by the second scan line Gate2) are turned on at a low level, the N1 node is reset to the first initialization signal (transmitted by the first initialization signal line VINIT1), and the N2 node is reset to the third initialization signal (transmitted by the third initialization signal line VINIT3); the second stage is the repeated reset stage of the N1 node; the third stage is that the first gate drive signal (transmitted by the first scan line Gate1) is turned on at a low level, and the data signal (transmitted by the data line Vdata) is written to the N1 node; then the light-emitting control signal EM is at a low level, and the pixel emits light.

[0079] In the picture holding frame, there is stage ④, in which the light-emitting control signal EM is turned off at a high level and the second gate drive signal is turned on at a low level. At this time, the anode of the light-emitting element is reset to the second initialization signal (transmitted by the second initialization signal line VINIT2), and the N2 node is reset to the third initialization signal (for example: the voltage value of the third initialization signal is 2V); then the light-emitting control signal EM is turned on at a low level, and the pixel emits light.

[0080] The display substrate provided by the present disclosure comprises a first gate drive circuit, a second gate drive circuit, and a light-emission control drive circuit. The light-emission control drive circuit drives a multi-pulse light-emission control signal EM output within a frame to control light emission. The second gate drive circuit drives a multi-pulse second gate drive signal output within a frame to control anode reset and N2 node reset. The first gate drive circuit drives a three-pulse first gate drive signal output within a frame to control data signal writing and N1 node reset.

[0081] Since the display substrate provided in the present application includes multiple gate driving circuits, how to take into account the demand for a narrow frame of the display substrate becomes the focus.

[0082] Referring to Figures 4, 6, 7 and 12, an embodiment of the present disclosure provides a display substrate, including: multiple first gate driving circuits Gate1-GOA and multiple second gate driving circuits Gate2-GOA, the first gate driving signal GOUT1 output by the first gate driving circuit Gate1-GOA and the second gate driving signal GOUT2 output by the second gate driving circuit Gate2-GOA have different timings; the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA share at least one signal line.

[0083] Exemplarily, the first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA are connected to the same sub-pixel driving circuit.

[0084] Exemplarily, the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are connected to the sub-pixel driving circuit of the same row; or, the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are connected to the sub-pixel driving circuit of the same color.

[0085] Exemplarily, the first gate drive circuit Gate1-GOA includes multiple transistors and storage capacitors, and the first gate drive circuit Gate1-GOA is respectively coupled to the first level signal line VGH, the second level signal line VGL, the first clock signal line GCK, the second clock signal line GCB and the first frame start signal line GSTV1. The multiple transistors and storage capacitors included in the first gate drive circuit Gate1-GOA are jointly controlled by the corresponding signals provided by the above-mentioned signal lines to output the first gate drive signal GOUT1.

[0086] Exemplarily, the second gate drive circuit Gate2-GOA includes multiple transistors and storage capacitors, and the second gate drive circuit Gate2-GOA is respectively coupled to the first level signal line VGH, the second level signal line VGL, the first clock signal line GCK, the second clock signal line GCB and the second frame start signal line GSTV2. The multiple transistors and storage capacitors included in the second gate drive circuit Gate2-GOA are jointly controlled by the corresponding signals provided by the above-mentioned signal lines to output the second gate drive signal GOUT2.

[0087] In more detail, as shown in FIG8 to FIG12 , the circuit structures of the first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA are substantially the same.

[0088] The first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA include a first transistor T1 to an eighth transistor T8 , a first capacitor C1 and a second capacitor C2 .

[0089] A gate of the first transistor T1 is coupled to the first clock signal line GCK, a first electrode of the first transistor T1 is coupled to the first frame start signal line GSTV1, and a second electrode of the first transistor T1 is coupled to the gate of the second transistor T2.

[0090] A first electrode of the second transistor T2 is coupled to the first clock signal line GCK, and a second electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3 .

[0091] A gate of the third transistor T3 is coupled to the first clock signal line GCK, and a first electrode of the third transistor T3 is coupled to the second level signal line VGL.

[0092] The gate of the fourth transistor T4 is coupled to the second electrode of the third transistor T3. The second electrode of the fourth transistor T4 serves as the output end of the gate drive circuit. The output end outputs the first gate drive signal GOUT1 in the first gate drive circuit Gate1-GOA, and the output end outputs the second gate drive signal GOUT2 in the second gate drive circuit Gate2-GOA.

[0093] A first plate C21 of the second capacitor C2 is coupled to the gate of the fourth transistor T4 , and a second plate C22 of the second capacitor C2 is coupled to the first electrode of the fourth transistor T4 .

[0094] A gate of the fifth transistor T5 is coupled to the second electrode of the eighth transistor T8 , a first electrode of the fifth transistor T5 is coupled to the second clock signal line GCB, and a second electrode of the fifth transistor T5 is coupled to the second electrode of the fourth transistor T4 .

[0095] A first plate C11 of the first capacitor C1 is coupled to the gate of the fifth transistor T5 , and a second plate C12 of the first capacitor C1 is coupled to the second electrode of the fifth transistor T5 .

[0096] A gate of the sixth transistor T6 is coupled to the gate of the fourth transistor T4 , a first electrode of the sixth transistor T6 is coupled to the first level signal line VGH, and a second electrode of the sixth transistor T6 is coupled to the first electrode of the seventh transistor T7 .

[0097] A gate of the seventh transistor T7 is coupled to the second clock signal line GCB, and a second electrode of the seventh transistor T7 is coupled to the second electrode of the first transistor T1 .

[0098] A gate of the eighth transistor T8 is coupled to the second level signal line VGL, and a first electrode of the eighth transistor T8 is coupled to a second electrode of the seventh transistor T7.

[0099] Illustratively, the first-level signal transmitted by the first-level signal line VGH coupled to the first gate driver circuit Gate1-GOA is identical to the first-level signal transmitted by the first-level signal line VGH coupled to the second gate driver circuit Gate2-GOA. The second-level signal transmitted by the second-level signal line VGL coupled to the first gate driver circuit Gate1-GOA is identical to the second-level signal transmitted by the second-level signal line VGL coupled to the second gate driver circuit Gate2-GOA. The first clock signal transmitted by the first clock signal line GCK coupled to the first gate driver circuit Gate1-GOA is identical to the first clock signal transmitted by the first clock signal line GCK coupled to the second gate driver circuit Gate2-GOA. The second clock signal transmitted by the second clock signal line GCB coupled to the first gate driver circuit Gate1-GOA is identical to the second clock signal transmitted by the second clock signal line GCB coupled to the second gate driver circuit Gate2-GOA.

[0100] It is worth noting that since the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA are both a row of gate drive circuits driving a row of pixels, that is, a one-to-one drive design, the first clock signal connected to the first gate drive circuit Gate1-GOA and the first clock signal connected to the second gate drive circuit Gate2-GOA have the same pulse width and frequency, and the second clock signal connected to the first gate drive circuit Gate1-GOA and the second clock signal connected to the second gate drive circuit Gate2-GOA have the same pulse width and frequency.

[0101] Exemplarily, the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA share at least one of the first level signal line VGH, the second level signal line VGL, the first clock signal line GCK and the second clock signal line GCB.

[0102] Exemplarily, the line width of the signal line shared by the first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA is greater than the line width of the signal line not shared, but is not limited thereto.

[0103] Optionally, the line width of the first clock signal line GCK and the line width of the second clock signal line GCB are both greater than the line width of the first level signal line VGH, and are both greater than the line width of the second level signal line VGL.

[0104] Optionally, the line width of the first level signal line VGH is greater than the line widths of the first clock signal line GCK and the second clock signal line GCB, and greater than the line width of the second level signal line VGL.

[0105] According to the specific structure of the display substrate described above, the display substrate provided in the embodiment of the present disclosure effectively improves the low-frequency flicker problem of the display substrate by configuring the display substrate to include multiple first gate drive circuits Gate1-GOA and multiple second gate drive circuits Gate2-GOA. Furthermore, by configuring the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA to share at least one signal line, the width of the border jointly occupied by the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA, as well as the signal line connecting the two, is effectively reduced. This not only facilitates a narrow border for the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0106] As shown in FIG7 to FIG12, in some embodiments, the display substrate includes a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits Gate1-GOA and the plurality of second gate driving circuits Gate2-GOA are both located in the peripheral area;

[0107] In a peripheral area close to the same side of the display area, at least a portion of the first gate driving circuit Gate1 -GOA and at least a portion of the second gate driving circuit Gate2 -GOA are arranged in a mirror image.

[0108] Exemplarily, the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA may be distributed on the left frame and / or the right frame of the display substrate.

[0109] As shown in Figures 9, 10, and 12, illustratively, at least a portion of the first gate driver circuit Gate1-GOA and at least a portion of the second gate driver circuit Gate2-GOA are mirror-imaged on the left and / or right borders of the display substrate. Exemplarily, the mirrored portions include transistors, capacitors, and / or conductive connections, but are not limited thereto.

[0110] Exemplarily, the orthographic projection of at least part of the first gate driving circuit Gate1-GOA on the base substrate of the display substrate is mirror-symmetric to the orthographic projection of at least part of the second gate driving circuit Gate2-GOA on the base substrate about a first symmetry axis, and the orthographic projection of the first symmetry axis on the base substrate is located between the orthographic projection of the first gate driving circuit Gate1-GOA on the base substrate and the orthographic projection of the second gate driving circuit Gate2-GOA on the base substrate.

[0111] As shown in Figures 9, 10, and 12, illustratively, when at least a portion of the first gate drive circuit Gate1-GOA and at least a portion of the second gate drive circuit Gate2-GOA are mirror-imaged, the fourth transistor T4 in the first gate drive circuit Gate1-GOA is located on a side of the first gate drive circuit Gate1-GOA away from the second gate drive circuit Gate2-GOA. The fifth transistor T5 in the first gate drive circuit Gate1-GOA is located on a side of the first gate drive circuit Gate1-GOA away from the second gate drive circuit Gate2-GOA.

[0112] As shown in Figures 9, 10, and 12, illustratively, when at least a portion of the first gate drive circuit Gate1-GOA and at least a portion of the second gate drive circuit Gate2-GOA are mirror-imaged, the fourth transistor T4 in the second gate drive circuit Gate2-GOA is located on a side of the second gate drive circuit Gate2-GOA that is away from the first gate drive circuit Gate1-GOA. The fifth transistor T5 in the second gate drive circuit Gate2-GOA is located on a side of the second gate drive circuit Gate2-GOA that is away from the first gate drive circuit Gate1-GOA.

[0113] In the display substrate provided in the above embodiment, by setting at least a portion of the first gate drive circuit Gate1-GOA and at least a portion of the second gate drive circuit Gate2-GOA in a mirror image, the space occupied by the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA can be compressed to a minimum, and at the same time, it is beneficial to realize the sharing of signal lines, thereby achieving the purpose of narrowing the frame of the display substrate.

[0114] As shown in FIG. 7 to FIG. 12 , in some embodiments, the first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA are configured to share a first level signal line VGH, and the first level signal line VGH transmits a DC signal with a first level.

[0115] Exemplarily, the first level signal line VGH includes at least a portion extending along a first direction, an orthographic projection of the first gate drive circuit Gate1-GOA on the base substrate and an orthographic projection of the second gate drive circuit Gate2-GOA on the base substrate are arranged along a second direction, and the first direction intersects the second direction. Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a lateral direction, but is not limited thereto.

[0116] The above configuration effectively reduces the width of the frame shared by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA, and the first level signal line VGH connected thereto, which is not only conducive to narrowing the frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0117] As shown in Figures 7 to 12, in some embodiments, at least a portion of the positive projection of the first level signal line VGH on the base substrate of the display substrate is set to be located between the positive projection of the first gate driving circuit Gate1-GOA on the base substrate and the positive projection of the second gate driving circuit Gate2-GOA on the base substrate.

[0118] The above-mentioned setting method enables at least part of the first gate drive circuit Gate1-GOA and at least part of the second gate drive circuit Gate2-GOA to be respectively located on both sides of the first level signal line VGH. Since the first level signal line VGH transmits a DC signal with a stable potential, the above-mentioned setting method is beneficial for the first level signal line VGH to shield the signal interference between the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA, thereby effectively improving the stability of the display substrate.

[0119] As shown in Figures 18 to 24, in some embodiments, the orthographic projection of the first level signal line VGH on the base substrate is set to at least partially overlap with the orthographic projection of the first gate drive circuit Gate1-GOA on the base substrate; and / or the orthographic projection of the first level signal line VGH on the base substrate is set to at least partially overlap with the orthographic projection of the second gate drive circuit Gate2-GOA on the base substrate.

[0120] Exemplarily, the orthographic projection of the first-level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the transistor included in the first gate drive circuit Gate1-GOA on the base substrate; and / or, the orthographic projection of the first-level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the transistor included in the second gate drive circuit Gate2-GOA on the base substrate.

[0121] For example, as shown in Figures 18 and 19, the orthographic projection of the first level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the gate of the first transistor T1 included in the first gate drive circuit Gate1-GOA on the base substrate; the orthographic projection of the first level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the gate of the seventh transistor T7 included in the first gate drive circuit Gate1-GOA on the base substrate.

[0122] For example, as shown in Figures 18 and 19, the orthographic projection of the first-level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the gate of the first transistor T1 included in the second gate drive circuit Gate2-GOA on the base substrate; the orthographic projection of the first-level signal line VGH on the base substrate at least partially overlaps with the orthographic projection of the gate of the seventh transistor T7 included in the second gate drive circuit Gate2-GOA on the base substrate.

[0123] The above configuration further reduces the width of the frame occupied by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA and the signal lines connecting the two, which is not only conducive to the narrow frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0124] As shown in Figures 7 to 12 and Figures 18 to 24, in some embodiments, the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA are set to share a first clock signal line GCK and / or a second clock signal line GCB, and the first clock signal transmitted by the first clock signal line GCK and the second clock signal transmitted by the second clock signal line GCB have opposite phases.

[0125] Exemplarily, the first clock signal line GCK includes at least a portion extending along the first direction, the second clock signal line GCB includes at least a portion extending along the first direction, and the first clock signal line GCK and the second clock signal line GCB are arranged along the second direction.

[0126] In the display substrate provided by the above embodiment, by setting the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA to share the first clock signal line GCK and / or the second clock signal line GCB, it is possible to reduce a group of clock signal lines while ensuring the normal driving of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA, thereby effectively reducing the border width jointly occupied by the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA and the signal lines connecting the two, which is not only conducive to the narrow border of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0127] In some embodiments, at least a portion of the first gate driving circuit Gate1-GOA and at least a portion of the second gate driving circuit Gate2-GOA are mirror-symmetrical about a first symmetry axis;

[0128] The first symmetric axis at least partially overlaps with the first clock signal line GCK, as shown in Figures 7 to 12, or the first symmetric axis at least partially overlaps with the second clock signal line GCB, as shown in Figures 18 to 25, or the first symmetric axis at least partially overlaps with the first level signal line VGH.

[0129] The above-mentioned setting of the first symmetry axis overlapping with the common signal line, the first clock signal line GCK, the second clock signal line GCB or the first level signal line VGH enables at least a portion of the first gate drive circuit Gate1-GOA and at least a portion of the second gate drive circuit Gate2-GOA to be respectively located on both sides of the common signal line, thereby well ensuring the connection reliability between the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA and the common signal line, and reducing the layout difficulty of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA.

[0130] The above-mentioned setting makes the first symmetry axis at least partially overlap with the first level signal line VGH, so that at least part of the first gate drive circuit Gate1-GOA and at least part of the second gate drive circuit Gate2-GOA are respectively located on both sides of the first level signal line VGH. Since the first level signal line VGH transmits a DC signal with a stable potential, the above-mentioned setting method is beneficial for the first level signal line VGH to shield the signal interference between the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA, thereby effectively improving the stability of the display substrate.

[0131] As shown in Figures 18 to 25, in some embodiments, the orthographic projection of the first level signal line VGH on the base substrate is set between the orthographic projection of the first clock signal line GCK on the base substrate and the orthographic projection of the second clock signal line GCB on the base substrate.

[0132] The above-mentioned setting method enables the first clock signal line GCK and the second clock signal line GCB to be respectively located on both sides of the first level signal line VGH, so that the first level signal line VGH effectively shields the interference between the first clock signal line GCK and the second clock signal line GCB, thereby ensuring the working stability of the gate drive circuit.

[0133] As shown in Figures 18 to 24, in some embodiments, the orthographic projection of the first clock signal line GCK on the base substrate at least partially overlaps with the orthographic projection of one of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the base substrate; the orthographic projection of the second clock signal line GCB on the base substrate at least partially overlaps with the orthographic projection of the other of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the base substrate.

[0134] Exemplarily, the orthographic projection of the first clock signal line GCK on the substrate at least partially overlaps with the orthographic projection of the transistor included in one of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the substrate; the orthographic projection of the second clock signal line GCB on the substrate at least partially overlaps with the orthographic projection of the transistor included in the other of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the substrate.

[0135] Exemplarily, the orthographic projection of the first clock signal line GCK on the substrate at least partially overlaps with the orthographic projection of the capacitor structure included in one of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the substrate; the orthographic projection of the second clock signal line GCB on the substrate at least partially overlaps with the orthographic projection of the capacitor structure included in the other of the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA on the substrate.

[0136] As shown in Figures 18 and 19, the orthographic projection of the first clock signal line GCK on the substrate at least partially overlaps with the orthographic projection of the gate of the first transistor T1 included in the first gate drive circuit Gate1-GOA on the substrate, the orthographic projection of the active pattern of the second transistor T2 included in the first gate drive circuit Gate1-GOA on the substrate, and the orthographic projection of the second capacitor included in the first gate drive circuit Gate1-GOA on the substrate.

[0137] As shown in Figures 18 and 19, the orthographic projection of the second clock signal line GCB on the substrate at least partially overlaps with the orthographic projection of the gate of the first transistor T1 included in the second gate drive circuit Gate2-GOA on the substrate, the orthographic projection of the active pattern of the second transistor T2 included in the second gate drive circuit Gate2-GOA on the substrate, and the orthographic projection of the second capacitor included in the second gate drive circuit Gate2-GOA on the substrate.

[0138] The above configuration further reduces the width of the frame occupied by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA and the signal lines connecting the two, which is not only conducive to the narrow frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0139] As shown in Figures 7 to 12 and Figures 18 to 24, in some embodiments, the first gate driving circuit Gate1-GOA is coupled to the first frame start signal line GSTV1, and the second gate driving circuit Gate2-GOA is coupled to the second frame start signal line GSTV2.

[0140] Exemplarily, the first frame start signal line GSTV1 includes at least a portion extending along the first direction, and the second frame start signal line GSTV2 includes at least a portion extending along the first direction. The first frame start signal line GSTV1 and the second frame start signal line GSTV2 can be independently controlled.

[0141] In the display substrate provided in the above embodiment, the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA are set to be connected to their respective original frame start signal lines, and keep access to their respective original frame start signals, so that when the gate drive signals are subsequently debugged, it is still possible to control the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA to output different pulses by adjusting the respective accessed frame start signals, thereby achieving the purpose of driving low-frequency pixels.

[0142] As shown in Figures 7 to 12 and Figures 18 to 24, in some embodiments, the orthographic projection of the first level signal line VGH on the base substrate is set to be between the orthographic projection of the first frame start signal line GSTV1 on the base substrate and the orthographic projection of the second frame start signal line GSTV2 on the base substrate.

[0143] The above setting method enables the first frame start signal line GSTV1 and the second frame start signal line GSTV2 to be located on both sides of the first level signal line VGH, respectively, so that the first level signal line VGH effectively shields the interference between the first frame start signal line GSTV1 and the second frame start signal line GSTV2, thereby ensuring the working stability of the gate drive circuit.

[0144] For example, as shown in Figures 7 to 12, in some embodiments, the first clock signal line GCK, the second clock signal line GCB, the first level signal line VGH, the first frame start signal line GSTV1, and the second frame start signal GSTV2 are located between the first gate driver circuit Gate1-GOA and the second gate driver circuit Gate2-GOA. For example, the first frame start signal line GSTV1 and the second frame start signal GSTV2 are located on the same side of the second clock signal line GCB; and the first clock signal line GCK and the first level signal line VGH are located on the same side of the second clock signal line GCB.

[0145] For example, as shown in Figures 7 to 12, in some embodiments, the first frame start signal line GSTV1 and the second frame start signal line GSTV2 are located on the same side of the second clock signal line GCB, the first frame start signal line GSTV1 is coupled to the first gate driver circuit Gate1-GOA, the second frame start signal line GSTV2 is coupled to the second gate driver circuit Gate2-GOA, and the distance between the first frame start signal line GSTV1 and the first gate driver circuit Gate1-GOA is greater than the distance between the second frame start signal line GSTV2 and the second gate driver circuit Gate2-GOA. For example, the distance between the first frame start signal line GSTV1 and the first transistor T1 of the first gate driver circuit Gate1-GOA (i.e., the length of the connecting line segment from the first transistor T1 of the first gate driver circuit Gate1-GOA to GSTV1) is greater than the distance between the second frame start signal line GSTV2 and the first transistor T1 of the second gate driver circuit Gate2-GOA (i.e., the length of the connecting line segment from the first transistor T1 of the second gate driver circuit Gate2-GOA to the second frame start signal line GSTV2).

[0146] For example, as shown in Figures 7 to 12, in some embodiments, the distance from the output end of the first gate driver circuit Gate1-GOA to the sub-pixel (or sub-pixel driver circuit) is less than the distance from the output end of the second gate driver circuit Gate2-GOA to the same sub-pixel (or sub-pixel driver circuit). For example, the distance from the output end of the first gate driver circuit Gate1-GOA (e.g., the drain of the fifth transistor T5) to the sub-pixel (or sub-pixel driver circuit) (e.g., the length of the GOUT1 connecting line segment) is less than the distance from the output end of the second gate driver circuit Gate2-GOA (e.g., the drain of the fifth transistor T5) to the sub-pixel (or sub-pixel driver circuit) (e.g., the length of the GOUT2 connecting line segment).

[0147] For example, as shown in Figures 7 to 12, in some embodiments, the output terminal GOUT2 of the second gate driver circuit Gate2-GOA (the connecting line segment of the second gate driver circuit Gate2-GOA coupled to the sub-pixel) overlaps with the first clock signal line GCK, the second clock signal line GCB, the first level signal line VGH, the first frame start signal line GSTV1, and the second frame start signal GSTV2. For example, the orthographic projection of the output terminal GOUT2 of the second gate driver circuit Gate2-GOA on the substrate is perpendicular to the orthographic projection of the first clock signal line GCK, the second clock signal line GCB, the first level signal line VGH, the first frame start signal line GSTV1, and the second frame start signal GSTV2 on the substrate.

[0148] As shown in Figures 18 to 24, in some embodiments, the orthographic projection of the first frame start signal line GSTV1 on the base substrate at least partially overlaps with the orthographic projection of the first gate drive circuit Gate1-GOA on the base substrate; the orthographic projection of the second frame start signal line GSTV2 on the base substrate at least partially overlaps with the orthographic projection of the second gate drive circuit Gate2-GOA on the base substrate.

[0149] Exemplarily, the orthographic projection of the first frame start signal line GSTV1 on the substrate at least partially overlaps with the orthographic projection of the transistor included in the first gate drive circuit Gate1-GOA on the substrate; the orthographic projection of the second frame start signal line GSTV2 on the substrate at least partially overlaps with the orthographic projection of the transistor included in the second gate drive circuit Gate2-GOA on the substrate.

[0150] As shown in Figures 18 and 19, the orthographic projection of the first frame start signal line GSTV1 on the base substrate at least partially overlaps with the orthographic projection of the active pattern of the first transistor T1 included in the first gate drive circuit Gate1-GOA on the base substrate, the orthographic projection of the active pattern of the sixth transistor T6 included in the first gate drive circuit Gate1-GOA on the base substrate, and the orthographic projection of the active pattern of the seventh transistor T7 included in the first gate drive circuit Gate1-GOA on the base substrate.

[0151] As shown in Figures 18 and 19, the orthographic projection of the second frame start signal line GSTV2 on the base substrate at least partially overlaps with the orthographic projection of the active pattern of the first transistor T1 included in the second gate drive circuit Gate2-GOA on the base substrate, the orthographic projection of the active pattern of the sixth transistor T6 included in the second gate drive circuit Gate2-GOA on the base substrate, and the orthographic projection of the active pattern of the seventh transistor T7 included in the second gate drive circuit Gate2-GOA on the base substrate.

[0152] The above configuration further reduces the border width jointly occupied by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA, and the frame start signal line connected thereto, which is not only conducive to narrowing the border of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0153] As shown in Figures 18 to 25, in some embodiments, the orthographic projection of the first frame start signal line GSTV1 on the substrate substrate and the orthographic projection of the second frame start signal line GSTV2 on the substrate substrate are set between the orthographic projection of the first clock signal line GCK on the substrate substrate and the orthographic projection of the second clock signal line GCB on the substrate substrate.

[0154] The above configuration allows the first clock signal line GCK and the second clock signal line GCB to be spaced farther apart, thereby better shielding interference caused by signal transitions between the first clock signal line GCK and the second clock signal line GCB.

[0155] As shown in Figure 24, in some embodiments, at least one of the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame start signal line GSTV2 is made of the second source and drain metal layer in the display substrate.

[0156] Exemplarily, the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a first passivation layer, a first planarizing layer, a second source-drain metal layer, a second passivation layer, a second planarizing layer, etc., which are stacked in sequence on the base substrate in a direction away from the base substrate.

[0157] Exemplarily, at least one of the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame start signal line GSTV2 is made of a conductive layer located on the side of the first source and drain metal layer in the display substrate facing away from the base substrate.

[0158] At least one of the signal lines is made of the second source-drain metal layer in the display substrate, which not only helps to reduce the voltage drop of the signal line, but also avoids short circuit between the signal line and the circuit structure below it, effectively improving the reliability of the display substrate.

[0159] As shown in Figure 12, in some embodiments, at least one of the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame start signal line GSTV2 is made of the first source and drain metal layer in the display substrate.

[0160] In some embodiments, at least one of the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame start signal line GSTV2 includes two stacked conductive layers, one conductive layer is made of the second source and drain metal layer, and the other conductive layer is made of the third source and drain metal layer in the display substrate.

[0161] Exemplarily, the display substrate further includes the third source-drain metal layer, and the third source-drain metal layer is located on a side of the second source-drain metal layer facing away from the base substrate.

[0162] At least one of the above-mentioned signal lines includes two stacked conductive layers, one conductive layer is made of the second source-drain metal layer, and the other conductive layer is made of the third source-drain metal layer in the display substrate. This is not only beneficial to reducing the voltage drop of the signal line, but also can avoid short circuit between the signal line and the circuit structure below it, effectively improving the reliability of the display substrate.

[0163] As shown in FIG. 18 and FIG. 19 , in some embodiments, the channel width-to-length ratio of the output transistor included in the first gate driving circuit Gate1 -GOA is equal to the channel width-to-length ratio of the output transistor included in the second gate driving circuit Gate2 -GOA.

[0164] Exemplarily, the output transistors include a fourth transistor T4 and a fifth transistor T5.

[0165] The above configuration is more conducive to achieving mirror symmetry between the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA, and is conducive to narrowing the frame of the display substrate.

[0166] As shown in FIG. 25 , in some embodiments, the channel width-to-length ratio of the output transistor included in the first gate driving circuit Gate1 -GOA is greater than the channel width-to-length ratio of the output transistor included in the second gate driving circuit Gate2 -GOA.

[0167] Exemplarily, the channel width-to-length ratio of the output transistor included in the first gate driving circuit Gate1-GOA is 1.25 times, 1.5 times or 2.0 times the channel width-to-length ratio of the output transistor included in the second gate driving circuit Gate2-GOA, but is not limited thereto.

[0168] The above-mentioned differentiated design of the channel width-to-length ratio of the output transistor included in the first gate drive circuit Gate1-GOA and the channel width-to-length ratio of the output transistor included in the second gate drive circuit Gate2-GOA can not only be compatible with both the high-frequency drive mode and the low-frequency drive mode, but also can further reduce the border width of the display substrate.

[0169] As shown in FIG. 19 , in some embodiments, at least some target devices having the same functions in the first gate driving circuit Gate1 -GOA and the second gate driving circuit Gate2 -GOA are coupled.

[0170] Exemplarily, the target device having the same function includes a first transistor T1 and a seventh transistor T7. The gate of the first transistor T1 in the first gate driver circuit Gate1-GOA is coupled to the gate of the first transistor T1 in the second gate driver circuit Gate2-GOA. The gate of the seventh transistor T7 in the first gate driver circuit Gate1-GOA is coupled to the gate of the seventh transistor T7 in the second gate driver circuit Gate2-GOA.

[0171] As shown in Figures 18 and 19, the target device with the same function also includes a second capacitor C2, and the second plate C22 of the second capacitor C2 in the first gate drive circuit Gate1-GOA is coupled to the second plate C22 of the second capacitor C2 in the second gate drive circuit Gate2-GOA, and is punched and connected to the first level signal line VGH.

[0172] The above arrangement is conducive to reducing the wiring length of the signal node, and when sharing the signal, the electrical connection with the shared signal line can be achieved through a punch hole, which is conducive to simplifying the circuit structure.

[0173] As shown in FIG2 to FIG4, in some embodiments, the display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines Vdata, a plurality of second initialization signal lines VINIT2, and a plurality of third initialization signal lines VINIT3. The first sub-pixel driving circuit includes a first driving transistor T23, a first data writing transistor T24, a first compensation transistor T22, a second reset transistor T27, and a third reset transistor T28.

[0174] The gate of the first data writing transistor T24 is coupled to the output end of the corresponding first gate driving circuit Gate1-GOA, the first electrode of the first data writing transistor T24 is coupled to the corresponding data line Vdata, and the second electrode of the first data writing transistor T24 is coupled to the first electrode of the first driving transistor T23;

[0175] The gate of the first compensation transistor T22 is coupled to the output end of the corresponding first gate driving circuit Gate1-GOA, the first electrode of the first compensation transistor T22 is coupled to the second electrode of the first driving transistor T23, and the second electrode of the first compensation transistor T22 is coupled to the gate of the first driving transistor T23;

[0176] A gate of the second reset transistor T27 is coupled to an output terminal of the corresponding second gate driving circuit Gate2-GOA, a first electrode of the second reset transistor T27 is coupled to the corresponding second initialization signal line VINIT2, and a second electrode of the second reset transistor T27 is coupled to the corresponding light-emitting element;

[0177] The gate of the third reset transistor T28 is coupled to the output end of the corresponding second gate driving circuit Gate2-GOA, the first electrode of the third reset transistor T28 is coupled to the corresponding third initialization signal line VINIT3, and the second electrode of the third reset transistor T28 is coupled to the first electrode of the first driving transistor T23.

[0178] Exemplarily, the display substrate further includes: a plurality of first initialization signal lines VINIT1, a plurality of first scan lines Gate1, a plurality of second scan lines Gate2, a plurality of reset lines Reset, a plurality of emission control lines, and a plurality of power lines VDD. The sub-pixel driving circuit includes an 8T1C circuit structure. The sub-pixel driving circuit further includes: a first reset transistor T21, a first power control transistor T25, and a first emission control transistor T26.

[0179] Exemplarily, the first initialization signal line VINIT1 transmits a first initialization signal, the second initialization signal line VINIT2 transmits a second initialization signal, the third initialization signal line VINIT3 transmits a third initialization signal, the first scan line Gate1 transmits a first gate drive signal GOUT1, the second scan line Gate2 transmits a second gate drive signal GOUT2, the light-emitting control line transmits a light-emitting control signal EM, the reset line Reset transmits a reset signal, and the power line VDD transmits a power signal.

[0180] A gate of the first reset transistor T21 is coupled to the corresponding reset line Reset, a first electrode of the first reset transistor T21 is coupled to the corresponding first initialization signal line VINIT1, and a second electrode of the first reset transistor T21 is coupled to the gate of the first driving transistor T23.

[0181] The gate of the first power control transistor T25 is coupled to the corresponding light emitting control line, the first electrode of the first power control transistor T25 is coupled to the corresponding power line VDD, and the second electrode of the first power control transistor T25 is coupled to the first electrode of the first driving transistor T23.

[0182] The gate of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting control line, the first electrode of the first light-emitting control transistor T26 is coupled to the second electrode of the first driving transistor T23, and the second electrode of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting element. The cathode of the light-emitting element receives a negative power supply signal VSS.

[0183] The gate of the first data writing transistor T24 is coupled to the output end of the corresponding first gate driving circuit Gate1 -GOA through the corresponding first scan line Gate1 .

[0184] The gate of the first compensation transistor T22 is coupled to the output terminal of the corresponding first gate driving circuit Gate1 -GOA through the corresponding first scan line Gate1 .

[0185] A gate of the second reset transistor T27 is coupled to an output terminal of the corresponding second gate driving circuit Gate2 -GOA through the corresponding second scan line Gate2 .

[0186] The gate of the third reset transistor T28 is coupled to the output terminal of the corresponding second gate driving circuit Gate2-GOA through the corresponding second scan line Gate2.

[0187] As shown in FIG5 and FIG6, in some embodiments, the display substrate further includes a plurality of second sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines Vdata, and a plurality of second initialization signal lines VINIT2. The second sub-pixel driving circuit includes a second driving transistor T33, a second data writing transistor T34, a second compensation transistor T32, and a second reset transistor T27.

[0188] A gate of the second data writing transistor T34 is coupled to an output terminal of a corresponding second gate driving circuit Gate2-GOA, a first electrode of the second data writing transistor T34 is coupled to the corresponding data line Vdata, and a second electrode of the second data writing transistor T34 is coupled to a first electrode of the second driving transistor T33;

[0189] The gate of the second compensation transistor T32 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA, the first electrode of the second compensation transistor T32 is coupled to the second electrode of the second driving transistor T33, and the second electrode of the second compensation transistor T32 is coupled to the gate of the second driving transistor T33;

[0190] The gate of the second reset transistor T27 is coupled to the output end of the corresponding second gate driving circuit Gate2-GOA, the first electrode of the second reset transistor T27 is coupled to the corresponding second initialization signal line VINIT2, and the second electrode of the second reset transistor T27 is coupled to the corresponding light-emitting element.

[0191] Exemplarily, the display substrate further includes: a plurality of first initialization signal lines VINIT1, a plurality of first scan lines Gate1, a plurality of second scan lines Gate2, a plurality of reset lines Reset, a plurality of emission control lines, and a plurality of power lines VDD. The sub-pixel driving circuit includes a 7T1C circuit structure. The sub-pixel driving circuit further includes: a first reset transistor T21, a first power control transistor T25, and a first emission control transistor T26.

[0192] Exemplarily, the first initialization signal line VINIT1 transmits a first initialization signal, the second initialization signal line VINIT2 transmits a second initialization signal, the first scan line Gate1 transmits a first gate drive signal GOUT1, the second scan line Gate2 transmits a second gate drive signal GOUT2, the light-emitting control line transmits a light-emitting control signal EM, the reset line Reset transmits a reset signal, and the power line VDD transmits a power signal.

[0193] A gate of the first reset transistor T21 is coupled to the corresponding reset line Reset, a first electrode of the first reset transistor T21 is coupled to the corresponding first initialization signal line VINIT1, and a second electrode of the first reset transistor T21 is coupled to the gate of the second driving transistor T33.

[0194] The gate of the first power control transistor T25 is coupled to the corresponding light emitting control line, the first electrode of the first power control transistor T25 is coupled to the corresponding power line VDD, and the second electrode of the first power control transistor T25 is coupled to the first electrode of the second driving transistor T33.

[0195] The gate of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting control line, the first electrode of the first light-emitting control transistor T26 is coupled to the second electrode of the second driving transistor T33, and the second electrode of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting element. The cathode of the light-emitting element receives a negative power supply signal VSS.

[0196] The gate of the second data writing transistor T34 is coupled to the output terminal of the corresponding second gate driving circuit Gate2 -GOA through the corresponding second scan line Gate2 .

[0197] A gate of the second compensation transistor T32 is coupled to an output terminal of a corresponding first gate driving circuit Gate1 -GOA through a corresponding first scan line Gate1 .

[0198] A gate of the second reset transistor T27 is coupled to an output terminal of the corresponding second gate driving circuit Gate2 -GOA through the corresponding second scan line Gate2 .

[0199] When the sub-pixel driving circuit of the above-mentioned 7T1C structure is adopted, in high and low frequency applications, the gate driving signals of the second compensation transistor T32 and the second data writing transistor T34 are provided by different gate driving circuits. At this time, the first gate driving circuit Gate1-GOA connected to the second compensation transistor T32 and the second gate driving circuit Gate2-GOA connected to the second data writing transistor T34 are mirrored, and other signal lines except the frame start signal line can be shared.

[0200] When the display substrate adopts the first sub-pixel driving circuit and the second sub-pixel driving circuit, the low-frequency flicker problem can be effectively improved.

[0201] As shown in FIG. 13 to FIG. 17 , in some embodiments, the display substrate further includes:

[0202] a first electrostatic discharge circuit (including a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16), wherein the first electrostatic discharge circuit is coupled to the first gate drive circuit Gate1-GOA;

[0203] a second electrostatic discharge circuit (including a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12), wherein the second electrostatic discharge circuit is coupled to the second gate drive circuit Gate2-GOA;

[0204] The first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged in a mirror image, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line.

[0205] In the display substrate provided by the above embodiment, the first electrostatic discharge circuit and the second electrostatic discharge circuit are mirror-imaged and share at least one signal line, which is more conducive to narrowing the frame of the display substrate.

[0206] In some embodiments, the first electrostatic discharge circuit and the second electrostatic discharge circuit share a first level line VGH and / or a second level line VGL.

[0207] As shown in FIG26 , in some embodiments, the peripheral area further includes:

[0208] Multiple light-emitting control drive circuits EM-GOA, wherein the multiple light-emitting control drive circuits EM-GOA are divided into multiple groups of light-emitting control drive circuits EM-GOA, each group of light-emitting control drive circuits EM-GOA includes two light-emitting control drive circuits EM-GOA arranged in a mirror image, and the two light-emitting control drive circuits EM-GOA share at least one signal line.

[0209] As shown in FIG. 26 , illustratively, the at least one shared signal line includes: a first level signal line VGH, at least one signal line among a third clock signal line ECK and a fourth clock signal line ECB.

[0210] As shown in FIG26 , one of the two mirror-image emission control and driving circuits EM-GOA is connected to the third frame start signal line ESTV1, while the other is connected to the fourth frame start signal line ESTV2. The third and fourth frame start signal lines ESTV1 and ESTV2 can be independently controlled.

[0211] Illustratively, one light emitting control driving circuit EM-GOA may be used to control the first power supply control transistor T25 in FIG. 2 or FIG. 5 , and another light emitting control driving circuit EM-GOA may be used to control the first power supply control transistor T25 in FIG. 2 or FIG. 5 .

[0212] Exemplarily, the display substrate includes a low-temperature polycrystalline silicon oxide display substrate.

[0213] It is worth noting that the light emission control driving circuit EM-GOA can adopt the circuit structure shown in Figure 27, but is not limited thereto. Figure 27 shows that the light emission control driving circuit EM-GOA includes a 41st transistor T41, a 42nd transistor T42, a 43rd transistor T43, a 44th transistor T44, a 45th transistor T45, a 46th transistor T46, a 47th transistor T47, a 48th transistor T48, a 49th transistor T49, a 50th transistor T50, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and an output terminal EOUT1 of the light emission control driving circuit EM-GOA.

[0214] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate.

[0215] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0216] In the display substrate provided in the above embodiment, by providing the display substrate with multiple first gate drive circuits and multiple second gate drive circuits, the low-frequency flicker problem of the display substrate is effectively improved. Furthermore, by providing the first gate drive circuit and the second gate drive circuit with a shared signal line, the width of the border occupied by the first gate drive circuit and the second gate drive circuit, as well as the signal line connecting them, is effectively reduced. This not only facilitates a narrower border on the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0217] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0218] The present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate. The method includes:

[0219] A plurality of first gate drive circuits and a plurality of second gate drive circuits are manufactured, wherein the first gate drive signal output by the first gate drive circuit and the second gate drive signal output by the second gate drive circuit have different timings; the first gate drive circuit and the second gate drive circuit share at least one signal line.

[0220] In the display substrate provided by the embodiments of the present disclosure, by configuring the display substrate to include multiple first gate drive circuits and multiple second gate drive circuits, the low-frequency flicker problem of the display substrate is effectively improved. Furthermore, by configuring the first gate drive circuit and the second gate drive circuit to share at least one signal line, the width of the border occupied by the first gate drive circuit and the second gate drive circuit, as well as the signal line connecting the two, is effectively reduced. This not only facilitates a narrower border for the display substrate, but also effectively reduces the power consumption of the gate drive circuit.

[0221] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0222] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0223] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0224] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0225] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0226] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0227] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0228] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: Multiple first gate drive circuits and multiple second gate drive circuits, the first gate drive signals output by the first gate drive circuits and the second gate drive signals output by the second gate drive circuits have different timings; the first gate drive circuits and the second gate drive circuits share at least one signal line.

2. The display substrate according to claim 1, wherein The display substrate includes a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits and the plurality of second gate driving circuits are both located in the peripheral area; In a peripheral area close to a same side of the display area, at least a portion of the first gate driving circuit and at least a portion of the second gate driving circuit are arranged in a mirror image.

3. The display substrate according to claim 2, wherein: The first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal with a first level.

4. The display substrate according to claim 3, wherein: At least a portion of the orthographic projection of the first-level signal line on the base substrate of the display substrate is located between the orthographic projection of the first gate driving circuit on the base substrate and the orthographic projection of the second gate driving circuit on the base substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first level signal line on the base substrate at least partially overlaps with the orthographic projection of the first gate driving circuit on the base substrate; And / or, the orthographic projection of the first level signal line on the base substrate at least partially overlaps with the orthographic projection of the second gate driving circuit on the base substrate. The display substrate according to claim 3 , wherein: The first gate driving circuit and the second gate driving circuit share a first clock signal line and / or a second clock signal line. The first clock signal transmitted by the first clock signal line and the second clock signal transmitted by the second clock signal line have opposite phases.

7. The display substrate according to claim 6, wherein: At least part of the first gate drive circuit and at least part of the second gate drive circuit are mirror-symmetrical about a first symmetry axis; the first symmetry axis at least partially overlaps with the first clock signal line, or the first symmetry axis at least partially overlaps with the second clock signal line, or the first symmetry axis at least partially overlaps with the first level signal line.

8. The display substrate according to claim 6, wherein: The orthographic projection of the first level signal line on the base substrate is located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate.

9. The display substrate according to claim 6, wherein: An orthographic projection of the first clock signal line on the substrate at least partially overlaps with an orthographic projection of one of the first gate driving circuit and the second gate driving circuit on the substrate; An orthographic projection of the second clock signal line on the substrate at least partially overlaps with an orthographic projection of the other of the first gate driving circuit and the second gate driving circuit on the substrate.

10. The display substrate according to claim 6, wherein: The first gate driving circuit is coupled to a first frame start signal line, and the second gate driving circuit is coupled to a second frame start signal line.

11. The display substrate according to claim 10, wherein: The orthographic projection of the first level signal line on the base substrate is located between the orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate.

12. The display substrate according to claim 10, wherein: The orthographic projection of the first frame start signal line on the base substrate at least partially overlaps with the orthographic projection of the first gate driving circuit on the base substrate; The orthographic projection of the second frame start signal line on the base substrate at least partially overlaps with the orthographic projection of the second gate driving circuit on the base substrate.

13. The display substrate according to claim 10, wherein: The orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate are located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate.

14. The display substrate according to claim 10, wherein: At least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line is made of the second source-drain metal layer in the display substrate.

15. The display substrate according to claim 14, wherein: At least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line includes two stacked conductive layers, one conductive layer is made of the second source-drain metal layer, and the other conductive layer is made of the third source-drain metal layer in the display substrate.

16. The display substrate according to claim 1, wherein The channel width-to-length ratio of the output transistor included in the first gate driving circuit is equal to the channel width-to-length ratio of the output transistor included in the second gate driving circuit.

17. The display substrate according to claim 1, wherein The channel width-to-length ratio of the output transistor included in the first gate driving circuit is greater than the channel width-to-length ratio of the output transistor included in the second gate driving circuit.

18. The display substrate according to claim 1, wherein At least some target devices having the same function in the first gate driving circuit and the second gate driving circuit are coupled.

19. The display substrate according to claim 1, wherein The display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines, a plurality of second initialization signal lines, and a plurality of third initialization signal lines, wherein the first sub-pixel driving circuit includes a first driving transistor, a first data writing transistor, a first compensation transistor, a second reset transistor, and a third reset transistor; The gate of the first data writing transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the first data writing transistor is coupled to the corresponding data line, and the second electrode of the first data writing transistor is coupled to the first electrode of the first driving transistor; The gate of the first compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the first compensation transistor is coupled to the second electrode of the first driving transistor, and the second electrode of the first compensation transistor is coupled to the gate of the first driving transistor; The gate of the second reset transistor is coupled to the output terminal of the corresponding second gate driving circuit, the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and the second electrode of the second reset transistor is coupled to the corresponding light emitting element; The gate of the third reset transistor is coupled to the output end of the corresponding second gate driving circuit, the first electrode of the third reset transistor is coupled to the corresponding third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the first driving transistor.

20. The display substrate according to claim 1, wherein The display substrate further includes a plurality of second sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines and a plurality of second initialization signal lines, wherein the second sub-pixel driving circuit includes a second driving transistor, a second data writing transistor, a second compensation transistor and a second reset transistor; The gate of the second data writing transistor is coupled to the output terminal of the corresponding second gate driving circuit, the first electrode of the second data writing transistor is coupled to the corresponding data line, and the second electrode of the second data writing transistor is coupled to the first electrode of the second driving transistor; The gate of the second compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, the first electrode of the second compensation transistor is coupled to the second electrode of the second driving transistor, and the second electrode of the second compensation transistor is coupled to the gate of the second driving transistor; A gate of the second reset transistor is coupled to an output terminal of the corresponding second gate driving circuit, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to a corresponding light-emitting element.

21. The display substrate according to claim 1, wherein The display substrate further includes: a first electrostatic discharge circuit coupled to the first gate driving circuit; a second electrostatic discharge circuit coupled to the second gate drive circuit; The first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged in a mirror image, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line.

22. The display substrate according to claim 1, wherein The surrounding area also includes: Multiple light-emitting control driving circuits are divided into multiple groups of light-emitting control driving circuits, each group of light-emitting control driving circuits includes two light-emitting control driving circuits arranged in a mirror image, and the two light-emitting control driving circuits share at least one signal line.

23. A display device comprising the display substrate according to any one of claims 1 to 22.

24. A method for manufacturing a display substrate, for manufacturing the display substrate according to any one of claims 1 to 22, the method comprising: A plurality of first gate drive circuits and a plurality of second gate drive circuits are manufactured, wherein the first gate drive signal output by the first gate drive circuit and the second gate drive signal output by the second gate drive circuit have different timings; the first gate drive circuit and the second gate drive circuit share at least one signal line.