Neural Network Path Planning

Abstract

A system has one or more neural networks to calculate 1106 a plurality of paths, through which an autonomous device is to traverse. The path calculation may be based upon distances, which are based up

Description

TECHNICAL FIELD

[0001] At least one embodiment pertains to processing resources used to calculate a path through an environment using neural networks. For example, at least one embodiment, pertains to processors or computing resources used to calculate distances to a location in an environment using neural networks to calculate a path according to various novel techniques described herein. BACKGROUND

[0002] Calculating a path through an environment is an important task in many contexts. In various cases, calculating a path to a goal through an environment can be difficult, such as when the goal and the environment undergo various changes. Calculating a path to a goal through an environment can also require large amounts of computing resources. Techniques for calculating a path through an environment may therefore be improved. SUMMARY OF THE INVENTION

[0003] Aspects and embodiments of the present invention are set out in the appended claims. These and other aspects and embodiments of the invention are also described herein.

[0004] According to various aspects described herein, there may be provided apparatuses, systems, and techniques to calculate a plurality of paths, through which an autonomous device may be to traverse. In at least one embodiment, a plurality of paths may be calculated using one or more neural networks based, at least in part, on one or more distance values output by the one or more neural networks.

[0006] The disclosure extends to any novel aspects or features described and / or illustrated herein. [0007 ] Further features of the disclosure are characterized by the independent and dependent claims. [0008 ] Any feature in one aspect of the disclosure may be applied to other aspects of the disclosure, in any appropriate combination. In particular, method aspects may be applied to apparatus or system aspects, and vice versa.

[0009] Furthermore, features implemented in hardware may be implemented in software, and vice versa. Any reference to software and hardware features herein should be construed accordingly.

[0010] Any system or apparatus feature as described herein may also be provided as a method feature, and vice versa. System and / or apparatus aspects described functionally (including means plus function features) may be expressed alternatively in terms of their corresponding structure, such as a suitably programmed processor and associated memory. [0011 ] It should also be appreciated that particular combinations of the various features described and defined in any aspects of the disclosure can be implemented and / or supplied and / or used independently.

[0012] The disclosure also provides computer programs and computer program products comprising software code adapted, when executed on a data processing apparatus, to perform any of the methods and / or for embodying any of the apparatus and system features described herein, including any or all of the component steps of any method.

[0013] The disclosure also provides a computer or computing system (including networked or distributed systems) having an operating system which supports a computer program for carrying out any of the methods described herein and / or for embodying any of the apparatus or system features described herein.

[0014] The disclosure also provides a computer readable media having stored thereon any one or more of the computer programs aforesaid.

[0015] The disclosure also provides a signal carrying any one or more of the computer programs aforesaid.

[0016] The disclosure extends to methods and / or apparatus and / or systems as herein described with reference to the accompanying drawings.

[0017] Aspects and embodiments of the disclosure will now be described purely by way of example, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 illustrates an example of an implicit environment function for an environment, according to at least one embodiment;

[0019] FIG. 2 illustrates an example of an implicit environment function for different goal positions in an environment, according to at least one embodiment;

[0020] FIG. 3 illustrates an example of an implicit environment function for different goal positions and environments, according to at least one embodiment; [0021 ] FIG. 4 illustrates an example of an agent navigating to a goal using an implicit environment function, according to at least one embodiment;

[0022] FIG. 5 illustrates an example of environment fields for a multiple person navigation environment, according to at least one embodiment;

[0023] FIG. 6 illustrates an example of use of an implicit environment field for a 3D environment, according to at least one embodiment;

[0024] FIG. 7 illustrates an example of results using an implicit environment function, according to at least one embodiment;

[0025] FIG. 8 illustrates an example of results of agent navigation, according to least one embodiment;

[0026] FIG. 9 and FIG. 10 illustrate examples of results of fitting given human sequences to searched trajectories in 3D indoor environments, according to at least one embodiment;

[0027] FIG. 11 illustrates an example of a process to calculate a plurality of paths using an implicit environment function, according to at least one embodiment;

[0028] FIG. 12A illustrates inference and / or training logic, according to at least one embodiment;

[0029] FIG. 12B illustrates inference and / or training logic, according to at least one embodiment;

[0030] FIG. 13 illustrates training and deployment of a neural network, according to at least one embodiment;

[0031] FIG. embodiment; 14 illustrates an example data center system, according to at least one

[0032] FIG. embodiment; 15 A illustrates an example of an autonomous vehicle, according to at least one

[0033] FIG. 15B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 15 A, according to at least one embodiment;

[0034] FIG. 15C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 15 A, according to at least one embodiment;

[0035] FIG. 15D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 15 A, according to at least one embodiment;

[0036] FIG. embodiment; 16 is a block diagram illustrating a computer system, according to at least one

[0037] FIG. embodiment; 17 is a block diagram illustrating a computer system, according to at least one

[0038] FIG. 18 illustrates a computer system, according to at least one embodiment;

[0039] FIG. 19 illustrates a computer system, according to at least one embodiment;

[0040] FIG. 20A illustrates a computer system, according to at least one embodiment;

[0041] FIG. 20B illustrates a computer system, according to at least one embodiment; FIG. 20C illustrates a computer system, according to at least one embodiment;

[0043] FIG. 20D illustrates a computer system, according to at least one embodiment;

[0044] FIGS. 20E and 20F illustrate a shared programming model, according to at least one embodiment;

[0045] FIG. 21 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0046] FIGS. 22A and 22B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0047] FIGS. 23A and 23B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0048] FIG. 24 illustrates a computer system, according to at least one embodiment;

[0049] FIG. 25A illustrates a parallel processor, according to at least one embodiment;

[0050] FIG. 25B illustrates a partition unit, according to at least one embodiment; [0051 ] FIG. 25C illustrates a processing cluster, according to at least one embodiment;

[0052] FIG. 25D illustrates a graphics multiprocessor, according to at least one embodiment;

[0053] FIG. 26 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0054] FIG. 27 illustrates a graphics processor, according to at least one embodiment;

[0055] FIG. 28 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0056] FIG. 29 illustrates a deep learning application processor, according to at least one embodiment;

[0057] FIG. 30 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment;

[0058] FIG. 31 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0059] FIG. 32 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0060] FIG. 33 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0061] FIG. 34 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0062] FIG. 35 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0063] FIGS. 36A and 36B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0064] FIG. 37 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

[0065] FIG. 38 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0066] FIG. 39 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0067] FIG. 40 illustrates a streaming multi-processor, according to at least one embodiment.

[0068] FIG. 41 is an example data flow diagram for an advanced computing pipeline, in accordance with at least one embodiment;

[0069] FIG. 42 is a system diagram for an example system for training, adapting, instantiating and deploying machine learning models in an advanced computing pipeline, in accordance with at least one embodiment;

[0070] FIG. 43 includes an example illustration of an advanced computing pipeline 4210A for processing imaging data, in accordance with at least one embodiment; [0071 ] FIG. 44A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment;

[0072] FIG. 44B includes an example data flow diagram of a virtual instrument supporting an CT scanner, in accordance with at least one embodiment;

[0073] FIG. 45A illustrates a data flow diagram for a process to train a machine learning model, in accordance with at least one embodiment; and

[0074] FIG. 45B is an example illustration of a client-server architecture to enhance annotation tools with pre-trained annotation models, in accordance with at least one embodiment. DETAILED DESCRIPTION

[0075] In at least one embodiment, a neural network, based on an environment, a position, and a goal position, calculates a distance between said position and said goal position along a feasible trajectory through said environment. In at least one embodiment, a position refers to any suitable location, area, and / or region of an environment. In at least one embodiment, a goal position refers to a position in an environment that one or more agents are to navigate to. In at least one embodiment, an environment, also referred to as a scene, refers to any suitable two-dimensional (2D) or three-dimensional (3D) environment that can comprise various obstacles. In at least one embodiment, an environment can correspond to any suitable real-world environment or simulated environment. In at least one embodiment, given an environment, a first position, and a second position, a neural network calculates a reaching distance from said first position to said second position, which refers to a distance from said first position to said second position along a feasible trajectory through said environment. In at least one embodiment, a feasible trajectory refers to a trajectory that is geometrically feasible and / or semantically plausible, as described in further detail below. In at least one embodiment, a feasible trajectory refers to any suitable trajectory through an environment that does not collide or otherwise intersect with any obstacles and / or inaccessible regions of said environment.

[0076] In at least one embodiment, a neural network represents an environment through an environment field that encodes reaching distances of various positions in an environment to a goal position. In at least one embodiment, a neural network represents an environment internally through an environment field. In at least one embodiment, an environment field is a representation that comprises a collection of values indicating a reaching distance for each position in an environment to a goal position. In at least one embodiment, an environment field represents an environment, in which each value of said environment field corresponds to a position of said environment. In at least one embodiment, a particular value in an environment field corresponds to a particular position in an environment, in which said particular value is a reaching distance value from said particular position in said environment to a goal position in said environment.

[0077] In at least one embodiment, an environment field can be represented through a visual representation, such as an image, in which different reaching distance values are assigned different color values. In at least one embodiment, one or more systems visualize an environment field by at least using a neural network to calculate a reaching distance value for each position in an environment to a goal position, and utilizing calculated reaching distance values to visualize said environment field. In at least one embodiment, an environment field visualization is continuous. In at least one embodiment, while various environment field visualizations described herein may comprise discrete sections, environment field visualizations can comprise continuous color gradients, continuous shading, and / or any suitable continuous visualizations that indicate reaching distance values.

[0078] In at least one embodiment, an environment field is utilized to guide dynamic behavior of agents inside an environment. In at least one embodiment, an environment is represented by an image, in which each position corresponds to a pixel of said image. In at least one embodiment, a position of an environment corresponds to any suitable location, region, or area of said environment. In at least one embodiment, an environment is structured as a grid, in which a position corresponds to a set of pixels that correspond to a grid cell. In at least one embodiment, a position corresponds to any suitable set of pixels. In at least one embodiment, an image is any suitable image, such as a red-green-blue (RGB) image, black / white (B / W) image, grayscale image, RGB-depth (RGB-D) image, and / or variations thereof. In at least one embodiment, an agent refers to any suitable entity, such as an autonomous device, robot, human, or other entity, that is navigating or otherwise moving through an environment. In at least one embodiment, a neural implicit function represents an environment internally through an environment field. In at least one embodiment, a neural implicit function is a neural network that approximates or otherwise models a function, such as a function that outputs a reaching distance to a goal position for a position in an environment. In at least one embodiment, a neural implicit function that approximates or otherwise models a function that outputs a reaching distance to a goal position for a position in an environment is referred to as an implicit environment function.

[0079] In at least one embodiment, one or more systems utilize a neural implicit function that represents an environment through an environment field to guide an agent navigating a scene, such as navigating an agent to reach a given goal in a physically plausible and / or feasible manner. In at least one embodiment, for each position in a scene, an environment field captures a distance from a position to a given goal position along a geometrically feasible and / or semantically plausible trajectory. In at least one embodiment, a geometrically feasible trajectory refers to a trajectory through an environment that does not collide with any obstacles of said environment. In at least one embodiment, a semantically plausible trajectory refers to a trajectory through an environment that is physically appropriate to follow by one or more agents. In at least one embodiment, for example, a semantically implausible trajectory can be a trajectory through an environment that requires a human agent to crawl under an obstacle; in this example, crawling may not be a physically appropriate action for said human agent. In at least one embodiment, one or more systems use a neural implicit function to calculate a plurality of paths through which an agent is to traverse or otherwise navigate. In at least one embodiment, one or more systems navigate an agent utilizing a neural implicit function by repeatedly moving said agent to a next location with a smallest reaching distance, until said agent reaches a goal position.

[0089] In at least one embodiment, neural implicit functions can be generalized to arbitrary goal positions and arbitrary scenes / environments, allowing generalization to different environment fields given different goal positions and / or scenes / environments using a single neural implicit function. In at least one embodiment, a neural implicit function is able to learn to determine or otherwise calculate continuous environment fields using discretely sampled training data. In at least one embodiment, querying a reaching distance between any position and a goal position only requires a fast network forward pass, enabling efficient trajectory prediction. [ 0081 ] In at least one embodiment, to enforce semantic plausibility of an environment field in indoor environments, one or more systems define accessible regions, which refer to plausible regions for agents to appear in. In at least one embodiment, one or more systems determine accessible regions for various environments using one or more neural network models, such as a variational auto-encoder, and designate locations outside of said accessible regions as obstacles, also referred to as inaccessible regions. In at least one embodiment, one or more systems utilize a neural implicit function that represents an environment through an environment field in various human trajectory modeling in 3D environments, such as various indoor environments, outdoor environments, or other suitable environments, and agent navigation in 2D environments, such as various mazes or other suitable environments.

[0082] In at least one embodiment, a neural implicit function is trained using training data generated based on one or more environments. In at least one embodiment, accessible regions and inaccessible regions are defined for environments by one or more systems using various neural network models, and / or other appropriate systems. In at least one embodiment, training data is generated by one or more systems using any suitable path planning algorithm, method, system, and / or variations thereof. In at least one embodiment, one or more systems generate training data by processing an environment with defined accessible regions and inaccessible regions using one or more path planning algorithms to calculate one or more reaching distances from one or more accessible positions in said environment to one or more goal positions in said environment, in which said training data comprises one or more of said one or more reaching distances, said one or more accessible positions, and / or said one or more goal positions, and train a neural network using said training data.

[0083] In preceding and following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in art that inventive concepts may be practiced without one or more of these specific details.

[0084] In at least one embodiment, techniques described herein achieve various technical advantages, including but not limited to: an ability to use a neural network to represent an environment to facilitate guidance for agent behavior / navigation in said environment; an ability to use a neural network to represent an environment through an environment field that ensures geometric and semantic feasibility; an ability to use a neural network to calculate one or more reaching distances for one or more positions to a goal in an environment in a single forward pass; and various other technical advantages.

[0085] In at least one embodiment, one or more systems train a neural implicit function to learn to represent an environment through a continuous environment field, in which each value of each position of said continuous environment field indicates a reaching distance from a particular position of said environment to a goal position. In at least one embodiment, one or more systems model an environment field as a wave propagation to compute reaching distance. In at least one embodiment, a wave propagation refers to a phenomena in which a distance between an initial position and a goal is equivalent to a minimal amount of time required by a wave, starting from said initial position, to propagate its front boundary to reach said goal.

[0086] In at least one embodiment, one or more systems denote all positions that can be reached by an agent as accessible regions, and all other positions as obstacles, also referred to as inaccessible regions. In at least one embodiment, for a spreading wave denoted by t (e.g., a closed curve in an environment), said wave spreads based on a speed function, denoted by / (%), defined at each location. In at least one embodiment, a current position of a spreading wave, denoted by t, is modeled by an arrival time function, denoted by u(x), with respect to a location, denoted by x, starting from a goal position. In at least one embodiment, when / (%) >0, one or more systems formulate an arrival time function as a continuous shortest-path problem through an equation such as an Eikonal equation, or any suitable equation, that is represented through a following equation, although any variation thereof can be utilized: ||Vu(%)|| / (%) = l,x E fl in which fl denotes a feasible region (e.g., accessible region), V denotes a gradient, ||'|| denotes a Euclidean norm, and u(%e) = 0 at a goal location denoted by %e. In at least one embodiment, one or more systems specify an environment layout in which, at obstacles, a wave expansion speed, denoted by / (%), is set to an infinitesimally small positive value, or any suitable value, as a wave cannot go through obstacles, and within an accessible region, a wave expansion speed is set to a constant value of 1, or any suitable value.

[0087] In at least one embodiment, one or more systems solve an Eikonal equation, such as those described herein, through a neural implicit function that models a continuous energy surface. In at least one embodiment, a neural implicit function, also referred to as an implicit environment function, neural network model, neural network function, machine learning function, implicit neural representation, and / or variations thereof, is a neural network that approximates one or more functions. In at least one embodiment, one or more systems train a neural implicit function to represent an environment through an environment field as a mapping from location coordinates, denoted by x 6 Ji2, to an arrival time, denoted by u(x) 6 Ji. In at least one embodiment, one or more systems train a neural implicit function using training data comprising discretely sampled pairs of {x, u(x)} to represent an environment through a continuous field.

[0088] In at least one embodiment, one or more systems utilize one or more path planning algorithms, methods, and / or systems, such as Breath First Searching (BFS), Dijkstra’s algorithm, Fast Marching Method (FMM), Rapidly Exploring Random Tree (RRT), Probabilistic Roadmaps (PRM), and / or variations thereof, to generate training data for a neural implicit function. In at least one embodiment, one or more path planning algorithms, methods, and / or systems, based on an input environment and a goal position, determine a reaching distance from each accessible position of said input environment to said goal position. In at least one embodiment, training data comprises an environment, a goal position, and a reaching distance for each accessible position in said environment. In at least one embodiment, an accessible position refers to a position in an environment that resides in an accessible region.

[0089] In at least one embodiment, one or more systems utilize a path planning method that solves in one or more environments, such as an environment structured as a grid. In at least one embodiment, one or more path planning methods initiate a discrete map starting from a goal position, and iteratively expand and update neighboring feasible grid cells according to a speed using Eikonal updating criteria, or any suitable criteria, until reaching a starting position. In at least one embodiment, one or more path planning methods include a method, such as an FMM implementation, that obtains a discrete grid (e.g., grid corresponding to an environment) with a given goal position as inputs and outputs a reaching distance from each accessible position (e.g., position of an environment) to said goal position. In at least one embodiment, one or more systems train a neural implicit function to regress a reaching distance at each grid cell given a cell’s coordinates (e.g., normalized to [-1, 1]) as inputs. In at least one embodiment, FIGS. 1-3 illustrate examples of implicit environment functions.

[0090] FIG. 1 illustrates an example 100 of an implicit environment function for an environment, according to at least one embodiment. In at least one embodiment, one or more processes, functions, and / or operations illustrated in FIGS. 1-11 are performed or otherwise executed by any suitable processing system or unit, such as a graphics processing unit (GPU), parallel processing unit (PPU), central processing unit (CPU), and / or variations thereof, and in any suitable order, such as sequential, parallel, and / or variations thereof. In at least one embodiment, a training framework 102 trains an implicit environment function 106 using training data 104 to determine an implicit environment function 108. In at least one embodiment, one or more systems input a query position 110 to an implicit environment function 108, which represents an environment through an environment field, visualized by an environment field visualization 112, to determine a reaching distance 114.

[0091] In at least one embodiment, a training framework 102 is a collection of one or more hardware and / or software computing resources with instructions that, when executed, performs one or more neural network training processes, functions, and / or operations. In at least one embodiment, a training framework 102 is in accordance with those described in connection with FIG. 13. In at least one embodiment, a training framework 102 is a framework such as PyTorch, TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, a training framework 102 is a software program executing on computer hardware, application executing on computer hardware, and / or variations thereof. In at least one embodiment, a training framework 102 trains an implicit environment function 106 using training data 104 to determine an implicit environment function 108.

[0092] In at least one embodiment, training data 104 is generated by one or more path planning algorithms, methods, and / or systems based on one or more environments. In at least one embodiment, training data 104 is a collection of data that comprises one or more reaching distances from one or more accessible positions in an environment to a particular goal position in said environment. In at least one embodiment, training data 104 is implemented through one or more data structures, such as an array or list, or any suitable collection of data, that encodes reaching distances and positions corresponding to said reaching distances. In at least one embodiment, a position of an environment corresponds to any suitable location, region, or area of said environment. In at least one embodiment, an environment is represented by an image, in which each position corresponds to a pixel and / or collection of pixels of said image. In at least one embodiment, an environment is represented by a set of points (e.g., point cloud data), in which each position corresponds to a point and / or collection of points of said set of points. In at least one embodiment, training data 104 is generated by one or more path planning algorithms, methods, and / or systems that, based on an input environment (e.g., through an image, set of points, and / or variations thereof) and a goal position, outputs a reaching distance for each accessible position in said environment to said goal position.

[0093] In at least one embodiment, a training framework 102 trains an implicit environment function 106 using training data 104 to represent an environment with a particular goal position (e.g., an environment and a goal position used to generate training data 104) through an environment field. In at least one embodiment, an implicit environment function 106 is any suitable neural network model, algorithm, representation, function, and / or variations thereof. In at least one embodiment, an implicit environment function comprises various neural network models such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), Boltzmann Machine (BM), Restricted Boltzmann Machine (RBM), deep belief network (DBN), deep convolutional network (DCN), extreme learning machine (ELM), deep residual network (DRN), support vector machines (SVM), and / or variations thereof.

[0094] In at least one embodiment, a training framework 102 trains an implicit environment function 106 by inputting a position of training data 104 to said implicit environment function 106, causing said implicit environment function 106 to calculate a reaching distance for said position, comparing said calculated reaching distance for said position to a reaching distance of training data 104, also referred to as a ground truth reaching distance, corresponding to said position, calculating loss using one or more loss functions based on said comparison, and updating said implicit environment function 106 based on calculated loss. In at least one embodiment, a training framework 102 updates one or more weights, biases, and / or structural connections (e.g., architecture(s) and / or configuration(s) of one or more components) of an implicit environment function 106 such that calculated loss is minimized. In at least one embodiment, a training framework 102 calculates loss using any suitable loss function, such as cross-entropy loss, binary cross-entropy loss, softmax loss, logistic loss, focal loss, and / or variations thereof.

[0095] In at least one embodiment, an implicit environment function 106 is trained when calculated loss for said implicit environment function 106 is below a defined threshold, which can be any suitable value. In at least one embodiment, a training framework 102 trains an implicit environment function 106 to represent reaching distances for positions to a particular goal position in an environment used to generate training data 104. In at least one embodiment, a training framework 102 trains an implicit environment function 106 to determine an implicit environment function 108, which is said implicit environment function 106 after one or more training processes. In at least one embodiment, an implicit environment function 108 is a trained implicit environment function 106. In at least one embodiment, an implicit environment function 108 is specific to an environment and a goal position utilized to generate training data 104.

[0096] In at least one embodiment, an implicit environment function 108 represents an environment (e.g., an environment used to generate training data 104) through an environment field. In at least one embodiment, an implicit environment function 108 represents an environment internally through an environment field representation. In at least one embodiment, an environment field is a representation of an environment in which each position of said environment field corresponds to a position of said environment, and each position of said environment field comprises or otherwise indicates a reaching distance value to a particular goal position. In at least one embodiment, a reaching distance value for a particular position of an environment field indicates a reaching distance from a corresponding position of an environment to a goal position in said environment.

[0097] In at least one embodiment, an implicit environment function 108 represents an environment via an environment field through one or more data structures and / or collections of data that encode positions of said environment and reaching distances for said positions to a particular goal position in said environment. In at least one embodiment, an environment field is visualized through an environment field visualization 112. In at least one embodiment, an environment field visualization 112 is an image in which each position of said environment field visualization 112 corresponds to a position of an environment field. In at least one embodiment, different colors, shades, patterns, and / or variations thereof of an environment field visualization 112 correspond to different reaching distance values. In at least one embodiment, referring to FIG. 1, an environment field visualization 112 comprises lighter shading for lower reaching distance values, darker shading for higher reaching distance values, and completely dark shading for inaccessible regions. In at least one embodiment, an environment field visualization can represent reaching distance values of an environment field in any suitable manner, such as a color gradient (e.g., light color for lower reaching distance values, darker color for higher reaching distance values, or any suitable scheme), specific colors (e.g., particular colors for lower reaching distance values, different particular colors for higher reaching distance values), and / or variations thereof.

[0098] In at least one embodiment, one or more systems input a query position 110 to an implicit environment function 108 to determine a reaching distance 114. In at least one embodiment, a query position 110 is a position in an environment, and is implemented through one or more data objects, types, and / or variations thereof, that encode said position. In at least one embodiment, a query position 110 comprises coordinate data indicating a position. In at least one embodiment, an implicit environment function 108 processes a query position 110 to calculate a reaching distance 114. In at least one embodiment, a reaching distance 114 is a reaching distance value and is implemented through one or more data objects, types, and / or variations thereof, that encode said reaching distance value. In at least one embodiment, a reaching distance 114 comprises a reaching distance value from a position in an environment indicated by a query position 110 to a particular goal position in said environment (e.g., an environment and a particular goal position utilized to generate training data 104). In at least one embodiment, one or more systems utilize a determined reaching distance 114 for various navigation tasks, as described in further detail with regards to FIGS. 4 - 11. In at least one embodiment, one or more systems utilize determined reaching distance values to calculate a plurality of paths, through which an entity, such as an autonomous device, is to traverse.

[0099] In at least one embodiment, one or more systems train an implicit function to predict different environment fields for different goal positions in a same environment, which can be referred to as a conditional implicit function. FIG. 2 illustrates an example 200 of an implicit environment function for different goal positions in an environment, according to at least one embodiment. In at least one embodiment, a training framework 202 trains an implicit environment function 206 using training data 204 to determine an implicit environment function 208. In at least one embodiment, one or more systems input a query position 210 and a goal position 212 to an implicit environment function 208, which represents an environment through an environment field, visualized by environment field visualizations 214A-214B, to calculate a reaching distance 216. In at least one embodiment, a training framework 202, training data 204, an implicit environment function 206, an implicit environment function 208, a query position 210, a goal position 212, environment field visualizations 214A-214B, and a reaching distance 216 are in accordance with those described in connection with FIG. 1.

[0100] In at least one embodiment, a training framework 202 is a collection of one or more hardware and / or software computing resources with instructions that, when executed, performs one or more neural network training processes, functions, and / or operations. In at least one embodiment, a training framework 202 trains an implicit environment function 206 using training data 204 to determine an implicit environment function 208. In at least one embodiment, training data 204 is generated by one or more path planning algorithms, methods, and / or systems based on one or more environments. In at least one embodiment, training data 204 is a collection of data that comprises one or more reaching distances for one or more accessible positions in an environment to one or more goal positions in said environment. In at least one embodiment, training data 204 is implemented through one or more data structures, such as an array or list, or any suitable collection of data, that encodes reaching distances, and positions and goal positions corresponding to said reaching distances.

[0101] In at least one embodiment, training data 204 is generated by one or more path planning algorithms, methods, and / or systems that, based on an input environment (e.g., through an image, set of points, and / or variations thereof) and one or more goal positions, output one or more reaching distances for each accessible position in said environment to said one or more goal positions. In at least one embodiment, training data 204 is generated by one or more systems by inputting an environment and one or more randomly sampled goal positions to one or more path planning algorithms, methods, and / or systems to determine one or more reaching distances from each accessible position in said environment to said one or more randomly sampled goal positions.

[0102] In at least one embodiment, a training framework 202 trains an implicit environment function 206 using training data 204 to represent an environment (e.g., an environment used to generate training data 204) with any suitable goal position through an environment field. In at least one embodiment, an implicit environment function 206 is any suitable neural network model, algorithm, representation, function, and / or variations thereof. In at least one embodiment, an implicit environment function 206 comprises various neural network models such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), Boltzmann Machine (BM), Restricted Boltzmann Machine (RBM), deep belief network (DBN), deep convolutional network (DCN), extreme learning machine (ELM), deep residual network (DRN), support vector machines (SVM), and / or variations thereof.

[0103] In at least one embodiment, a training framework 202 trains an implicit environment function 206 by inputting a position and a goal position of training data 204 to said implicit environment function 206, causing said implicit environment function 206 to calculate a reaching distance for said position to said goal position, comparing said calculated reaching distance for said position to said goal position to a reaching distance of training data 204, also referred to as a ground truth reaching distance, corresponding to said position and said goal position, calculating loss using one or more loss functions based on said comparison, and updating said implicit environment function 206 based on calculated loss. In at least one embodiment, a training framework 202 updates one or more weights, biases, and / or structural connections (e.g., architecture(s) and / or configuration(s) of one or more components) of an implicit environment function 206 such that calculated loss is minimized. In at least one embodiment, a training framework 202 calculates loss using any suitable loss function, such as cross-entropy loss, binary cross-entropy loss, softmax loss, logistic loss, focal loss, and / or variations thereof.

[0104] In at least one embodiment, an implicit environment function 206 is trained when calculated loss for said implicit environment function 206 is below a defined threshold, which can be any suitable value. In at least one embodiment, a training framework 202 trains an implicit environment function 206 to represent reaching distances for positions to any suitable goal position in an environment used to generate training data 204. In at least one embodiment, a training framework 202 trains an implicit environment function 206 to determine an implicit environment function 208, which is said implicit environment function 206 after one or more training processes. In at least one embodiment, an implicit environment function 208 is a trained implicit environment function 206. In at least one embodiment, an implicit environment function 208 is specific to an environment utilized to generate training data 204.

[0105] In at least one embodiment, an implicit environment function 208 represents an environment (e.g., an environment used to generate training data 204) through an environment field. In at least one embodiment, an implicit environment function 208 represents an environment with any suitable goal position internally through an environment field representation. In at least one embodiment, an implicit environment function 208 determines an environment field representation based on an input goal position (e.g., goal position 212). In at least one embodiment, an implicit environment function 208 represents an environment via an environment field through one or more data structures and / or collections of data that encode positions of said environment and reaching distances for said positions to a particular goal position (e.g., input via a goal position 212) in said environment.

[0106] In at least one embodiment, an environment field is visualized through environment field visualizations 214A-214B. In at least one embodiment, an environment field visualization is an image in which each position of said environment field visualization corresponds to a position of an environment field. In at least one embodiment, different colors, shades, patterns, and / or variations thereof of an environment field visualization correspond to different reaching distance values. In at least one embodiment, referring to FIG. 2, environment field visualizations 214A-214B comprise lighter shading for lower reaching distance values, darker shading for higher reaching distance values, and completely dark shading for inaccessible regions. In at least one embodiment, referring to FIG. 2, an implicit environment function 208 determines an environment field visualized by an environment field visualization 214A based on a first goal position value (e.g., indicated by goal position 212) corresponding to a goal position in a top left corner of an environment, and / or a different environment field visualized by an environment field visualization 214B based on a second goal position value (e.g., indicated by goal position 212) corresponding to a goal position in a bottom right corner of an environment.

[0107] In at least one embodiment, one or more systems input a query position 210 and a goal position 212 to an implicit environment function 208 to calculate a reaching distance 216. In at least one embodiment, one or more systems concatenate a query position 210 and a goal position 212. In at least one embodiment, a query position 210 is a position in an environment, and is implemented through one or more data objects, types, and / or variations thereof, that encode said position. In at least one embodiment, a query position 210 comprises coordinate data indicating a position. In at least one embodiment, a goal position 212 is a goal position in an environment, and is implemented through one or more data objects, types, and / or variations thereof, that encode said position. In at least one embodiment, a goal position 212 comprises coordinate data indicating a goal position.

[0108] In at least one embodiment, an implicit environment function 208 processes a query position 210 and a goal position 212 to determine a reaching distance 216 (e.g., an environment field value at a query position 210). In at least one embodiment, a reaching distance 216 is a reaching distance value and is implemented through one or more data objects, types, and / or variations thereof, that encode said reaching distance value. In at least one embodiment, a reaching distance 216 comprises a reaching distance value from a position in an environment indicated by a query position 210 to a particular goal position indicated by a goal position 212 in said environment (e.g., an environment utilized to generate training data 204). In at least one embodiment, one or more systems utilize a determined reaching distance 216 for various navigation tasks, as described in further detail with regards to FIGS. 4-11.

[0109] In at least one embodiment, one or more systems, to extend an implicit function to an arbitrary environment, train an implicit environment function to generalize to any environment and / or any goal position, also referred to as a context-aligned implicit function. In at least one embodiment, given a scene context (e.g., a representation of an environment, such as an image or set of points), one or more systems extract scene context features using a fully convolutional environment encoder. In at least one embodiment, one or more systems forward a concatenation of goal coordinates, query position coordinates, and scene context features aligned to said query position into an implicit function, and regress a reaching distance value for said query position. In at least one embodiment, a fully convolutional environment encoder enlarges a receptive field at a query position such that an implicit function has sufficient contextual information to predict a reaching distance to a goal. In at least one embodiment, scene environment feature alignment causes an implicit function to focus on a query position while ignoring other scene context information. In at least one embodiment, one or more systems utilize various neural network models, such as hypernetworks, to encode arbitrary environments and goals.

[0110] In at least one embodiment, one or more systems train a context-aligned implicit function using different environments (e.g., mazes), along with reaching distances computed by one or more path planning algorithms, methods, and / or systems as training data. In at least one embodiment, during inference, an implicit environment function predicts or otherwise calculates an environment field for an environment with a given goal position, and is utilized to search for a feasible trajectory from any start position to said goal position. [01II] FIG. 3 illustrates an example 300 of an implicit environment function for different goal positions and environments, according to at least one embodiment. In at least one embodiment, a training framework 302 trains an implicit environment function 306 using training data 304 to determine an implicit environment function 308. In at least one embodiment, one or more systems input a query position 316, a goal position 318, and features 314 determined by an encoder 312 based on environment images 310, to an implicit environment function 308, which represents an environment through an environment field, visualized by environment field visualizations 320A-320B, to determine a reaching distance 322. In at least one embodiment, a training framework 302, training data 304, an implicit environment function 306, an implicit environment function 308, a query position 316, a goal position 318, environment field visualizations 320A-320B, and a reaching distance 322 are in accordance with those described in connection with FIGS. 1 and 2.

[0112] In at least one embodiment, a training framework 302 is a collection of one or more hardware and / or software computing resources with instructions that, when executed, performs one or more neural network training processes, functions, and / or operations. In at least one embodiment, a training framework 302 trains an implicit environment function 306 using training data 304 to determine an implicit environment function 308. In at least one embodiment, training data 304 is a collection of data that comprises one or more reaching distances for one or more accessible positions in one or more environments to one or more goal positions in said one or more environments. In at least one embodiment, training data 304 is implemented through one or more data structures, such as an array or list, or any suitable collection of data, which encodes reaching distances, positions, goal positions, and / or environments.

[0113] In at least one embodiment, training data 304 is generated by one or more path planning algorithms, methods, and / or systems that, based on an input environment (e.g., through an image, set of points, features of an environment, and / or variations thereof) and one or more goal positions, output one or more reaching distances for each accessible position in said environment to said one or more goal positions. In at least one embodiment, training data 304 is generated by one or more systems by inputting an environment and one or more randomly sampled goal positions to one or more path planning algorithms, methods, and / or systems to determine one or more reaching distances for each accessible position in said environment to said one or more randomly sampled goal positions. In at least one embodiment, training data 304 is generated by one or more path planning algorithms, methods, and / or systems based on one or more environments. In at least one embodiment, for example, training data 304 comprises one or more reaching distances for each accessible position of a first environment to one or more goal positions in said first environment, one or more reaching distances for each accessible position of a second environment to one or more goal positions in said second environment, and so on for any number of environments. In at least one embodiment, one or more systems use various neural network models, and / or other appropriate systems, to define accessible and / or inaccessible regions for an environment.

[0114] In at least one embodiment, a training framework 302 trains an implicit environment function 306 using training data 304 to represent any suitable environment with any suitable goal position through an environment field. In at least one embodiment, an implicit environment function 306 is any suitable neural network model, algorithm, representation, function, and / or variations thereof. In at least one embodiment, an implicit environment function 306 comprises various neural network models such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), Boltzmann Machine (BM), Restricted Boltzmann Machine (RBM), deep belief network (DBN), deep convolutional network (DCN), extreme learning machine (ELM), deep residual network (DRN), support vector machines (SVM), and / or variations thereof. [0115} In at least one embodiment, a training framework 302 trains an implicit environment function 306 by determining features of each environment used to generate training data 304. In at least one embodiment, a training framework 302 determines or otherwise generates features, also referred to as environment features, scene features, scene context features, and / or variations thereof, from an environment through an encoder (e.g., an encoder 312). In at least one embodiment, an encoder is a neural network that processes an input and outputs a representation of said input, also referred to as features of said input, that indicates various features of said input. In at least one embodiment, features of an input can comprise indications of various details or other characteristics of said input, such as edges, certain patterns, objects, obstacles, accessible / inaccessible regions, other features, and / or variations thereof. In at least one embodiment, features are represented through a feature map, a set of feature vectors, or any suitable representation. In at least one embodiment, an encoder is a convolutional neural network (CNN), recurrent neural network (RNN), and / or variations thereof. In at least one embodiment, an encoder is a convolutional-based encoder. In at least one embodiment, a training framework 302 inputs an environment (e.g., via an image, set of points, or other representation) to an encoder to determine features of said environment, which are represented through a feature map output by said encoder, or any suitable representation, such as one or more feature vectors.

[0116] In at least one embodiment, a training framework 302 performs various feature alignment processes on determined features based on a query position. In at least one embodiment, a training framework 302 performs one or more feature alignment processes on features determined from an environment based on a query position that attenuate or otherwise enhance portions of said features corresponding to said query position. In at least one embodiment, a feature map indicates features of each position of an environment, in which a training framework 302 aligns said feature map based on a query position in said environment by attenuating or otherwise enhancing particular aspects of said feature map that correspond to said query position (e.g., features of said query position).

[0117] In at least one embodiment, a training framework 302 trains an implicit environment function 306 by inputting a position, a goal position, and features of an environment (e.g., features which may be aligned based on a position) of training data 304 to said implicit environment function 306, causing said implicit environment function 306 to calculate a reaching distance for said position to said goal position, comparing said calculated reaching distance for said position to said goal position to a reaching distance of training data 304, also referred to as a ground truth reaching distance, corresponding to said position, said goal position, and said environment, calculating loss using one or more loss functions based on said comparison, and updating said implicit environment function 306 based on calculated loss. In at least one embodiment, a training framework 302 updates one or more weights, biases, and / or structural connections (e.g., architecture(s) and / or configuration(s) of one or more components) of an implicit environment function 306 such that calculated loss is minimized. In at least one embodiment, a training framework 302 calculates loss using any suitable loss function, such as cross-entropy loss, binary cross-entropy loss, softmax loss, logistic loss, focal loss, and / or variations thereof.

[0118] In at least one embodiment, an implicit environment function 306 is trained when calculated loss for said implicit environment function 306 is below a defined threshold, which can be any suitable value. In at least one embodiment, a training framework 302 trains an implicit environment function 306 to represent reaching distances for positions to any suitable goal position for any suitable environment. In at least one embodiment, a training framework 302 trains an implicit environment function 306 to determine an implicit environment function 308, which is said implicit environment function 306 after one or more training processes. In at least one embodiment, an implicit environment function 308 is a trained implicit environment function 306. In at least one embodiment, an implicit environment function 308 processes environments that may or may not have been utilized to generate training data 304.

[0119] In at least one embodiment, an implicit environment function 308 represents an environment through an environment field. In at least one embodiment, an implicit environment function 308 represents any suitable environment with any suitable goal position internally through an environment field representation. In at least one embodiment, an implicit environment function 308 determines an environment field representation based on an input goal position (e.g., goal position 318) and features of an environment (e.g., features 314). In at least one embodiment, an implicit environment function 308 represents an environment (e.g., an environment corresponding to features 314) via an environment field through one or more data structures and / or collections of data that encode positions of said environment and reaching distances for said positions to a particular goal position (e.g., input via a goal position 318) in said environment.

[0120] In at least one embodiment, an environment field is visualized through environment field visualizations 320A-320B. In at least one embodiment, an environment field visualization is an image in which each position of said environment field visualization corresponds to a position of an environment field. In at least one embodiment, different colors, shades, patterns, and / or variations thereof of an environment field visualization correspond to different reaching distance values. In at least one embodiment, referring to FIG. 3, environment field visualizations 320A-320B comprise lighter shading for lower reaching distance values, darker shading for higher reaching distance values, and completely dark shading for inaccessible regions. In at least one embodiment, referring to FIG. 3, an implicit environment function 308 determines an environment field visualized by an environment field visualization 320A based on features (e.g., indicated by features 314) of an environment corresponding to an environment image 310A determined by an encoder 312 and a first goal position value (e.g., indicated by goal position 318) corresponding to a goal position in a bottom right corner of said environment, and / or a different environment field visualized by an environment field visualization 320B based on features (e.g., indicated by features 314) of an environment corresponding to an environment image 31 OB determined by an encoder 312 and a second goal position value (e.g., indicated by goal position 318) corresponding to a goal position in a top right corner of said environment.

[0121] In at least one embodiment, environment images 310 comprise images, or other representations, such as sets of points, of environments. In at least one embodiment, a representation of an environment is referred to as an environment context and / or a scene context. In at least one embodiment, one or more systems input an environment (e.g., via an image or other representation of environment images 310 representing an environment) to an encoder 312 to determine features of said environment, which are represented through a feature map output by encoder 312, or any suitable representation, such as one or more feature vectors. In at least one embodiment, one or more systems perform various feature alignment processes on determined features based on a query position (e.g., indicated by a query position 316). In at least one embodiment, one or more systems perform one or more feature alignment processes on features determined from an environment (e.g., represented via an image or other representation) based on a query position that attenuate or otherwise enhance portions of said features corresponding to said query position. In at least one embodiment, a feature map indicates features of each position of an environment, in which one or more systems align said feature map based on a query position in said environment by attenuating or otherwise enhancing particular aspects of said feature map that correspond to said query position (e.g., features of said query position).

[0122] In at least one embodiment, features 314 comprise features output by an encoder 312 (e.g., a feature map) based on an environment (e.g., an environment represented by a representation of environment images 310). In at least one embodiment, features 314 comprise features output by an encoder 312 based on an environment (e.g., an environment represented by a representation of environment images 310) processed through one or more alignment processes based on a query position 316 (e.g., an aligned feature map).

[0123] In at least one embodiment, one or more systems input features 314, a query position 316, and a goal position 318 to an implicit environment function 308 to calculate a reaching distance 322. In at least one embodiment, one or more systems concatenate input features 314, a query position 316, and a goal position 318. In at least one embodiment, a query position 316 is a position in an environment, and is implemented through one or more data objects, types, and / or variations thereof, that encode said position. In at least one embodiment, a query position 316 comprises coordinate data indicating a position. In at least one embodiment, a goal position 318 is a goal position in an environment, and is implemented through one or more data objects, types, and / or variations thereof, that encode said position. In at least one embodiment, a goal position 318 comprises coordinate data indicating a goal position.

[0124] In at least one embodiment, an implicit environment function 308 processes features 314, a query position 316, and a goal position 318 to determine a reaching distance 322 (e.g., an environment field value at a query position 316). In at least one embodiment, a reaching distance 322 is a reaching distance value and is implemented through one or more data objects, types, and / or variations thereof, that encode said reaching distance value. In at least one embodiment, a reaching distance 322 comprises a reaching distance value for an environment corresponding to features 314 (e.g., an environment utilized to generate features 314) from a position in said environment indicated by a query position 316 to a particular goal position indicated by a goal position 318 in said environment.

[0125] In at least one embodiment, a query position 316 indicates one or more positions in an environment corresponding to features 314 (e.g., an environment utilized to generate features 314), in which a reaching distance 322 comprises a reaching distance value for each position of said one or more positions to a particular goal position indicated by a goal position 318 in said environment. In at least one embodiment, features 314 comprises one or more features each aligned to a particular position of a query position 316. In at least one embodiment, an implicit environment function 308 calculates any number of reaching distance values for any number of query positions to a particular goal position in a single forward pass. In at least one embodiment, one or more systems utilize a determined reaching distance 322 to determine a plurality of paths for various navigation tasks, as described in further detail with regards to FIGS. 4 - 11.

[0126] FIG. 4 illustrates an example 400 of an agent navigating to a goal using an implicit environment function, according to at least one embodiment. In at least one embodiment, an agent 404 navigates to a goal 408 using an implicit environment function, such as those described elsewhere in this disclosure. In at least one embodiment, an agent 404 is any suitable entity that can navigate an environment. In at least one embodiment, an agent 404 is an autonomous device associated with one or more systems that implement or otherwise utilize one or more implicit environment functions. In at least one embodiment, an autonomous device is a device such as an autonomous vehicle, autonomous aircraft (e.g., drone), robot, and / or variations thereof. In at least one embodiment, an agent 404 comprises one or more systems with one or more hardware and / or software resources that implement or otherwise utilize one or more implicit environment functions. In at least one embodiment, an agent 404 communicates to one or more systems that comprise one or more hardware and / or software resources that implement or otherwise utilize one or more implicit environment functions. In at least one embodiment, an implicit environment function is trained through one or more processes such as those described in connection with FIGS. 1-3.

[0127] In at least one embodiment, an environment 402 is any suitable environment such as various indoor environments, outdoor environments, maze environments, and / or variations thereof. In at least one embodiment, an environment 402 is a physical environment. In at least one embodiment, an agent 404 is a virtual entity in which an environment 402 is a virtual or otherwise simulated environment. In at least one embodiment, an environment 402 comprises various inaccessible regions, depicted in FIG. 4 by completely dark shaded regions. In at least one embodiment, inaccessible regions correspond to regions inaccessible to an agent 404. In at least one embodiment, for example, an agent 404 is an autonomous vehicle, in which inaccessible regions correspond to obstacles, objects, and / or variations thereof that said autonomous vehicle cannot travel on or through, such as a building or other vehicle. In at least one embodiment, an environment 402 comprises a goal 408.

[0128] In at least one embodiment, a goal 408 indicates a position, also referred to as a location, in an environment 402. In at least one embodiment, a goal 408 is a position in an environment 402 where an agent 404 is to navigate to. In at least one embodiment, one or more systems define a navigation task indicating that an agent 404 is to navigate through an environment 402 to a goal 408. In at least one embodiment, one or more systems input features of an environment 402 to an implicit environment function. In at least one embodiment, one or more systems determine features of an environment 402 by processing a representation of said environment 402. In at least one embodiment, an environment 402 is represented in any suitable manner, such as through an image, set of points, point cloud, set of voxels, and / or variations thereof. In at least one embodiment, an environment is represented through any suitable 2D representation, such as an image, set of points, and / or variations thereof, or any suitable 3D representation, such as an image with depth information, point cloud, set of voxels, and / or variations thereof.

[0129] In at least one embodiment, one or more systems determine features of an environment 402 by inputting a representation of said environment 402 to one or more encoders which output said features. In at least one embodiment, one or more systems perform various feature alignment processes on features to determine one or more aligned features, each aligned to a particular position of said environment 402. In at least one embodiment, one or more systems input features of an environment and an indication of a position of a goal 408 to an implicit environment function. In at least one embodiment, one or more systems input an indication of one or more positions of an environment 402, one or more features (e.g., features aligned to said one or more positions), and an indication of a position of a goal 408 to an implicit environment function. In at least one embodiment, an indication of a position refers to any suitable indication of said position, such as coordinate data or other indications.

[0130] In at least one embodiment, an implicit environment function outputs a reaching distance value for each position (e.g., each accessible position) in an environment 402 to a goal 408. In at least one embodiment, an implicit environment function outputs a reaching distance value for each position input to said implicit environment function. In at least one embodiment, one or more systems visualize an environment field for an environment 402 using reaching distance values by visualizing each reaching distance value for each position of environment 402 through a particular color scheme, shading scheme, and / or variations thereof. In at least one embodiment, for example, one or more systems visualize an environment field by assigning different shades to particular reaching distance values, such as lighter shading for lower reaching distance values, darker shading for higher reaching distance values, and completely dark shading for inaccessible regions.

[0131] In at least one embodiment, one or more systems utilize reaching distance values to guide an agent 404 to a goal 408. In at least one embodiment, one or more systems determine a reaching distance value for each position accessible to an agent 404 from its current position. In at least one embodiment, one or more systems define a step size for an agent 404 that corresponds to a distance of each step of movement an agent 404 can take, in which said one or more systems determine a reaching distance value for each position accessible to an agent 404 through a step, size of said step corresponding to said defined step size, from its current position. In at least one embodiment, a step refers to a step of movement or navigation of an entity. In at least one embodiment, a step size refers to how far an entity travels per step. In at least one embodiment, a step size can be any suitable distance value. In at least one embodiment, one or more systems represent an environment 402 through a grid, in which each grid cell represents a position, and an agent 404 can move to any grid cell immediately accessible to a current grid cell of agent 404. In at least one embodiment, a size of a grid cell can be any suitable value. In at least one embodiment, an agent 404 can move from a center of a grid cell to a center of an adjacent accessible grid cell. In at least one embodiment, one or more systems determine a reaching distance value for each grid cell accessible to an agent 404 from its current grid cell.

[0132] In at least one embodiment, one or more systems determine a reaching distance value for each position accessible through a step from a current position of an agent 404. In at least one embodiment, a size of a step of an agent 404 corresponds to a distance travelled through one or more movements of agent 404, and can be any suitable distance value. In at least one embodiment, for example, an agent 404 is an autonomous robot comprising robotic legs, wheels, and / or other hardware for movement, in which, a size of a step corresponds to a distance travelled through one or more steps of said robot legs, distance travelled through one or more rotations of said wheels, and / or variations thereof. In at least one embodiment, one or more systems determine a position with a minimum reaching distance value of a set of positions accessible through a step from a current position of agent 404, determine a path to said position, and cause agent 404 to navigate using said path to said position. In at least one embodiment, one or more systems determine a position with a minimum reaching distance value of a set of positions by comparing each reaching distance value of each position of said set of positions, and determining which position of said set of positions has a minimum reaching distance value. In at least one embodiment, a position is determined with a minimum reaching distance value, a maximum reaching distance value, a reaching distance value under a threshold, or any suitable reaching distance value. In at least one embodiment, one or more systems utilize reaching distance values to calculate a plurality of paths (e.g., paths 406A-406E) through which an entity (e.g., an agent) is to traverse or otherwise navigate.

[0133] In at least one embodiment, one or more systems cause an agent to navigate to one or more positions until said agent is within a step size from a goal and can navigate to said goal, in which said one or more systems cause said agent to navigate to said goal. In at least one embodiment, for example, for a navigation task, one or more systems determine a first position with a minimum reaching distance value of a first set of positions accessible through a step from a current position of agent, determine a first path to said first position, and cause said agent to navigate through said first path to said first position, in which said one or more systems then determine a second position with a minimum reaching distance value of a second set of positions accessible through a step from a new current position of agent, determine a second path to said second position, and cause said agent to navigate through said second path to said second position and so on, until said agent is at a position within a step size from a goal position, in which said one or more systems can cause said agent to navigate to said goal position to complete said navigation task. 10134] In at least one embodiment, referring to FIG. 4, path 406A indicates a path to a position with a minimum reaching distance value of a set of positions accessible through a step from a current position of an agent 404. In at least one embodiment, referring to FIG. 4, one or more systems cause an agent 404 to navigate to a first position through a path 406A. In at least one embodiment, referring to FIG. 4, one or more systems then determine a second position with a minimum reaching distance value of a set of positions accessible through a step from a first position of an agent 404, and determine a path 406B from said first position to said second position. In at least one embodiment, referring to FIG. 4, one or more systems cause an agent 404 to navigate to a second position through a path 406B. In at least one embodiment, referring to FIG. 4, one or more systems then determine a third position with a minimum reaching distance value of a set of positions accessible through a step from a second position of an agent 404, and determine a path 406C from said second position to said third position. In at least one embodiment, referring to FIG. 4, one or more systems cause an agent 404 to navigate to a third position through a path 406C. In at least one embodiment, referring to FIG. 4, one or more systems then determine a fourth position with a minimum reaching distance value of a set of positions accessible through a step from a third position of an agent 404, and determine a path 406D from said third position to said fourth position. In at least one embodiment, referring to FIG. 4, one or more systems cause an agent 404 to navigate to a fourth position through a path 406D. In at least one embodiment, referring to FIG. 4, one or more systems then determine that a goal 408 is accessible through a step from a fourth position of an agent 404, and determine a path 406E from said fourth position to goal 408. In at least one embodiment, referring to FIG. 4, one or more systems cause an agent 404 to navigate to a goal 408 through a path 406E.

[0135] In at least one embodiment, one or more systems navigate an agent through an environment through determining one or more reaching distance values for one or more positions accessible from an agent’s current position, determining one or more reaching distance values for one or more positions accessible through a step, in which size of said step is pre-defined, from an agent’s current position, representing an environment through a grid and determining one or more reaching distance values for one or more grid cells accessible from an agent’s current grid cell, and / or variations thereof. In at least one embodiment, one or more systems use an implicit environment function to calculate a plurality of paths, also referred to as a plurality of trajectories and / or a trajectory, for an agent to traverse or otherwise navigate to a goal.

[0136] FIG. 5 illustrates an example 500 of environment fields for a multiple person navigation environment, according to at least one embodiment. In at least one embodiment, FIG. 5 illustrates environment fields from a top-down view, also referred to as a bird’s eye view, of an environment. In at least one embodiment, a scene 502A, a scene 502B, an environment field visualization 504A, and an environment field visualization 504B are in accordance with those described elsewhere in this disclosure.

[0137] In at least one embodiment, a scene 502A and / or a scene 502B are top-down views of an environment. In at least one embodiment, a scene 502A and / or a scene 502B are top-down views of a 3D environment. In at least one embodiment, one or more systems capture a scene 502A and / or a scene 502B using a depth camera, or other suitable hardware that can capture depth information. In at least one embodiment, images of a scene 502A and / or a scene 502B comprise depth information associated with each pixel of said images.

[0138] In at least one embodiment, to model human walking, one or more systems define a floor area as an accessible region for humans in a bird’s eye view of a 3D scene. In at least one embodiment, one or more systems determine depth of each pixel in a bird’s eye view rendering and label pixels with maximum depth as a floor. In at least one embodiment, one or more systems denote all pixels belonging to a floor area as accessible and other pixels as obstacles, also referred to as inaccessible. In at least one embodiment, one or more systems utilize a bird’s eye view image with denoted accessible and inaccessible regions to train an implicit environment function. In at least one embodiment, one or more systems utilize arbitrary goal positions as well as arbitrary environments to train an implicit environment function to determine an environment field of any bird’s eye view image.

[0139] In at least one embodiment, one or more systems, during inference, given a start and a goal position, search for a feasible trajectory that leads a human to navigate from said start position to said goal while avoiding collision with obstacles in a room. In at least one embodiment, one or more systems define a human step size, which can be a value that approximates an average human step size, and move a human one step towards a direction that yields a largest reaching distance reduction. In at least one embodiment, one or more systems repeat this process until a human reaches a goal. In at least one embodiment, given a searched trajectory in a bird’s eye view, one or more systems align an existing human walking sequence onto it by rotating a human pose towards a tangent direction of a trajectory at each time step. 10140] In at least one embodiment, one or more systems utilize an implicit environment function to navigate multiple people in a multiple person environment. In at least one embodiment, FIG. 5 illustrates a navigation task in a multiple person environment. In at least one embodiment, scene 502A depicts a scene at a first time, in which a human 506A is to navigate to a goal. In at least one embodiment, one or more systems denote a human 508A as an obstacle. In at least one embodiment, one or more systems input features of a scene 502A into an implicit environment function to determine reaching distance values, and generate an environment field visualization 504A based on said reaching distance values. In at least one embodiment, one or more systems navigate a human 506A based on an environment field visualization 504A. In at least one embodiment, scene 502B depicts a scene at a second time, in which a human 506B (e.g., corresponding to a human 506A) has moved as part of a navigation task, and a human 508B (e.g., corresponding to a human 508A) has also moved. In at least one embodiment, one or more systems denote a human 508B as an obstacle. In at least one embodiment, one or more systems input features of a scene 502B into an implicit environment function to determine reaching distance values, and generate an environment field visualization 504B based on said reaching distance values. In at least one embodiment, one or more systems navigate a human 506B based on an environment field visualization 504B. In at least one embodiment, an environment field changes dynamically based on changes to an environment. In at least one embodiment, an environment field can be generated any number of times for any number of changes of an environment by inputting features corresponding to a current state of said environment. In at least one embodiment, one or more systems, during training of an implicit environment function, denote random spaces as obstacles to mimic an arbitrary scene with arbitrary obstacles which can be encountered during inference. [0141 ] FIG. 6 illustrates an example 600 of use of an implicit environment field for a 3D environment, according to at least one embodiment. In at least one embodiment, one or more systems utilize an implicit environment function to process a 3D environment 602 to determine an accessible region visualization 604, an environment field visualization 606, and a trajectory visualization 608. In at least one embodiment, an environment field visualization 606 is in accordance with those described elsewhere in this disclosure.

[0142] In at least one embodiment, a 3D environment 602 is any suitable environment such as various indoor environments, outdoor environments, maze environments, and / or variations thereof. In at least one embodiment, a 3D environment 602 is a physical environment. In at least one embodiment, a 3D environment 602 is an environment in which an entity is to navigate through to a goal as part of a navigation task.

[0143] In at least one embodiment, one or more systems define accessible regions for 3D environments, also referred to as 3D scenes. In at least one embodiment, one or more systems train a generative model to generate an accessible region for humans in a 3D environment. In at least one embodiment, one or more systems learn a distribution of human torso locations in 3D scenes, conditioned on a scene context, through a variational auto-encoder (VAE). In at least one embodiment, one or more systems generate features from a scene point cloud using one or more layers such as a pooling layer of a network such as Point-Net as a scene context feature. In at least one embodiment, one or more systems map a context feature together with human torso location observations to a normal distribution using an encoder. In at least one embodiment, one or more systems utilize a decoder that reconstructs a human torso location given a concatenation of a sampled noise from a normal distribution and a scene context feature. In at least one embodiment, one or more systems train a VAE using a reconstruction objective on human torso locations together with an objective such as a Kullback-Leibler (KL) divergence objective. In at least one embodiment, one or more systems, during inference, sample random noise from a standard normal distribution to generate feasible locations for human torsos to formulate an accessible region in a 3D scene. In at least one embodiment, one or more systems, to further suppress a noisy generation by a VAE model and filter out locations that potentially lead to collisions with furniture in a room, project all generated locations to a bird’s eye view and remove locations that fall on furniture or walls. In at least one embodiment, an accessible region visualization 604 is a visualization of generated accessible regions, in which a VAE predicts plausible locations suitable for humans to sit, walk, etc. while avoiding collisions with furniture in a room. In at least one embodiment, a generated accessible region uniformly spreads out in a 3D room and is plausible for all kinds of human actions. In at least one embodiment, for example, points on an obstacle such as a chair or sofa are feasible locations for sitting human torsos, while points in midair are possible locations for walking human torsos.

[0144] In at least one embodiment, one or more systems train an implicit environment function to model a full 3D space. In at least one embodiment, one or more systems train an implicit environment function to model a particular 3D environment. In at least one embodiment, one or more systems, for training of an implicit environment function, utilize arbitrary goal positions in a fixed scene environment. In at least one embodiment, an input to an implicit function is a concatenation of goal coordinates and query position coordinates. In at least one embodiment, an output is a reaching distance from a query position to a goal. In at least one embodiment, one or more systems discretize a 3D scene to a voxel grid of any suitable size (e.g., a 64 x 64 x 64 voxel grid) and mark all voxel cells within a generated accessible region as accessible and other voxel cells as obstacles, also referred to as inaccessible. In at least one embodiment, one or more systems determine a trajectory to navigate an entity from a start location to a goal by at least querying an implicit function for reaching distances at all possible positions said entity can reach, and navigating said entity to a position with a smallest reaching distance until said entity reaches said goal. In at least one embodiment, one or more systems set a step size as average human step size and determine all possible directions a human can take in a 3D space. In at least one embodiment, an environment field visualization 606 is a visualization of an environment field determined by an implicit environment function trained to model a particular 3D environment. In at least one embodiment, an environment field visualization 606 depicts lighter shading for lower reaching distance values and darker shading for higher reaching distance values. In at least one embodiment, in an environment field, closer a point is to a goal, smaller its reaching distance value is. [0145 J In at least one embodiment, a trajectory visualization 608 is a visualization of a trajectory calculated by one or more systems for an entity to navigate to a goal. In at least one embodiment, one or more systems calculate a trajectory comprising a plurality of paths. In at least one embodiment, one or more systems optimize a trajectory based on a given pose sequence and guarantee that a human is navigated towards physically feasible locations; this yields a plausible trajectory aligned with a given human pose sequence. In at least one embodiment, one or more systems, at each step, use a step size computed from adjacent locations in a pose sequence instead of a predefined average step size. In at least one embodiment, one or more systems, for each possible location a human can reach within one step size, check if a human is well supported and a human is not colliding with other objects at these locations and move a human to a location with a smallest reaching distance value while utilizing these constraints and / or other constraints. In at least one embodiment, one or more systems, to determine if a pose is well supported, check if a torso, a left lap, and / or a right lap joints of sitting poses, as well as feet joints of standing poses, have non-positive signed distances to a scene surface. In at least one embodiment, one or more systems, to determine if a pose collides with other objects, check if all joints of a pose, except various support joints, have non-negative signed distances. In at least one embodiment, one or more systems, based on various entity poses, determine a trajectory, visualized in a trajectory visualization 608, for an entity (e.g., a human) to navigate to a goal. In at least one embodiment, a trajectory successfully avoids colliding with obstacles (e.g., furniture) in a room while leading an entity (e.g., a human) towards a goal. In at least one embodiment, entity poses (e.g., human poses) are also plausible at each location on a trajectory.

[0146] FIG. 7 illustrates an example 700 of results using an implicit environment function, according to at least one embodiment. In at least one embodiment, a table 702, a table 704, a table 706, and a table 708 illustrate various results using an implicit environment function such as those described herein.

[0147] In at least one embodiment, one or more systems train a conditional VAE and all implicit functions using a solver such as an Adam solver with any suitable learning rate (e.g., a learning rate of 5 x 10-5). In at least one embodiment, one or more systems, to balance a KL-divergence and reconstruction objectives in a VAE, utilize a schedule such as a Cyclical Annealing Schedule.

[0148] In at least one embodiment, one or more systems evaluate an implicit environment function (IEF) on datasets such as a Minigrid and Gridworld maze datasets, which include 2D mazes with randomly placed obstacles. In at least one embodiment, an implicit environment function determines an environment field that accurately encodes a reaching distance from any accessible point to a goal while successfully detecting all obstacles in a maze. In at least one embodiment, one or more systems use a success rate (e.g., a percentage of paths that successfully lead an agent to a goal among all searched paths) as an evaluation metric.

[0149] In at least one embodiment, table 1 702 depicts results of an ablation study on network architectures. In at least one embodiment, 11x11 mazes are from a dataset such as a Minigrid dataset while all other mazes are from a dataset such as a Gridworld dataset. In at least one embodiment, “IF” denotes an implicit function. In at least one embodiment, a context-aligned implicit function performs comparably to hypernetworks on smaller-sized mazes (e.g., 8x8 and 11x11 mazes). In at least one embodiment, hypernetworks fail on larger-sized mazes (e.g., 16 x 16 and 28 x 28 mazes), in which a context-aligned implicit function is superior over hypernetworks.

[0150] In at least one embodiment, one or more systems evaluate an implicit environment function with a network such as a value iteration networks (VIN) on a dataset such as a Minigrid dataset. In at least one embodiment, one or more systems utilize a same train and test split as VIN, and learn different implicit functions for mazes of different sizes. In at least one embodiment, table 2 704 depicts a success rate and average time taken to search a path by different methods. In at least one embodiment, a batch size of 1 is utilized, or any suitable value. In at least one embodiment, an implicit environment function achieves a comparable success rate with much less time in larger-sized mazes compared to VIN. In at least one embodiment, an implicit environment function only needs one network forwarding pass to obtain reaching distance values of all locations in a maze and can guide an agent at any location to reach a goal.

[0151] In at least one embodiment, one or more systems utilize an implicit environment function to model long-term dynamic human motion on a dataset such as a Proximal Relationships with Object exclusion (PROX) dataset. In at least one embodiment, an implicit environment function can predict long-term dynamic human motion across any number of video frames. In at least one embodiment, an implicit environment field represents an environment through an environment field that encodes a reaching distance between any point to a goal position. In at least one embodiment, areas that are closer to a goal have a lower reaching distance value and vice versa. In at least one embodiment, an environment field dynamically changes based on a positions of people in an environment. In at least one embodiment, an inaccessible region corresponds to a region with large reaching distance values (e.g., over a particular threshold). In at least one embodiment, an implicit environment function can model an environment field in a scene and generalize to a dynamically changing environment.

[0152] In at least one embodiment, table 3 706 depicts quantitative comparisons with sampling-based path planning methods, such as Rapidly-exploring random trees (RRT) and probabilistic roadmaps (PRM). In at least one embodiment, AFF indicates a pose dependent search. In at least one embodiment, one or more systems evaluate metrics such as a distance between an ending of a searched path and a goal, and an average time cost for a single trajectory search. In at least one embodiment, one or more systems set a number of sampling points and nearest neighbors in PRM to any suitable values, such as 500 and 5, respectively. In at least one embodiment, one or more systems set a maximum iteration for trajectory search in RRT to any suitable value, such as 500 iterations. In at least one embodiment, an implicit environment field is more efficient, as each step can be predicted by a single fast network forward pass.

[0153] In at least one embodiment, one or more systems quantitatively compare trajectory predictions against a network such as a PathNet using a distance metric as well as a ratio of valid poses to all poses on a trajectory. In at least one embodiment, one or more systems define a pose as valid if it is both well supported and not collision-free in a scene. In at least one embodiment, one or more systems utilize train and test trajectories such as those of a long-term human motion prediction with scene context (HMP) method, with each trajectory including 30 frames. In at least one embodiment, a PathNet in HMP requires torso locations in a first 10 frames of each trajectory as input and predicts torso locations for following 20 frames. In at least one embodiment, one or more systems predict any number of locations (e.g., 30 locations) that lead a human from a start position in a first frame to a goal in a last frame. In at least one embodiment, table 4 708 depicts quantitative evaluations. In at least one embodiment, an implicit environment function is more effective at navigating humans towards goal positions. In at least one embodiment, after using a pose-dependent trajectory search process, an implicit environment function is able to better fit human poses to a scene, as shown in a last column in table 4 708.

[0154] In at least one embodiment, an implicit environment field represents an environment through an environment field that encodes a reaching distance between a pair of points in either 2D or 3D space. In at least one embodiment, a learned environment field is a continuous energy surface that can navigate agents in 2D mazes in dynamically changing scene environments. In at least one embodiment, an environment field is extended to 3D scenes to model dynamic human motion in indoor environments.

[0155] In at least one embodiment, to encode different maze environments as well as goal positions, one or more systems utilize networks such as a hypernetwork. In at least one embodiment, a hypernetwork refers a neural network that generates a network for a main network, also referred to as a hyponetwork. In at least one embodiment, for each maze map, one or more systems use a hypernetwork to predict a parameters of a hyponetwork (e.g., an implicit environment function). In at least one embodiment, a hyponetwork obtains as input a concatenation of goal coordinates as well as query position coordinates and outputs a reaching distance between them. In at least one embodiment, a hypernetwork includes any suitable layers, such as 11 convolutional layers followed by 7 fully-connected layers. In at least one embodiment, a hyponetwork includes any suitable layers, such as 7 fully-connected layers, each of which is followed by a periodic activation.

[0156] In at least one embodiment, instead of using a reaching distance computed by FMM as supervision to train an implicit environment function, one or more systems utilize a reciprocal of a reaching distance from a feasible point to a goal and normalize it to a range of [0, 1], and train an implicit environment function to predict negative values instead of extremely small values for locations occupied by obstacles. In at least one embodiment, an implicit environment function can differentiate feasible locations and obstacles.

[0157] In at least one embodiment, during training of a VAE model, besides points on training human trajectories, one or more systems also augment more points in a scene. In at least one embodiment, one or more systems utilize a random standing human pose and include all locations that can afford this pose (e.g., a pose can be supported by a floor and does not collide with other objects). In at least one embodiment, one or more systems train a conditional VAE model for all training trajectories in various different scenes, while a separate implicit function is trained for each 3D indoor scene. In at least one embodiment, one or more models are trained using a solver such as an Adam solver using a learning rate of 5 x 10'5. In at least one embodiment, one or more systems implement one or more models using a framework such as a PyTorch framework, or any suitable framework.

[0158] FIG. 8 illustrates an example 800 of results of agent navigation, according to least one embodiment. In at least one embodiment, paths 802 depicts various mazes, ground truth paths (e.g., depicted as straight lines) and searched paths (e.g., depicted as dotted lines). In at least one embodiment, learned level set 804 depicts various mazes and searched paths. In at least one embodiment, learned IEF 806 depicts various mazes and environment fields determined by an implicit environment function. In at least one embodiment, an implicit environment function determines an environment field that captures a reaching distance from any point to a goal and guides an agent from a starting position to a goal.

[0159] FIG. 9 and FIG. 10 illustrate examples of results of fitting given human sequences to searched trajectories in 3D indoor environments, according to at least one embodiment. In at least one embodiment, given a human sequence, one or more systems compute a step size of a human at each time step and dynamically determine a best next move with respect to step size.

[0160] In at least one embodiment, one or more systems utilize a given human pose to avoid moving humans to locations that violate physical constraints in a room (e.g., locations that cannot well support a human or lead to collision with other objects). In at least one embodiment, one or more systems, if it is determined that a location can afford a human body mesh, or other suitable representation, such as a skeleton, skeleton mesh, and / or variations thereof, consider vertices belonging to a body part instead of joints. In at least one embodiment, one or more systems utilize a human body mesh, a skeleton, a skeleton mesh, and / or any suitable representation of a human. In at least one embodiment, for example, to check if a sitting human is well supported, one or more systems check if vertices belonging to a gluteus part have non-positive signed distance values to object surfaces, and to check if a human is colliding with other objects, one or more systems check if vertices belonging to legs and thighs have non-negative signed distance values.

[0161] In at least one embodiment, FIG. 9 and FIG. 10 visualize an environment field in a last two rows. In at least one embodiment, reaching distances are smaller (e.g., shaded less) as points are closer to a goal position and vice versa. In at least one embodiment, arrows point to a goal position (e.g., a human torso position in a last time step).

[0162] FIG. 11 illustrates an example of a process 1100 to calculate a plurality of paths using an implicit environment function, according to at least one embodiment. In at least one embodiment, some or all of process 1100 (or any other processes described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 1100 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals.

[0163] In at least one embodiment, process 1100 is performed by one or more systems such as those described in this present disclosure. In at least one embodiment, one or more systems include any suitable system with a collection of one or more hardware and / or software resources with instructions that, when executed, performs various implicit environment function training operations, implicit environment function processing operations, neural network functions, navigation operations (e.g., causing an entity to navigate to a location), environment processing functions, and / or various other operations such as those described herein. In at least one embodiment, process 1100 is performed by one or more systems associated with an autonomous device.

[0164] In at least one embodiment, a system performing at least a part of process 1100 includes executable code to at least obtain 1102 a first location, a set of locations, and a final location. In at least one embodiment, a location is a location in an environment and can be referred to as a position. In at least one embodiment, an environment is any suitable environment, such as a 2D environment, 3D environment, indoor environment, outdoor environment, simulated environment, maze, and / or variations thereof. In at least one embodiment, an environment comprises an autonomous device. In at least one embodiment, an autonomous device is a system such as an autonomous car, autonomous robot, and / or variations thereof. In at least one embodiment, an autonomous device is to navigate from a first location to a final location, also referred to as a goal position or location, in an environment as part of a navigation task. In at least one embodiment, a first location is a location of an autonomous device. In at least one embodiment, a set of locations are one or more locations in an environment. In at least one embodiment, a set of locations include one or more locations in accessible regions of an environment.

[0165] In at least one embodiment, a system performing at least a part of process 1100 includes executable code to at least cause 1104 one or more neural networks to calculate a set of distances based at least in part on set of locations and final location. In at least one embodiment, one or more neural networks include an implicit environment function. In at least one embodiment, a system inputs a set of locations and a final location to an implicit environment function. In at least one embodiment, a system inputs features of an environment to an implicit environment function. In at least one embodiment, a system generates features of an environment by inputting a representation of said environment to one or more neural networks, such as an encoder. In at least one embodiment, a representation of an environment is any suitable representation, such as an image, point cloud data, set of points, and / or variations thereof. In at least one embodiment, a representation can be captured using various image capturing hardware, such as a camera, depth camera, sensor device, and / or variations thereof. In at least one embodiment, a system performs various alignment processes on generated features.

[0166] In at least one embodiment, one or more neural networks output a set of distances corresponding to a set of locations. In at least one embodiment, a set of distances are reaching distances corresponding to a set of locations. In at least one embodiment, a reaching distance is also referred to as a distance value, distance, reaching distance value, and / or variations thereof. In at least one embodiment, a first distance of a set of distances corresponds to a first location of a set of locations, and indicates a distance of a feasible path from said first location to a final location. In at least one embodiment, a set of locations are relative to a final location. In at least one embodiment, a set of distances for a set of locations are relative to a final location. In at least one embodiment, a feasible path refers to a path that is semantically and / or geometrically feasible. In at least one embodiment, a feasible path refers to any suitable path that an autonomous device can navigate through. In at least one embodiment, an implicit environment function outputs a set of distances in a single forward pass.

[0167] In at least one embodiment, a system performing at least a part of process 1100 includes executable code to at least calculate 1106 a plurality of paths based at least in part on set of distances, wherein plurality of paths form a path from first location to final location. In at least one embodiment, a system determines a subset of locations accessible from a first location by an autonomous device. In at least one embodiment, a location is accessible to an autonomous device if said autonomous device can navigate to said location from a current location of said autonomous device. In at least one embodiment, an accessible location is a location that an autonomous device can navigate to within a single step. In at least one embodiment, a system calculates a size for a step of an autonomous device, which corresponds to a distance value of how far said autonomous device travels per step. In at least one embodiment, a system defines a step size as any suitable value.

[0168] In at least one embodiment, a system determines a subset of distances of a set of distances corresponding to a subset of locations. In at least one embodiment, a system determines a second location of a subset of locations corresponding to a minimum distance of a subset of distances. In at least one embodiment, a second location corresponds to a minimum distance, maximum distance, or any suitable distance of a subset of distances. In at least one embodiment, a second location corresponds to a location in a particular direction from a first location of an autonomous device. In at least one embodiment, a system calculates a first path comprising a path from a first location to a second location. In at least one embodiment, a system causes an autonomous device to navigate to a second location using a first path.

[0169] In at least one embodiment, a system continuously determines paths for an autonomous device until said autonomous device can navigate to a final location. In at least one embodiment, for example, a system determines a second subset of locations accessible from a second location of an autonomous device, obtains a second subset of distances corresponding to said second subset of locations, determines a third location of said second subset of locations (e.g., corresponding to a minimum distance, or any suitable distance), calculates a second path from said second location to said third location, and causes said autonomous device to navigate to said third location using said second path, and so on until a final location is accessible from a current location of said autonomous device, in which said system causes said autonomous device to navigate to said final location.

[0170] In at least one embodiment, a system trains one or more neural networks to calculate a plurality of paths, through which an autonomous device is to traverse. In at least one embodiment, a system obtains an environment and a location, causes one or more algorithms to determine one or more reaching distance values for one or more locations in said environment to said location, and trains one or more neural networks at least using said one or more reaching distance values. In at least one embodiment, a system trains one or more neural networks by causing said one or more neural networks to process one or more locations to calculate one or more predicted reaching distance values, and updating said one or more neural networks based on differences between said one or more predicted reaching distance values and one or more reaching distance values output by one or more algorithms. In at least one embodiment, a system updates or otherwise trains one or more neural networks to minimize differences (e.g., update such that differences are under a pre-defined threshold) between predicted reaching distance values and reaching distance values output by one or more algorithms. In at least one embodiment, one or more algorithms include various path planning algorithms, various FMM algorithms, or any suitable algorithm. In at least one embodiment, a system trains one or more neural networks such that trained one or more neural networks can predict reaching distance values that are similar or same as reaching distance values output by one or more algorithms. In at least one embodiment, a system utilizes predicted reaching distance values to determine a plurality of paths through which an autonomous device is to traverse.

[0171] In at least one embodiment, one or more processes of process 1100, as well as those described in connection with process 1100, can be performed in any suitable order, including sequential, parallel, and / or variations thereof. In at least one embodiment, process 1100 can include various processes described elsewhere in this disclosure. INFERENCE AND TRAINING LOGIC

[0172] FIG. 12A illustrates inference and / or training logic 1215 used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided below in conjunction with FIGS. 12A and / or 12B.

[0173] In at least one embodiment, inference and / or training logic 1215 may include, without limitation, code and / or data storage 1201 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1215 may include, or be coupled to code and / or data storage 1201 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1201 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1201 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0174] In at least one embodiment, any portion of code and / or data storage 1201 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1201 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or code and / or data storage 1201 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0175] In at least one embodiment, inference and / or training logic 1215 may include, without limitation, a code and / or data storage 1205 to store backward and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1205 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 1215 may include, or be coupled to code and / or data storage 1205 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0176] In at least one embodiment, code, such as graph code, causes loading of weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1205 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1205 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1205 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 1205 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0177] In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be separate storage structures. In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be a combined storage structure. In at least one embodiment, code and / or data storage 1201 and code and / or data storage 1205 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 1201 and code and / or data storage 1205 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0178] In at least one embodiment, inference and / or training logic 1215 may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”) 1210, including integer and / or floating point units, to perform logical and / or mathematical operations based, at least in part on, or indicated by, training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 1220 that are functions of input / output and / or weight parameter data stored in code and / or data storage 1201 and / or code and / or data storage 1205. In at least one embodiment, activations stored in activation storage 1220 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 1210 in response to performing instructions or other code, wherein weight values stored in code and / or data storage 1205 and / or data storage 1201 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1205 or code and / or data storage 1201 or another storage on or off-chip.

[0179] In at least one embodiment, ALU(s) 1210 are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 1210 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs 1210 may be included within a processor’s execution units or otherwise within a bank of ALUs accessible by a processor’s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1201, code and / or data storage 1205, and activation storage 1220 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1220 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Furthermore, inferencing and / or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and / or processed using a processor’s fetch, decode, scheduling, execution, retirement and / or other logical circuits.

[0180] In at least one embodiment, activation storage 1220 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1220 may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, a choice of whether activation storage 1220 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0181] In at least one embodiment, inference and / or training logic 1215 illustrated in FIG. 12A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 1215 illustrated in FIG. 12A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

[0182] FIG. 12B illustrates inference and / or training logic 1215, according to at least one embodiment. In at least one embodiment, inference and / or training logic 1215 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and / or training logic 1215 illustrated in FIG. 12B may be used in conjunction with an application-specific integrated circuit (ASIC), such as TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 1215 illustrated in FIG. 12B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and / or training logic 1215 includes, without limitation, code and / or data storage 1201 and code and / or data storage 1205, which may be used to store code (e.g., graph code), weight values and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 12B, each of code and / or data storage 1201 and code and / or data storage 1205 is associated with a dedicated computational resource, such as computational hardware 1202 and computational hardware 1206, respectively. In at least one embodiment, each of computational hardware 1202 and computational hardware 1206 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 1201 and code and / or data storage 1205, respectively, result of which is stored in activation storage 1220.

[0183] In at least one embodiment, each of code and / or data storage 1201 and 1205 and corresponding computational hardware 1202 and 1206, respectively, correspond to different layers of a neural network, such that resulting activation from one storage / computational pair 1201 / 1202 of code and / or data storage 1201 and computational hardware 1202 is provided as an input to a next storage / computational pair 1205 / 1206 of code and / or data storage 1205 and computational hardware 1206, in order to mirror a conceptual organization of a neural network. In at least one embodiment, each of storage / computational pairs 1201 / 1202 and 1205 / 1206 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) subsequent to or in parallel with storage / computation pairs 1201 / 1202 and 1205 / 1206 may be included in inference and / or training logic 1215.

[0184] In at least one embodiment, one or more systems depicted in FIGS. 12A-12B are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIGS. 12A-12B are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIGS. 12A-12B are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11. NEURAL NETWORK TRAINING AND DEPLOYMENT [0185 ] FIG. 13 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network 1306 is trained using a training dataset 1302. In at least one embodiment, training framework 1304 is a PyTorch framework, whereas in other embodiments, training framework 1304 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1304 trains an untrained neural network 1306 and enables it to be trained using processing resources described herein to generate a trained neural network 1308. In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner.

[0186] In at least one embodiment, untrained neural network 1306 is trained using supervised learning, wherein training dataset 1302 includes an input paired with a desired output for an input, or where training dataset 1302 includes input having a known output and an output of neural network 1306 is manually graded. In at least one embodiment, untrained neural network 1306 is trained in a supervised manner and processes inputs from training dataset 1302 and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 1306. In at least one embodiment, training framework 1304 adjusts weights that control untrained neural network 1306. In at least one embodiment, training framework 1304 includes tools to monitor how well untrained neural network 1306 is converging towards a model, such as trained neural network 1308, suitable to generating correct answers, such as in result 1314, based on input data such as a new dataset 1312. In at least one embodiment, training framework 1304 trains untrained neural network 1306 repeatedly while adjust weights to refine an output of untrained neural network 1306 using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 1304 trains untrained neural network 1306 until untrained neural network 1306 achieves a desired accuracy. In at least one embodiment, trained neural network 1308 can then be deployed to implement any number of machine learning operations. [0187 ] In at least one embodiment, untrained neural network 1306 is trained using unsupervised learning, wherein untrained neural network 1306 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1302 will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network 1306 can learn groupings within training dataset 1302 and can determine how individual inputs are related to untrained dataset 1302. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1308 capable of performing operations useful in reducing dimensionality of new dataset 1312. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1312 that deviate from normal patterns of new dataset 1312.

[0188] In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset 1302 includes a mix of labeled and unlabeled data. In at least one embodiment, training framework 1304 may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network 1308 to adapt to new dataset 1312 without forgetting knowledge instilled within trained neural network 1308 during initial training.

[0189] In at least one embodiment, training framework 1304 is a framework processed in connection with a software development toolkit such as an Open VINO (Open Visual Inference and Neural network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as those developed by Intel Corporation of Santa Clara, CA.

[0190] In at least one embodiment, OpenVINO is a toolkit for facilitating development of applications, specifically neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variations thereof.

[0191] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0192] In at least one embodiment, OpenVINO comprises one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model, and optimizes said model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model that are utilized for training. In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., resizing inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0193] In at least one embodiment, OpenVINO comprises one or more software libraries for inferencing, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library, or any suitable programming language library. In at least one embodiment, an inference engine is utilized to infer input data. In at least one embodiment, an inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.

[0194] In at least one embodiment, OpenVINO provides various abilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution, or heterogeneous computing, refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to, for example, run a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0195] In at least one embodiment, OpenVINO includes various functionality similar to functionalities associated with a CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0196] In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11. DATA CENTER

[0197] FIG. 14 illustrates an example data center 1400, in which at least one embodiment may be used. In at least one embodiment, data center 1400 includes a data center infrastructure layer 1410, a framework layer 1420, a software layer 1430 and an application layer 1440.

[0198] In at least one embodiment, as shown in FIG. 14, data center infrastructure layer 1410 may include a resource orchestrator 1412, grouped computing resources 1414, and node computing resources (“node C.R.s”) 1416(1 )-1416(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node C.R.S 1416(1)-1416(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1418(1)-1418(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.S from among node C.R.S 1416(1)-1416(N) may be a server having one or more of above-mentioned computing resources.

[0199] In at least one embodiment, grouped computing resources 1414 may include separate groupings of node C.R.S housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.S within grouped computing resources 1414 may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.S including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0200] In at least one embodiment, resource orchestrator 1412 may configure or otherwise control one or more node C.R.S 1416(1)-1416(N) and / or grouped computing resources 1414. In at least one embodiment, resource orchestrator 1412 may include a software design infrastructure (“SDI”) management entity for data center 1400. In at least one embodiment, resource orchestrator 1212 may include hardware, software or some combination thereof.

[0201] In at least one embodiment, as shown in FIG. 14, framework layer 1420 includes a job scheduler 1422, a configuration manager 1424, a resource manager 1426 and a distributed file system 1428. In at least one embodiment, framework layer 1420 may include a framework to support software 1432 of software layer 1430 and / or one or more application(s) 1442 of application layer 1440. In at least one embodiment, software 1432 or application(s) 1442 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 1420 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1428 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1422 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1400. In at least one embodiment, configuration manager 1424 may be capable of configuring different layers such as software layer 1430 and framework layer 1420 including Spark and distributed file system 1428 for supporting large-scale data processing. In at least one embodiment, resource manager 1426 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1428 and job scheduler 1422. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1414 at data center infrastructure layer 1410. In at least one embodiment, resource manager 1426 may coordinate with resource orchestrator 1412 to manage these mapped or allocated computing resources.

[0202] In at least one embodiment, software 1432 included in software layer 1430 may include software used by at least portions of node C.R.s 1416(1)-1416(N), grouped computing resources 1414, and / or distributed file system 1428 of framework layer 1420. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0203] In at least one embodiment, application(s) 1442 included in application layer 1440 may include one or more types of applications used by at least portions of node C.R.S 1416(1)-1416(N), grouped computing resources 1414, and / or distributed file system 1428 of framework layer 1420. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, application and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[0204] In at least one embodiment, any of configuration manager 1424, resource manager 1426, and resource orchestrator 1412 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 1400 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0205] In at least one embodiment, data center 1400 may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1400. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 1400 by using weight parameters calculated through one or more training techniques described herein.

[0206] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services.

[0207] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 14 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0208] In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11. AUTONOMOUS VEHICLE

[0209] FIG. 15A illustrates an example of an autonomous vehicle 1500, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1500 (alternatively referred to herein as “vehicle 1500”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1500 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1500 may be an airplane, robotic vehicle, or other kind of vehicle.

[0210] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1500 may be capable of functionality in accordance with one or more of Level 1 through Level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1500 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment. [0211 ] In at least one embodiment, vehicle 1500 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1500 may include, without limitation, a propulsion system 1550, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1550 may be connected to a drive train of vehicle 1500, which may include, without limitation, a transmission, to enable propulsion of vehicle 1500. In at least one embodiment, propulsion system 1550 may be controlled in response to receiving signals from a throttle / accelerator(s) 1552.

[0212] In at least one embodiment, a steering system 1554, which may include, without limitation, a steering wheel, is used to steer vehicle 1500 (e.g., along a desired path or route) when propulsion system 1550 is operating (e.g., when vehicle 1500 is in motion). In at least one embodiment, steering system 1554 may receive signals from steering actuator(s) 1556. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1546 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 1548 and / or brake sensors.

[0213] In at least one embodiment, controller(s) 1536, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 15A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1500. For instance, in at least one embodiment, controller(s) 1536 may send signals to operate vehicle brakes via brake actuator(s) 1548, to operate steering system 1554 via steering actuator(s) 1556, to operate propulsion system 1550 via throttle / accelerator(s) 1552. In at least one embodiment, controller(s) 1536 may include one or more onboard (e.g., integrated) computing devices that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1500. In at least one embodiment, controller(s) 1536 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0214] In at least one embodiment, controller(s) 1536 provide signals for controlling one or more components and / or systems of vehicle 1500 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 1558 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1560, ultrasonic sensor(s) 1562, LIDAR sensor(s) 1564, inertial measurement unit (“IMU”) sensor(s) 1566 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 1596, stereo camera(s) 1568, wide-view camera(s) 1570 (e.g., fisheye cameras), infrared camera(s) 1572, surround camera(s) 1574 (e.g., 360 degree cameras), long-range cameras (not shown in FIG. 15 A), mid-range camera(s) (not shown in FIG. 15 A), speed sensor(s) 1544 (e.g., for measuring speed of vehicle 1500), vibration sensor(s) 1542, steering sensor(s) 1540, brake sensor(s) (e.g., as part of brake sensor system 1546), and / or other sensor types. |0215] In at least one embodiment, one or more of controller(s) 1536 may receive inputs (e.g., represented by input data) from an instrument cluster 1532 of vehicle 1500 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1534, an audible annunciator, a loudspeaker, and / or via other components of vehicle 1500. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 15A)), location data (e.g., vehicle’s 1500 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1536, etc. For example, in at least one embodiment, HMI display 1534 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0216] In at least one embodiment, vehicle 1500 further includes a network interface 1524 which may use wireless antenna(s) 1526 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1524 may be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM’), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, wireless antenna(s) 1526 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0217] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 15A for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0218] FIG. 15B illustrates an example of camera locations and fields of view for autonomous vehicle 1500 of FIG. 15 A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1500.

[0219] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1500. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity. [()220] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all cameras) may record and provide image data (e.g., video) simultaneously. [0221 ] In at least one embodiment, one or more camera may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within vehicle 1500 (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that a camera mounting plate matches a shape of a wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirrors. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each corner of a cabin.

[0222] In at least one embodiment, cameras with a field of view that include portions of an environment in front of vehicle 1500 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controller(s) 1536 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0223] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 1570 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 1570 is illustrated in FIG. 15B, in other embodiments, there may be any number (including zero) wide-view cameras on vehicle 1500. In at least one embodiment, any number of long-range camera(s) 1598 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1598 may also be used for object detection and classification, as well as basic object tracking.

[0224] In at least one embodiment, any number of stereo camera(s) 1568 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1568 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of vehicle 1500, including a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1568 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 1500 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1568 may be used in addition to, or alternatively from, those described herein.

[0225] In at least one embodiment, cameras with a field of view that include portions of environment to sides of vehicle 1500 (e.g., side-view cameras) may be used for surround view, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1574 (e.g., four surround cameras as illustrated in FIG. 15B) could be positioned on vehicle 1500. In at least one embodiment, surround camera(s) 1574 may include, without limitation, any number and combination of wide-view cameras, fisheye camera(s), 360 degree camera(s), and / or similar cameras. For instance, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of vehicle 1500. In at least one embodiment, vehicle 1500 may use three surround camera(s) 1574 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[0226] In at least one embodiment, cameras with a field of view that include portions of an environment behind vehicle 1500 (e.g., rear-view cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 1598 and / or mid-range camera(s) 1576, stereo camera(s) 1568, infrared camera(s) 1572, etc.,) as described herein.

[0227] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 15B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0228] FIG. 15C is a block diagram illustrating an example system architecture for autonomous vehicle 1500 of FIG. 15 A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 1500 in FIG. 15C is illustrated as being connected via a bus 1502. In at least one embodiment, bus 1502 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 1500 used to aid in control of various features and functionality of vehicle 1500, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1502 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1502 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1502 may be a CAN bus that is ASIL B compliant.

[0229] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of busses forming bus 1502, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using different protocols. In at least one embodiment, two or more busses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1502 may communicate with any of components of vehicle 1500, and two or more busses of bus 1502 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 1504 (such as SoC 1504(A) and SoC 1504(B)), each of controller(s) 1536, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1500), and may be connected to a common bus, such CAN bus.

[0230] In at least one embodiment, vehicle 1500 may include one or more controller(s) 1536, such as those described herein with respect to FIG. 15 A. In at least one embodiment, controller(s) 1536 may be used for a variety of functions. In at least one embodiment, controller(s) 1536 may be coupled to any of various other components and systems of vehicle 1500, and may be used for control of vehicle 1500, artificial intelligence of vehicle 1500, infotainment for vehicle 1500, and / or other functions.

[0231] In at least one embodiment, vehicle 1500 may include any number of SoCs 1504. In at least one embodiment, each of SoCs 1504 may include, without limitation, central processing units (“CPU(s)”) 1506, graphics processing units (“GPU(s)”) 1508, processor(s) 1510, cache(s) 1512, accelerator(s) 1514, data store(s) 1516, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 1504 may be used to control vehicle 1500 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1504 may be combined in a system (e.g., system of vehicle 1500) with a High Definition (“HD”) map 1522 which may obtain map refreshes and / or updates via network interface 1524 from one or more servers (not shown in FIG. 15C).

[0232] In at least one embodiment, CPU(s) 1506 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 1506 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 1506 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 1506 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1506 (e.g., CCPLEX) may be configured to support simultaneous cluster operations enabling any combination of clusters of CPU(s) 1506 to be active at any given time.

[0233] In at least one embodiment, one or more of CPU(s) 1506 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 1506 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines which best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode.

[0234] In at least one embodiment, GPU(s) 1508 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 1508 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 1508 may use an enhanced tensor instruction set. In at least one embodiment, GPU(s) 1508 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96 KB storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 1508 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1508 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 1508 may use one or more parallel computing platforms and / or programming models (e g., NVIDIA’s CUDA model).

[0235] In at least one embodiment, one or more of GPU(s) 1508 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, GPU(s) 1508 could be fabricated on Fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming.

[0236] In at least one embodiment, one or more of GPU(s) 1508 may include a high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”).

[0237] In at least one embodiment, GPU(s) 1508 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 1508 to access CPU(s) 1506 page tables directly. In at least one embodiment, embodiment, when a GPU of GPU(s) 1508 memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 1506. In response, 2 CPU of CPU(s) 1506 may look in its page tables for a virtual-to-physical mapping for an address and transmit translation back to GPU(s) 1508, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 1506 and GPU(s) 1508, thereby simplifying GPU(s) 1508 programming and porting of applications to GPU(s) 1508.

[0238] In at least one embodiment, GPU(s) 1508 may include any number of access counters that may keep track of frequency of access of GPU(s) 1508 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of a processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[0239] In at least one embodiment, one or more of SoC(s) 1504 may include any number of cache(s) 1512, including those described herein. For example, in at least one embodiment, cache(s) 1512 could include a level three (“L3”) cache that is available to both CPU(s) 1506 and GPU(s) 1508 (e.g., that is connected to CPU(s) 1506 and GPU(s) 1508). In at least one embodiment, cache(s) 1512 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3 cache may include 4 MB of memory or more, depending on embodiment, although smaller cache sizes may be used.

[0240] In at least one embodiment, one or more of SoC(s) 1504 may include one or more accelerator(s) 1514 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1504 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to complement GPU(s) 1508 and to off-load some of tasks of GPU(s) 1508 (e.g., to free up more cycles of GPU(s) 1508 for performing other tasks). In at least one embodiment, accelerator(s) 1514 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN.

[0241] In at least one embodiment, accelerator(s) 1514 (e.g., hardware acceleration cluster) may include one or more deep learning accelerator (“DLA”). In at least one embodiment, DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs”) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI 6, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events.

[0242] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1508, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1508 for any function. For example, in at least one embodiment, a designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1508 and / or accelerator(s) 1514.

[0243] In at least one embodiment, accelerator(s) 1514 may include programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”) 1538, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0244] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[0245] In at least one embodiment, DMA may enable components of PVA to access system memory independently of CPU(s) 1506. In at least one embodiment, DMA may support any number of features used to provide optimization to a PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0246] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA, and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0247] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on one image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correcting code (“ECC”) memory, to enhance overall system safety.

[0248] In at least one embodiment, accelerator(s) 1514 may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s) 1514. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, comprising, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may include a computer vision network on-chip that interconnects a PVA and a DLA to memory (e.g., using APB).

[0249] In at least one embodiment, a computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both a PVA and a DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0250] In at least one embodiment, one or more of SoC(s) 1504 may include a real-time ray-tracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0251] In at least one embodiment, accelerator(s) 1514 can have a wide array of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, a PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, a PVA performs well on semi-dense or dense regular computation, even on small data sets, which might require predictable run-times with low latency and low power. In at least one embodiment, such as in vehicle 1500, PVAs might be designed to run classic computer vision algorithms, as they can be efficient at object detection and operating on integer math.

[0252] For example, according to at least one embodiment of technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0253] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example.

[0254] In at least one embodiment, a DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 1566 that correlates with vehicle 1500 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1564 or RADAR sensor(s) 1560), among others.

[0255] In at least one embodiment, one or more of SoC(s) 1504 may include data store(s) 1516 (e.g., memory). In at least one embodiment, data store(s) 1516 may be on-chip memory of SoC(s) 1504, which may store neural networks to be executed on GPU(s) 1508 and / or a DLA. In at least one embodiment, data store(s) 1516 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 1516 may comprise L2 or L3 cache(s).

[0256] In at least one embodiment, one or more of SoC(s) 1504 may include any number of processor(s) 1510 (e.g., embedded processors). In at least one embodiment, processor(s) 1510 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, a boot and power management processor may be a part of a boot sequence of SoC(s) 1504 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 1504 thermals and temperature sensors, and / or management of SoC(s) 1504 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 1504 may use ring-oscillators to detect temperatures of CPU(s) 1506, GPU(s) 1508, and / or accelerator(s) 1514. In at least one embodiment, if temperatures are determined to exceed a threshold, then a boot and power management processor may enter a temperature fault routine and put SoC(s) 1504 into a lower power state and / or put vehicle 1500 into a chauffeur to safe stop mode (e.g., bring vehicle 1500 to a safe stop).

[0257] In at least one embodiment, processor(s) 1510 may further include a set of embedded processors that may serve as an audio processing engine which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM. [0258 ] In at least one embodiment, processor(s) 1510 may further include an always-on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0259] In at least one embodiment, processor(s) 1510 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 1510 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1510 may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0260] In at least one embodiment, processor(s) 1510 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-view camera(s) 1570, surround camera(s) 1574, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 1504, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle’s destination, activate or change a vehicle’s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0261] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weights of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from a previous image to reduce noise in a current image.

[0262] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use, and GPU(s) 1508 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 1508 are powered on and active doing 3D rendering, a video image compositor may be used to offload GPU(s) 1508 to improve performance and responsiveness.

[0263] In at least one embodiment, one or more SoC of SoC(s) 1504 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 1504 may further include an input / output controller(s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0264] In at least one embodiment, one or more Soc of SoC(s) 1504 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, SoC(s) 1504 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1564, RADAR sensor(s) 1560, etc. that may be connected over Ethernet channels), data from bus 1502 (e.g., speed of vehicle 1500, steering wheel position, etc.), data from GNSS sensor(s) 1558 (e.g., connected over an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1504 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 1506 from routine data management tasks.

[0265] In at least one embodiment, SoC(s) 1504 may be an end-to-end platform with a flexible architecture that spans automation Levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 1504 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 1514, when combined with CPU(s) 1506, GPU(s) 1508, and data store(s) 1516, may provide for a fast, efficient platform for Level 3-5 autonomous vehicles.

[0266] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0267] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1520) may include text and word recognition, allowing reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of a sign, and to pass that semantic understanding to path planning modules running on a CPU Complex.

[0268] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, such warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs a vehicle’s path planning software (preferably executing on a CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, a flashing light may be identified by operating a third deployed neural network over multiple frames, informing a vehicle’s path-planning software of a presence (or an absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within a DLA and / or on GPU(s) 1508.

[0269] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1500. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns on lights, and, in a security mode, to disable such vehicle when an owner leaves such vehicle. In this way, SoC(s) 1504 provide for security against theft and / or carjacking.

[0270] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1596 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1504 use a CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 1558. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, and when in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing a vehicle, pulling over to a side of a road, parking a vehicle, and / or idling a vehicle, with assistance of ultrasonic sensor(s) 1562, until emergency vehicles pass.

[0271] In at least one embodiment, vehicle 1500 may include CPU(s) 1518 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1504 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1518 may include an X86 processor, for example. CPU(s) 1518 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1504, and / or monitoring status and health of controller(s) 1536 and / or an infotainment system on a chip (“infotainment SoC”) 1530, for example.

[0272] In at least one embodiment, vehicle 1500 may include GPU(s) 1520 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1504 via a high-speed interconnect (e.g., NVIDIA’s NVLINK channel). In at least one embodiment, GPU(s) 1520 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 1500.

[0273] In at least one embodiment, vehicle 1500 may further include network interface 1524 which may include, without limitation, wireless antenna(s) 1526 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1524 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 150 and another vehicle and / or an indirect link may be established (e.g., across networks and over Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1500 information about vehicles in proximity to vehicle 1500 (e.g., vehicles in front of, on a side of, and / or behind vehicle 1500). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1500.

[0274] In at least one embodiment, network interface 1524 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1536 to communicate over wireless networks. In at least one embodiment, network interface 1524 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0275] In at least one embodiment, vehicle 1500 may further include data store(s) 1528 which may include, without limitation, off-chip (e.g., off SoC(s) 1504) storage. In at least one embodiment, data store(s) 1528 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that may store at least one bit of data.

[0276] In at least one embodiment, vehicle 1500 may further include GNSS sensor(s) 1558 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 1558 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethernet-to-Serial (e.g., RS-232) bridge.

[0277] In at least one embodiment, vehicle 1500 may further include RADAR sensor(s) 1560. In at least one embodiment, RADAR sensor(s) 1560 may be used by vehicle 1500 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 1560 may use a CAN bus and / or bus 1502 (e.g., to transmit data generated by RADAR sensor(s) 1560) for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 1560 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more sensor of RADAR sensors(s) 1560 is a Pulse Doppler RADAR sensor.

[0278] In at least one embodiment, RADAR sensor(s) 1560 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, RADAR sensor(s) 1560 may help in distinguishing between static and moving objects, and may be used by ADAS system 1538 for emergency brake assist and forward collision warning. In at least one embodiment, sensors 1560(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, a central four antennae may create a focused beam pattern, designed to record vehicle’s 1500 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, another two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving a lane of vehicle 1500.

[0279] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 1560 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spots in a rear direction and next to a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1538 for blind spot detection and / or lane change assist.

[0280] In at least one embodiment, vehicle 1500 may further include ultrasonic sensor(s) 1562. In at least one embodiment, ultrasonic sensor(s) 1562, which may be positioned at a front, a back, and / or side location of vehicle 1500, may be used for parking assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 1562 may be used, and different ultrasonic sensor(s) 1562 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1562 may operate at functional safety levels of ASIL B. [0281 ] In at least one embodiment, vehicle 1500 may include LIDAR sensor(s) 1564. In at least one embodiment, LIDAR sensor(s) 1564 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1564 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1500 may include multiple LIDAR sensors 1564 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0282] In at least one embodiment, LIDAR sensor(s) 1564 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1564 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, LIDAR sensor(s) 1564 may include a small device that may be embedded into a front, a rear, a side, and / or a corner location of vehicle 1500. In at least one embodiment, LIDAR sensor(s) 1564, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1564 may be configured for a horizontal field of view between 45 degrees and 135 degrees. [02 83 ] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 1500 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to a range from vehicle 1500 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 1500. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0284] In at least one embodiment, vehicle 1500 may further include IMU sensor(s) 1566. In at least one embodiment, IMU sensor(s) 1566 may be located at a center of a rear axle of vehicle 1500. In at least one embodiment, IMU sensor(s) 1566 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 1566 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1566 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0285] In at least one embodiment, IMU sensor(s) 1566 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s) 1566 may enable vehicle 1500 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to IMU sensor(s) 1566. In at least one embodiment, IMU sensor(s) 1566 and GNSS sensor(s) 1558 may be combined in a single integrated unit.

[0286] In at least one embodiment, vehicle 1500 may include microphone(s) 1596 placed in and / or around vehicle 1500. In at least one embodiment, microphone(s) 1596 may be used for emergency vehicle detection and identification, among other things.

[0287] In at least one embodiment, vehicle 1500 may further include any number of camera types, including stereo camera(s) 1568, wide-view camera(s) 1570, infrared camera(s) 1572, surround camera(s) 1574, long-range camera(s) 1598, mid-range camera(s) 1576, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 1500. In at least one embodiment, which types of cameras used depends on vehicle 1500. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 1500. In at least one embodiment, a number of cameras deployed may differ depending on embodiment. For example, in at least one embodiment, vehicle 1500 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera might be as described with more detail previously herein with respect to FIG. 15A and FIG. 15B.

[0288] In at least one embodiment, vehicle 1500 may further include vibration sensor(s) 1542. In at least one embodiment, vibration sensor(s) 1542 may measure vibrations of components of vehicle 1500, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1542 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when a difference in vibration is between a power-driven axle and a freely rotating axle).

[0289] In at least one embodiment, vehicle 1500 may include ADAS system 1538. In at least one embodiment, ADAS system 1538 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 1538 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0290] In at least one embodiment, ACC system may use RADAR sensor(s) 1560, LIDAR sensor(s) 1564, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls distance to another vehicle immediately ahead of vehicle 1500 and automatically adjusts speed of vehicle 1500 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system performs distance keeping, and advises vehicle 1500 to change lanes when necessary. In at least one embodiment, a lateral ACC is related to other ADAS applications, such as LC and CW. [0291 ] In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1524 and / or wireless antenna(s) 1526 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 1500), while I2V communication provides information about traffic further ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 1500, a CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[0292] In at least one embodiment, an FCW system is designed to alert a driver to a hazard, so that such driver may take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse.

[0293] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid collision and, if that driver does not take corrective action, that AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, an impact of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or crash imminent braking.

[0294] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 1500 crosses lane markings. In at least one embodiment, an LDW system does not activate when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct vehicle 1500 if vehicle 1500 starts to exit its lane.

[0295] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile’s blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0296] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside a rear-camera range when vehicle 1500 is backing up. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component.

[0297] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 1500 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1536). For example, in at least one embodiment, ADAS system 1538 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1538 may be provided to a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, a supervisory MCU determines how to reconcile conflict to ensure safe operation. 10298] In at least one embodiment, a primary computer may be configured to provide a supervisory MCU with a confidence score, indicating that primary computer’s confidence in a chosen result. In at least one embodiment, if that confidence score exceeds a threshold, that supervisory MCU may follow that primary computer’s direction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where a confidence score does not meet a threshold, and where primary and secondary computers indicate different results (e.g., a conflict), a supervisory MCU may arbitrate between computers to determine an appropriate outcome.

[0299] In at least one embodiment, a supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) in a supervisory MCU may learn when a secondary computer’s output may be trusted, and when it cannot. For example, in at least one embodiment, when that secondary computer is a RADAR-based FCW system, a neural network(s) in that supervisory MCU may learn when an FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU suitable for running neural network(s) with associated memory. In at least one embodiment, a supervisory MCU may comprise and / or be included as a component of SoC(s) 1504.

[0300] In at least one embodiment, ADAS system 1538 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, that secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes an overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on a primary computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a supervisory MCU may have greater confidence that an overall result is correct, and a bug in software or hardware on that primary computer is not causing a material error.

[0301] In at least one embodiment, an output of ADAS system 1538 may be fed into a primary computer’s perception block and / or a primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 1538 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces a risk of false positives, as described herein.

[0302] In at least one embodiment, vehicle 1500 may further include infotainment SoC 1530 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system SoC 1530, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1530 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1500. For example, infotainment SoC 1530 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 1534, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1530 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle 1500, such as information from ADAS system 1538, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information. [0303 ] In at least one embodiment, infotainment SoC 1530 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1530 may communicate over bus 1502 with other devices, systems, and / or components of vehicle 1500. In at least one embodiment, infotainment SoC 1530 may be coupled to a supervisory MCU such that a GPU of an infotainment system may perform some self-driving functions in event that primary controller(s) 1536 (e.g., primary and / or backup computers of vehicle 1500) fail. In at least one embodiment, infotainment SoC 1530 may put vehicle 1500 into a chauffeur to safe stop mode, as described herein.

[0304] In at least one embodiment, vehicle 1500 may further include instrument cluster 1532 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1532 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 1532 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 1530 and instrument cluster 1532. In at least one embodiment, instrument cluster 1532 may be included as part of infotainment SoC 1530, or vice versa.

[0305] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 15C for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0306] FIG. 15D is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 1500 of FIG. 15 A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server(s) 1578, network(s) 1590, and any number and type of vehicles, including vehicle 1500. In at least one embodiment, server(s) 1578 may include, without limitation, a plurality of GPUs 15 84(A)-15 84(H) (collectively referred to herein as GPUs 1584), PCIe switches 1582(A)-1582(D) (collectively referred to herein as PCIe switches 1582), and / or CPUs 1580(A)-1580(B) (collectively referred to herein as CPUs 1580). In at least one embodiment, GPUs 1584, CPUs 1580, and PCIe switches 1582 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 1588 developed by NVIDIA and / or PCIe connections 1586. In at least one embodiment, GPUs 1584 are connected via an NVLink and / or NVSwitch SoC and GPUs 1584 and PCIe switches 1582 are connected via PCIe interconnects. Although eight GPUs 1584, two CPUs 1580, and four PCIe switches 1582 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 1578 may include, without limitation, any number of GPUs 1584, CPUs 1580, and / or PCIe switches 1582, in any combination. For example, in at least one embodiment, server(s) 1578 could each include eight, sixteen, thirty-two, and / or more GPUs 1584.

[0307] In at least one embodiment, server(s) 1578 may receive, over network(s) 1590 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 1578 may transmit, over network(s) 1590 and to vehicles, neural networks 1592, updated or otherwise, and / or map information 1594, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1594 may include, without limitation, updates for HD map 1522, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 1592, and / or map information 1594 may have resulted from new training and / or experiences represented in data received from any number of vehicles in an environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 1578 and / or other servers).

[0308] In at least one embodiment, server(s) 1578 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 1590), and / or machine learning models may be used by server(s) 1578 to remotely monitor vehicles.

[0309] In at least one embodiment, server(s) 1578 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 1578 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 1584, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 1578 may include deep learning infrastructure that uses CPU-powered data centers.

[0310] In at least one embodiment, deep-learning infrastructure of server(s) 1578 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 1500. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 1500, such as a sequence of images and / or objects that vehicle 1500 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1500 and, if results do not match and deep-learning infrastructure concludes that AI in vehicle 1500 is malfunctioning, then server(s) 1578 may transmit a signal to vehicle 1500 instructing a fail-safe computer of vehicle 1500 to assume control, notify passengers, and complete a safe parking maneuver.

[0311] In at least one embodiment, server(s) 1578 may include GPU(s) 1584 and one or more programmable inference accelerators (e.g., NVIDIA’s TensorRT 3 devices). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 1215 are used to perform one or more embodiments. Details regarding hardware structure(x) 1215 are provided herein in conjunction with FIGS. 12A and / or 12B.

[0312] In at least one embodiment, one or more systems depicted in FIGS. 15A-15D are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIGS. 15A-15D are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIGS. 15A-15D are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11. COMPUTER SYSTEMS

[0313] FIG. 16 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1600 may include, without limitation, a component, such as a processor 1602 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1600 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1600 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces, may also be used.

[0314] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[0315] In at least one embodiment, computer system 1600 may include, without limitation, processor 1602 that may include, without limitation, one or more execution units 1608 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1600 is a single processor desktop or server system, but in another embodiment, computer system 1600 may be a multiprocessor system. In at least one embodiment, processor 1602 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1602 may be coupled to a processor bus 1610 that may transmit data signals between processor 1602 and other components in computer system 1600.

[0316] In at least one embodiment, processor 1602 may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 1604. In at least one embodiment, processor 1602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1602. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file 1606 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

[0317] In at least one embodiment, execution unit 1608, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1602. In at least one embodiment, processor 1602 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1608 may include logic to handle a packed instruction set 1609. In at least one embodiment, by including packed instruction set 1609 in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1602. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor’s data bus to perform one or more operations one data element at a time.

[0318] In at least one embodiment, execution unit 1608 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1600 may include, without limitation, a memory 1620. In at least one embodiment, memory 1620 may be a Dynamic Random Access Memory (“DRAM’) device, a Static Random Access Memory (“SRAM’) device, a flash memory device, or another memory device. In at least one embodiment, memory 1620 may store instruction(s) 1619 and / or data 1621 represented by data signals that may be executed by processor 1602.

[0319] In at least one embodiment, a system logic chip may be coupled to processor bus 1610 and memory 1620. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub (“MCH”) 1616, and processor 1602 may communicate with MCH 1616 via processor bus 1610. In at least one embodiment, MCH 1616 may provide a high bandwidth memory path 1618 to memory 1620 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 1616 may direct data signals between processor 1602, memory 1620, and other components in computer system 1600 and to bridge data signals between processor bus 1610, memory 1620, and a system I / O interface 1622. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1616 may be coupled to memory 1620 through high bandwidth memory path 1618 and a graphics / video card 1612 may be coupled to MCH 1616 through an Accelerated Graphics Port (“AGP”) interconnect 1614.

[0320] In at least one embodiment, computer system 1600 may use system I / O interface 1622 as a proprietary hub interface bus to couple MCH 1616 to an I / O controller hub (“ICH”) 1630. In at least one embodiment, ICH 1630 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1620, a chipset, and processor 1602. Examples may include, without limitation, an audio controller 1629, a firmware hub (“flash BIOS”) 1628, a wireless transceiver 1626, a data storage 1624, a legacy I / O controller 1623 containing user input and keyboard interfaces 1625, a serial expansion port 1627, such as a Universal Serial Bus (“USB”) port, and a network controller 1634. In at least one embodiment, data storage 1624 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 10321 j In at least one embodiment, FIG. 16 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 16 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 16 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system 1600 are interconnected using compute express link (CXL) interconnects.

[0322] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 16 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0323] In at least one embodiment, one or more systems depicted in FIG. 16 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 16 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 16 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0324] FIG. 17 is a block diagram illustrating an electronic device 1700 for utilizing a processor 1710, according to at least one embodiment. In at least one embodiment, electronic device 1700 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0325] In at least one embodiment, electronic device 1700 may include, without limitation, processor 1710 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1710 is coupled using a bus or interface, such as a I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 17 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 17 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 17 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 17 are interconnected using compute express link (CXL) interconnects.

[0326] In at least one embodiment, FIG 17 may include a display 1724, a touch screen 1725, a touch pad 1730, a Near Field Communications unit (“NFC”) 1745, a sensor hub 1740, a thermal sensor 1746, an Express Chipset (“EC”) 1735, a Trusted Platform Module (“TPM”) 1738, BlOS / firmware / flash memory (“BIOS, FW Flash”) 1722, a DSP 1760, a drive 1720 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1750, a Bluetooth unit 1752, a Wireless Wide Area Network unit (“WWAN”) 1756, a Global Positioning System (GPS) unit 1755, a camera (“USB 3.0 camera”) 1754 such as a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1715 implemented in, for example, an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0327] In at least one embodiment, other components may be communicatively coupled to processor 1710 through components described herein. In at least one embodiment, an accelerometer 1741, an ambient light sensor (“ALS”) 1742, a compass 1743, and a gyroscope 1744 may be communicatively coupled to sensor hub 1740. In at least one embodiment, a thermal sensor 1739, a fan 1737, a keyboard 1736, and touch pad 1730 may be communicatively coupled to EC 1735. In at least one embodiment, speakers 1763, headphones 1764, and a microphone (“mic”) 1765 may be communicatively coupled to an audio unit (“audio codec and class D amp”) 1762, which may in turn be communicatively coupled to DSP 1760. In at least one embodiment, audio unit 1762 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM’) 1757 may be communicatively coupled to WWAN unit 1756. In at least one embodiment, components such as WLAN unit 1750 and Bluetooth unit 1752, as well as WWAN unit 1756 may be implemented in a Next Generation Form Factor (“NGFF”).

[0328] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 17 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0329] In at least one embodiment, one or more systems depicted in FIG. 17 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 17 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 17 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0330] FIG. 18 illustrates a computer system 1800, according to at least one embodiment. In at least one embodiment, computer system 1800 is configured to implement various processes and methods described throughout this disclosure. [0331 ] In at least one embodiment, computer system 1800 comprises, without limitation, at least one central processing unit (“CPU”) 1802 that is connected to a communication bus 1810 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1800 includes, without limitation, a main memory 1804 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1804, which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1822 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1800.

[0332] In at least one embodiment, computer system 1800, in at least one embodiment, includes, without limitation, input devices 1808, a parallel processing system 1812, and display devices 1806 that can be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light emitting diode (“LED”) display, a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1808 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein can be situated on a single semiconductor platform to form a processing system.

[0333] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 18 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0334] In at least one embodiment, one or more systems depicted in FIG. 18 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 18 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 18 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0335] FIG. 19 illustrates a computer system 1900, according to at least one embodiment. In at least one embodiment, computer system 1900 includes, without limitation, a computer 1910 and a USB stick 1920. In at least one embodiment, computer 1910 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1910 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer. [033€>] In at least one embodiment, USB stick 1920 includes, without limitation, a processing unit 1930, a USB interface 1940, and USB interface logic 1950. In at least one embodiment, processing unit 1930 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1930 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1930 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing unit 1930 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1930 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0337] In at least one embodiment, USB interface 1940 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1940 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1940 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1950 may include any amount and type of logic that enables processing unit 1930 to interface with devices (e.g., computer 1910) via USB connector 1940.

[0338] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in system FIG. 19 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [0339 ] In at least one embodiment, one or more systems depicted in FIG. 19 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 19 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 19 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0340] FIG. 20A illustrates an exemplary architecture in which a plurality of GPUs 2010(l)-2010(N) is communicatively coupled to a plurality of multi-core processors 2005(l)-2005(M) over high-speed links 2040(1 )-2040(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 2040( l)-2040(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, values of which may be different from figure to figure.

[0341] In addition, and in at least one embodiment, two or more of GPUs 2010 are interconnected over high-speed links 2029(1)-2029(2), which may be implemented using similar or different protocols / links than those used for high-speed links 2040(1 )-2040(N). Similarly, two or more of multi-core processors 2005 may be connected over a high-speed link 2028 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 20A may be accomplished using similar protocols / links (e.g., over a common interconnection fabric).

[0342] In at least one embodiment, each multi-core processor 2005 is communicatively coupled to a processor memory 2001(1 )-2001 (M), via memory interconnects 2026( l)-2026(M), respectively, and each GPU 2010(l)-2010(N) is communicatively coupled to GPU memory 2020(1 )-2020(N) over GPU memory interconnects 2050(1 )-2050(N), respectively. In at least one embodiment, memory interconnects 2026 and 2050 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memories 2001(1 )-2001(M) and GPU memories 2020 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memories 2001 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0343] As described herein, although various multi-core processors 2005 and GPUs 2010 may be physically coupled to a particular memory 2001, 2020, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 2001(1 )-2001 (M) may each comprise 64 GB of system memory address space and GPU memories 2020(l)-2020(N) may each comprise 32 GB of system memory address space resulting in a total of 256 GB addressable memory when M=2 and N=4. Other values for N and M are possible.

[0344] FIG. 20B illustrates additional details for an interconnection between a multi-core processor 2007 and a graphics acceleration module 2046 in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 2046 may include one or more GPU chips integrated on a line card which is coupled to processor 2007 via high-speed link 2040 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 2046 may alternatively be integrated on a package or chip with processor 2007.

[0345] In at least one embodiment, processor 2007 includes a plurality of cores 2060A-2060D, each with a translation lookaside buffer (“TLB”) 2061A-2061D and one or more caches 2062A-2062D. In at least one embodiment, cores 2060A-2060D may include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, caches 2062A-2062D may comprise Level 1 (LI) and Level 2 (L2) caches. In addition, one or more shared caches 2056 may be included in caches 2062A-2062D and shared by sets of cores 2060A-2060D. For example, one embodiment of processor 2007 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 2007 and graphics acceleration module 2046 connect with system memory 2014, which may include processor memories 2001(1 )-2001(M) of FIG. 20A.

[0346] In at least one embodiment, coherency is maintained for data and instructions stored in various caches 2062A-2062D, 2056 and system memory 2014 via inter-core communication over a coherence bus 2064. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 2064 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 2064 to snoop cache accesses.

[0347] In at least one embodiment, a proxy circuit 2025 communicatively couples graphics acceleration module 2046 to coherence bus 2064, allowing graphics acceleration module 2046 to participate in a cache coherence protocol as a peer of cores 2060A-2060D. In particular, in at least one embodiment, an interface 2035 provides connectivity to proxy circuit 2025 over high-speed link 2040 and an interface 2037 connects graphics acceleration module 2046 to high-speed link 2040.

[0348] In at least one embodiment, an accelerator integration circuit 2036 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 2031(1 )-2031(N) of graphics acceleration module 2046. In at least one embodiment, graphics processing engines 2031(l)-2031(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, graphics processing engines 2031 (1)-2031(N) alternatively may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 2046 may be a GPU with a plurality of graphics processing engines 2031(1 )-2031(N) or graphics processing engines 2031(1 )-2031(N) may be individual GPUs integrated on a common package, line card, or chip.

[0349] In at least one embodiment, accelerator integration circuit 2036 includes a memory management unit (MMU) 2039 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 2014. In at least one embodiment, MMU 2039 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 2038 can store commands and data for efficient access by graphics processing engines 2031(l)-2031(N). In at least one embodiment, data stored in cache 2038 and graphics memories 2033(l)-2033(M) is kept coherent with core caches 2062A-2062D, 2056 and system memory 2014, possibly using a fetch unit 2044. As mentioned, this may be accomplished via proxy circuit 2025 on behalf of cache 2038 and memories 2033(l)-2033(M) (e.g., sending updates to cache 2038 related to modifications / accesses of cache lines on processor caches 2062A-2062D, 2056 and receiving updates from cache 2038).

[0350] In at least one embodiment, a set of registers 2045 store context data for threads executed by graphics processing engines 2031(1 )-2031(N) and a context management circuit 2048 manages thread contexts. For example, context management circuit 2048 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 2048 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In at least one embodiment, an interrupt management circuit 2047 receives and processes interrupts received from system devices. [0351 ] In at least one embodiment, virtual / effective addresses from a graphics processing engine 2031 are translated to real / physical addresses in system memory 2014 by MMU 2039. In at least one embodiment, accelerator integration circuit 2036 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 2046 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 2046 may be dedicated to a single application executed on processor 2007 or may be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 2031 (1)-2031(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0352] In at least one embodiment, accelerator integration circuit 2036 performs as a bridge to a system for graphics acceleration module 2046 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integration circuit 2036 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 2031 (1)-2031(N), interrupts, and memory management.

[0353] In at least one embodiment, because hardware resources of graphics processing engines 2031(l)-2031(N) are mapped explicitly to a real address space seen by host processor 2007, any host processor can address these resources directly using an effective address value. In at least one embodiment, one function of accelerator integration circuit 2036 is physical separation of graphics processing engines 2031 (1)-2031(N) so that they appear to a system as independent units.

[0354] In at least one embodiment, one or more graphics memories 2033(1 )-2033(M) are coupled to each of graphics processing engines 2031(1 )-2031(N), respectively and N=M. In at least one embodiment, graphics memories 2033(1 )-2033(M) store instructions and data being processed by each of graphics processing engines 2031(1 )-2031(N). In at least one embodiment, graphics memories 2033(1 )-2033(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0355] In at least one embodiment, to reduce data traffic over high-speed link 2040, biasing techniques can be used to ensure that data stored in graphics memories 2033(l)-2033(M) is data that will be used most frequently by graphics processing engines 2031 (1)-2031(N) and preferably not used by cores 2060A-2060D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 2031 (1)-2031(N)) within caches 2062A-2062D, 2056 and system memory 2014.

[0356] FIG. 20C illustrates another exemplary embodiment in which accelerator integration circuit 2036 is integrated within processor 2007. In this embodiment, graphics processing engines 2031(1 )-2031(N) communicate directly over high-speed link 2040 to accelerator integration circuit 2036 via interface 2037 and interface 2035 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 2036 may perform similar operations as those described with respect to FIG. 20B, but potentially at a higher throughput given its close proximity to coherence bus 2064 and caches 2062A-2062D, 2056. In at least one embodiment, an accelerator integration circuit supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 2036 and programming models which are controlled by graphics acceleration module 2046.

[0357] In at least one embodiment, graphics processing engines 2031(1 )-2031(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 2031(1 )-2031(N), providing virtualization within a VM / partition.

[0358] In at least one embodiment, graphics processing engines 2031(1 )-2031(N), may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 2031(1)-2031(N) to allow access by each operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 2031 (1)-2031(N) are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 2031(l)-2031(N) to provide access to each process or application.

[0359] In at least one embodiment, graphics acceleration module 2046 or an individual graphics processing engine 2031(l)-2031(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 2014 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 2031 (1)-2031(N) (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of a process element within a process element linked list.

[0360] FIG. 20D illustrates an exemplary accelerator integration slice 2090. In at least one embodiment, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 2036. In at least one embodiment, an application is effective address space 2082 within system memory 2014 stores process elements 2083. In at least one embodiment, process elements 2083 are stored in response to GPU invocations 2081 from applications 2080 executed on processor 2007. In at least one embodiment, a process element 2083 contains process state for corresponding application 2080. In at least one embodiment, a work descriptor (WD) 2084 contained in process element 2083 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 2084 is a pointer to a job request queue in an application’s effective address space 2082.

[0361] In at least one embodiment, graphics acceleration module 2046 and / or individual graphics processing engines 2031 (1)-2031(N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process states and sending a WD 2084 to a graphics acceleration module 2046 to start a job in a virtualized environment may be included.

[0362] In at least one embodiment, a dedicated-process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns graphics acceleration module 2046 or an individual graphics processing engine 2031. In at least one embodiment, when graphics acceleration module 2046 is owned by a single process, a hypervisor initializes accelerator integration circuit 2036 for an owning partition and an operating system initializes accelerator integration circuit 2036 for an owning process when graphics acceleration module 2046 is assigned.

[0363] In at least one embodiment, in operation, a WD fetch unit 2091 in accelerator integration slice 2090 fetches next WD 2084, which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 2046. In at least one embodiment, data from WD 2084 may be stored in registers 2045 and used by MMU 2039, interrupt management circuit 2047 and / or context management circuit 2048 as illustrated. For example, one embodiment of MMU 2039 includes segment / page walk circuitry for accessing segment / page tables 2086 within an OS virtual address space 2085. In at least one embodiment, interrupt management circuit 2047 may process interrupt events 2092 received from graphics acceleration module 2046. In at least one embodiment, when performing graphics operations, an effective address 2093 generated by a graphics processing engine 2031 (1)-2031(N) is translated to a real address by MMU 2039.

[0364] In at least one embodiment, registers 2045 are duplicated for each graphics processing engine 2031(1)-2031(N) and / or graphics acceleration module 2046 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 2090. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialized Registers Register # Description 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0365] Exemplary registers that may be initialized by an operating system are shown in Table 2. Table 2 - Operating System Initialized Registers Register # Description 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[0366] In at least one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or graphics processing engines 2031(1 )-2031(N). In at least one embodiment, it contains all information required by a graphics processing engine 2031(1)-2031(N) to do work, or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0367] FIG. 20E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 2098 in which a process element list 2099 is stored. In at least one embodiment, hypervisor real address space 2098 is accessible via a hypervisor 2096 which virtualizes graphics acceleration module engines for operating system 2095.

[0368] In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 2046. In at least one embodiment, there are two programming models where graphics acceleration module 2046 is shared by multiple processes and partitions, namely time-sliced shared and graphics directed shared.

[0369] In at least one embodiment, in this model, system hypervisor 2096 owns graphics acceleration module 2046 and makes its function available to all operating systems 2095. In at least one embodiment, for a graphics acceleration module 2046 to support virtualization by system hypervisor 2096, graphics acceleration module 2046 may adhere to certain requirements, such as (1) an application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 2046 must provide a context save and restore mechanism, (2) an application’s job request is guaranteed by graphics acceleration module 2046 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 2046 provides an ability to preempt processing of a job, and (3) graphics acceleration module 2046 must be guaranteed fairness between processes when operating in a directed shared programming model.

[0370] In at least one embodiment, application 2080 is required to make an operating system 2095 system call with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 2046 and can be in a form of a graphics acceleration module 2046 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 2046. [037 i ] In at least one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuit 2036 (not shown) and graphics acceleration module 2046 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 2096 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 2083. In at least one embodiment, CSRP is one of registers 2045 containing an effective address of an area in an application’s effective address space 2082 for graphics acceleration module 2046 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[0372] Upon receiving a system call, operating system 2095 may verify that application 2080 has registered and been given authority to use graphics acceleration module 2046. In at least one embodiment, operating system 2095 then calls hypervisor 2096 with information shown in Table 3. Table 3 - OS to Hypervisor Call Parameters Parameter # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked) 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN)

[0373] In at least one embodiment, upon receiving a hypervisor call, hypervisor 2096 verifies that operating system 2095 has registered and been given authority to use graphics acceleration module 2046. In at least one embodiment, hypervisor 2096 then puts process element 2083 into a process element linked list for a corresponding graphics acceleration module 2046 type. In at least one embodiment, a process element may include information shown in Table 4. Table 4 -Process Element Information Element # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 Storage Descriptor Register (SDR)

[0374] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 2090 registers 2045.

[0375] As illustrated in FIG. 20F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 2001(1 )-2001(N) and GPU memories 2020(l)-2020(N). In this implementation, operations executed on GPUs 2010(l)-2010(N) utilize a same virtual / effective memory address space to access processor memories 2001(1 )-2001 (M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 2001(1), a second portion to second processor memory 2001(N), a third portion to GPU memory 2020(1), and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 2001 and GPU memories 2020, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0376] In at least one embodiment, bias / coherence management circuitry 2094A-2094E within one or more of MMUs 2039A-2039E ensures cache coherence between caches of one or more host processors (e.g., 2005) and GPUs 2010 and implements biasing techniques indicating physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 2094A-2094E are illustrated in FIG. 20F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 2005 and / or within accelerator integration circuit 2036.

[0377] One embodiment allows GPU memories 2020 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 2020 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement allows software of host processor 2005 to setup operands and access computation results, without overhead of tradition I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU memories 2020 without cache coherence overheads can be critical to execution time of an offloaded computation. In at least one embodiment, in cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 2010. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[0378] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, a bias table may be used, for example, which may be a page-granular structure (e.g., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU memories 2020, with or without a bias cache in a GPU 2010 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0379] In at least one embodiment, a bias table entry associated with each access to a GPU attached memory 2020 is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 2010 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 2020. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 2005 (e.g., over a high-speed link as described herein). In at least one embodiment, requests from processor 2005 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 2010. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, a bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0380] In at least one embodiment, one mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 2005 bias to GPU bias, but is not for an opposite transition. [0381 ] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 2005. In at least one embodiment, to access these pages, processor 2005 may request access from GPU 2010, which may or may not grant access right away. In at least one embodiment, thus, to reduce communication between processor 2005 and GPU 2010 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 2005 and vice versa.

[0382] Hardware structure(s) 1215 are used to perform one or more embodiments. Details regarding a hardware structure(s) 1215 may be provided herein in conjunction with FIGS. 12A and / or 12B.

[0383] In at least one embodiment, one or more systems depicted in FIGS. 20A-20F are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIGS. 20A-20F are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIGS. 20A-20F are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0384] FIG. 21 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0385] FIG. 21 is a block diagram illustrating an exemplary system on a chip integrated circuit 2100 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 2100 includes one or more application processor(s) 2105 (e.g., CPUs), at least one graphics processor 2110, and may additionally include an image processor 2115 and / or a video processor 2120, any of which may be a modular IP core. In at least one embodiment, integrated circuit 2100 includes peripheral or bus logic including a USB controller 2125, a UART controller 2130, an SPI / SDIO controller 2135, and an I22S / I22C controller 2140. In at least one embodiment, integrated circuit 2100 can include a display device 2145 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2150 and a mobile industry processor interface (MIPI) display interface 2155. In at least one embodiment, storage may be provided by a flash memory subsystem 2160 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2165 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 2170.

[0386] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in integrated circuit 2100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0387] In at least one embodiment, one or more systems depicted in FIG. 21 are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIG. 21 are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIG. 21 are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0388] FIGS. 22A and 22B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0389] FIGS. 22A and 22B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 22A illustrates an exemplary graphics processor 2210 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 22B illustrates an additional exemplary graphics processor 2240 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 2210 of FIG. 22A is a low power graphics processor core. In at least one embodiment, graphics processor 2240 of FIG. 22B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 2210, 2240 can be variants of graphics processor 2110 of FIG. 21.

[0390] In at least one embodiment, graphics processor 2210 includes a vertex processor 2205 and one or more fragment processor(s) 2215A-2215N (e.g., 2215A, 2215B, 2215C, 2215D, through 2215N-1, and 2215N). In at least one embodiment, graphics processor 2210 can execute different shader programs via separate logic, such that vertex processor 2205 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 2215A-2215N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 2205 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 2215A-2215N use primitive and vertex data generated by vertex processor 2205 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 2215A-2215N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API. [039 i ] In at least one embodiment, graphics processor 2210 additionally includes one or more memory management units (MMUs) 2220A-2220B, cache(s) 2225A-2225B, and circuit interconnect(s) 2230A-2230B. In at least one embodiment, one or more MMU(s) 2220A-2220B provide for virtual to physical address mapping for graphics processor 2210, including for vertex processor 2205 and / or fragment processor(s) 2215A-2215N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 2225A-2225B. In at least one embodiment, one or more MMU(s) 2220A-2220B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 2105, image processors 2115, and / or video processors 2120 of FIG. 21, such that each processor 2105-2120 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 2230A-2230B enable graphics processor 2210 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[0392] In at least one embodiment, graphics processor 2240 includes one or more shader core(s) 2255A-2255N (e.g., 2255A, 2255B, 2255C, 2255D, 2255E, 2255F, through 2255N-1, and 225 5N) as shown in FIG. 22B, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 2240 includes an inter-core task manager 2245, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 225 5A-225 5N and a tiling unit 2258 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0393] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in integrated circuit 22A and / or 22B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0394] In at least one embodiment, one or more systems depicted in FIGS. 22A and 22B are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIGS. 22A and 22B are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIGS. 22A and 22B are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0395] FIGS. 23A and 23B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 23A illustrates a graphics core 2300 that may be included within graphics processor 2110 of FIG. 21, in at least one embodiment, and may be a unified shader core 2255A-2255N as in FIG. 22B in at least one embodiment. FIG. 23B illustrates a highly-parallel general-purpose graphics processing unit (“GPGPU”) 2330 suitable for deployment on a multi-chip module in at least one embodiment.

[0396] In at least one embodiment, graphics core 2300 includes a shared instruction cache 2302, a texture unit 2318, and a cache / shared memory 2320 that are common to execution resources within graphics core 2300. In at least one embodiment, graphics core 2300 can include multiple slices 2301A-2301N or a partition for each core, and a graphics processor can include multiple instances of graphics core 2300. In at least one embodiment, slices 2301A-2301N can include support logic including a local instruction cache 2304A-2304N, a thread scheduler 2306A-2306N, a thread dispatcher 2308A-2308N, and a set of registers 2310A-2310N. In at least one embodiment, slices 2301A-2301N can include a set of additional function units (AFUs 2312A-2312N), floating-point units (FPUs 2314A-2314N), integer arithmetic logic units (ALUs 2316A-2316N), address computational units (ACUs 2313A-2313N), double-precision floating-point units (DPFPUs 2315 A-2315N), and matrix processing units (MPUs 2317A-2317N).

[0397] In at least one embodiment, FPUs 2314A-2314N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 2315A-2315N perform double precision (64-bit) floating point operations. In at least one embodiment, ADUs 2316A-2316N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 2317A-2317N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 2317-2317N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 2312A-2312N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0398] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in graphics core 2300 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0399] FIG. 23B illustrates a general-purpose processing unit (GPGPU) 2330 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 2330 can be linked directly to other instances of GPGPU 2330 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 2330 includes a host interface 2332 to enable a connection with a host processor. In at least one embodiment, host interface 2332 is a PCI Express interface. In at least one embodiment, host interface 2332 can be a vendor-specific communications interface or communications fabric. In at least one embodiment, GPGPU 2330 receives commands from a host processor and uses a global scheduler 2334 to distribute execution threads associated with those commands to a set of compute clusters 2336A-2336H. In at least one embodiment, compute clusters 2336A-2336H share a cache memory 2338. In at least one embodiment, cache memory 2338 can serve as a higher-level cache for cache memories within compute clusters 2336A-2336H.

[0400] In at least one embodiment, GPGPU 2330 includes memory 2344A-2344B coupled with compute clusters 2336A-2336H via a set of memory controllers 2342A-2342B. In at least one embodiment, memory 2344A-2344B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. [0401 ] In at least one embodiment, compute clusters 2336A-2336H each include a set of graphics cores, such as graphics core 2300 of FIG. 23 A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2336A-2336H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[0402] In at least one embodiment, multiple instances of GPGPU 2330 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 2336A-2336H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 2330 communicate over host interface 2332. In at least one embodiment, GPGPU 2330 includes an I / O hub 2339 that couples GPGPU 2330 with a GPU link 2340 that enables a direct connection to other instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2330. In at least one embodiment, GPU link 2340 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2330 are located in separate data processing systems and communicate via a network device that is accessible via host interface 2332. In at least one embodiment GPU link 2340 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 2332.

[0403] In at least one embodiment, GPGPU 2330 can be configured to train neural networks. In at least one embodiment, GPGPU 2330 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 2330 is used for inferencing, GPGPU 2330 may include fewer compute clusters 2336A-2336H relative to when GPGPU 2330 is used for training a neural network. In at least one embodiment, memory technology associated with memory 2344A-2344B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 2330 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0404] Inference and / or training logic 1215 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1215 are provided herein in conjunction with FIGS. 12A and / or 12B. In at least one embodiment, inference and / or training logic 1215 may be used in GPGPU 2330 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0405] In at least one embodiment, one or more systems depicted in FIGS. 23A and 23B are utilized to implement one or more implicit environment functions. In at least one embodiment, one or more systems depicted in FIGS. 23A and 23B are utilized to use one or more neural networks, such as one or more implicit environment functions, to calculate a plurality of paths through which an entity, such as an autonomous device, is to traverse. In at least one embodiment, one or more systems depicted in FIGS. 23A and 23B are utilized to implement one or more systems and / or processes such as those described in connection with FIGS. 1-11.

[0406] FIG. 24 is a block diagram illustrating a computing system 2400 according to at least one embodiment. In at least one embodiment, computing system 2400 includes a processing subsystem 2401 having one or more processor(s) 2402 and a system memory 2404 communicating via an interconnection path that may include a memory hub 2405. In at least one embodiment, memory hub 2405 may be a separate component within a chipset component or may be integrated within one or more processor(s) 2402. In at least one embodiment, memory hub 2405 couples with an I / O subsystem 2411 via a communication link 2406. In at least one embodiment, I / O subsystem 2411 includes an I / O hub 2407 that can enable computing system 2400 to receive input from one or more input device(s) 2408. In at least one embodiment, I / O hub 2407 can enable a display controller, which may be included in one or more processor(s) 2402, to provide outputs to one or more display device(s) 2410A. In at least one embodiment, one or more display device(s) 2410A coupled with I / O hub 2407 can include a local, internal, or embedded display device.

[0407] In at least one embodiment, processing subsystem 2401 includes one or more parallel processor(s) 2412 coupled to memory hub 2405 via a bus or other communication link 2413. In at least one embodiment, communication link 2413 may use one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor-specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 2412 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of parallel processor(s) 2412 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 241OA coupled via I / O Hub 2407. In at least one embodiment, parallel processor(s) 2412 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 241 OB.

[0408] In at least one embodiment, a system storage unit 2414 can connect to I / ...

Claims

1. A processor, comprising:one or more circuits to use one or more neural networks to represent an environment through distances of various positions in the environment to a goal position, wherein the one or more neural networks are configured to output a distance of an input position to the goal position.

2. The processor of claim 1, wherein the one or more circuits are to usethe one or more neural networks to calculate a plurality of paths through the environment by at least:obtaining a first location, a set of locations, and a final location;causing the one or more neural networks to calculate a set of distances based at least in part on the set of locations and the final location; andcalculating the plurality of paths based at least in part on the set of distances, wherein the plurality of paths form a path from the first location to the final location.

3. The processor of claim 2, wherein:the first location is a location of an autonomous device; anda subset of locations of the set of locations are accessible to the autonomous device from the first location.

4. The processor of claim 3, wherein the one or more circuits are to calculate a first path of the plurality of paths by at least:obtaining a subset of distances of the set of distances corresponding to the subset of locations;selecting a second location of the subset of locations based at least in part on the subset of distances; andcalculating the first path comprising a path from the first location to the second location.

5. The processor of claim 4, wherein the second location corresponds to a minimum distance of the subset of distances.

6. The processor of any of claims 2-5, wherein the one or more neural networks calculate the set of distances in a single forward pass.

7. The processor of any of claims 2-6, wherein a distance of the set of distances corresponds to a distance along a path from a location of the set of locations to the final location.

8. A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to use one or more neural networks to represent an environment through distances of various positions in the environment to a goal position, wherein the one or more neural networks are configured to output a distance of an input position to the goal position.

9. The machine-readable medium of claim 8, wherein the set of instructions further comprise instructions, which if performed by the one or more processors, cause the one or more processors to:obtain features of the environment;select a location in the environment; andinput at least the features and the location to the one or more neural networks to obtain a plurality of distances corresponding to a plurality of locations in the environment.

10. The machine-readable medium of claim 9, wherein the set of instructions further comprise instructions, which if performed by the one or more processors, cause the one or more processors to:select a set of locations accessible to an autonomous device;obtain a set of distances of the plurality of distances corresponding to the set of locations; andselect a first location of the set of locations based at least in part on the set of distances, wherein a first path of the plurality of paths indicates a path from the autonomous device to the first location.

11. The machine-readable medium of claim 10, wherein the set of instructions further comprise instructions, which if performed by the one or more processors, cause the one or more processors to cause the autonomous device to navigate to the first location using the first path.

12. The machine-readable medium of claim 11, wherein the autonomous device is an autonomous car.

13. The machine-readable medium of any of claims 9-12, wherein the features are generated by one or more encoders based on a representation of the environment.

14. The machine-readable medium of claim 13, wherein the representation of the environment is an image or a point cloud.

15. A system, comprising:one or more computers having one or more processors to use one or more neural networks to represent an environment through distances of various positions in the environment to a goal position, wherein the one or more neural networks are configured to output a distance of an input position to the goal position.

16. The system of claim 15, wherein the one or more processors are further to:capture a representation of an environment; anduse the one or more neural networks to calculate the plurality of paths from a first location of an autonomous device to a second location in the environment.

17. The system of claim 16, wherein the one or more processors are further to use the one or more neural networks to calculate one or more distance values for one or more locations in the environment based at least in part on the representation of the environment.

18. The system of claim 17, wherein the one or more processors are further to:calculate a size for a step of the autonomous device;select a set of locations accessible through the step from the first location of the autonomous device; andselect a third location of the set of locations based at least in part on the one or more distance values.

19. The system of any of claims 16-18, wherein the representation of the environment is captured through one or more depth cameras.

20. The system of any of claims 16-19, wherein the representation of the environment is a 2D or 3D representation.

21. The system of any of claims 15-20, wherein the autonomous device is an autonomous robot.

22. A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:train one or more neural networks to represent an environment through distances of various positions in the environment to a goal position, wherein the one or more neural networks are configured to output a distance of an input position to the goal position.

23. The machine-readable medium of claim 22, wherein the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to:obtain the environment and a location;cause one or more algorithms to determine one or more reaching distance values for one or more locations in the environment to the location; andtrain the one or more neural networks at least using the one or more reaching distance values.

24. The machine-readable medium of claim 23, wherein the set of instructions further include instructions, which if performed by the one or more processors, cause the one or more processors to:cause the one or more neural networks to process at least the one or more locations to calculate one or more predicted reaching distance values; andupdate the one or more neural networks based at least in part on differences between the one or more predicted reaching distance values and the one or more reaching distance values.

25. The machine-readable medium of claim 23 or claim 24, wherein the one or more algorithms include one or more fast marching method (FMM) algorithms.

26. The machine-readable medium of any of claims 23-25, wherein a first reaching distance value of the one or more reaching distance values corresponds to a first location of the one or more locations and indicates a distance along a path from the first location to the location.

27. The machine-readable medium of claim 26, wherein the path is a geometrically feasible path.

28. A processor comprising:one or more circuits to train one or more neural networks represent an environment through distances of various positions in the environment to a goal position, wherein the one or more neural networks are configured to output a distance of an input position to the goal position.

29. The processor of claim 28, wherein the one or more circuits are further to:cause one or more algorithms to process at least the environment, a set of positions, and a goal position;obtain a set of distance values based at least in part on results of the one or more algorithms; andtrain the one or more neural networks using the set of distance values.

30. The processor of claim 29, wherein the one or more circuits are further to train the one or more neural networks to process at least the environment, the set of positions, and the goal position to calculate the set of distance values.

31. The processor of claim 29 or claim 30, wherein a first distance value of the set of distance values indicates a distance along a semantically feasible path from a first position of the set of positions to the goal position.

32. The processor of any of claims 29-31, wherein the one or more algorithms include one or more path planning algorithms.

33. The processor of any of claims 28-32, wherein the one or more neural networks include one or more implicit environment functions.

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