Display device

Abstract

A display has a display area capable surrounded by a bezel, a plurality of subpixels included in the display area, and a plurality of data lines for supplying data signals for image display to the plu

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims priority from Korean Patent Application No. 10-2023-0196884, filed on December 29, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display device. BACKGROUND

[0002] As technology advances, a display device may provide shooting functions and various sensing functions in addition to image display functions. Accordingly, a display device is required to equip with electronic devices such as a camera and a detection sensor (which may also be referred as a light receiving device or sensor).

[0003] Since an electronic device may receive light from the front of a display device, so the electronic device is required to be installed in a location capable of receiving the light. Therefore, in general display devices, a camera (i.e., a camera lens) and a detection sensor are exposed to the front. As a result, a bezel of the display device may become larger or there may be significant limitations in the design of the display device. SUMMARY

[0004] Embodiments of the present disclosure may provide a display device having a light-transmitting structure which allows an electronic device to normally receive light (e.g., visible light, infrared light, or ultraviolet light) without exposing the electronic device receiving light to the front.

[0005] Embodiments of the present disclosure may provide a display device capable of improving the transmittance of an optical area (i.e, a first area) through which light can pass through.

[0006] Embodiments of the present disclosure may provide a display device having a structure to reduce the metal ratio in an optical area (i.e., a first area) through which light can be transmitted.

[0007] Embodiments of the present disclosure may provide a display device having a panel structure capable of improving a detection performance of a detection sensor using light passing through an optical area (i.e., a first area).

[0008] Embodiments of the present disclosure may provide a display device having a panel structure capable of improving a performance of a camera using light passing through an optical area (i.e., a first area).

[0009] A display device according to embodiments of the present disclosure may include a substrate including a display area capable of displaying an image and a nondisplay area outside the display area, a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of light emitting devices, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels.

[00010] The display area may include a first area capable of transmitting light and a second area located outside the first area.

[00011] The second area may include an upper area above the first area and a lower area under the first area.

[00012] The plurality of data lines may include an upper data line disposed in the upper area, a lower data line disposed in the lower area, and a bypass line configured to electrically connect the upper data line and the lower data line and bypass the first area.

[00013] The bypass line may include a first bypass line connected to the upper data line, a second bypass line connected to the lower data line, and a third bypass line for connecting the first bypass line and the second bypass line.

[00014] The bypass line may include a horizontal bypass line extending horizontally, and a vertical bypass line extending vertically, and wherein the first bypass line and the second bypass line are horizontal bypass lines, and the third bypass line is a vertical bypass line.

[00015] The horizontal bypass line may be disposed in a first metal layer, and the vertical bypass line may be disposed in a second metal layer different from the first metal layer.

[00016] Each of the plurality of light emitting devices may include a plurality of pixel electrodes.

[00017] The plurality of pixel electrodes may include a first pixel electrode disposed in the upper area and included in a first subpixel, a second pixel electrode disposed in the upper area and included in a second subpixel, a third pixel electrode disposed in the first area and included in a third subpixel, a fourth pixel electrode disposed in the first area and included in a fourth subpixel, a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel.

[00018] The first data line may be connected to the first subpixel, the third subpixel, and the fifth subpixel.

[00019] The upper data line may be connected to the second subpixel.

[00020] The lower data line may be connected to the sixth subpixel.

[00021] In a display device according to embodiments of the present disclosure, the third pixel electrode and the fourth pixel electrode may be electrically connected to each other.

[00022] An emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel may be the same.

[00023] Each of the first subpixel, the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel may include a light emitting device and a subpixel circuit for driving the light emitting device. The subpixel circuit may include two or more transistors.

[00024] The fourth subpixel may include a light emitting device, but may not include a subpixel circuit. In this case, the light emitting device of the fourth subpixel may be driven by a subpixel circuit of the third subpixel.

[00025] A driving current output from the subpixel circuit of the third subpixel may be supplied to the third pixel electrode and the fourth pixel electrode.

[00026] The display device according to embodiments of the present disclosure may further include a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode.

[00027] The third pixel electrode, the connection line and the fourth pixel electrode may be integrated.

[00028] The plurality of pixel electrodes may include a seventh pixel electrode disposed in the upper area and included in a seventh subpixel, an eighth pixel electrode disposed in the second area and included in an eighth subpixel, and a ninth pixel electrode disposed in the lower area and included in the ninth subpixel.

[00029] The plurality of data lines may include a second data line connected to the seventh subpixel, the eighth subpixel and the ninth subpixel.

[00030] An emission color of each of the seventh subpixel, the eighth subpixel and the ninth subpixel may be different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel.

[00031] The second data line may intersect and overlap a portion (i.e., the connection line) in which the third pixel electrode and the fourth pixel electrode are connected.

[00032] For example, in the first area and the second area, the first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane.

[00033] As another example, the first data line and the second data line may be disposed in the same metal layer in the second area. The first data line and the second data line may be disposed on different metal layers in at least a partial area of the first area.

[00034] As an example, in the second area, the first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane. The first area may include a transmission area and a non-transmission area. The first data line and the second data line may be disposed in different metal layers and may overlap in a vertical direction in the transmission area. The first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane in the non-transmission area.

[00035] The display device according to embodiments of the present disclosure may further include an electronic device which is located below the substrate, overlaps with the first area, and perform a predetermined operation using light passing through the first area.

[00036] Embodiments of the present disclosure may provide a display device includubg a substrate including a display area capable of displaying an image and a nondisplay area outside the display area, a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels .

[00037] The display area may include a first area capable of transmitting light and a second area located outside the first area.

[00038] The second area may include an upper area above the first area and a lower area under the first area.

[00039] The plurality of pixel electrodes may include a first pixel electrode disposed in the upper area and included in a first subpixel, a second pixel electrode disposed in the upper area and included in a second subpixel, a third pixel electrode disposed in the first area and included in a third subpixel, a fourth pixel electrode disposed in the first area and included in a fourth subpixel, a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel.

[00040] The plurality of data lines may include a first data line extending from the upper area, passing through the first area to the lower area, and connected to the first subpixel, the third subpixel, and the fifth subpixel, an upper data line disposed in the upper area and connected to the second subpixel, and a lower data line disposed in the lower area and connected to the sixth subpixel.

[00041] The third pixel electrode and the fourth pixel electrode may be electrically connected to each other.

[00042] The display device according to embodiments of the present disclosure may further include a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode.

[00043] According to the embodiments of the present disclosure, there may provide a display device having a light-transmitting structure which allows an electronic device to normally receive light (e.g., visible light, infrared light, or ultraviolet light) without exposing the electronic device receiving light to the front.

[00044] According to the embodiments of the present disclosure, there may provide a display device capable of improving the transmittance of an optical area (i.e, a first area) through which light can pass through.

[00045] According to the embodiments of the present disclosure, there may provide a display device having a structure to reduce the metal ratio in an optical area (i.e., a first area) through which light can be transmitted.

[00046] According to the embodiments of the present disclosure, there may provide a display device having a panel structure capable of improving a detection performance of a detection sensor using light passing through an optical area (i.e., a first area).

[00047] According to the embodiments of the present disclosure, there may provide a display device having a panel structure capable of improving a performance of a camera using light passing through an optical area (i.e., a first area).

[00048] The effects of the present disclosure are not limited to the effects described above, and other effects not described will be clearly understood by those skilled in the art from the description below. BRIEF DESCRIPTION OF THE DRAWINGS

[00049] FIGS. 1A, IB and IC illustrate display devices according to embodiments of the present disclosure. FIG. 2 illustrates a system configuration diagram of a display device according to embodiments of the present disclosure. FIG. 3 illustrates a display panel according to embodiments of the present disclosure. FIG. 4 illustrates a general area, a first optical area, and a second optical area in a display panel according to embodiments of the present disclosure. FIG. 5 illustrates signal lines arranged on a display panel according to embodiments of the present disclosure. FIGS. 6 and 7 are plan views of an optical area of the display panel according to embodiments of the present disclosure. FIGS. 8 and 9 are cross-sectional views of a partial area within the optical area of the display panel according to embodiments of the present disclosure. FIG. 10 illustrates signal strength when receiving and processing light passing through an optical area of a display panel according to embodiments of the present disclosure. FIG. 11 is a plan view of a display panel according to embodiments of the present disclosure. FIGS. 12 and 13 are plan views of a partial area within an optical area of a display panel according to embodiments of the present disclosure. FIGS. 14 to 18 are cross-sectional views of partial areas of FIGS. 12 and 13. FIG. 19 is a cross-sectional view of a connection area between a vertical bypass line and a horizontal bypass line in a display panel according to embodiments of the present disclosure. DETAILED DESCRIPTION

[00050] Hereinafter, embodiments of the disclosure are described in detail with reference to the accompanying drawings. In assigning reference numerals to components of each drawing, the same components may be assigned the same numerals even when they are shown on different drawings. When determined to make the subject matter of the disclosure unclear, the detailed of the known art or functions may be skipped. As used herein, when a component "includes," "has," or "is composed of" another component, the component may add other components unless the component "only" includes, has, or is composed of" the other component. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[00051] Such denotations as "first," "second," "A," "B," "(a)," and "(b)," may be used in describing the components of the disclosure. These denotations are provided merely to distinguish a component from another, and the essence, order, or number of the components are not limited by the denotations.

[00052] In describing the positional relationship between components, when two or more components are described as "connected", "coupled" or "linked", the two or more components may be directly "connected", "coupled" or "linked" ", or another component may intervene. Here, the other component may be included in one or more of the two or more components that are "connected", "coupled" or "linked" to each other.

[00053] When such terms as, e.g., "after", "next to", "after", and "before", are used to describe the temporal flow relationship related to components, operation methods, and fabricating methods, it may include a non-continuous relationship unless the term "immediately" or "directly" is used.

[00054] When a component is designated with a value or its corresponding information (e.g., level), the value or the corresponding information may be interpreted as including a tolerance that may arise due to various factors (e.g., process factors, internal or external impacts, or noise).

[00055] Hereinafter, various embodiments of the disclosure are described in detail with reference to the accompanying drawings .

[00056] FIGS. 1A, IB and IC illustrate a display device 100 according to embodiments of the present disclosure.

[00057] Referring to FIGS. 1A, IB and IC, a display device 100 according to embodiments of the present disclosure may include a display panel 110 which displays an image and one or more electronic devices 11 and 12.

[00058] The display panel 110 may include a display area DA where an image is displayed and a nondisplay area NDA where an image is not displayed. A plurality of subpixels and a plurality of signal lines for driving the plurality of subpixels may be disposed in the display area DA. The non-display area NDA may be an area outside the display area DA. Various signal lines may be disposed in the non-display area NDA, and various driving circuits may be connected to the non-display area NDA. The non-display area NDA may be bent so that it is not visible from the front or may be obscured by a case (not shown) . The non-display area NDA may be also referred as a bezel or a bezel area.

[00059] The display device 100 according to embodiments of the present disclosure may include one or more electronic devices 11 and 12 located below the display panel 110 (i.e., opposite the viewing surface). Here, one or more electronic devices 11 and 12 may be provided separately from the display panel 110.

[00060] One or more electronic devices 11 and 12 may be devices which receive light passing through the display panel 110 and perform a predetermined operation using the received light.

[00061] For example, the one or more electronic devices 11 and 12 may include one or more of a photographing device such as a camera (i.e., image sensor), a detection sensor such as a proximity sensor, and an illuminance sensor. Here, for example, the detection sensor may be an infrared sensor.

[00062] Light required for the operation of one or more electronic devices 11 and 12 may enter the front side (i.e., viewing side) of the display panel 110, pass through the display panel 110, and may be transmitted to one or more electronic devices 11 and 12 located below the display panel 110 (i.e., opposite the viewing surface). For example, light required for the operation of one or more electronic devices 11 and 12 and passing through the display panel 110 may include one or more of visible light, infrared light, and ultraviolet light.

[00063] Referring to FIGS. 1A, IB, and IC, in the display panel 110 according to embodiments of the present disclosure, the display area DA may include a general area NA and one or more optical areas OA1 and OA2. One or more optical areas OA1 and OA2 may be areas which overlap with one or more electronic devices 11 and 12.

[00064] According to the example of FIG. 1A, the display area DA may include a general area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11.

[00065] According to the example of FIG. IB, the display area DA may include a general area NA, a first optical area 0A1, and a second optical area 0A2. In the example of FIG. IB, the general area NA may exist between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area 0A1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[00066] According to the example of FIG. IC, the display area DA may include a general area NA, a first optical area 0A1, and a second optical area 0A2. In the example of FIG. IC, the general area NA may not exist between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 may be in contact with each other. Here, at least a portion of the first optical area 0A1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[00067] One or more optical areas 0A1 and 0A2 are required to include both an image display structure and a light transmission structure. That is, since one or more optical areas OA1 and OA2 are part of the display area DA, light emitting areas of subpixels for image display are required to be disposed in the one or more optical areas 0A1 and OA2 . Additionally, a light transmission structure is required to be formed in one or more optical areas OA1 and OA2 to transmit light to one or more electronic devices 11 and 12.

[00068] One or more electronic devices 11 and 12 may be located behind (i.e., below or opposite to the viewing surface) the display panel 110 and receive light passing through the display panel 110.

[00069] One or more electronic devices 11 and 12 may be not exposed to the front (i.e., viewing side) of the display panel 110. Accordingly, when the user looks at the front of the display device 110, the electronic devices 11 and 12 may be not visible to the user.

[00070] For example, a first electronic device 11 may be a camera which receives light (e.g., visible light) in the visible light wavelength band, and a second electronic device 12 may be a detection sensor such as a proximity sensor or illuminance sensor. For example, the detection sensor may be an infrared sensor for detecting light (e.g., infrared rays) in the infrared wavelength band. Alternatively, the first electronic device 11 may be a detection sensor, and the second electronic device 12 may be a camera.

[00071] Hereinafter, for convenience of explanation, there is exemplified a case in which the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based detection sensor. Here, the camera may be a camera lens or an image sensor.

[00072] In the case that the first electronic device 11 is a camera, the camera may be located behind (i.e., below) the display panel 110, but may be a front camera for photographing the front direction of the display panel 110. Accordingly, the user may view a viewing surface of the display panel 110 and take pictures (self-photographs) using a camera which is not visible to the viewing surface.

[00073] The general area NA and one or more optical areas 0A1 and OA2 included in the display area DA may be areas where an image can be displayed. However, the general area NA may be an area in which a light transmission structure does not need to be formed, and one or more optical areas OA1 and OA2 may be areas in which a light transmission structure is required to be formed.

[00074] Therefore, one or more optical areas OA1 and OA2 are required to have transmittance above a specific level, and the general area NA may not have light transmittance or may have low transmittance below a specific level.

[00075] For example, one or more optical areas OA1 and OA2 and the general area NA may have different resolutions, subpixel arrangement structures, number of subpixels per unit area, electrode structures, line structures, electrode arrangement structures, or line arrangement structures etc.

[00076] For example, the number of subpixels per unit area in one or more optical areas OA1 and 0A2 may be smaller than the number of subpixels per unit area in the general area NA. That is, the resolution of one or more optical areas OA1 and OA2 may be lower than the resolution of the general area NA. Here, the number of subpixels per unit area may mean the same as resolution, pixel density, or pixel integration. For example, a unit of the number of subpixels per unit area may be PPI (Pixels Per Inch) , which means the number of pixels in 1 inch.

[00077] For example, the number of subpixels per unit area in the first optical area OA1 may be less than the number of subpixels per unit area in the general area NA. The number of subpixels per unit area in the second optical area OA2 may be greater than or equal to the number of subpixels per unit area in the first optical area OA1, and may be less than the number of subpixels per unit area in the general area NA.

[00078] Meanwhile, as a method to increase the transmittance of at least one of the first optical area OA1 and the second optical area OA2, there may be applied a differential pixel density design method, as described above. According to the differential pixel density design method, the display panel 110 may be designed so as for the number of subpixels per unit area of at least one of the first optical area OA1 and the second optical area OA2 to be less than the number of subpixels per unit area of the general area NA.

[00079] However, in some cases, a differential pixel size design method may be applied as another method to increase the transmittance of at least one of the first optical area 0A1 and the second optical area OA2. According to the differential pixel size design method, the display panel 110 may be designed so as for the number of subpixels per unit area of at least one of the first optical area OA1 and the second optical area OA2 to be the same as or similar to the number of subpixels per unit area of the general area NA, but for a size of each subpixel SP (i.e., the size of the light emitting area) disposed in at least one of the first optical area OA1 and the second optical area OA2 to be smaller than the size of each subpixel SP (i.e., the size of the light emitting area)placed in the general area NA.

[00080] Hereinafter, for convenience of explanation, it will be described by assuming that the differential pixel density design method is applied among two methods (differential pixel density design method, differential pixel size design method) for increasing the transmittance of at least one of the first optical area OA1 and the second optical area OA2. Accordingly, hereinafter, a small number of subpixels per unit area may be an expression corresponding to a small subpixel size, and a large number of subpixels per unit area may be an expression corresponding to a large subpixel size.

[00081] The first optical area OA1 may have various shapes such as circular, oval, square, hexagon, or octagon. The second optical area OA2 may have various shapes, such as circular, oval, square, hexagon, or octagon. The first optical area OA1 and the second optical area OA2 may have the same shape or different shapes.

[00082] Referring to FIG. IC, in the case that the first optical area 0A1 and the second optical area 0A2 are in contact, the entire optical area including the first optical area OA1 and the second optical area OA2 may also have various shapes, such as circular, oval, square, hexagon, or octagon. Hereinafter, for convenience of explanation, it will be exemplified a case in which each of the first optical area 0A1 and the second optical area 0A2 has a circular shape.

[00083] In the display device 100 according to the embodiments of the present disclosure, if the first electronic device 11, which is not exposed to the outside and is hidden at the bottom of the display panel 100, is a camera, a display device 100 according to embodiments of the present disclosure may be referred as a display device to which UDC (Under Display Camera) technology is applied.

[00084] Accordingly, in the display device 100 according to embodiments of the present disclosure, there may not be required to be formed a notch or camera hole for camera exposure in the display panel 110, so that there is no reduction in area of the display area DA. Accordingly, since a notch or camera hole for camera exposure does not need to be formed in the display panel 110, the size of the bezel area may be reduced, design restrictions may be eliminated, and the degree of freedom in design may be increased.

[00085] In the display device 100 according to embodiments of the present disclosure, although the one or more electronic devices 11 and 12 are hidden behind the display panel 110, the one or more electronic devices 11 and 12 are required to be able to receive light normally and normally perform a designated function thereof.

[00086] In addition, in the display device 100 according to embodiments of the present disclosure, although the one or more electronic devices 11 and 12 are hidden behind the display panel 110 and are located overlapping with the display area DA, there is required that the normal image display function is possible in one or more optical areas OA1 and OA2 overlapping with one or more electronic devices 11 and 12 in the display area DA.

[00087] Since the above-mentioned first optical area OA1 is designed as a transmissive area, a image display characteristics in the first optical area OA1 may be different from those in the general area NA.

[00088] In addition, when designing the first optical area OA1 to improve image display characteristics, there is a possibility that the transmittance of the first optical area OA1 may decrease.

[00089] Therefore, embodiments of the present disclosure may provide a structure of the first optical area OA1 capable of improving the transmittance in the first optical area OA1 while preventing image quality deviation between the first optical area OA1 and the general area NA.

[00090] In addition, embodiments of the present disclosure may provide, for the second optical area OA2 in addition to the first optical area 0A1, a structure of the second optical area OA2 capable of improving the image quality and the transmittance in the second optical area OA2 .

[00091] In addition, in the display device 100 according to embodiments of the present disclosure, the first optical area OA1 and the second optical area OA2 are similar in that they are light-transmission areas, but the usage examples thereof may be different from each other.

[00092] Therefore, in the display device 100 according to embodiments of the present disclosure, the structure of the first optical area OA1 and the structure of the second optical area OA2 are basically similar or the same, but a resolution, a subpixel arrangement structure, the number of subpixels per unit area, a electrode structure, a line structure, a electrode arrangement structure or a line arrangement structure thereof may be different from each other.

[00093] FIG. 2 illustrates a system configuration diagram of a display device 100 according to embodiments of the present disclosure.

[00094] Referring to FIG. 2, the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may be a circuit for driving the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230 and a display controller 240.

[00095] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA where an image is not displayed. The non-display area NDA may be an area outside the display area DA, and may also be referred to as a bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or may be an area which is bent and not visible from the front of the display device 100.

[00096] The display panel 110 may include a substrate SUB and a plurality of subpixels SP disposed on the substrate SUB. Additionally, the display panel 110 may further include various types of signal lines to drive the plurality of subpixels SP.

[00097] The display device 100 according to embodiments of the present disclosure may be a liquid crystal display device or the like, or may be a self-luminous display device in which the display panel 110 emits light on its own. When the display device 100 according to embodiments of the present disclosure is a self-luminous display device, each of the plurality of subpixels SP may include a light emitting device. For example, the display device 100 according to embodiments of the present disclosure may be an organic light emitting display device in which a light emitting device is implemented as an organic light emitting diode (OLED). For another example, the display device 100 according to embodiments of the present disclosure may be an inorganic light emitting display device in which the light emitting device is implemented as an inorganic-based light emitting diode. For another example, the display device 100 according to embodiments of the present disclosure may be a quantum dot display device in which a light emitting device is implemented with quantum dots, which are self-luminous semiconductor crystals.

[00098] The structure of each of the plurality of subpixels SP may vary depending on the type of the display device 100. For example, if the display device 100 is a self-luminous display device in which subpixels SP emit light by themselves, each subpixel SP may include a light emitting device emitting light by itself, one or more transistors, and one or more capacitors.

[00099] For example, various types of signal lines may include a plurality of data lines DL transmitting data signals (also called data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also called scan signals). [000100] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction and the second direction may be a row direction. Alternatively, the first direction may be a row direction and the second direction may be a column direction. Hereinafter, for convenience of explanation, it will be exemplified a case in which each of the plurality of data lines DL is arranged in a column direction, and each of the plurality of gate lines GL is arranged in a row direction. [000101] The data driving circuit 220 is a circuit for driving a plurality of data lines DL and connecting the the plurality of data lines DL, and may output data signals to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving a plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL. [000102] The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230, and may control the driving timing for the plurality of data lines DL and the driving timing of the plurality of gate lines GL. [000103] The display controller 240 may supply a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and may supply a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230. [000104] The display controller 240 may receive input image data from a host system 250 and supply image data to the data driving circuit 22 0 based on the input image data. [000105] The data driving circuit 220 may receive image data in digital form from the display controller 240 and convert the received image data into analog data signals to output to a plurality of data ines DL. [000106] The gate driving circuit 230 may receive a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage along with various gate driving control signals GCS, and may generate gate signals and supply the generated gate signals to the plurality of gate lines GL. [000107] For example, the data driving circuit 220 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on panel (COP) method, or may be implemented using a chip-on-film (COF) method and connected to the display panel 110. [000108] The gate driving circuit 230 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method, or may be implemented using a chip-on-film (COF) method and connected to the display panel 110. Alternatively, the gate driving circuit 230 may be a gate in panel (GIP) type and may be formed in the non-display area NDA of the display panel 110. The gate driving circuit 230 may be disposed on or connected to the substrate. That is, if the gate driving circuit 230 is a GIP type, the gate driving circuit 230 may be disposed in the non-display area NDA of the substrate. The gate driving circuit 230 may be connected to the substrate if the gate driving circuit 230 is a chip-on-glass (COG) type, a chip-on-film (COF) type, etc. [000109] Meanwhile, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be arranged not to overlap the subpixels SP, or may be arranged to partially or entirely overlap with the subpixels SP. [000110] The data driving circuit 220 may be connected to one side (e.g., the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. [000111] The gate driving circuit 230 may be connected to one side (e.g., left or right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be connected to both sides (e.g., left and right side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110. [000112] The display controller 240 may be implemented as a separate component from the data driving circuit 220, or may be integrated with the data driving circuit 220 and implemented as an integrated circuit. [000113] The display controller 240 may be a timing controller used in typical display technology, or may be a control device capable of further performing other control functions including a timing controller, or may be a control device different from the timing controller, or may be a control device other than a timing controller, or may be a circuit within the control device. The display controller 240 may be implemented with various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or Processor. [000114] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 220 and the gate driving circuit 230 through a printed circuit board, a flexible printed circuit. [000115] The display controller 240 may transmit and receive signals with the data driving circuit 220 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), or a serial peripheral interface (SPI). [000116] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to embodiments of the present disclosure may include a touch sensor and a touch sensing circuit for detecting an occurrenace of a touch by a touch object such as a finger or pen or detection a touch position by sensing the touch sensor. [000117] The touch sensing circuit may include a touch driving circuit 260 for driving and sensing a touch sensor to generate and output touch sensing data, and a touch controller 270 for detecting the occurrence of a touch or detecting the touch position using touch sensing data. [000118] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines to electrically connect a plurality of touch electrodes and the touch driving circuit 260. [000119] The touch sensor may exist outside the display panel 110 in the form of a touch panel or may exist inside the display panel 110. If the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. If the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate. [000120] If the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate SUB along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110. [000121] The touch driving circuit 260 may supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes. [000122] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method. [000123] If the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., finger, pen, etc.). According to the selfcapacitance sensing method, each of the plurality of touch electrodes may serve as a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 may drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes. [000124] If the touch sensing circuit performs touch sensing using the mutual-capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual-capacitance sensing method, the plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 may drive driving touch electrodes and sense sensing touch electrodes. [000125] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as one device. Additionally, the touch driving circuit 260 and the data driving circuit 220 may be implemented as separate devices or as one device. [000126] The display device 100 may further include a power supply circuit which supplies various types of power to the display driving circuit and / or the touch sensing circuit. [000127] The display device 100 according to embodiments of the present disclosure may be a mobile terminal such as a smart phone or tablet, or a monitor or television of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images. [000128] As described above, in the display panel 110, the display area DA may include a general area NA and one or more optical areas OA1 and OA2. The general area NA and one or more optical areas OA1 and OA2 may be areas in which images can be displayed. However, the general area NA may be an area in which a light transmission structure does not need to be formed, and the one or more optical areas OA1 and OA2 may be areas in which a light transmission structure needs to be formed. [000129] As described above, the display area DA in the display panel 110 may include one or more optical areas OA1 and OA2 along with the general area NA. However, for convenience of explanation, it is assumed that the display area DA includes both the first optical area OA1 and the second optical area OA2 (FIGS. IB and IC). [000130] FIG. 3 illustrates a display panel 110 according to embodiments of the present disclosure. [000131] Referring to FIG. 3, a plurality of subpixels SP may be disposed in the display area DA of the display panel 110. A plurality of subpixels SP may be disposed in the general area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA. [000132] Referring to FIG. 3, each of the plurality of subpixels SP may include a light emitting device ED and a subpixel circuit SPC configured to drive the light emitting device ED. [000133] Referring to FIG. 3, the subpixel circuit SPC may include a driving transistor DT for driving the light emitting device ED, a scan transistor ST for transferring the data voltage VDATA to the driving transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame. [000134] The driving transistor DT may include a first node Nl, a second node N2, and a third node N3. [000135] The first node Nl may be electrically connected to the light emitting device ED. The second node N2 may be connected to the scan transistor ST. The third node N3 may be connected to a driving voltage line VDDL. [000136] The first node Nl may be electrically connected to the pixel electrode PE of the light emitting device ED. The data voltage VDATA may be applied to the second node N2. A driving voltage VDD may be applied to the third node N3. [000137] The first node Nl may be a source node or a drain node, the second node N2 may be a gate node, and the third node N3 may be a drain node or a source node. Hereinafter, for convenience of explanation, in the driving transistor DT, it will be exemplified a case in which the first node Nl is a source node, the second node N2 is a gate node, and the third node N3 is a drain node. [000138] The light emitting device ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. [000139] The pixel electrode PE may be an electrode disposed in each subpixel SP. For example, the pixel electrode PE may be electrically connected directly or indirectly (via another transistor) to the first node N1 of the driving transistor DT of each subpixel SP. [000140] The common electrode CE may be an electrode commonly disposed in the plurality of subpixels SP. For example, the common electrode CE may be electrically connected to a base voltage line VSSL. A base voltage VSS, which is a type of common driving voltage, may be applied to the common electrode CE through the base voltage line VSSL. [000141] For example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Alternatively, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode. Hereinafter, for convenience of explanation, it is assumed that the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode. [000142] The intermediate layer EL may include an emission layer EML and a common intermediate layer EL_COM. [000143] For example, the emission layer EML may be disposed in each of the plurality of subpixels SP, or in another example, may be commonly disposed in the plurality of subpixels SP. The common intermediate layer EL COM may be commonly disposed across the plurality of subpixels SP. [000144] The emission layer EML may be disposed in each emission area EA, and the common intermediate layer EL_COM may be commonly disposed across the plurality of emission areas EA and the non-emission area. [000145] The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 may be disposed between the pixel electrode PE and the emission layer EML, and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 may be disposed between the emission layer EML and the common electrode CE, and may include at least one layer (e.g., an organic layer). [000146] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transfer layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL, an electron injection layer EIL, and the like. [000147] The hole injection layer may inject holes from the pixel electrode PE to the hole transport layer, the hole transport layer may transport holes to the emission layer EML, and the electron injection layer may inject electrons from the common electrode CE to the electron transport layer, and the electron transport layer may transport electrons to the emission layer EML. [000148] Each light emitting device ED may include an overlapping portion of a pixel electrode PE, an emission layer EML in the intermediate layer EL, and a common electrode CE. A predetermined emission area EA may be formed by each light emitting device ED. For example, the emission area EA may be defined as an area where the pixel electrode PE, the emission layer EML in the intermediate layer EL, and the common electrode CE overlap. [000149] For example, the light emitting device ED may be an organic light emitting diode (OLED) based on organic materials, an inorganic light emitting diode based on inorganic materials, or a quantum dot light emitting device, in the case that the light emitting device ED is an organic light emitting diode, the intermediate layer EL in the light emitting device ED may include an organic layer containing an organic material. [000150] The scan transistor ST may be controlled on-off by a scan signal SC as a type of gate signal applied through the scan signal line SCL as a type of gate line GL, and may be electrically connected between the second node N2 of the driving transistor DT and the data line DL. [000151] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. [000152] The subpixel circuit SPC may have a 2T (Transistor)-IC (Capacitor) structure including two transistors DT and ST and one capacitor Cst, as shown in FIG. 3, and may further include one or more transistors or one or more capacitors in some case. [000153] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT rather than a parasitic capacitor (e.g., Cgs, Cgd) as an internal capacitor which may exist between the first node N1 and the second node N2 of the driving transistor DT. Each of the driving transistor DT and scan transistor ST may be an n-type transistor or a p-type transistor. [000154] The circuit elements within each subpixel SP (in particular, light emitting devices EDs implemented with organic light emitting diodes (OLEDs) containing organic materials) may be vulnerable to external moisture or oxygen. Therefore, there may be disposed an encapsulation layer ENCAP on the display panel 110 to prevent oxygen from penetrating into the circuit elements (particularly, the light emitting device ED) . The encapsulation layer ENCAP may be disposed to cover the light emitting devices ED. [000155] Referring to FIG. 3, the display device 100 according to embodiments of the present disclosure may include, in order to sense the user’s touch, a touch sensor layer TSL including a plurality of sensor electrodes, a touch driving circuit 260 configured to sense a plurality of sensor electrodes, and a touch controller 270 configured to determine the presence or absence of a touch or touch coordinates using the sensing result (i.e., touch sensing data) of the touch driving circuit 260. [000156] The touch sensor layer TSL may be embedded into the display panel 110. For example, the touch sensor layer TSL may be disposed on the encapsulation layer ENCAP within the display panel 110. [000157] The display panel 110 may further include a plurality of touch pads TP electrically connected to the touch driving circuit 260, and a plurality of touch routing lines TL for electrically connecting a plurality of sensor electrodes included in the touch sensor layer TSL to a plurality of touch pads TP connected to the touch driving circuit 260. [000158] FIG. 4 illustrates a general area NA, a first optical area 0A1, and a second optical area OA2 in a display panel 110 according to embodiments of the present disclosure. [000159] Referring to FIG. 4, the display panel 110 according to embodiments of the present disclosure may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The display area DA may include a first optical area OA1, a second optical area OA2, and a general area NA. [000160] Since the first optical area 0A1, the second optical area OA2, and the general area NA are included in the display area DA, they may have a display structure. For example, each of the first optical area OA1, the second optical area OA2 and the general area NA may include a plurality of emission areas EA. [000161] In addition, the first optical area OA1 and the second optical area OA2 may be areas through which light can be transmitted, and the general area NA may be an area through which light cannot be transmitted or where light transmission is minimal. The general area NA may refer to an area through which light cannot be transmitted, excluding the first optical area OA1 and the second optical area OA2. Here, the light transmission may mean that light passes between the front and back surfaces of the display panel 110. [000162] The first optical area OA1 may be an area which overlaps with the first electronic device 11. The second optical area OA2 may be an area which overlaps the second electronic device 12. [000163] Each of the first optical area 0A1 and the second optical area OA2 may have a light transmission structure. However, the first optical area OA1 and the second optical area OA2 may have different structural characteristics. For example, the transmittance of the first optical area OA1 may be higher than the transmittance of the second optical area OA2. The resolution or the number of subpixels per unit area of the first optical area OA1 may be lower or smaller than the resolution or the number of subpixels per unit area of the second optical area OA2. [000164] The first electronic device 11 may perform a predetermined operation using light in a first wavelength band among the light passing through the first optical area 0A1. The second electronic device 12 may perform a predetermined operation using light in a second wavelength band different from the first wavelength band among the light transmitting through the second optical area OA2. [000165] The first wavelength band may include one or more of a visible light wavelength band, an infrared wavelength band, and an ultraviolet wavelength band. The second wavelength band includes one or more of a visible light wavelength band, an infrared wavelength band, and an ultraviolet wavelength band, but may be different from the first wavelength band. [000166] For example, the first electronic device 11 may be a camera and the second electronic device 12 may be a detection sensor. The first electronic device 11 may perform a camera operation using light in the visible light wavelength band corresponding to the first wavelength band among the light passing through the first optical area OA1. The second electronic device 12 may perform a sensing operation using light in an infrared wavelength band corresponding to the second wavelength band among the light transmitting through the second optical area OA2 . [000167] Referring to FIG. 4, each of the first optical area OA1 and the second optical area 0A2 may be circular or octagonal. However, the present disclosure is not limited thereto, each of the first optical area OA1 and the second optical area OA2 may have various shapes, such as an elliptical or oval shape, a polygonal shape, or an irregular shape. [000168] The first optical area OA1 and the second optical area OA2 may have the same shape. Alternatively, the first optical area OA1 and the second optical area OA2 may have different shapes. [000169] Referring to FIG. 4, the display area DA may include a plurality of emission areas EA. Since the general area NA, the first optical area OA1 and the second optical area OA2 are areas included in the display area DA, each of the general area NA, first optical area OA1 and second optical area OA2 may include a plurality of emission areas EA. [000170] The plurality of emission areas EA may include emission areas emitting light of three or more colors. For example, the plurality of emission areas EA may include a first color emission area emitting first color light, a second color emission area that emitting second color light, and a third color emission area emitting third color light. [000171] For example, if the first color light is red light, the second color light is green light, and the third color light is blue light, the first color emission area may be referred to as a red emission area EA_R, the second color emission area may be referred to as a green emission area EA_G, and the third color emission area may be referred to as a blue emission area EA_B. [000172] The red emission area EA_R, green emission area EA^G and blue emission area EA^B may have the same size (i.e., emission area size). Alternatively, at least one of the red emission area EA R, green emission area EA_G and blue emission area EA_B may have a size (i.e., emission area size) different from the others. [000173] As described above, the first color, second color, and third color may be different colors, and may be various colors. For example, the first color, second color and third color may be red, green and blue, respectively. Hereinafter, for convenience of explanation, it will be exemplified a case in which the first color is red, the second color is green, and the third color is blue, However, is not limited thereto. [000174] In the case that the first color is red, the second color is green, and the third color is blue, the size of the blue emission area EA^B (i.e., emission area size) may be the largest among the size of the red emission area EA_R (i.e., emission area size), the size of the green emission area EA_G (i.e., emission area size), and the size of the blue emission area EA^B (i.e., emission area size). [000175] The light emitting device ED disposed in the red emission area EA_R may include an emission layer EML emitting red light. The light emitting device ED disposed in the green emission area EA_G may include an emission layer EML emitting green light. The light emitting device ED disposed in the blue emission area EA_B may include an emission layer EML emitting blue light. [000176] Among the emission layer EML emitting red light, the emission layer EML emitting green light, and the emission layer EML emitting blue light, the organic material contained in the emission layer EML emitting blue light may be the most susceptible to material deterioration. Accordingly, by designing the size of the blue emission area EA^B to be the largest, the current density supplied to the light emitting device ED disposed in the blue emission area EA B can be minimal. Therefore, the degree of deterioration of the light emitting device ED disposed in the blue emission area EA_B may become similar to the degree of deterioration of the light emitting device ED disposed in the red emission area EA^R and the light emitting device ED disposed in the green emission area EA_G. [000177] Therefore, there may be eliminated or reduced a deterioration variation between the light emitting device ED disposed in the red emission area EA_R, the light emitting device ED disposed in the green emission area EA_G, and the light emitting device ED disposed in the blue emission area EA_B, thereby improving image quality. [000178] Referring to FIG. 4, each of the plurality of first transmission areas TAI included in the first optical area OA1 may have various shapes such as circular, oval, polygonal, or irregular shapes. Each of the plurality of second transmission areas TA2 included in the second optical area OA2 may have various shapes, such as circular, oval, polygonal, or irregular shapes. [000179] The plurality of first transmission areas TAI may have the same shape. Alternatively, some of the plurality of first transmission areas TAI may have a shape different from the others. The plurality of second transmission areas TA2 may have the same shape. Alternatively, some of the plurality of second transmission areas TA2 may have a different shape from the others. [000180] The first transmission area TAI and the second transmission area TA2 may have the same shape. Alternatively, the first transmission area TAI and the second transmission area TA2 may have different shapes. [000181] Referring to FIG. 4, the general area NA may all correspond to a non-transmission area. That is, the general area NA may include a non-transmission area NTA including a plurality of emission areas EA. That is, the entire general area NA may be a non-transmission area NTA, and the general area NA may not include the transmission area TA. [000182] The first optical area OA1 may further include a non-transmission area NTA including a plurality of emission areas EA and a plurality of first transmission areas TAI. The non-transmission area NTA included in the first optical area OA1 may be an area through which no light is transmitted, or may be an area where light is transmitted with a lower transmittance than the first transmission area TAI. [000183] The second optical area OA2 may further include a non-transmission area NTA including a plurality of emission areas EA, and a plurality of second transmission areas TA2. The non-transmission area NTA included in the second optical area OA2 may be an area through which no light is transmitted, or may be an area through which light is transmitted with a lower transmittance than the second transmission area TA2. [000184] Meanwhile, the common electrode CE may include a plurality of common electrode holes CH corresponding to a plurality of openings. A plurality of common electrode holes CH may be formed in the first optical area OA1 and the second optical area OA2. That is, positions where the plurality of common electrode holes CH are formed may be the first optical area OA1 and the second optical area CA2. [000185] Referring to FIG. 4, the positions where the plurality of common electrode holes CH are formed in the common electrode CE may correspond to the plurality of first transmission areas TAI included in the first optical area OA1, respectively. In addition, positions where the plurality of common electrode holes CH are formed in the common electrode CE may respectively correspond to the plurality of second transmission areas TA2 included in the second optical area OA2. Accordingly, the transmittance of each of the first optical area OA1 and the second optical area OA2 may be improved. [000186] FIG. 5 illustrates signal lines SL arranged on a display panel 110 according to embodiments of the present disclosure. [000187] Referring to FIG. 5, the display panel 110 according to embodiments of the present disclosure may include a plurality of subpixels SP and a plurality of signal lines SL for driving the plurality of subpixels SP) . [000188] Referring to FIG. 5, each of the plurality of subpixels SP may include a light emitting device ED and a subpixel circuit SPC for driving the light emitting device ED. The emission area EA may be formed by the light emitting device ED. [000189] Referring to FIG. 5, the plurality of signal lines SL may supply various driving signals necessary for driving the plurality of subpixels SP to the plurality of subpixels SP. [000190] For example, various driving signals may include a data signal VDATA for driving the data line DL and a scan signal SC for driving the gate line GL. The various driving signals may further include a driving voltage VDD for driving the driving voltage line VDDL and a base voltage VSS for driving the base voltage line VSSL connected to the common electrode CE. [000191] Accordingly, the plurality of signal lines may include a plurality of data lines DL for supplying data signals VDATA and a plurality of gate lines GL for supplying gate signals such as scan signals SC. The plurality of signal lines may further include a driving voltage line VDDL for supplying the driving voltage VDD and a base voltage line VSSL for supplying the base voltage VSS. [000192] Referring to FIG. 5, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. [000193] Referring to FIG. 5, each of the general area NA, the first optical area 0A1 and the second optical area OA2 may include a plurality of emission areas EA. A plurality of light emitting devices ED and a plurality of subpixel circuits SPG may be disposed in each of the general area NA, the first optical area OA1 and the second optical area 0A2. [000194] Referring to FIG. 5, the plurality of signal lines SL may include a plurality of general signal lines SL_NA and a plurality of specific signal lines SL^OA. [000195] The plurality of general signal lines SL NA may be signal lines disposed only in the general area NA without passing through the first optical area OA1 and the second optical area OA2. [000196] The plurality of specific signal lines SL^OA may be signal lines passing through at least one of the first optical area OA1 and the second optical area OA2 . [000197] For example, a plurality of general signal lines SL^NAmay include a plurality of data lines DL^NA and a plurality of gate lines GL_NA which do not pass through the first optical area OA1 and the second optical area OA2 . [000198] For example, a plurality of specific signal lines SL^OA may include a plurality of data lines DL_0A and a plurality of gate lines DL_OA passing through at least one of the first optical area OA1 and the second optical area OA2. [000199] As described above, since the plurality of specific signal lines SL^OA pass through at least one of the first optical area OA1 and the second optical area OA2, the transmission characteristics of the first optical area OA1 and the second optical area OA2 may be influenced by a plurality of specific signal lines SL^OA. [000200] Meanwhile, positions where the plurality of common electrode holes CH are formed in the common electrode CE may respectively correspond to the plurality of first transmission areas TAI included in the first optical area 0A1. In addition, positions where the plurality of common electrode holes CH are formed in the common electrode CE may respectively correspond to the plurality of second transmission areas TA2 included in the second optical area OA2. Accordingly, the transmittance of each of the first optical area 0A1 and the second optical area OA2 may be improved. [000201] In order to further increase the transmittance of the first optical area OA1, when the plurality of specific signal lines SL_OA pass through the first optical area 0A1, the plurality of specific signal lines SL^OA may be arranged to bypass the plurality of common electrode holes CH corresponding to the plurality of first transmission areas TAI. Similarly, in order to further increase the transmittance of the second optical area OA2, when the plurality of specific signal lines SL^OA pass through the second optical area 0A2, the plurality of specific signal lines SL_OA may be arranged to bypass the plurality of common electrode holes CH corresponding to the plurality of second transmission 3I7G8.S TA2 « [000202] In this case, a plurality of specific signal lines SL OA passing through at least one of the first optical area OA1 and the second optical area OA2 may have a line length greater than the plurality of general signal lines SL^NA which do not pass through the first optical area 0A1 and the second optical area 0A2. [000203] Accordingly, the plurality of specific signal lines SL_OA and the plurality of general signal lines SL_NA may have different electrical characteristics (e.g., different line resistance, different signal transmission delays, etc.). As a result, the driving characteristics between the subpixels SP connected to the plurality of specific signal lines SL_OA and the subpixels SP connected to the plurality of general signal lines SL_NA may become different, which may cause deterioration in image quality. [000204] Meanwhile, when manufacturing the display panel 110, there may be performed a process for patterning the common electrode CE having a plurality of common electrode holes CH. In this case, if a change in the patterning process of the common electrode CE occurs, the transmittance of the plurality of common electrode holes CH of the common electrode CE may change, and there may occur the transmittance difference between the plurality of common electrode holes CH. [000205] Accordingly, the display panel 110 according to embodiments of the present disclosure may have a line characteristic deviation reduction structure. [000206] According to the line characteristic deviation reduction structure according to embodiments of the present disclosure, there may be reduced a deviation in electrical characteristics (e.g., deviation in line resistance, deviation in signal transmission delay, etc.) between the plurality of specific signal lines SL_OA passing through at least one of the first optical area OA1 and the second optical area OA2 and the plurality of general signal lines SL_NA which do not pass through the first optical area OA1 and the second optical area OA2. [000207] In addition, the display panel 110 according to embodiments of the present disclosure may have a structure to reduce the range of transmittance variation. [000208] According to the structure for reducing the transmittance variation range according to the embodiments of the present disclosure, the transmittance variation range between the plurality of common electrode holes CH may be reduced even if process change occurs. Here, the plurality of common electrode holes CH may correspond to a plurality of first transmission areas TAI in the first optical area 0A1 or a plurality of second transmission areas TA2 in the second optical area OA2, respectively. [000209] Hereinafter, for convenience of explanation, the first optical area OA1 and the second optical area 0A2 are referred to as an optical area OA, and the first transmission area TAI in the first optical area OA1 and the second transmission area TA2 in the second optical area OA2 are referred to as a transmission area TA. [000210] Hereinafter, it will be described a structure for improving the transmission characteristics of the optical area OA of the display panel 110 according to embodiments of the present disclosure with reference to a plurality of exemplary drawings. [000211] FIGS. 6 and 7 are plan views of an optical area OA of the display panel 110 according to embodiments of the present disclosure. [000212] The display panel 110 according to embodiments of the present disclosure may include a substrate SUB including a display area DA on which an image is displayed, a plurality of signal lines SL disposed on the substrate SUB, and a common electrode CE disposed on the substrate SUB. [000213] The display area DA may include an optical area OA through which light is transmitted and a general area NA located outside the optical area OA. The general area NA may include a plurality of emission areas EA. [000214] The optical area OA may include a plurality of transmission areas TA and a non-transmission area NTA excluding the plurality of transmission areas TA. [000215] The non-transmission area NTA included in the optical area OA may include a plurality of emission areas EA formed by a plurality of light emitting device ED. Additionally, a plurality of subpixel circuits SPC may be disposed in the non-transmission area NTA included in the optical area OA. [000216] The common electrode CE may include a plurality of common electrode holes CH. The location where the plurality of common electrode holes CH are formed may be the optical area OA. That is, a plurality of common electrode holes CH may exist in the optical area OA. [000217] The plurality of common electrode holes CH may be positioned to respectively correspond to the plurality of transmission areas TA. [000218] As described above, the plurality of signal lines SL may include a plurality of general signal lines SL which do not pass through the optical area OA, and a plurality of specific signal lines SLjCA which pass through the optical area OA. [000219] For example, a plurality of specific signal lines SL_OA passing through the optical area OA may include a plurality of data lines DL. The plurality of specific signal lines SL^OA passing through the optical area OA may include a plurality of gate lines GL. [000220] Referring to FIG. 6, a plurality of data lines DL passing through the optical area OA may be arranged while bypassing a plurality of transmission areas TA. [000221] Accordingly, the transmittance of the optical area OA may be improved. [000222] Referring to FIG. 7, the plurality of data lines DL passing through the optical area OA may be disposed across at least one of the plurality of transmission areas TA without bypassing the plurality of transmission areas TA. [000223] Accordingly, the length deviation between the plurality of data lines DL passing through the optical area OA and the plurality of data lines DL not passing through the optical area OA may be reduced, so that the signal transmission characteristic deviation (i.e., line characteristic deviation) may be reduced. [000224] Referring to FIG. 7, each of the plurality of common electrode holes CH may overlap with the plurality of data lines DL passing through the optical area OA. [000225] Each of the plurality of common electrode holes CH illustrated in FIGS. 6 and 7 may be triangular. However, this only an example, and the common electrode hole CH may have various shapes. [000226] FIGS. 8 and 9 are cross-sectional views of a partial area within the optical area of the display panel according to embodiments of the present disclosure. FIG. 8 is a cross-sectional view taken along line A-B of FIG. 6, and FIG. 9 is a cross-sectional view taken along line C-D of FIG. 7. [000227] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may include a substrate SUB including a display area DA on which an image is displayed, a plurality of signal lines SL disposed on the substrate SUB, and a common electrode CE disposed on the substrate SUB. [000228] Referring to FIGS. 8 and 9, an optical area OA may include a plurality of emission areas EA and a plurality of transmission areas TA. [000229] Referring to FIGS. 8 and 9, the common electrode CE may include a plurality of common electrode holes CH. The plurality of common electrode holes CH may be positioned to respectively correspond to the plurality of transmission areas TA. [000230] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may include a pixel electrode PE disposed in one emission area EA among the plurality of emission areas EA included in the optical area OA, a driving transistor DT disposed in the optical area OA for supplying driving current to the pixel electrode PE, a capacitor Cst disposed in the optical area OA, a bank 833 disposed on the pixel electrode PE and having an opening, and an intermediate layer EL disposed between the bank 833 and the common electrode CE and located on a portion of the pixel electrode PE through the opening of the bank 833. [000231] Tin area where the pixel electrode PE, the intermediate layer EL and the common electrode CE overlap may constitute one light emitting device ED, and may correspond to one emission area EA. [000232] The driving transistor DT and the capacitor Cst may be disposed in a non-transmission area NTA other than the plurality of transmission areas TA within the optical area OA. [000233] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may further include a scan transistor ST disposed in an area other than the plurality of transmission areas TA within the optical area OA. [000234] Referring to FIGS. 8 and 9, the scan transistor ST may be connected to a data line DL, which is one of the plurality of specific signal lines SL_OA. [000235] Referring to FIGS. 8 and 9, the data line DL, which is a specific signal line SL_OA connected to the scan transistor ST among the plurality of specific signal lines SL_OA, may be disposed within a metal layer located between the source and drain electrodes of the driving transistor DT and the pixel electrode PE. [000236] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may further include an encapsulation layer ENCAP disposed on the common electrode CE, and a touch sensor metals TSM disposed on the encapsulation layer ENCAP and located in the general area NA and the optical area OA. [000237] Referring to FIGS. 8 and 9, the touch sensor metals TSM may overlap with the bank 833. Among the touch sensor metals TSM, the touch sensor metals TSM disposed in the optical area OA may be located in a nontransmission area NTA excluding the plurality of emission areas EA and the plurality of transmission areas TA within the optical area OA. [000238] Hereinafter, it will be described a vertical structure of the display panel 110 in more detail with reference to FIGS. 8 and 9. [000239] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may include a transistor forming portion, a light emitting device forming portion, and an encapsulation portion when viewed from a vertical structure, and may further include a touch sensor portion. [000240] Referring to FIGS. 8 and 9, the display panel 110 according to embodiments of the present disclosure may include a substrate SUB, a first buffer layer 811 on the substrate SUB, a first gate insulating layer 812 on the first buffer layer 811, a first interlayer insulating layer 813 on the first gate insulating layer 812, a second buffer layer 821 on the first interlayer insulating layer 813, a second gate insulating layer 822 on the second buffer layer 821, a second interlayer insulating layer 823 on the second gate insulating layer 822, a first planarization layer 831 on the second interlayer insulating layer 823, and a second planarization layer 832 on the first planarization layer 831. [000241] The display panel 110 according to embodiments of the present disclosure may further include a first gate metal layer located between the first gate insulating layer 812 and the first interlayer insulating layer 813, a first source-drain metal layer located between the second interlayer insulating layer 823 and the first planarization layer 831, and a second source-drain metal layer located between the first planarization layer 831 and the second planarization layer 832. [000242] The display panel 110 according to embodiments of the present disclosure may further include a second gate metal layer between the first interlayer insulating layer 813 and the second buffer layer 821, and a third gate metal layer between the second gate insulating layer 822 and the second interlayer insulating layer 823. [000243] The display panel 110 according to embodiments of the present disclosure may further includes a first active layer ACT1 between the first buffer layer 811 and the first gate insulating layer 812, and a second active layer ACT2 between the second buffer layer 821 and the second gate insulating layer 822. [000244] Referring to FIGS. 8 and 9, the transistor forming portion may include a substrate SUB, a first buffer layer 811 on the substrate SUB, and various transistors DT and ST, a storage capacitor Cst, and various electrodes or signal lines. [000245] Referring to FIGS. 8 and 9, the substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and may include an intermediate substrate layer IPD between the first substrate SUB1 and the second substrate SUB2. For example, each of the first substrate SUB1 and the second substrate SUB2 may include polyimide PI. For example, the intermediate substrate layer IPD may be an inorganic layer and may block moisture penetration. [000246] Referring to FIGS. 8 and 9, the first buffer layer 811 may be a single layer or a multi-layer. If the first buffer layer 811 is a multi-layer, the first buffer layer 811 may include a multi-buffer layer 811a and an active buffer layer 811b. [000247] The transistors DT and ST, the storage capacitors Cst, and various electrodes or signal lines may be formed on the first buffer layer 811. [000248] For example, the transistors DT and ST formed on the first buffer layer 811 may be made of the same material and may be located in the same layers. Alternatively, as shown in FIGS. 8 and 9, the driving transistor DT and the scan transistor ST may be made of different materials and located in different layers. [000249] Referring to FIGS. 8 and 9, the driving transistor DT, scan transistor ST, and storage capacitor Cst may be included in subpixel circuit SPG for driving the light emitting device ED included in the optical area OA. [000250] The scan transistor ST may include an active layer ACT1, a gate electrode GE1, a source electrode SEI, and a drain electrode DEI. [000251] The driving transistor DT may include an active layer ACT2, a gate electrode GE2, a source electrode SE2, and a second drain electrode DE2. [000252] The active layer ACT2 of the driving transistor DT may be located higher than the active layer ACT1 of the scan transistor ST. Depending on the height of the active layer, there may be distinguished an upper transistor and a lower transistor. The driving transistor DT may also be referred to as an upper transistor, and the scan transistor ST may also be referred to as a lower transistor. [000253] The source electrode SEI and drain electrode DEI of the scan transistor ST, which is the lower transistor, may be located in "a first source-drain metal layer." The gate electrode GE1 of the scan transistor ST, which is the lower transistor, may be located in "a first gate metal layer". [000254] The source electrode SE2 and drain electrode DE2 of the driving transistor DT, which is the upper transistor, may be located in "a first source-drain metal layer." The gate electrode GE2 of the driving transistor DT, which is the upper transistor, may be located in another "a third gate metal layer" higher than the first gate metal layer and the second gate metal layer. [000255] The first buffer layer 811 may be disposed under the active layer ACT1 of the scan transistor ST, and a second buffer layer 821 may be disposed under the active layer ACT2 of the driving transistor DT. That is, the active layer ACT1 of the scan transistor ST may be located on the first buffer layer 811, and the active layer ACT2 of the driving transistor DT may be located on the second buffer layer 821. Here, the second buffer layer 821 may be located higher than the first buffer layer 811. [000256] The active layer ACT1 of the scan transistor ST may be disposed on the first buffer layer 811, and the first gate insulating layer 812 may be disposed on the active layer ACT1 of the scan transistor ST. The gate electrode GE1 of the scan transistor ST may be disposed on the first gate insulating layer 812, and the first interlayer insulating layer 813 may be disposed on the gate electrode GE1 of the scan transistor ST. [000257] Here, the active layer ACT1 of the scan transistor ST may include a channel region overlapping with the gate electrode GE1, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region. [000258] The second buffer layer 821 may be disposed on the first interlayer insulating layer 813. [000259] The active layer ACT2 of the driving transistor DT may be disposed on the second buffer layer 821, and the second gate insulating layer 822 may be disposed on the active layer ACT2 of the driving transistor DT. The gate electrode GE2 of the driving transistor DT may be disposed on the second gate insulating layer 822, and the second interlayer insulating layer 823 may be disposed on the gate electrode GE2 of the driving transistor DT. [000260] Here, the active layer ACT2 of the driving transistor DT may include a channel region overlapping with the gate electrode GE2, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region. [000261] The source electrode SE2 and the drain electrode DE2 of the driving transistor DT may be disposed on the second interlayer insulating layer 823. Additionally, the source electrode SEI and the drain electrode DEI of the scan transistor ST may be disposed on the second interlayer insulating layer 823. [000262] The source electrode SEI and drain electrode DEI of the scan transistor ST may be connected to the source connection region and the drain connection region of the active layer ACT1 of the scan transistor ST, respectively, through the through holes of the second interlayer insulating layer 823, the second gate insulating layer 822, the second buffer layer 821, the first interlayer insulating layer 813, and the first gate insulating layer 812. [000263] The source electrode SE2 and drain electrode DE2 of the driving transistor DT may be connected to the source connection region and the drain connection region of the active layer ACT2 of the driving transistor DT, respectively, through the through holes of the second interlayer insulating layer 823 and the second gate insulating layer 822. [000264] The storage capacitor Cst may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2. [000265] The first capacitor electrode PLT1 of the storage capacitor Cst may be electrically connected directly or indirectly to the gate electrode GE2 of the driving transistor DT, and the second capacitor electrode PLT2 of the storage capacitor Cst may be electrically connected directly or indirectly to the source electrode SE2 of the driving transistor DT. [000266] The first capacitor electrode PLT1 of the storage capacitor Cst may be located within the first gate metal layer made of the first gate metal. The second capacitor electrode PLT2 of the storage capacitor Cst may be located in a second gate metal layer made of a second gate metal. [000267] Meanwhile, a lower metal BML may be disposed under the active layer ACT2 of the driving transistor DT. The lower metal BML may overlap all or part of the active layer ACT2 of the driving transistor DT. The lower metal BML may include the second gate metal of the second gate metal layer. [0002 68] For example, the lower metal BML may be electrically connected to the gate electrode GE2 of the driving transistor DT. As another example, the lower metal BML may serve as a light shield which blocks light coming from the lower part. In this case, the lower metal BML may be electrically connected to the source electrode SE2 of the driving transistor DT. [000269] Referring to FIGS. 8 and 9, a first planarization layer 831 may be disposed on the driving transistor DT and the scan transistor ST. That is, the first planarization layer 831 may be disposed on the source electrode SE2 and drain electrode DE2 of the driving transistor DT and the source electrode SEI and drain electrode DEI of the scan transistor ST. [000270] Referring to FIGS. 8 and 9, a second source-drain metal layer may exist between the first planarization layer 831 and the second planarization layer 832 . [000271] The source electrode SE2 of the driving transistor DT and the pixel electrode PE of the light emitting device ED may be electrically connected through a relay pattern formed in the second source-drain metal layer. [000272] Referring to FIGS. 8 and 9, the data line DL passing through the transmission area TA may be formed within the second source-drain metal layer. That is, the data line DL passing through the transmission area TA may include a second source-drain metal. [000273] Referring to FIGS. 8 and 9, the active layer ACT2 of the driving transistor DT as an upper transistor, and the active layer ACT1 of the scan transistor ST as a lower transistor may include different semiconductor materials. [000274] For example, the active layer ACT2 of the driving transistor DT as the upper transistor may include an oxide semiconductor material. For example, oxide semiconductor materials may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO) , zinc oxide (ZnO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), or zinc indium tin oxide (ZITO), etc. [000275] For example, the active layer ACT1 of the scan transistor ST, which is the lower transistor, may include a semiconductor material different from the active layer ACT2 of the driving transistor DT as the upper transistor. [000276] For example, the active layer ACT1 of the scan transistor ST, which is a lower transistor, may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (LTPS). [000277] Referring to FIGS. 8 and 9, a light emitting device forming portion may be located on the second planarization layer PNL2. [000278] The light emitting device forming portion may include a light emitting device ED formed on the second planarization layer PNL2. The light emitting device ED may be disposed in the optical area OA. [000279] Referring to FIGS. 8 and 9, the light emitting device ED may be formed by overlapping a pixel electrode PE, an intermediate layer EL, and a common electrode CE. That is, the light emitting device ED may be a portion in which the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap. [000280] The pixel electrode PE may be disposed on the second planarization layer 832. [000281] A bank 833 may be disposed on the pixel electrode PE. [000282] The bank 833 may include a plurality of bank holes, and a portion of the pixel electrode PE may be exposed through the plurality of bank holes. That is, a plurality of bank holes formed in the bank 833 may overlap with a part of the pixel electrode PE. [000283] The intermediate layer EL may be disposed on the bank 833. The intermediate layer EL may contact a portion of the pixel electrode PE through the bank hole. [000284] At least one spacer may exist between the intermediate layer EL and the bank 833. The spacer may include the same material as the bank 833. [000285] A common electrode CE may be disposed on the intermediate layer EL. The common electrode CE may include a plurality of common electrode holes CH. A plurality of common electrode holes CH formed in the common electrode CE may be disposed in the optical area OA. [000286] The common electrode hole CH may have a location corresponding to the transmission area TA. [000287] Referring to FIG. 8, the data line DL may be located to avoid the transmission area TA. Accordingly, the data line DL does not exist in the transmission area TA. [000288] Referring to FIG. 9, the data line DL may be disposed while passing through the transmission area TA. Accordingly, the data line DL may exist in the transmission area TA. For example, the data line DL may be a transparent line containing a transparent material. [000289] Referring to FIGS. 8 and 9, the encapsulation portion may be located on the cathode electrode CE. The encapsulation portion may include an encapsulation layer ENCAP formed on the common electrode CE. [000290] The encapsulation layer ENCAP may be a layer capable of preventing moisture or oxygen from penetrating into the light emitting device ED disposed below the encapsulation layer ENCAP. In particular, the encapsulation layer ENCAP may prevent moisture or oxygen from penetrating into the intermediate layer EL, which may include an organic layer. Here, the encapsulation layer ENCAP may be formed by a single layer or multiple layers. [000291] The encapsulation layer ENCAP may include a first encapsulation layer 841, a second encapsulation layer 842, and a third encapsulation layer 843. [000292] For example, the encapsulation layer ENCAP may include alternating inorganic and organic layers. In this case, for example, the first encapsulation layer 841 and the third encapsulation layer 843 may be inorganic layers, and the second encapsulation layer 842 may be an organic layer. In the case that the second encapsulation layer 842 is composed of an organic layer, the second encapsulation layer 842 may serve as a planarization layer. [000293] Meanwhile, the display panel 110 according to embodiments of the present disclosure may have a built-in touch sensor or an embedded touch sensor. In this case, the display panel 110 according to embodiments of the present disclosure may include a touch sensor layer TSL on the encapsulation layer ENCAP. [000294] The touch sensor layer TSL may include touch sensor metals TSM and bridge metals BRG, and may further include insulating layer configurations such as a sensor buffer layer 851, a sensor interlayer insulating layer 852 and a sensor protection layer 853. [000295] The sensor buffer layer 851 may be disposed on the encapsulation layer ENCAP. [000296] The bridge metals BRG may be disposed on the sensor buffer layer 851, and the sensor interlayer insulating layer 852 may be disposed on the bridge metals BRG. [000297] The touch sensor metals TSM may be disposed on the sensor interlayer insulating layer 852. Some of the touch sensor metals TSM may be connected to the corresponding bridge metal BRG through holes in the sensor interlayer insulating layer 852. [000298] The touch sensor metals TSM and bridge metals BRG may be disposed in the general area NA and in the non-transmission area NTA in the optical area OA. [000299] In the case that the display panel 110 has a top light-emission structure, when placing the touch sensor metals TSM and bridge metals BRG in the nontransmission area NTA in the optical area OA, the touch sensor metals TSM and bridge metals BRG may be arranged so as not to overlap the emission area EA of the nontransmission area NTA. [000300] A plurality of touch sensor metals TSM may form one touch electrode (or one touch electrode line), and may be arranged in a mesh shape and electrically connected. A portion of the touch sensor metals TSM and another portion of the touch sensor metals TSM may be electrically connected through a bridge metal BRG to form one touch electrode (or one touch electrode line). [000301] The sensor protection layer 853 may be disposed to cover the touch sensor metals TSM and bridge metals BRG. [000302] Meanwhile, if the display panel 110 is a type including a built-in touch sensor, at least a portion of the touch sensor metal TSM located on the encapsulation layer ENCAP in the display area DA may be extended and disposed along the outer inclined surface of the encapsulation layer ENCAP, and may be electrically connected to a pad located further outside the outer inclined surface of the encapsulation layer ENCAP. Here, the pad may be disposed in the non-display area NDA and may be a metal pattern to which the touch driving circuit 260 is electrically connected. [000303] Referring to FIGS. 8 and 9, the display device 100 according to embodiments of the present disclosure may include an electronic device 800 located below the substrate SUB and overlapping the optical area OA. The electronic device 800 may be one of the first electronic device 11 and the second electronic device 12 (as shown in FIGS. 1A, IB, and IC). [000304] The electronic device 800 may perform a determined operation according to a first light in the first wavelength band among the light transmitted through the optical area OA and received. For example, the first wavelength band may correspond to a visible light wavelength band or an infrared wavelength band. [000305] FIG. 10 illustrates signal strength or signal intensity when receiving and processing light passing through an optical area OA of a display panel 110 according to embodiments of the present disclosure. [000306] Referring to FIG. 10, light incident on the upper surface of the display panel 110 may transmits (i.e., pass through) the optical area OA of the display panel 110, and may be received by the electronic device 800 located below the display panel 110 and overlapping the optical area OA. [000307] The electronic device 800 may perform a predetermined operation using received light. [000308] Depending on the amount of light received by the electronic device 800, there may vary the performance and quality of operations performed by the electronic device 800. [000309] As an example, if the electronic device 800 is an infrared sensor for detecting a nearby object, the performance and quality of a sensing operation performed using infrared rays may vary depending on the amount of infrared rays penetrating the optical area OA of the display panel 110. [000310] The amount of infrared rays passing through the optical area OA of the display panel 110 may correspond to an intensity or a value of a point spread function (PSF). Here, the intensity of the point spread function may correspond to the signal intensity of infrared rays during reception processing by the electronic device 800. The intensity of the point spread function may be an indicator of the detection performance of the infrared sensor. [000311] If the metal ratio in the optical area OA increases, that is, if the transmittance of the optical area OA decreases, the intensity of the point spread function, which is an indicator of the detection performance of the infrared sensor, may also decrease. [000312] If the metal ratio in the optical area OA decreases, that is, if the transmittance of the optical area OA increases, the intensity of the point spread function, which is an indicator of the detection performance of the infrared sensor, may also increase. [000313] As another example, in the case that the electronic device 800 is an image sensor or a camera, the performance and quality of the camera operation performed using visible light may vary depending on the amount of visible light passing through the optical area OA of the display panel 110. [000314] The amount of visible light passing through the optical area OA of the display panel 110 may correspond to intensity or a value of a modulation transfer function (MTF). Here, the value of the modulation transfer function may correspond to the signal intensity of visible light during reception processing by the electronic device 800. Here, the value of the modulation transfer function may be an indicator of the camera performance and may indicate the level of sharpness. [000315] If the metal ratio in the optical area OA increases, that is, if the transmittance of the optical area OA decreases, the value of the modulation transfer function, which is a performance indicator of the camera, may also decrease. [000316] If the metal ratio in the optical area OA decreases, that is, if the transmittance of the optical area OA increases, the value of the modulation transfer function, which is a performance indicator of the camera, may increase. [000317] Hereinafter, it will be described a transmittance improvement structure of the optical area OA of the display panel 110 according to embodiments of the present disclosure. The transmittance improvement structure of the optical area OA may include a structure capable of lowering the metal ratio in the optical area OA. [000318] Hereinafter, for convenience of explanation, the optical area OA will be referred to as a first area OA, and the general area NA will be referred to as a second area NA. [000319] FIG. 11 is a plan view of the display panel 110 according to embodiments of the present disclosure. [000320] Referring to FIG. 11, the display panel 110 according to embodiments of the present disclosure may include a substrate SUB including a display area DA capable of displaying an image and a non-display area NDA outside the display area DA, a plurality of subpixels SP included in the display area DA and each including a plurality of light emitting device ED, and a plurality of data lines DL for supplying data signals for image display to a plurality of subpixels SP. [000321] Referring to FIG. 11, the display area DA may include a first area OA capable of transmitting light and a second area NA located outside the first area OA. The second area NA may include an upper area NAI adjacent to an upper edge of the first area OA, and a lower area NA2 adjacent to a lower edge of the first area OA. [000322] In FIG. 11, as an example, the first area OA is indicated by a dotted circle, and an area outside the dotted circle may be the second area NA. The upper area NAI of the second area NA may be an area located at the top of the first area OA among the outer areas of the first area OA. The lower area NA2 of the second area NA may be an area located at the bottom of the first area OA among the outer areas of the first area OA. [000323] Referring to FIG. 11, the plurality of subpixels SP disposed in the display area DA may include first to twelfth subpixels SP1 to SP12. [000324] Referring to FIG. 11, the plurality of subpixels SP disposed in the upper area NAI of the second area NA may include the first subpixel SP1, the second subpixel SP2, and the seventh subpixel SP7, and a tenth subpixel SP10. [000325] Referring to FIG. 11, the plurality of subpixels SP disposed in the lower area NA2 of the second area NA may include the fifth subpixel SP5, the sixth subpixel SP6, and the ninth subpixel SP9, and a twelfth subpixel SP12. [000326] Referring to FIG. 11, the plurality of subpixels SP disposed in the first area OA may include a third subpixel SP3, a fourth subpixel SP4, an eighth subpixel SP8, and an eleventh subpixel SP11. [000327] Referring to FIG. 11, for example, the plurality of subpixels SP disposed in the display area DA may include a red subpixel which emits red light, a green subpixel which emits green light, and a blue subpixel which emits blue light. [000328] Referring to FIG. 11, a plurality of subpixels SP disposed in the display area DA may each include a plurality of pixel electrodes PE. For example, the plurality of pixel electrodes PE may include a red pixel electrode PE(R) included in the red subpixel, a green pixel electrode PE(G) included in the green subpixel, and a blue pixel electrode PE (B) included in the blue subpixel. [000329] Referring to FIG. 11, the plurality of data lines DL disposed in the display area DA may include a red data line DL(R) for supplying data signals to the red subpixel, green data lines DL(G), DL(G)_U and DL(G)_D for supplying data signals to the green subpixels, and a blue data line DL(B) for supplying data signals to the blue subpixel. [000330] Referring to FIG. 11, a plurality of data lines DL disposed in the display area DA may be arranged in the second area NA, which is the general area NA. [000331] Referring to FIG. 11, some (e.g., DL(R), DL(G), DL(B)) of the plurality of data lines DL disposed in the second area NA may pass through a first area OA, which is the optical area OA. [000332] However, other parts (e.g., DL(G)_U and DL(G)_D) of the plurality of data lines DL disposed in the second area NA may be disposed while bypassing the first area OA, which is the optical area OA, without passing through the first area OA. [000333] For example, an upper data line DL(G)_U may be disposed in the upper area NAI of the second area NA, and a lower data line DL(G)_D may be disposed in the lower area NA2 of the second area NA. The upper data line DL(G)_U and the lower data line DL(G)_D may be electrically connected through a bypass line BW which bypasses the first area OA. The upper data line DL(G)_U, the lower data line DL(G)_D, and the bypass line BW may be electrically connected to correspond to a single data line, and this single data line may bypass the first area OA without passing through the first area OA. [000334] For example, referring to FIG. 11, the plurality of data lines DL may include a first data line DL1 passing through all of the upper area NAI, the first area OA, and the lower area NA2. [000335] In the example of FIG. 11, the first data line DL1 may be a green data line DL(G) for supplying a data signal to green subpixels disposed in each of the upper area NAI, the first area OA, and the lower area NA2. However, this is only an example and is not limited thereto. [000336] The plurality of data lines DL may further include an upper data line DL(G)_U disposed in the upper area NAI of the second area NA, a lower data line DL(G)_D disposed in the lower area NA2 of the second area NA, and a bypass line which electrically connects the upper data line DL(G)_U and lower data line DL(G)_D and bypasses the first area OA. In this case, the upper data line DL(G)_U, the lower data line DL(G) D and bypass line BW may be electrically connected to serve as a single data line. [000337] In the example of FIG. 11, the upper data line DL(G)_U may be a green data line DL(G)JJ for supplying a data signal to the green subpixel placed in the upper area NAI. In addition, the lower data line DL(G)_D may be a green data line DL(G)_D for supplying a data signal to the green subpixel disposed in the lower area NA2. However, this is only an example and is not limited thereto. [000338] Referring to FIG. 11, the bypass line BW may include a first bypass line BW1 connected to the upper data line DL(G)_U, a second bypass line BW2 connected to the lower data line DL(G)_D, and a third bypass line BW3 which connects the first bypass line BW1 and the second bypass line BW2. [000339] Referring to FIG. 11, the bypass line BW may include a horizontal bypass line H^BW extending in a horizontal direction and a vertical bypass line V_BW extending in a vertical direction, and connecting to the data driving circuit 220. Referring to FIG. 11, the horizontal bypass line H_BW and the upper data line DL(G)_U along with the lower data line DL(G)_D may form a mesh type. [000340] Referring to FIG. 11, crossings between the bypass line BW and the upper data line DL(G) U along with the lower data line DL(G)_D may have connecting points. For example, a first connecting point is formed at a crossing between the upper data line DL(G)JJ and the first bypass line BW1 (which is a horizontal bypass line H_BW), a second connecting point is formed at a crossing between the lower data line DL(G)_D and the second bypass line BW2(which is a horizontal bypass line H^BW), a third connecting point is formed at a crossing between the first bypass line BW1(which is a horizontal bypass line H BW) and the third bypass line BW3(which is a vertical bypass line V_BW), and a fourth connecting point is formed at a crossing between the second bypass line BW2 (which is a horizontal bypass line H_BW)and the third bypass line BW3(which is a vertical bypass line V_BW). [000341] Referring to FIG. 11, the horizontal bypass line H_BW may include a first bypass line BW1 and a second bypass line BW2, and the vertical bypass line V^BW may include a third bypass line BW3. [000342] The horizontal bypass line H_BW and the vertical bypass line V_BW may intersect each other and may overlap with each other in the vertical direction. [000343] Accordingly, the horizontal bypass line H^BW and the vertical bypass line V^BW may be disposed in different metal layers. For example, the horizontal bypass line H BW may be disposed in a first metal layer, and the vertical bypass line V_BW may be disposed in a second metal layer different from the first metal layer. For example, the first metal layer may be a first source-drain metal layer and the second metal layer may be a second source-drain metal layer. [000344] Referring to FIG. 11, the plurality of pixel electrodes PE included in each of the plurality of light emitting device ED may include a first pixel electrode PEI disposed in the upper area NAI and included in the first subpixel SP1, a second pixel electrode PE2 disposed in the upper area NAI and included in the second subpixel SP2, a third pixel electrode PE3 disposed in the first area OA and included in the third subpixel SP3, a fourth pixel electrode PE4 disposed in the first area OA and included in the fourth subpixel SP4, a fifth pixel electrode PE5 disposed in the lower area NA2 and included in the fifth subpixel SP5, and a sixth pixel electrode PE6 disposed in the lower area NA2 and included in the sixth subpixel SP6. [000345] Referring to FIG. 11, the first data line DL1 may be connected to the first subpixel SP1 in the upper area NAI, the third subpixel SP3 in the first area OA, and the fifth subpixel SP5 in the lower area NA2. [000346] The first data line DL1 may supply data signals to the first subpixel SP1 in the upper area NAI, the third subpixel SP3 in the first area OA, and the fifth subpixel SP5 in the lower area NA2. [000347] Referring to FIG. 11, the upper data line DL(G)_U may be connected to the second subpixel SP2 disposed in the upper area NAI, and the lower data line DL(G)_D may be connected to the sixth subpixel SP6 disposed in the lower area NA2. [000348] Referring to FIG. 11, the display panel 110 according to embodiments of the present disclosure may further include a connection line CW which electrically connects the third pixel electrode PE3 and the fourth pixel electrode PE4. [000349] The connection line CW may be disposed in the first area OA, which is the optical area OA. [000350] Referring to FIG. 11, the emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be the same. [000351] In the example of FIG. 11, the emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5, and the sixth subpixel SP6 may be green, but is not limited thereto. [000352] Referring to FIG. 11, a part (e.g., the third subpixel SP3) of the plurality of subpixels SP3 and SP4 disposed in the first area OA may include the light emitting device ED and the subpixel circuit SPG. [000353] The subpixel circuit SPG included in some (e.g., third subpixel (SP3)) of the plurality of subpixels SP3 and SP4 disposed in the first area OA may include a driving transistor DT, a scan transistor ST and a storage capacitor Cst, (as shown in FIG. 3). [000354] Referring to FIG. 11, the subpixel circuit SPG included in some (e.g., third subpixel SP3) of the plurality of subpixels SP3 and SP4 disposed in the first area OA may include a red subpixel circuit SPG(R) included in the red subpixel, a green subpixel circuit SPC(G) included in the green subpixel, and a blue subpixel circuit SPC(B) included in the blue subpixel. [000355] Referring to FIG. 11, another part (e.g., fourth subpixel SP4) of the plurality of subpixels SP3 and SP4 disposed in the first area OA may include a light emitting device ED, but may not include a subpixel circuit SPG. [000356] Referring to the example of FIG. 11, each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fifth subpixel SP5, and the sixth subpixel SP6 may include a light emitting device ED and a subpixel circuit PC(G) for driving the light emitting device ED. Here, the subpixel circuit SPC(G) may include two or more transistors DT and ST. [000357] Referring to the example of FIG. 11, the fourth subpixel SP4 may include the light emitting device ED, but may not include the subpixel circuit SPC(G) . The light emitting device ED of the fourth subpixel SP4 may be driven by the subpixel circuit SPC(G) of the third subpixel SP3. [000358] Accordingly, the driving current output from the subpixel circuit SPC(G) of the third subpixel SP3 may be supplied to the third pixel electrode PE3, and may be also supplied to the fourth pixel electrode PE4 through the connection line CW. [000359] Referring to FIG. 11, a plurality of pixel electrodes PE may further include a seventh pixel electrode PE7 disposed in the upper area NAI and included in the seventh subpixel SP7, an eighth pixel electrode PE8 disposed in the first area OA and included in the eighth subpixel SP8, and a ninth pixel electrode PE9 disposed in the lower area NA2 and included in the ninth subpixel SP9. [000360] The plurality of data lines DL may further include a second data line DL2 connected to the seventh subpixel SP7 in the upper area NAI, the eighth subpixel SP8 in the first area OA, and the ninth subpixel SP9 in the lower area NA2. [000361] In the example of FIG. 11, the second data line DL2 may be a blue data line DL(B) for supplying a data signal to blue subpixels disposed in each of the upper area NAI, the first area OA, and the lower area NA2, however is not limited thereto. [000362] Emission color of each of the seventh subpixel SP7 in the upper area NAI, the eighth subpixel SP8 in the first area OA and the ninth subpixel SP9 in the lower area NA2 may be different from emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5 and the sixth subpixel SP6. [000363] For example, the emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5 and the sixth subpixel SP6 may be green, and the emission color of the seventh subpixel SP7 in the upper area NAI, the eighth subpixel SP8 in the first area OA and the ninth subpixel SP9 in the lower area NA2 may be blue, however is not limited thereto. [000364] Referring to FIG. 11, the second data line DL2 may intersect and overlap with the connection line CW. The first data line DL1 may also intersect and overlap with the connection line CW. [000365] Referring to FIG. 11, the plurality of pixel electrodes PE may further include a tenth pixel electrode PE10 disposed in the upper area NAI and included in the tenth subpixel SP10, an eleventh pixel electrode PE11 disposed in the first area OA and included in the eleventh subpixel SP11, and a twelfth pixel electrode PE12 disposed in the lower area NA2 and included in the twelfth subpixel SP12. [000366] Referring to FIG. 11, the plurality of data lines DL may further include a third data line DL3 connected to the tenth subpixel SP10 of the upper area NAI, the eleventh subpixel SP11 of the first area OA, and the twelfth subpixel SP12 of the lower area NA2. [000367] In the example of FIG. 11, the third data line DL3 may be a red data line DL(R) for supplying a data signal to the red subpixels disposed in each of the upper area NAI, the first area OA and the lower area NA2, but is not limited thereto. [000368] Referring to FIG. 11, the emission color of each of the tenth subpixel SP10, the eleventh subpixel SP11 and the twelfth subpixel SP12 may be different from the emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5 and the sixth subpixel SP6. [000369] For example, the emission color of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fourth subpixel SP4, the fifth subpixel SP5 and the sixth subpixel SP6 may be green, and the emission color of each of the tenth subpixel SP10, the eleventh subpixel SP11 and the twelfth subpixel SP12 may be red, however is not limited thereto. [000370] Referring to FIG. 11, the display panel 110 according to embodiments of the present disclosure may further include a common electrode CE disposed on the plurality of pixel electrodes PE. [000371] Referring to FIG. 11, within the first area OA, the common electrode CE may have a plurality of common electrode holes CH. For example, within the first area OA, the common electrode CE may have a common electrode hole CH between the first data line DL1 and the third data line DL3. [000372] The display panel 110 according to embodiments of the present disclosure may include a substrate SUB including a display area DA capable of displaying an image and a non-display area NDA outside the display area DA, a plurality of subpixels SP included in the display area DA and each including a plurality of light emitting devices ED, and a plurality of data lines DL for supplying data signals for image display to a plurality of subpixels SP. [000373] The display area DA may include a first area OA, which is an optical area capable of transmitting light, and a second area NA, which is a general area located outside the first area OA. [000374] The second area NA may include an upper area NAI adjacent to an upper edge of the first area OA, and a lower area NA2 adjacent to a lower edge of the first area OA. [000375] The plurality of light emitting devices ED may each include a plurality of pixel electrodes PE. [000376] The plurality of pixel electrodes PE may be disposed in the first area OA, and may include two pixel electrodes PE3 and PE4 which are electrically connected to each other. [000377] The display panel 110 according to embodiments of the present disclosure may be disposed in the first area OA, and may further include a connection line CW which electrically connects the two pixel electrodes PE3 and PE4. [000378] The plurality of data lines DL may include a first data line DL1 connected to one of two subpixels (e.g., a subpixel including PE3) including two pixel electrodes PE3 and PE4. Among the two subpixels containing two pixel electrodes PE3 and PE4, the remaining one (e.g., the subpixel containing PE4) may not connected to the data line. [000379] FIGS. 12 and 13 are plan views of a portion of the first area OA1, which is the optical area OA, of the display panel 110 according to embodiments of the present disclosure. [000380] Referring to FIGS. 12 and 13, the first area OA1, which is the optical area OA of the display panel 110, may include a transmission area TA and a nontransmission area NTA. [000381] Referring to FIGS. 12 and 13, the nontransmission area NTA may include a circuit area CA where a plurality of subpixel circuits, each included in a plurality of subpixels, are disposed. For example, the plurality of subpixel circuits may include a red subpixel circuit included in a red subpixel, a green subpixel circuit included in a green subpixel, and a blue subpixel circuit included in a blue subpixel. [000382] Referring to FIGS. 12 and 13, the nontransmission area NTA may include a plurality of emission areas each corresponding to a plurality of subpixels. Accordingly, a plurality of pixel electrodes PE(R), PE (G) and PE (B) may be disposed in the non-transmission area NTA. [000383] Referring to FIGS. 12 and 13, a plurality of contact holes CNT (R), CNT(G) and CNT(B) may be placed in the non- transmission area NTA for connecting a plurality of pixel electrodes PE(R), PE(G) and PE (B) to a plurality of subpixel circuits, respectively. [000384] For example, a plurality of pixel electrodes PE(R), PE(G) and PE(B) may include a red pixel electrode PE (R) included in the red subpixel, and a green pixel electrodes PE(G) included in the green subpixel, and a blue pixel electrode PE(B) included in the blue subpixel. For reference, the arrangement of the red pixel electrode PE(R), green pixel electrode PE(G) and blue pixel electrode PE(B) in FIGS. 12 and 13 is different from the arrangement of the red pixel electrode PE(R), the green pixel electrode PE(G) and blue pixel electrode PE (B) of FIG. 11. [000385] For example, a plurality of contact holes CNT(R), CNT(G) and CNT(B) may include a contact hole CNT(R) between the red pixel electrode PE(R) and the red subpixel circuit, a contact hole CNT(G) between the green pixel electrode PE(G) and the green subpixel circuit, and a contact hole CNT(B) between the blue pixel electrode PE(B) and the blue subpixel circuit. [000386] Referring to FIGS. 12 and 13, two green pixel electrodes PE(G) may be connected by a connection line CW. The two green pixel electrodes PE(G) connected by the connection line CW may correspond to the third pixel electrode PE3 and the fourth pixel electrode PE4 of FIG. 11 . [000387] Referring to FIGS. 12 and 13, the blue pixel electrode PE(B) may correspond to the eighth pixel electrode PE8 of FIG. 11. [000388] Referring to FIG. 11, in the second area NA which is the general area NA, four data lines (e.g., red data line, green data line, blue data line, green data line) may be arranged repeatedly. [000389] In the upper area NAI of the second area NA which is the general area NA, the red data line DL (R) , the green data line DL(G)_U as the upper data line, and the blue data line DL(B), and the green data line DL (G) may be arranged in order. [000390] Referring to FIG. 11, in the lower area NA2 of the second area NA which is the general area NA, a red data line DL (R) , a green data line DL(G)_D as the lower data line, a blue data line DL (B) , and a green data line DL(G) may be arranged in order. [000391] Referring to FIGS. 12 and 13, in the first area OA which is the optical area OA, three data lines (e.g., red data line DL(R), blue data line DL(B), green data line DL(G)) may be arranged repeatedly. [000392] Referring to FIGS. 12 and 13, in the first area OA, there is omitted a green data line in an area 1200 between the red data line DL(R) and the blue data line DL(B). Accordingly, metal may be reduced within the first area OA which is the optical area OA. As a result, the metal ratio in the first area OA as the optical area OA may be lowered and the transmittance may be increased. [000393] In FIGS. 12 and 13, the green data line DL(G) may correspond to the first data line DL1 in FIG. 11, and the blue data line DL(B) may correspond to the second data line DL2 in FIG 11, and the red data line DL(R) may correspond to the third data line DL3 in FIG. 11. [000394] Referring to FIGS. 12 and 13, the red data line DL (R) , which is the third data line DL3, may overlap the red pixel electrode PE(R). [000395] The area 1200 where the green data line is omitted may be an area immediately adjacent to the red data line DL(R), which is the third data line DL3, and may overlap with the red pixel electrode PE(R). [000396] In the upper area NAI of the second area NA which is the general area NA, the red pixel electrode PE (R) may overlap with two data lines DL (R) and DL(G)_U. In addition, in the lower area NA2 of the second area NA which is the general area NA, the red pixel electrode PE(R) may overlap with two data lines DL(R) and DL(G)_D. [000397] However, as described above, in the first area OA which is the optical area OA, the red pixel electrode PE(R) only overlaps with one data line DL(R). Accordingly, the light emission characteristics of the red subpixel in the first area OA may be different from the light emission characteristics of the red subpixel in the second area NA. [000398] In order to reduce this deviation in light emission characteristics, as shown in FIGS. 12 and 13, the red data line DL(R), which is the third data line DL3, may include a protrusion 1210. The protrusion 1210 may overlap the red pixel electrode PE(R) in the first area OA. [000399] That is, referring to FIGS. 12 and 13, the red data line DL(R), which is the third data line DL3, may overlap with the red subpixel PE(R) which is the eleventh subpixel PE11 of FIG. 11. The red data line DL(R) as the third data line DL3 may include a protrusion 1210 that protrudes into the area 1200 where the green data line is omitted. [000400] The protrusion 1210 may overlap with the red subpixel PE(R) which is the eleventh subpixel PE11 of FIG. 11 in the data line longitudinal direction (i.e., column direction, data line extension direction). [000401] Referring to FIGS. 12 and 13, the third pixel electrode PE3, the connection line CW and the fourth pixel electrode PE4 may be integrally formed. That is, the connection line CW may be composed of a pixel electrode material. [000402] Referring to FIG. 12, in the first area OA, the first data line DL1 and the second data line DL2 may be disposed in the same metal layer (e.g., second metal layer) and spaced apart from each other on the same plane. Similarly, in the second area NA, the first data line DL1 and the second data line DL2 may be disposed in the same metal layer (e.g., second metal layer) and spaced apart from each other on the same plane. [000403] Referring to FIG. 13, in at least a portion of the first area OA, the first data line DL1 and the second data line DL2 may be disposed in the different metal layers (e.g., a first metal layer and a second metal layer) . Alternatively, in the second area NA, the first data line DL1 and the second data line DL2 may be disposed in the same metal layer (e.g., second metal layer). [000404] That is, in the second area NA, the first data line DL1 and the second data line DL2 may be disposed in the same metal layer and spaced apart from each other on the same plane. In the transmission area TA among the transmission area TA and the non-transmission area NTA included in the first area OA, the first data line DL1 and the second data line DL2 may be disposed in different metal layers (e.g., first metal layer, second metal layer), and may overlap in the vertical direction. In the non-transmission area NTA among the transmission area TA and the non-transmission area NTA included in the first area OA, the first data line DL1 and the second data line DL2 may be disposed within the same metal layer (e.g., second metal layer) and spaced apart from each other on the same plane. [000405] Referring to FIG. 13, for example, the first metal layer may be a metal layer between the second interlayer insulating layer 823 and the first planarization layer 831, and may be a first source-drain metal layer. The second metal layer may be a metal layer between the first planarization layer 831 and the second planarization layer 832, and may be a second source-drain metal layer. For example, the blue data line DL(B), which is the second data line DL2, may be disposed in the first metal layer, and the green data line DL(G), which is the first data line DL1, may be disposed in the second metal layer. [000406] FIGS. 14 to 18 are cross-sectional views of the display panel 110 having a transmittance improvement structure according to embodiments of the present disclosure. However, in the cross-sectional views of FIGS. 14 to 18, the stacked structure is the same as that in FIGS. 8 and 9. Therefore, it will be omitted description of the stacked structure. Additionally, in the following description, FIGS. 11 to 13 are also referred to. [000407] FIG. 14 is a cross-sectional view taken along the line X1-X2 of FIGS. 12 and 13, FIG. 15 is a cross-sectional view taken along the line X3-X4 of FIGS. 12 and 13, FIG. 16 is a cross-sectional view taken along the line X5-X6 of FIG. 13, FIG. 17 is a cross-sectional view taken along the line X7-X8 of FIG. 13, and FIG. 18 is a cross-sectional view taken along the line X9-X10 of FIG. 13. [000408] Referring to FIG. 14, in the area indicated by the line X1-X2 of FIGS. 12 and 13, there may be a blue emission area EA_B of the blue subpixel and a red emission area EA_R of the red subpixel. That is, the blue pixel electrode PE(B) and the red pixel electrode PE (R) may be disposed in the area indicated by the line X1-X2 in FIGS. 12 and 13. [000409] Referring to FIG. 14, in the area indicated by the line X1-X2 of FIGS. 12 and 13, there may be disposed a transistor TFT included in the green subpixel circuit SPG (G), a transistor TFT included in the blue subpixel circuit SPC(B), and a transistor TFT included in the red subpixel circuit SPG(R). [000410] These transistors TFT may include a first active layer ACT1 and a first gate electrode GE1 on the first active layer ACT1. The first active layer ACT1 is an active layer of the lower transistor, and may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (FTPS). [000411] A shield metal SM which overlaps the first active layer ACT1 may be disposed under the transistors TFT. The shield metal SM may be disposed between the multi-buffer layer 811a and the active buffer layer 811b. [000412] A first upper metal TM1 overlapping with the first gate electrode GE1 may be disposed on the transistors TFT. The first upper metal TM1 may be disposed between the first interlayer insulating layer 813 and the second buffer layer 821. [000413] Referring to FIG. 14, a metal layer between the second interlayer insulating layer 823 and the first planarization layer 831 may be referred to as the first metal layer, and a metal layer between the first planarization layer 831 and the second planarization layer 832 may be referred to as a second metal layer. As shown in Fig.14, the second metal layer is upper than the first metal layer. [000414] A plurality of horizontal lines extending in the horizontal direction may be placed in the first metal layer, and a plurality of vertical lines extending in the vertical direction may be placed in the second metal layer. [000415] Referring to FIG. 14, data lines DL(R), DL(G) and DL(B), which are a type of vertical line, may be disposed in the second metal layer. Additionally, a power line PWL, which is another type of vertical line, may also be disposed in the second metal layer. [000416] Referring to FIG. 14, unlike the data lines DL(R), DL(G), and DL(B), the power line PWL may be a line to which a power supply voltage whose voltage level does not change according to frame changes is applied. For example, the power line PWL may include at least one of a driving voltage line VDDL and a base voltage line VSSL. [000417] As described above, the power line PWL may be disposed in the same metal layer (e.g., second metal layer) as the vertical bypass line V_BW. [000418] Referring to FIG. 14, one of the two red data lines DL(R) overlapping the red pixel electrode PE(R) may correspond to the protrusion 1210 protruding from the red data line DL(R), which is the third data line DL3 in FIGS. 12 and 13. [000419] Referring to FIG. 15, the third pixel electrode PE3 and the fourth pixel electrode PE4, which are two green pixel electrodes PE(G), may be connected to each other through a connection line CW. [000420] Referring to FIG. 15, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be formed integrally with the connection line CW. [000421] Referring to FIG. 15, below the fourth pixel electrode PE4, there may be disposed a second gate metal GM2, which corresponds to a second active layer ACT2 on the second buffer layer 821 and a second gate electrode GE2 on the second active layer ACT2. [000422] Referring to FIG. 15, a first upper metal TM1 may be disposed between the first interlayer insulating layer 813 and the second buffer layer 821, and a first gate metal GM1 may be disposed between the first gate insulating layer 812 and the first interlayer insulating layer 813. [000423] Referring to FIG. 16, the area marked with lines X5-X6 may be a boundary area between the transmission area TA and the non-transmission area NTA. [000424] Referring to FIG. 16, in an area indicated by the line X5-X6, the second data line DL2 may include an upper layer portion disposed on the same second metal layer as the first data line DL1, a lower layer portion disposed on a first metal layer lower than the second metal layer, a connection portion connecting the upper layer and the lower layer, and an extension portion extending below the first data line DL1. [000425] Referring to FIG. 16, in the area indicated by the line X5-X6, the second data line DL2 may go down in the vertical direction and shift in the horizontal direction to overlap the first data line DL1. Here, the first data line DL1 may be a green data line DL(G), and the second data line DL2 may be a blue data line DL(B). [000426] Referring to FIG. 16, in the area indicated by lines X5-X6, the first data line DL1 may be a first upper data line DL(G)_ML2 disposed on the second metal layer. The second data line DL2 may include a second lower data line DL(B)_ML1 disposed on the first metal layer and a second upper data line DL(B)_ML2 disposed on the second metal layer. [000427] Referring to FIG. 16, an upper blue data line DL(B) ML2 as the second upper data line may be connected to a lower blue data line DL(B)_ML1 through a hole in the first planarization layer 831. A lower blue data line DL(B)_ML1 as the second lower data line may extend slightly in the horizontal direction and overlap the upper green data line DL(G)_ML2. [ [000428] Referring to FIG. 17, the area indicated by lines X7-X8 is an area included in the transmission area TA. In the area indicated by lines X7-X8, the first data line DL1 and the second data line DL2 may overlap in the vertical direction. [000429] Referring to FIG. 17, in the area indicated by lines X7-X8, the first data line DL1 may be a first upper data line DL(G)JhL2 disposed on the second metal layer, and the second data line DL2 may be a second lower data line DL(B)_ML1 disposed on the first metal layer. [000430] Referring to FIG. 17, the area indicated by lines X7-X8 is an area included in the transmission area TA. In the area indicated by lines X7-X8, the first data line DL1 and the second data line DL2 may overlap in the vertical direction, thereby greatly improving the transmittance of the transmission area TA. [000431] Referring to FIG. 18, the area indicated by the line X9-X10 is included in the non-transmission area NTA, and may be a subpixel circuit area. [000432] Referring to FIG. 18, in the nontransmission area NTA, the first data line DL1 may include a first lower data line DL(G)_ML1 disposed within a first metal layer and a first upper data line DL(G)_ML2 disposed within a second metal layer different from the first metal layer. [000433] The first lower data line DL(G) ML1 and the first upper data line DL(G)_ML2 may be electrically connected to each other through holes in the first planarization layer 831, which is an insulating layer between the first metal layer and the second metal layer. [000434] Referring to FIG. 18, in the non transmission area NTA, the second data line DL2 may include a second lower data line DL(B)_ML1 disposed in the first metal layer and a second upper data line DL(B)JhL2 disposed in the second metal layer. [000435] The second lower data line DL(B)_ML1 and the second upper data line DL(B)_ML2 may be electrically connected to each other through different holes in the first planarization layer 831 which is an insulating layer. [000436] FIG. 19 is a cross-sectional view of a connection area between the vertical bypass line V BW and the horizontal bypass line H_BW in the display panel 110 according to embodiments of the present disclosure. However, in the cross-sectional view of FIG. 19, the stacked structure is the same as that in FIGS. 8 and 9. Therefore, it will be omitted description of the stacked structure. Additionally, in the following description, FIGS. 11 to 13 are also referred to. [000437] Referring to FIG. 19, the horizontal bypass line H BW may be disposed on the first metal layer, and the vertical bypass line V_BW may be disposed on a second metal layer different from the first metal layer. [000438] Referring to FIG. 19, the vertical bypass line V^BW may be connected to the horizontal bypass line H_BW through a hole in the first planarization layer 831, which is an insulating layer disposed between the first metal layer and the second metal layer. [000439] Referring to FIG. 19, the area where the horizontal bypass line H_BW and the vertical bypass line V_BW are arranged may be the second area NA, which is the general area NA. [000440] Referring to FIG. 19, an emission area EA of a subpixel may exist in the second area NA, and there may be disposed a pixel electrode therefor. Additionally, there may be disposed a transistor TFT included in a subpixel circuit of a subpixel in the second area NA. [000441] For example, each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, the fifth subpixel SP5 and the sixth subpixel SP6 shown in FIG. 11 may include a light emitting device ED and a subpixel circuit SPC(G), and the subpixel circuit SPG(G) may include two or more transistors DT and ST. [000442] The fourth subpixel SP4 may include the light emitting device ED, but may not include the subpixel circuit SPG(G). The source electrode and drain electrode of each of the two or more transistors may be disposed in the same first metal layer as the horizontal bypass line H^BW. [000443] The first data line DL1, the upper data line DL(G)_U, and the lower data line DL(G)_D may be disposed in the same second metal layer as the vertical bypass line V^BW. [000444] Referring to FIGS. 14 to 19, the display device 100 according to embodiments of the present disclosure may further include an electronic device 800 which is located below the substrate SUB, overlaps the first area OA, and perforins a specified operation using light passing through the first area OA. [000445] Embodiments of the present disclosure described above are briefly described as follows. [000446] A display device according to embodiments of the present disclosure may include a substrate including a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area, each including a plurality of light emitting devices, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels. [000447] The display area may include a first area capable of transmitting light and a second area located outside the first area. The second area may include an upper area above the first area and a lower area under the first area. [000448] The plurality of data lines may include a first data line extending from the upper area to the lower area passing through the first area, an upper data line disposed in the upper area, a lower data line disposed in the lower area, and a bypass line which electrically connects the upper data line and the lower data line and bypasses the first area. [000449] The bypass line may include a first bypass line connected to the upper data line, a second bypass line connected to the lower data line, and a third bypass line for connecting the first bypass line and the second bypass line. [000450] The bypass line may include a horizontal bypass line extending horizontally, and a vertical bypass line extending vertically, wherein the first bypass line and the second bypass line are horizontal bypass lines, and the third bypass line is a vertical bypass line. [000451] The horizontal bypass line may be disposed in a first metal layer, and the vertical bypass line may be disposed in a second metal layer different from the first metal layer. [000452] A display device according to embodiments of the present disclosure may further include a power line for applying a power voltage whose voltage level does not change depending on a frame change, wherein the power line is disposed in the second metal layer. [000453] The power line may be disposed within the same metal layer as the vertical bypass line. [000454] Each of the plurality of light emitting devices may include a plurality of pixel electrodes. [000455] The plurality of pixel electrodes may include a first pixel electrode disposed in the upper area and included in a first subpixel, a second pixel electrode disposed in the upper area and included in a second subpixel, a third pixel electrode disposed in the first area and included in a third subpixel, a fourth pixel electrode disposed in the first area and included in a fourth subpixel, a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel. [000456] The first data line may be connected to the first subpixel, the third subpixel, and the fifth subpixel. [000457] The upper data line may be connected to the second subpixel. [000458] The lower data line may be connected to the sixth subpixel. [000459] In the display device according to embodiments of the present disclosure, the third pixel electrode and the fourth pixel electrode may be electrically connected to each other. [000460] The emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel may be the same. [000461] Each of the first subpixel, the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel may include a light emitting device and a subpixel circuit for driving the light emitting device. The subpixel circuit may include two or more transistors, [000462] The fourth subpixel may include a light emitting device, but may not include a subpixel circuit. In this case, the light emitting device of the fourth subpixel may be driven by a subpixel circuit of the third subpixel. [000463] A a driving current output from the subpixel circuit of the third subpixel may be supplied to the third pixel electrode and the fourth pixel electrode. [000464] The display device according to embodiments of the present disclosure may further include a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode. [000465] The third pixel electrode, the connection line and the fourth pixel electrode may be integrally formed. [000466] The plurality of pixel electrodes may further include a seventh pixel electrode disposed in the upper area and included in a seventh subpixel, an eighth pixel electrode disposed in the second area and included in an eighth subpixel, and a ninth pixel electrode disposed in the lower area and included in the ninth subpixel. [000467] The plurality of data lines may include a second data line connected to the seventh subpixel, the eighth subpixel and the ninth subpixel. [000468] The emission color of each of the seventh subpixel, the eighth subpixel and the ninth subpixel may be different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel. [000469] The second data line may intersect and overlap a portion (i.e., the connection line) in which the third pixel electrode and the fourth pixel electrode are connected. [000470] For example, in the first area and the second area, the first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane. [000471] As another example, the first data line and the second data line may be disposed in the same metal layer in the second area. The first data line and the second data line may be disposed on different metal layers in at least a partial area of the first area. [000472] For example, in the second area, the first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane. The first area may include a transmission area and a non-transmission area. The first data line and the second data line may be disposed in different metal layers and overlap in a vertical direction in the transmission area. The first data line and the second data line may be disposed in the same metal layer and spaced apart from each other on the same plane in the non-transmission area. [000473] The plurality of pixel electrodes may further include a tenth pixel electrode disposed in the upper area and included in a tenth subpixel, an eleventh pixel electrode disposed in the first area and included in an eleventh subpixel, and a twelfth pixel electrode disposed in the lower area and included in the twelfth subpixel. [000474] The plurality of data lines may further include a third data line connected to the tenth subpixel, the eleventh subpixel, and the twelfth subpixel, [000475] The third data line may overlap with the tenth pixel electrode. [000476] The third data line may include a protrusion, and the protrusion may overlap with the eleventh pixel electrode in a longitudinal direction of the data lines, wherein an emission color of each of the tenth subpixel, the eleventh subpixel and the twelfth subpixel is different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel. [000477] The display device according to embodiments of the present disclosure may further include a common electrode disposed on a plurality of pixel electrodes. [000478] The common electrode may include a plurality of common electrode holes in the first area. [000479] The display device according to embodiments of the present disclosure may further include an electronic device which is located below the substrate, overlaps with the first area, and perform a predetermined operation using light passing through the first area. [000480] The display device according to embodiments of the present disclosure may further includea second interlayer insulating layer on the substrate; a first planarization layer on the second interlayer insulating layer; and a second planarization layer on the first planarization layer, wherein the first metal layer is between the second interlayer insulating layer and the first planarization layer, and the second metal layer is between the first planarization layer and the second planarization layer. [000481] A display device according to embodiments of the present disclosure may include a substrate including a display area capable of displaying an image and a non-display area outside the display area, a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of pixel electrodes, and a plurality of data lines for supplying data signals for image display to the plurality of subpixels. [000482] The display area may include a first area capable of transmitting light and a second area located outside the first area. [000483] The second area may include an upper area above the first area and a lower area under the first area. [000484] The plurality of pixel electrodes may include a first pixel electrode disposed in the upper area and included in a first subpixel, a second pixel electrode disposed in the upper area and included in a second subpixel, a third pixel electrode disposed in the first area and included in a third subpixel, a fourth pixel electrode disposed in the first area and included in a fourth subpixel, a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel, [000485] The plurality of data lines may include a first data line extending from the upper area to the lower area passing through the first area, and connected to the first subpixel, the third subpixel, and the fifth subpixel, an upper data line disposed in the upper area and connected to the second subpixel, and a lower data line disposed in the lower area and connected to the sixth subpixel. [000486] The third pixel electrode and the fourth pixel electrode may be electrically connected to each other. [000487] The display device according to embodiments of the present disclosure may further include a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode. [000488] A display device according to embodiments of the present disclosure may include a substrate including a display area capable of displaying an image and a non-display area outside the display area; a plurality of subpixels included in the display area; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels, wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area, wherein a part of the plurality of data lines passes through the first area, and other of plurality of data lines bypass the first area. [000489] According to embodiments of the present disclosure as described above, it is possible to provide a display device having a light-transmitting structure which allows an electronic device to normally receive light (e.g., visible light, infrared light, or ultraviolet light) without exposing the electronic device receiving light to the front. [000490] According to embodiments of the present disclosure, it is possible to provide a display device capable of improving the transmittance of an optical area (i.e, a first area) through which light can pass through. [000491] According to embodiments of the present disclosure, it is possible to provide a display device having a structure to reduce the metal ratio in an optical area (i.e., a first area) through which light can be transmitted. [000492] According to embodiments of the present disclosure, it is possible to provide a display device having a panel structure capable of improving a detection performance of a detection sensor using light passing through an optical area (i.e., a first area). [000493] According to embodiments of the present disclosure, it is possible to provide a display device having a panel structure capable of improving a performance of a camera using light passing through an optical area (i.e., a first area). [000494] The above description and the accompanying drawings provide an example of the technical idea of the present disclosure for illustrative purposes only. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Thus, the scope of the present disclosure is not limited to the embodiments shown. [000495] The present disclosure further comprises the following clauses: Clause 1. A display device comprising: a substrate including a display area capable of displaying an image and a non-display area outside the display area; a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of light emitting devices; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels, wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area, wherein the second area comprises an upper area above the first area and a lower area under the first area, wherein the plurality of data lines comprises, an upper data line disposed in the upper area, a lower data line disposed in the lower area, and a bypass line configured to electrically connect the upper data line and the lower data line and bypass the first area. Clause 2. The display device of clause 1, wherein the plurality of data lines further comprises: a first data line extending from the upper area to the lower area. Clause 3. The display device of clause 1 or clause 2, wherein the bypass line comprises: a first bypass line connected to the upper data line; a second bypass line connected to the lower data line; and a third bypass line for connecting the first bypass line and the second bypass line. Clause 4. The display device of any preceding clause, wherein crossings between the bypass line and the upper data line along with the lower data line have connecting points. Clause 5. The display device of clause 3, wherein a first connecting point is formed at a crossing between the upper data line and the first bypass line, a second connecting point is formed at a crossing between the lower data line and the second bypass line, a third connecting point is formed at a crossing between the first bypass line and the third bypass line, and a fourth connecting point is formed at a crossing between the second bypass line and the third bypass line. Clause 6. The display device of any preceding clause, wherein the bypass line comprises a horizontal bypass line extending horizontally, and a vertical bypass line extending vertically. Clause 7. The display device of clause 6, wherein a first connecting point is formed at a crossing between the upper data line and the horizontal bypass line, a second connecting point is formed at a crossing between the lower data line and the horizontal bypass line, a third connecting point and a fourth connecting point are formed at crossings between the horizontal bypass line and the vertical bypass line respectively. Clause 8. The display device of clause 6 or clause 7, wherein the horizontal bypass line is disposed in a first metal layer, and the vertical bypass line is disposed in a second metal layer different from the first metal layer. Clause 9. The display device of clause 8, wherein the second metal layer is upper than the first metal layer. Clause 10. The display device of any of clauses 6-9, wherein the horitontal bypass line and the upper data line along with the lower data line form a mesh type. Clause 11. The display device of clause 8 or clause 9, further comprising a power line for applying a power voltage whose voltage level does not change depending on a frame change, and wherein the power line is disposed in the second metal layer. Clause 12. The display device of any preceding clause, wherein each of the plurality of light emitting devices includes a plurality of pixel electrodes, wherein the plurality of pixel electrodes comprises: a first pixel electrode disposed in the upper area and included in a first subpixel; a second pixel electrode disposed in the upper area and included in a second subpixel; a third pixel electrode disposed in the first area and included in a third subpixel; a fourth pixel electrode disposed in the first area and included in a fourth subpixel; a fifth pixel electrode disposed in the lower area and included in a fifth subpixel; and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel, wherein the upper data line is connected to the second subpixel, wherein the lower data line is connected to the sixth subpixel, and wherein the third pixel electrode and the fourth pixel electrode are electrically connected to each other. Clause 13. The display device of clause 12, wherein the plurality of data lines further comprises: a first data line extending from the upper area to the lower area, wherein the first data line is connected to the first subpixel, the third subpixel, and the fifth subpixel. Clause 14. The display device of clause 12 or clause 13, wherein an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel is the same. Clause 15. The display device of any of clauses 12-14, wherein each of the first subpixel, the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel includes a light emitting device and a subpixel circuit for driving the light emitting device, and the subpixel circuit includes two or more transistors, wherein the fourth subpixel includes a light emitting device, but does not include a subpixel circuit, and the light emitting device of the fourth subpixel is driven by a subpixel circuit of the third subpixel. Clause 16. The display device of clause 15, wherein a driving current output from the subpixel circuit of the third subpixel is supplied to the third pixel electrode and the fourth pixel electrode. Clause 17. The display device of any of clauses 12-16, further comprising a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode. Clause 18. The display device of any of clauses 12-17, wherein the plurality of pixel electrodes comprises: a seventh pixel electrode disposed in the upper area and included in a seventh subpixel; an eighth pixel electrode disposed in the second area and included in an eighth subpixel; and a ninth pixel electrode disposed in the lower area and included in the ninth subpixel, wherein an emission color of each of the seventh subpixel, the eighth subpixel and the ninth subpixel is different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel. Clause 19. The display device of clause 18, wherein the plurality of data lines comprises a second data line connected to the seventh subpixel, the eighth subpixel and the ninth subpixel. Clause 20. The display device of clause 19, wherein the second data line intersects and overlaps a portion in which the third pixel electrode and the fourth pixel electrode are connected. Clause 21. The display device of clause 19 or clause 20, wherein the plurality of data lines further comprises: a first data line extending from the upper area to the lower area, wherein, in the first area and the second area, the first data line and the second data line are disposed in the same metal layer and spaced apart from each other on the same plane. Clause 22. The display device of any of clauses 19-21, wherein the plurality of data lines further comprises: a first data line extending from the upper area to the lower area, wherein the first data line and the second data line are disposed in the same metal layer in the second area, wherein the first data line and the second data line are disposed on different metal layers in at least a partial area of the first area. Clause 23. The display device of clause 22, wherein, in the second area, the first data line and the second data line are disposed in the same metal layer and spaced apart from each other on the same plane, wherein the first area includes a transmission area and a non-transmission area, wherein the first data line and the second data line are disposed in different metal layers and overlap in a vertical direction in the transmission area, wherein the first data line and the second data line are disposed in the same metal layer and spaced apart from each other on the same plane in the non-transmission area. Clause 24. The display device of any of clauses 12-23, wherein the plurality of pixel electrodes comprises: a tenth pixel electrode disposed in the upper area and included in a tenth subpixel; an eleventh pixel electrode disposed in the first area and included in an eleventh subpixel; and a twelfth pixel electrode disposed in the lower area and included in the twelfth subpixel, wherein an emission color of each of the tenth subpixel, the eleventh subpixel and the twelfth subpixel is different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel. Clause 25. The display device of clause 24, wherein the plurality of data lines further include a third data line connected to the tenth subpixel, the eleventh subpixel, and the twelfth subpixel, wherein the third data line overlaps the tenth pixel electrode, wherein the third data line includes a protrusion, and the protrusion overlaps with the eleventh pixel electrode in a longitudinal direction of the data lines. Clause 26. The display device of any preceding clause, further comprising a common electrode disposed on a plurality of pixel electrodes, wherein the common electrode includes a plurality of common electrode holes in the first area. Clause 27. The display device of any preceding clause, further comprising an electronic device which is located below the substrate, overlaps with the first area, and perforin a predetermined operation using light passing through the first area. Clause 28. The display device of clause 8, 9 or 11, further comprising: a second interlayer insulating layer on the substrate; a first planarization layer on the second interlayer insulating layer; and a second planarization layer on the first planarization layer, wherein the first metal layer is between the second interlayer insulating layer and the first planarization layer, and the second metal layer is between the first planarization layer and the second planarization layer. Clause 29. A display device comprising: a substrate including a display area capable of displaying an image and a non-display area outside the display area; a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of pixel electrodes; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels, wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area, wherein the second area comprises an upper area above the first area and a lower area under the first area, wherein the plurality of pixel electrodes comprises, a first pixel electrode disposed in the upper area and included in a first subpixel, a second pixel electrode disposed in the upper area and included in a second subpixel, a third pixel electrode disposed in the first area and included in a third subpixel, a fourth pixel electrode disposed in the first area and included in a fourth subpixel, a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, and a sixth pixel electrode disposed in the lower area and included in the sixth subpixel, wherein the plurality of data lines comprises, an upper data line disposed in the upper area and connected to the second subpixel, and a lower data line disposed in the lower area and connected to the sixth subpixel, wherein the third pixel electrode and the fourth pixel electrode are electrically connected to each other. Clause 30. The display device of clause 29, wherein the plurality of data lines further comprises, a first data line extending from the upper area to the lower area, and connected to the first subpixel, the third subpixel, and the fifth subpixel. Clause 31. The display device of clause 29 or clause 30, further comprising a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode. Clause 32. A display device comprising: a substrate including a display area capable of displaying an image and a non-display area outside the display area; a plurality of subpixels included in the display area; and a plurality of data lines for supplying data signals for image display to the plurality of subpixels, wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area. Clause 33. The display device of clause 32, wherein the plurality of data lines bypass the first area.

Claims

1. A display device comprising:a substrate including a display area capable of displaying an image and a non-display area outside the display area;a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of light emitting devices; anda plurality of data lines for supplying data signals for image display to the plurality of subpixels,wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area,wherein the second area comprises an upper area above the first area and a lower area under the first area, wherein the plurality of data lines comprises, an upper data line disposed in the upper area, a lower data line disposed in the lower area, anda bypass line configured to electrically connect the upper data line and the lower data line and bypass the first area.

2. The display device of claim 1, wherein the plurality of data lines further comprises:a first data line extending from the upper area to thelower area.

3. The display device of claim 1 or claim 2, wherein the bypass line comprises:a first bypass line connected to the upper data line;a second bypass line connected to the lower data line; anda third bypass line for connecting the first bypass line and the second bypass line.

4. The display device of any preceding claim, wherein crossings between the bypass line and the upper data line along with the lower data line have connecting points, optionally wherein a first connecting point is formed at a crossing between the upper data line and the first bypass line, a second connecting point is formed at a crossing between the lower data line and the second bypass line, a third connecting point is formed at a crossing between the first bypass line and the third bypass line, and a fourth connecting point is formed at a crossing between the second bypass line and the third bypass line.

5. The display device of any preceding claim, whereinthe bypass line comprises a horizontal bypass lineextending horizontally, and a vertical bypass line extending vertically, optionally wherein a first connecting point is formed at a crossing between the upper data line and the horizontal bypass line, a second connecting point is formed at a crossing between the lower data line and the horizontal bypass line, a third connecting point and a fourth connecting point are formed at crossings between the horizontal bypass line and the vertical bypass line respectively.

6. The display device of claim 5, wherein the horizontal bypass line is disposed in a first metal layer, and the vertical bypass line is disposed in a second metal layer different from the first metal layer, optionally wherein the second metal layer is upper than the first metal layer.

7. The display device of claim 5 or claim 6, wherein the horitontal bypass line and the upper data line along with the lower data line form a mesh type.

8. The display device of claim 6, further comprising a power line for applying a power voltage whose voltage level does not change depending on a frame change, andwherein the power line is disposed in the second metal layer.

9. The display device of any preceding claim, wherein each of the plurality of light emitting devices includes a plurality of pixel electrodes,wherein the plurality of pixel electrodes comprises:a first pixel electrode disposed in the upper area and included in a first subpixel;a second pixel electrode disposed in the upper area and included in a second subpixel;a third pixel electrode disposed in the first area and included in a third subpixel;a fourth pixel electrode disposed in the first area and included in a fourth subpixel;a fifth pixel electrode disposed in the lower area and included in a fifth subpixel; anda sixth pixel electrode disposed in the lower area and included in the sixth subpixel,wherein the upper data line is connected to the second subpixel,wherein the lower data line is connected to the sixth subpixel, andwherein the third pixel electrode and the fourth pixel electrode are electrically connected to each other.

10. The display device of claim 9, wherein the plurality of data lines further comprises:a first data line extending from the upper area to the lower area,wherein the first data line is connected to the first subpixel, the third subpixel, and the fifth subpixel.

11. The display device of claim 9 or claim 10, wherein an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel, and the sixth subpixel is the same.

12. The display device of any of claims 9-11, wherein each of the first subpixel, the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel includes a light emitting device and a subpixel circuit for driving the light emitting device, and the subpixel circuit includes two or more transistors,wherein the fourth subpixel includes a light emitting device, but does not include a subpixel circuit, and the light emitting device of the fourth subpixel is driven by a subpixel circuit of the third subpixel, optionally wherein a driving current output from the subpixel circuitof the third subpixel is supplied to the third pixel electrode and the fourth pixel electrode.

13. The display device of any of claims 9-12, further comprising a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode.

14. The display device of any of claims 9-13, wherein the plurality of pixel electrodes comprises:a seventh pixel electrode disposed in the upper area and included in a seventh subpixel;an eighth pixel electrode disposed in the second area and included in an eighth subpixel; anda ninth pixel electrode disposed in the lower area and included in the ninth subpixel,wherein an emission color of each of the seventh subpixel, the eighth subpixel and the ninth subpixel is different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel.

15. The display device of claim 14, wherein the plurality of data lines comprises a second data lineconnected to the seventh subpixel, the eighth subpixel and the ninth subpixel.

16. The display device of claim 15, wherein:the second data line intersects and overlaps a portion in which the third pixel electrode and the fourth pixel electrode are connected; and / orthe plurality of data lines further comprises:a first data line extending from the upper area to the lower area,wherein, in the first area and the second area, the first data line and the second data line are disposed in the same metal layer and spaced apart from each other on the same plane.

17. The display device of claim 15 or claim 16, wherein the plurality of data lines further comprises:a first data line extending from the upper area to the lower area,wherein the first data line and the second data line are disposed in the same metal layer in the second area, wherein the first data line and the second data line are disposed on different metal layers in at least a partial area of the first area, optionally wherein, in the second area, the first data line and the second data lineare disposed in the same metal layer and spaced apart from each other on the same plane,wherein the first area includes a transmission area and a non-transmission area,wherein the first data line and the second data line are disposed in different metal layers and overlap in a vertical direction in the transmission area,wherein the first data line and the second data line are disposed in the same metal layer and spaced apart from each other on the same plane in the non-transmission area.

18. The display device of any of claims 9-17, wherein the plurality of pixel electrodes comprises:a tenth pixel electrode disposed in the upper area and included in a tenth subpixel;an eleventh pixel electrode disposed in the first area and included in an eleventh subpixel; anda twelfth pixel electrode disposed in the lower area and included in the twelfth subpixel,wherein an emission color of each of the tenth subpixel, the eleventh subpixel and the twelfth subpixel is different from an emission color of each of the first subpixel, the second subpixel, the third subpixel, the fourth subpixel, the fifth subpixel and the sixth subpixel, optionally wherein the plurality of data linesfurther include a third data line connected to the tenth subpixel, the eleventh subpixel, and the twelfth subpixel, wherein the third data line overlaps the tenth pixel electrode,wherein the third data line includes a protrusion, and the protrusion overlaps with the eleventh pixel electrode in a longitudinal direction of the data lines.

19. The display device of any preceding claim, further comprising a common electrode disposed on a plurality of pixel electrodes,wherein the common electrode includes a plurality of common electrode holes in the first area.

20. The display device of any preceding claim, further comprising an electronic device which is located below the substrate, overlaps with the first area, and perform a predetermined operation using light passing through the first area.

21. The display device of claim 6 or 8, further comprising:a second interlayer insulating layer on the substrate;a first planarization layer on the second interlayer insulating layer; anda second planarization layer onthefirstplanarization layer,wherein the first metal layer is between the second interlayer insulating layer and the first planarization layer, and the second metal layer is between the first planarization layer and the second planarization layer.

22. A display device comprising:a substrate including a display area capable of displaying an image and a non-display area outside the display area;a plurality of subpixels included in the display area, each of the plurality of subpixels including a plurality of pixel electrodes; anda plurality of data lines for supplying data signals for image display to the plurality of subpixels,wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area,wherein the second area comprises an upper area above the first area and a lower area under the first area, wherein the plurality of pixel electrodes comprises,a first pixel electrode disposed in the upper area and included in a first subpixel,a second pixel electrode disposed in the upper area and included in a second subpixel,a third pixel electrode disposed in the first area and included in a third subpixel,a fourth pixel electrode disposed in the first area and included in a fourth subpixel,a fifth pixel electrode disposed in the lower area and included in a fifth subpixel, anda sixth pixel electrode disposed in the lower area and included in the sixth subpixel,wherein the plurality of data lines comprises,an upper data line disposed in the upper area and connected to the second subpixel, anda lower data line disposed in the lower area and connected to the sixth subpixel,wherein the third pixel electrode and the fourth pixel electrode are electrically connected to each other.

23. The display device of claim 22, wherein the plurality of data lines further comprises,a first data line extending from the upper area to the lower area, and connected to the first subpixel, the third subpixel, and the fifth subpixel.

24. The display device of claim 22 or claim 23, further comprising a connection line which is disposed in the first area and electrically connects the third pixel electrode and the fourth pixel electrode.

25. A display device comprising:a substrate including a display area capable of displaying an image and a non-display area outside the display area;a plurality of subpixels included in the display area; anda plurality of data lines for supplying data signals for image display to the plurality of subpixels,wherein the display area comprises a first area capable of transmitting light and a second area located outside the first area, andwherein the plurality of data lines bypass the first area.148

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