Display device

Abstract

A display 100 comprising a pixel 101 array AA, data lines (Figure 1; 102), a data driver (Figure 1; 110), gate lines 103, gate drivers 120 and a level shifter (Figure 1; 140). The level shifter genera

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0135567, filed October, 07, 2024, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND Field

[0001] The present disclosure relates to a display device. Discussion of Related Art

[0002] Electroluminescent display devices are divided into inorganic light emitting display devices and organic light emitting display devices according to a material of a light emitting layer. An active-matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as an “OLED”) which emits light by itself, and has advantages in that a response speed is fast and luminous efficiency, luminance, and a viewing angle are large.

[0003] In organic light-emitting display devices, organic light-emitting diodes (referred to as "OLEDs") are formed in each of pixels. These organic light display devices not only respond quickly and have excellent light-emitting efficiency, luminance, and viewing angle, but also have excellent contrast ratio and color reproduction rate because they can express black tones as complete black.

[0004] Some of display devices, for example, a liquid crystal display device or an organic light emitting display device includes a display panel including a plurality of sub-pixels, a driver outputting a driving signal for driving the display panel, a power supply generating power to be supplied to the display panel or the driver, and the like. SUMMARY

[0005] In this case, the driver may include a gate driver that outputs a gate signal. A plurality of gate drivers may be arranged among pixels within a display area. Clock lines for applying a start signal and clock signals are connected to the plurality of gate drivers.

[0006] However, since the clock lines are connected to the plurality of gate drivers, the number of resistors and capacitors increases in proportion to the number of gate drivers connected to the clock lines, resulting in an increase in RC delay. As a result, the voltage level of the clock signal may fail to reach the voltage level required for the gate driver to operate normally, and thus the gate driver may not operate normally.

[0007] The present disclosure is directed to solving all the above-described necessity and problems.

[0008] The present disclosure provides a display device.

[0009] It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

[0010] A display device according to examples of the present disclosure may include a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged; a data driver configured to output data voltages to the plurality of data lines; a gate driver arranged among the plurality of pixels and configured to output gate signals to the plurality of gate lines; and a level shifter configured to generate first and second clock signals for the gate driver, wherein the gate driver comprises: a first gate driver arranged on odd-numbered column lines and configured to receive the first clock signal; and a second gate driver arranged on even-numbered column lines and configured to receive the second clock signal.

[0011] A display device according to examples of the present disclosure may include a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged; a data driver configured to output data voltages to the plurality of data lines; a scan driver arranged among the plurality of pixels and configured to output scan signals to the plurality of gate lines; an EM driver arranged among the plurality of pixels and configured to output emission control signals to the plurality of gate lines; and a level shifter configured to generate clock signals for the scan driver and the EM driver, wherein the EM driver comprises: a first EM driver arranged on odd-numbered column lines and configured to receive a first-phase clock signal; and a second EM driver arranged on even-numbered column lines and configured to receive a second-phase clock signal.

[0012] The present disclosure alternately arranges a plurality of gate drivers along column line for odd-numbered and even-numbered pixel lines, and separates clock lines connected to the alternately arranged gate drivers to apply different clock signals through the separated clock lines, thereby reducing RC delay of the clock lines.

[0013] The present disclosure may enable the gate driver to normally output a gate signal by reducing RC delay of the clock lines, thereby reducing power consumption and improving luminance uniformity within a panel.

[0014] The present disclosure may increase a pulse width of the clock signal to sufficiently secure a panel design margin and an operation margin of the gate driver.

[0015] The present disclosure may enable low-power driving because power consumption may be reduced.

[0016] The effects of the present specification are not limited to the above- mentioned effects, and other effects that are not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the attached drawings, in which:

[0017] FIGS. 1A and IB are block diagrams showing a display device according to an embodiment of the present disclosure;

[0018] FIG. 2 is a diagram illustrating an arrangement of the gate drivers shown in FIG. IB;

[0019] FIG. 3 is a diagram illustrating a gate driver according to an embodiment of the present disclosure;

[0020] FIGS. 4Ato 4D are diagrams for explaining operations of a gate driver according to a comparative example;

[0021] FIGS. 5Ato 5D are diagrams for explaining operations of a gate driver according to a first embodiment;

[0022] FIG. 6 is a diagram for explaining a principle of generating a clock signal according to the first embodiment;

[0023] FIG. 7 is a diagram showing gate lines connected to the gate driver shown in FIG. 5 A;

[0024] FIGS. 8A and 8B are diagrams for explaining operations of a gate driver according to a second embodiment;

[0025] FIG. 9 is a diagram for explaining a principle of generating a clock signal according to the second embodiment;

[0026] FIG. 10 is a diagram for comparatively explaining simulation results of a comparative example and the embodiments; and

[0027] FIGS. 11 and 12 are diagrams showing other arrangement structures of the gate driver. DETAILED DESCRIPTION

[0028] Advantages and features of the present specification and methods of achieving them will become apparent with reference to preferable embodiments, which are described in detail, in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments to be described below and may be implemented in different forms, the embodiments are only provided to completely disclose the present disclosure and completely convey the scope of the present disclosure to those skilled in the art, and the present specification is defined by the disclosed claims.

[0029] Since the shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated items. The same reference numerals indicate the same components throughout the specification. Further, in describing the present disclosure, when it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0030] When ‘including,’ ‘having,’ ‘consisting,’ and the like mentioned in the present specification are used, other parts may be added unless ‘only’ is used. A case in which a component is expressed in a singular form includes a plural form unless explicitly stated otherwise.

[0031] In interpreting the components, it should be understood that an error range is included even when there is no separate explicit description.

[0032] In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as ‘on,’ ‘at an upper portion,’ ‘at a lower portion,’ ‘next to, and the like, one or more other parts may be located between the two parts unless ‘immediately’ or ‘directly’ is used.

[0033] Although first, second, and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component, which is mentioned, below may also be a second component within the technical spirit of the present disclosure.

[0034] The same reference numerals may refer to substantially the same elements throughout the present disclosure.

[0035] The following embodiments can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways. The embodiments can be carried out independently of or in association with each other.

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] FIGS. 1A and IB are block diagrams showing a display device according to an embodiment of the present disclosure.

[0038] Referring to FIGS. 1A to IB, the display device according to an embodiment of the present disclosure includes a display panel 100, and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0039] The display panel 100 may be, but not limited to, a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a heterogeneous panel of which at least a portion is curved or elliptical.

[0040] The display area AA of the display panel 100 includes a pixel array to display an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may be commonly connected to pixel circuits to supply a voltage required for driving pixels 101 to the pixels 101.

[0041] Each of the pixels 101 may be divided into a red sub-pixel, a green subpixel, and a blue sub-pixel for color implementation. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element may include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to the data lines, the gate lines, and the power lines. In the following description, a pixel may be interpreted as a subpixel.

[0042] The display area AA includes a plurality of pixel lines LI to Ln. Each of the pixel lines LI to Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in one pixel line share the gate lines 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines LI to Ln.

[0043] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on the screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

[0044] The power supply 150 receives an input voltage applied from the host system 300 and outputs a voltage needed to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a direct current to direct current converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply 150 may output a constant voltage (or direct current voltage), such as gate-on voltage, gate-off voltage, pixel driving voltage, cathode voltage, reference voltage, IC driving voltage of the display panel driving circuit, through the DC-DC converter. The gate-on voltage and the gate-off voltage may be supplied to the level shifter 140 and the gate driver 120. Voltages such as pixel driving voltage, cathode voltage, and reference voltage may be supplied to the pixels 101 through the power lines commonly connected to the pixels 101.

[0045] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are subdivided by a voltage dividing circuit into grayscale voltages. The gamma voltage generator may be implemented with a programmable gamma circuit that may adjust the voltage of each of the gamma reference voltages according to digital data. The timing controller 130, the host system 300, or a separate external device may update digital data stored in a register of the programmable gamma circuit through a communication interface.

[0046] The display panel driving circuit writes pixel data of the input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0047] The display panel driving circuit may further include a touch sensor driver for driving touch sensors. The touch sensor driver is not shown in FIG. 1. The data driver 110 and the touch sensor driver may be integrated into one source drive IC.

[0048] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each grayscale through a voltage dividing circuit. The per-grayscale gamma compensation voltages are supplied to a digital to analog converter (hereinafter referred to as “DAC”) disposed in each channel of the data driver 110.

[0049] The data driver 110 samples and latches digital data received from the timing controller 130 and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting first mode and second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

[0050] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring lines of the display area AA. The gate driver 120 may be disposed in at least one of left and right non-display areas NA outside the display area AA in the display panel 100 or at least a part thereof may be disposed within the display area AA.

[0051] The gate driver 120 sequentially outputs pulses of the gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the pulses of the gate signals using shift registers. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal being input to the pixel circuit through a plurality of gate lines, and an emission signal (or EM signal).

[0052] The gate driver 120 may be disposed in Gate In Panel (GIP) fashion in the non-display area, or in Gate in Active area (GIA) fashion between subpixels SP in the display area AA. For example, as shown in FIG. IB, the circuit of the gate driver 120 may be located between the pixels 101 within the display area AA.

[0053] The timing controller 130 receives digital video data of an input image and a timing signal synchronized with this data from the host system 300. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and horizontal period may be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of 1 horizontal period (1H).

[0054] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 300. The timing controller 130 may synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0055] The gate timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 may convert a voltage of the gate timing control signal received from the timing controller 130 to a swing width between the gate-on voltage and the gate-off voltage and supply it to the gate driver 120.

[0056] The timing controller 130 may analyze the input image for each frame and generate a control signal for selectively outputting gate signals according to the analysis result. The generated control signal may be provided to the shift register of the gate driver 120 through the level shifter 140.

[0057] The host system 300 may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system 300 may scale an image signal from a video source according to the resolution of the display panel 100, and may transmit it to the timing controller 130 together with the timing signals.

[0058] FIG. 2 is a diagram illustrating an arrangement of the gate drivers shown in FIG. IB.

[0059] Referring to FIG. 2, a gate driver according to an embodiment of the present disclosure may include a first scan driver SCI, a second scan driver SC2, and an EM driver EM. The first scan driver SCI, the second scan driver SC2, and the EM driver EM are arranged among pixels and may be arranged in different regions.

[0060] The first scan driver SCI, the second scan driver SC2, and the EM driver EM may be arranged for each pixel line. For example, a first scan driver SC1(1), a second scan driver SC2(1), and an EM driver EM(1) are arranged on a first pixel line LI, a first scan driver SC 1(2), a second scan driver SC2(2), and an EM driver EM(2) are arranged on a second pixel line L2, a first scan driver SC 1(3), a second scan driver SC2(3), and an EM driver EM(3) are arranged on a third pixel line L3, a first scan driver SC 1(4), a second scan driver SC2(4), and an EM driver EM(4) are arranged on a fourth pixel line L4, and they may be arranged up to an (n)th pixel line Ln.

[0061] Here, although a clock line CL for applying a start signal and a clock signal to the first scan driver SCI, the second scan driver SC2, and the EM driver EM is shown as a single line for convenience, it may include a plurality of clock lines. For example, clock lines to which a start signal is applied and clock lines to which two-phase clock signals are respectively applied may be connected to the EM driver EM.

[0062] Since a plurality of the same gate drivers are arranged on each pixel line LI to Ln, a plurality of the first scan drivers SCI, the second scan drivers SC2, and the EM drivers EM may be arranged, respectively.

[0063] The same gate drivers arranged on each pixel line are connected to the same gate line. The plurality of first scan drivers SCI arranged on each pixel line may simultaneously apply a first scan signal to pixels through a first gate line, the plurality of second scan drivers SC2 may simultaneously apply a second scan signal to pixels through a second gate line, and the plurality of EM drivers EM may simultaneously apply an EM signal to pixels through a third gate line.

[0064] FIG. 3 is a diagram illustrating a gate driver according to an embodiment of the present disclosure. Here, the gate driver will be described as an example of the EM driver that outputs the EM signal.

[0065] Referring to FIG. 3, a gate driver according to an embodiment of the present disclosure may include a first transistor Tl, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor Til, a twelfth transistor or a pull-up transistor T12, a thirteenth transistor or a pull-down transistor T13, a first capacitor Cl, a second capacitor C2, and a third capacitor C3.

[0066] The first transistor Tl is turned on by a voltage of a clock signal ECLK2 and applies a start signal EVST or a previous carry signal to a first node nl. The first transistor T1 includes a gate electrode to which the clock signal ECLK2 is applied, a first electrode to which the start signal EVST is applied, and a second electrode connected to the first node nl.

[0067] The second transistor T2 is turned on by a voltage of a clock signal ECLK1 and connects the first node nl to a second node n2. The second transistor T2 includes a gate electrode to which the clock signal ECLK1 is applied, a first electrode connected to the first node nl, and a second electrode connected to the second node n2.

[0068] The third transistor T3 is turned on by a voltage of a third node n3 and connects a second node n2 to a first power line PL1 to which a high-potential voltage VGH is applied The third transistor T3 includes a gate electrode connected to the third node n3, a first electrode connected to the second node n2, and a second electrode connected to the first power line PL1.

[0069] The fourth transistor T4 is turned on by a low-potential voltage VGL and connects a first node nl to a first control node Q. The fourth transistor T4 includes a gate electrode connected to a second power line PL2 to which the low-potential voltage VGL is applied, a first electrode connected to the first node nl, and a second electrode connected to the first control node Q.

[0070] The fifth transistor T5 is turned on by a voltage of a clock signal ECLK2 and connects the second power line PL2 to the third node n3. The fifth transistor T5 includes a gate electrode to which a clock signal ECLK2 is applied, a first electrode connected to a second power line PL2, and a second electrode connected to a third node n3.

[0071] The sixth transistor T6 is turned on by a voltage of a first node nl and applies the clock signal ECLK2 to a third node n3. The sixth transistor T6 includes a gate electrode connected to the first node nl, a first electrode to which the clock signal ECLK2 is applied, and a second electrode connected to the third node n3. The sixth transistor T6 may be implemented as a dual-gate transistor, but is not limited thereto.

[0072] The seventh transistor T7 is turned on by a low-potential voltage VGL and connects a third node n3 and a fourth node n4. The seventh transistor T7 includes a gate electrode connected to a second power line PL2, a first electrode connected to a third node n3, and a second electrode connected to a fourth node n4.

[0073] The eighth transistor T8 is turned on by a voltage of a fourth node n4 and applies the clock signal ECLK1 to a fifth node n5. The eighth transistor T8 includes a gate electrode connected to the fourth node n4, a first electrode to which the clock signal ECLK1 is applied, and a second electrode connected to the fifth node n5.

[0074] The ninth transistor T9 is turned on by a voltage of the clock signal ECLK1 and connects a fifth node n5 and a second control node Qb. The ninth transistor T9 includes a gate electrode to which the clock signal ECLK1 is applied, a first electrode connected to the fifth node n5, and a second electrode connected to the second control node Qb.

[0075] The tenth transistor T10 is turned on by a voltage of a first node nl and connects a first power line PL1 to the second control node Qb. The tenth transistor T10 includes a gate electrode connected to the first node nl, a first electrode connected to the second control node Qb, and a second electrode connected to the first power line PL1.

[0076] The eleventh transistor Til is turned on by a voltage of the first control node Q and applies the clock signal ECLK1 to a sixth node n6. The eleventh transistor Til includes a gate electrode connected to the first control node Q, a first electrode to which the clock signal ECLK1 is applied, and a second electrode connected to the sixth node n6.

[0077] The twelfth transistor T12 is turned on by a voltage of the first control node Q and outputs a low-potential voltage VGL through an output node OUT. The twelfth transistor T12 includes a gate electrode connected to the first control node Q, a first electrode connected to the second power line PL2, and a second electrode connected to the output node OUT.

[0078] The thirteenth transistor T13 is turned on by a voltage of the second control node Qb and outputs a high-potential voltage VGH through the output node OUT. The thirteenth transistor T13 includes a gate electrode connected to the second control node Qb, a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0079] A first capacitor Cl is connected between the gate electrode and a source electrode of the eighth transistor T8. A second capacitor C2 is connected between the gate electrode of the twelfth transistor T12, which is connected to the first control node Q, and a source electrode of the eleventh transistor Til. The second capacitor C2 may be charged by the clock signal ECLK1. The third capacitor C3 is connected between the gate electrode the thirteenth transistor T13 connected to the second control node Qb and a source electrode of the thirteenth transistor T13. The third capacitor C3 may be charged by the high-potential voltage VGH.

[0080] FIGS. 4Ato 4D are diagrams for explaining operations of a gate driver according to a comparative example. Here, for convenience of explanation, only the arrangement of the EM driver will be described.

[0081] Referring to FIGS. 4A to 4D, an EM driver according to a comparative example is arranged among pixels within a display area and may be arranged on each pixel line LI to Ln, and may apply a gate signal EM(n) to pixels P arranged on the corresponding pixel line based on a start signal EVST and clock signals ECLK1 and ECLK2.

[0082] In this case, the clock signals ECLK1 and ECLK2 applied to the gate driver EM are used to charge the second capacitor C2 as shown in FIG. 3. Since the second capacitor C2 is present in every gate driver, the greater the number of gate drivers, the greater the number of second capacitors C2 to be charged, and in addition, a parasitic capacitor Cpara generated on a clock line also increases.

[0083] Since a plurality of gate drivers EM are present within an active area, as shown in FIG. 4C, resistors R and capacitors C, which include the second capacitor C2 and the parasitic capacitor Cpara, are present for each gate driver EM on the clock line CL to which the clock signals ECLK1 and ECLK2 are applied, causing an increase of RC delay of the clock line CL. As the distance from the point where the clock signal is applied increases, the RC delay becomes larger, and as a result, the RC delay becomes greatest at the farthest point P from the point where the clock signal is applied.

[0084] As shown in FIG. 4D, due to the RC delay of the clock line, the clock signals ECLK1 and ECLK2 fail to reach the high-potential voltage VGH and the low-potential voltage VGL required for the gate driver to operate normally, and therefore the gate driver fails to normally output a gate signal EM(n).

[0085] In a first embodiment, a plurality of EM drivers are alternately arranged along column lines for odd-numbered and even-numbered pixel lines in order to separate clock lines to which clock signals are applied.

[0086] FIGS. 5Ato 5D are diagrams for explaining operations of a gate driver according to a first embodiment. Here, for convenience of explanation, only the arrangement of the EM driver will be described.

[0087] Referring to FIGS. 5A to 5D, a gate driver according to the first embodiment of the present disclosure includes a plurality of EM drivers EMI and EM2, and the plurality of EM drivers EMI and EM2 may be alternately arranged, along column lines RI to Rm, for odd-numbered and even-numbered row lines or pixel lines LI to Ln. Here, m and n are natural numbers.

[0088] For example, the plurality of EM drivers may include a first EM driver EMI connected to a first clock line CL1 and a second EM driver EM2 connected to a second clock line CL2.

[0089] For example, a plurality of first EM drivers EMI may be arranged only on odd-numbered pixel lines LI on a first column line RI, a plurality of second EM drivers EM2 may be arranged only on even-numbered pixel lines L2 on a second column line R2, a plurality of first EM drivers EMI may be arranged only on odd-numbered pixel lines L3 on a third column line R3, and a plurality of second EM drivers EM2 may be arranged only on even-numbered pixel lines L4 on a fourth column line R4.

[0090] Different start signals and clock signals may be applied to the first EM driver EMI and the second EM driver EM2. For example, a first start signal EVST1 and two-phase first clock signals ECLK1 and ECLK3 may be applied to the first EM driver EMI, and a second start signal EVST2 and two-phase second clock signals ECLK2 and ECLK4 may be applied to the second EM driver EM2.

[0091] As shown in FIG. 5B, the first start signal EVST1 and the second start signal EVST2 each have a pulse width of 6H, and the first start signal EVST1 may start 1H earlier than the second start signal EVST2.

[0092] In addition, the first clock signals ECLK1 and ECLK3 and the second clock signals ECLK2 and ECLK4 each have a pulse width of 2H, and the first clock signals ECLK1 and ECLK3 have a phase difference of 180 degrees from each other, and the second clock signals ECLK2 and ECLK4 also have a phase difference of 180 degrees from each other. The first clock signals ECLK1 and ECLK3 may start 1H earlier than the second clock signals ECLK2 and ECLK4. The first clock signal ECLK1, the second clock signal ECLK2, the first clock signal ECLK3, and the second clock signal ECLK4 have a phase difference of 90 degrees from one another in that order.

[0093] Since a plurality of first and second gate drivers are present within an active area and are alternately arranged along column lines for odd-numbered and even-numbered pixel lines, the number of capacitors including the second capacitor C2 and the parasitic capacitor Cpara is reduced by half compared to the number of gate drivers, as shown in FIG. 5C.

[0094] In addition, since the four-phase clock signals are applied through two separated clock lines, the resistance of each clock line is reduced by half, and because four-phase clock signals are applied, the period and pulse width of each clock signal increase to 2H, not 1H.

[0095] In the gate driver according to the first embodiment, since the clock lines are separated into two clock lines, the number of the resistors and capacitors is reduced, and RC delay of the clock lines is also reduced.

[0096] FIG. 6 is a diagram for explaining a principle of generating a clock signal according to the first embodiment.

[0097] Referring to FIG. 6, a timing controller 130 according to the first embodiment may generate a first start signal EVSTF, first clock signals ECLKF and ECLK3' to be applied to a first EM driver, and a second start signal EVST2', and second clock signals ECLK2' and ECLK4' to be applied to a second EM driver, and provide them to a level shifter 140.

[0098] The level shifter 140 may amplify the voltage levels of the first start signal EVSTF, first clock signals ECLKF and ECLK3', second start signal EVST2', and second clock signals ECLK2' and ECLK4' provided from the timing controller 130, and supply the amplified first start signal EVST1 and first clock signals ECLK1 and ECLK3 to the first EM driver EMI through a first clock line, and supply the amplified second start signal EVST2 and second clock signals ECLK2 and ECLK4 to the second EM driver EM2.

[0099] In this case, the level shifter 140 may be implemented as a first level shifter that generates the first clock signals and a second level shifter that generates the second clock signals, but is not limited thereto.

[00100] A power supply 150 may supply a high-potential voltage VGH and a low-potential voltage VGL to the level shifter 140.

[00101] FIG. 7 is a diagram showing gate lines connected to the gate driver shown in FIG. 5A.

[00102] Referring to FIG. 7, a gate driver according to an embodiment of the present disclosure may include a first scan driver SCI, a second scan driver SC2, and an EM driver EM. The first scan driver SCI and the second scan driver SC2 may be arranged for each pixel line, and the EM driver EM may be alternately arranged for each pixel line along column lines.

[00103] For each pixel line, a plurality of first scan drivers SCI may be commonly connected to a first gate line GL1, second scan drivers SC2 may be commonly connected to a second gate line GL2, and EM drivers EM may be commonly connected to a third gate line GL3.

[00104] In a second embodiment, clock lines for applying clock signals to a plurality of EM drivers are separated, and different clock lines are applied depending on the column line in which the EM drivers are arranged.

[00105] FIGS. 8A and 8B are diagrams for explaining operations of a gate driver according to a second embodiment.

[00106] Referring to FIGS. 8A and 8B, a gate driver according to the second embodiment of the present disclosure may include a plurality of EM drivers EM, and the plurality of EM drivers EM may be connected to different clock lines CL1 and CL2 along column lines.

[00107] For example, the plurality of EM drivers EM may include a first EM driver EMI connected to a first clock line CL1 and a second EM driver EM2 connected to a second clock line CL2.

[00108] A first start signal EVST1 and two-phase first clock signals ECLK1 and ECLK2 may be applied to the first EM driver EMI, and a second start signal EVST2 and two-phase second clock signals ECLK3 and ECLK4 may be applied to the second EM driver EM2. The first start signal EVST1 and the second start signal EVST2 may be identical, the first clock signal ECLK1 and the second clock signal ECLK3 may be identical, and the first clock signal ECLK2 and the second clock signal ECLK4 may be identical.

[00109] As shown in FIG. 8B, the first start signal EVST1 and the second start signal EVST2 each have a pulse width of 3H and are identical to each other.

[00110] In addition, the first clock signals ECLK1 and ECLK3 and the second clock signals ECLK2 and ECLK4 each have a pulse width of 1H, the first clock signals ECLK1 and ECLK2 have a phase difference of 180 degrees from each other, and the second clock signals ECLK3 and ECLK4 have a phase difference of 180 degrees from each other. The first clock signal ECLK1 and the second clock signal ECLK2 may be identical, and the first clock signal ECLK2 and the second clock signal ECLK4 may be identical.

[00111] That is, in the second embodiment, the same start signal and clock signals are applied to different clock lines.

[00112] A plurality of the first and second gate drivers are present in an active area, and since they are connected to different clock lines along column lines, as shown in FIG. 5C, the number of capacitors including the second capacitor C2 and a parasitic capacitor Cpara is reduced by half compared to the number of gate drivers.

[00113] In addition, since the clock lines to which four-phase clock signals are applied are separated into two clock lines, the resistance of each clock line is reduced by half.

[00114] In the gate driver according to the first embodiment, since the clock lines are separated into two clock lines, the number of the resistors and capacitors is reduced, and therefore RC delay of the clock lines is also reduced.

[00115] FIG. 9 is a diagram for explaining a principle of generating a clock signal according to the second embodiment.

[00116] Referring to FIG. 9, a timing controller 130 according to the second embodiment generates a first start signal EVSTF, first clock signals ECLKF and ECLK2' to be applied to a first EM driver, and a second start signal EVST2', and second clock signals ECLK3' and ECLK4' to be applied to a second EM driver, and may provide them to a level shifter 140.

[00117] The level shifter 140 may amplify the voltage levels of the first start signal EVSTF, first clock signals ECLKF and ECLK2', second start signal EVST2', and second clock signals ECLK3' and ECLK4' provided from the timing controller 130, and supply the amplified first start signal EVST1 and first clock signals ECLK1 and ECLK2 to the first EM driver arranged on a panel 100 through a first clock line, and supply the amplified second start signal EVST2 and second clock signals ECLK3 and ECLK4 to the second EM driver arranged on the panel 100.

[00118] In this case, the level shifter 140 may be implemented as a first level shifter that generates the first clock signals and a second level shifter that generates the second clock signals, but is not limited thereto.

[00119] A power supply 150 may supply a high-potential voltage VGH and a low-potential voltage VGL to the level shifter 140.

[00120] FIG. 10 is a diagram for comparatively explaining simulation results of a comparative example and the embodiments.

[00121] Referring to FIG. 10, it illustrates waveforms of clock signals in a comparative example, in which the same clock signal ECLK is applied to all EM drivers within a display panel, and in an embodiment, in which different clock signals ECLK are applied to EM drivers that are alternately arranged along column lines.

[00122] In the comparative example, the clock signal reaches 78.05% of the target voltage, whereas in the embodiment, the clock signal reaches 99.98% of the target voltage, indicating that RC delay is reduced.

[00123] FIGS. 11 and 12 are diagrams showing other arrangement structures of the gate driver.

[00124] Referring to FIG. 11, not only the EM driver EM but also the first scan driver SCI and the second scan driver SC2 may be alternately arranged along column lines for odd-numbered and even-numbered pixel lines.

[00125] Referring to FIG. 12, only the first scan driver SCI and the second scan driver SC2, excluding the EM driver EM, may be alternately arranged along column lines on odd-numbered and even-numbered pixel lines.

[00126] A plurality of first scan drivers SCI for each pixel line may be commonly connected to a first gate line GL1, second scan drivers SC2 may be commonly connected to a second gate line GL2, and EM drivers EM may be commonly connected to a third gate line GL3.

[00127] In this configuration, as shown in FIG. 8A, the clock lines for the EM driver EM may be separated along column lines.

[00128] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A display device comprising:a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged;a data driver configured to output data voltages to the plurality of data lines;a gate driver arranged among the plurality of pixels and configured to output gate signals to the plurality of gate lines; anda level shifter configured to generate first and second clock signals for the gate driver,wherein the gate driver comprises:a first gate driver arranged on odd-numbered column lines and configured to receive the first clock signal; anda second gate driver arranged on even-numbered column lines and configured to receive the second clock signal.

2. The display device according to claim 1, further comprising:a first clock line configured to apply the first clock signal to the first gate driver; anda second clock line configured to apply the second clock signal to the second gate driver.

3. The display device according to any preceding claim, wherein the first gate driver is arranged on odd-numbered column lines and odd-numbered row lines, andthe second gate driver is arranged on even-numbered column lines and even-numbered row lines.

4. The display device according to claim 2 or 3, wherein the first clock signal and the second clock signal have different phases.

5. The display device according to any of claims 2 to 4, wherein each of the first clock signal and the second clock signal has a pulse width of 2H.

6. The display device according to claim 1 or 2, wherein the first gate driver is arranged on all row lines of odd-numbered column lines, andthe second gate driver is arranged on all row lines of even-numbered column lines.

7. The display device according to claim 6, wherein the first clock signal and the second clock signal have the same phase.

8. The display device according to claim 6 or 7, wherein each of the first clock signal and the second clock signal has a pulse width of 1H.

9. A display device comprising:a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged;a data driver configured to output data voltages to the plurality of data lines;a scan driver arranged among the plurality of pixels and configured to output scan signals to the plurality of gate lines;an EM driver arranged among the plurality of pixels and configured to output emission control signals to the plurality of gate lines; anda level shifter configured to generate clock signals for the scan driver and the EM driver,wherein the EM driver comprises:a first EM driver arranged on odd-numbered column lines and configured to receive a first-phase clock signal; anda second EM driver arranged on even-numbered column lines and configured to receive a second-phase clock signal.

10. The display device according to claim 9, further comprising:a first clock line configured to apply the first-phase clock signal to the first EM driver; anda second clock line configured to apply the second-phase clock signal to the second EM driver.

11. The display device according to claim 9 or 10, wherein the first EM driver is arranged on odd-numbered column lines and odd-numbered row lines, andthe second EM driver is arranged on even-numbered column lines and even-numbered row lines.

12. The display device according to any of claims 9 to 11, wherein the first-phase clock signal and the second-phase clock signal are four-phase clock signals.

13. The display device according to any of claims 9 to 12, wherein each of the first-phase clock signal and the second-phase clock signal has a pulse width of 2H.

14. The display device according to claim 9 or 10, wherein the first EM driver is arranged on all row lines of odd-numbered column lines, andthe second EM driver is arranged on all row lines of even-numbered column lines.

15. The display device according to any of claims 9, 10 or 14, wherein the first-phase clock signal and the second-phase clock signal are two-phase clock signals.

16. The display device according to any of claims 9, 10, 14 or 15, wherein each of the first-phase clock signal and the second-phase clock signal has a pulse width of 1H.

17. The display device according to any of claims 9 to 16, wherein the EM driver comprises:a first transistor to a thirteenth transistor, and a first capacitor to a third capacitor,wherein the first transistor includes a gate electrode to which a second clock signal is applied, a first electrode to which a start signal is applied, and a second electrode connected to a first node;the second transistor includes a gate electrode to which a first clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node;the third transistor includes a gate electrode connected to a third node, a first electrode connected to the second node, and a second electrode connected to a first power line to which a high-potential voltage is applied;the fourth transistor includes a gate electrode connected to a second power line to which a low-potential voltage is applied, a first electrode connected to the first node, and a second electrode connected to a first control node;the fifth transistor includes a gate electrode to which the second clock signal is applied, a first electrode connected to the second power line, and a second electrode connected to the third node;the sixth transistor includes a gate electrode connected to the first node, a first electrode to which the second clock signal is applied, and a second electrode connected to the third node;the seventh transistor includes a gate electrode connected to the second power line, a first electrode connected to the third node, and a second electrode connected to a fourth node;the eighth transistor includes a gate electrode connected to the fourth node, a first electrode to which the first clock signal is applied, and a second electrode connected to a fifth node;the ninth transistor includes a gate electrode to which the first clock signal is applied, a first electrode connected to the fifth node, and a second electrode connected to a second control node;the tenth transistor includes a gate electrode connected to the first node, a first electrode connected to the second control node, and a second electrode connected to the first power line;the eleventh transistor includes a gate electrode connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to a sixth node;the twelfth transistor includes a gate electrode connected to the first control node, a first electrode connected to the second power line, and a second electrode connected to an output node;the thirteenth transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line;the first capacitor is connected between a gate electrode and a source electrode of the eighth transistor;the second capacitor is connected between a gate electrode of the twelfth transistor and a source electrode of the eleventh transistor; andthe third capacitor is connected between a gate electrode and a source electrode of the thirteenth transistor.T +44(0)30 0300 2000A

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