Semiconductor device having germanium region disposed in semiconductor substrate

Abstract

PURPOSE: To provide a semiconductor device having a germanium region disposed in a semiconductor substrate.SOLUTION: A single-photon avalanche detector (SPAD) device includes a silicon substrate including a recess in an upper surface of the silicon substrate. A p-type region is arranged in the silicon substrate below a lower surface of the recess. An n-type avalanche region is arranged in the silicon substrate below the p-type region and meets the p-type region at a p-n junction. A germanium region is disposed within the recess over the p-n junction.SELECTED DRAWING: Figure 1

Description

Background Art

[0001] A single-photon avalanche diode (SPAD) is a solid-state photodetector in the same family as a photodiode and an avalanche photodiode (APD). Similar to photodiodes and APDs, SPADs are based on a semiconductor p-n junction that can be illuminated by ionizing radiation such as gamma, X-rays, beta, and / or alpha through ultraviolet (UV) to visible wavelengths and infrared (IR) along a wide portion of the electromagnetic spectrum. During operation, photo-generated carriers are accelerated by the device's electric field to a kinetic energy sufficient to overcome the ionization energy of the bulk material, knocking electrons out of the atoms of the bulk material. A large avalanche of current carriers grows exponentially and can be triggered from just a single photon-initiated carrier. SPADs can detect a single photon that provides a countable short-time trigger pulse. However, because of the fast rate at which the avalanche occurs, they can also be used to obtain the arrival time of incident photons.

Summary of the Invention

Problems to be Solved by the Invention

[0002] A Germanium single-photon avalanche diode (Ge-SPAD) is a type of SPAD for operating in the eye-safe short-wave infrared (SWIR) region, but germanium itself has high dark count rate (DCR) material characteristics, especially at room temperature or above.

Means for Solving the Problems

[0003] The present invention provides, in some embodiments, a single-photon avalanche detector (SPAD) device comprising a silicon substrate, a p-type region, an n-type avalanche region, and a germanium region. The silicon substrate includes a recess within its upper surface. The p-type region is located in the silicon substrate below the lower surface of the recess. The n-type avalanche region is located in the silicon substrate below the p-type region and is in contact with the p-type region at the pn junction. The germanium region is located in the recess above the pn junction.

[0004] The present invention also provides, in some embodiments, a semiconductor structure comprising a semiconductor substrate, a silicon-based multiplication region, a germanium-based absorption region, and an electron channel. The silicon-based multiplication region is provided within the semiconductor substrate. The germanium-based absorption region is provided within the semiconductor substrate and is located above the silicon-based multiplication region. The electron channel is located between the silicon-based multiplication region and the germanium-based absorption region.

[0005] The present invention further provides a method in several embodiments. A semiconductor substrate is received. Ion implantation is performed to form a lateral connection region beneath the upper surface of the semiconductor substrate. Another ion implantation is performed to form a vertical connection region, and the vertical and lateral connection regions come into contact with each other to form a guard ring. A recess is formed within the upper surface of the semiconductor substrate, the recess is laterally surrounded by the guard ring and defined by the recessed upper surface of the semiconductor substrate and the inner sidewall of the semiconductor substrate. A germanium region is formed in the recess. [Effects of the Invention]

[0006] Various embodiments of the present invention utilize a separate absorption and multiplication (SAM) structure embedded for commercial use. [Brief explanation of the drawing]

[0007] The accompanying drawings are included to further illustrate the principles of the present invention, are incorporated herein, and constitute part thereof. The drawings illustrate embodiments of the present invention and, together with the description, serve to illustrate the principles of the present invention.

[0008] [Figure 1] Figure 1 is a cross-sectional view of several embodiments of an integrated chip having a SPAD device including a germanium region embedded in a silicon substrate. [Figure 2] Figure 2 is a cross-sectional view of several embodiments of an integrated chip having a SPAD device including a germanium region embedded in a silicon substrate. [Figure 3] Figure 3A is a cross-sectional view of several embodiments of an integrated chip having a SPAD device including a germanium region embedded in a silicon substrate. Figure 3B is a bandgap diagram of several embodiments of the SPAD device consistent with Figure 3A. [Figure 4] Figure 4 is a cross-sectional view of several embodiments of an integrated chip having multiple SPAD devices, each containing a germanium region embedded in a silicon substrate. [Figure 5] Figure 5 is a cross-sectional view of several embodiments of an integrated chip having multiple SPAD devices, each containing a germanium region embedded in a silicon substrate. [Figure 6] This shows a manufacturing flow according to several embodiments. [Figure 7] This shows a manufacturing flow according to several embodiments. [Figure 8] This shows a manufacturing flow according to several embodiments. [Figure 9] This shows a manufacturing flow according to several embodiments. [Figure 10] This shows a manufacturing flow according to several embodiments. [Figure 11] This shows a manufacturing flow according to several embodiments. [Figure 12]It shows the manufacturing flow according to some embodiments. [Figure 13] It shows the manufacturing flow according to some embodiments. [Figure 14] It shows the manufacturing flow according to some embodiments. [Figure 15] It shows another manufacturing flow according to another embodiment. [Figure 16] It shows another manufacturing flow according to another embodiment. [Figure 17] It shows another manufacturing flow according to another embodiment. [Figure 18] It shows another manufacturing flow according to another embodiment. [Figure 19] It shows another manufacturing flow according to another embodiment. [Figure 20] It shows another manufacturing flow according to another embodiment. [Figure 21] It shows another manufacturing flow according to another embodiment. [Figure 22] It shows another manufacturing flow according to another embodiment. [Figure 23] It shows another manufacturing flow according to another embodiment. [Figure 24] It shows another manufacturing flow according to another embodiment. [Figure 25] It shows another manufacturing flow according to another embodiment. [Figure 26] It shows another manufacturing flow according to another embodiment. [Figure 27] It shows another manufacturing flow according to another embodiment. [Figure 28] It shows another manufacturing flow according to another embodiment. [Figure 29] It shows another manufacturing flow according to another embodiment. [Figure 30] It is a flowchart of the manufacturing flow according to some embodiments.

Best Mode for Carrying Out the Invention

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. For the sake of simplifying this disclosure, specific examples of components and arrangements are described below. These are of course merely examples and are not intended to be limiting. For example, the formation on top of the first feature or on top of the second feature in the following description includes embodiments where the first and second features are formed so as to directly contact each other, and also embodiments where the first and second features do not directly contact each other and additional features are formed between the first feature and the second feature. Further, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and in itself does not indicate a relationship between the various embodiments and / or configurations being discussed.

[0010] Figure 1 shows a single-photon avalanche detector (SPAD) device 100 according to several embodiments. The SPAD device 100 includes a silicon substrate 102 with a recess 104 within its upper surface 102u. A p-type region 106 is located in the silicon substrate below the lowest part of the recess 104. An n-type avalanche region 108 is located in the silicon substrate 102 below the p-type region 106 and is in contact with the p-type region 106 at a pn junction 110 corresponding to a photodiode in the silicon substrate 102. A germanium region 112 is located within the recess 104. The upper surface of the germanium region 112 may be located at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), horizontal to the upper surface 102u of the substrate (see 112ul), or at a height (h) above the upper surface 102u of the substrate. In some embodiments, a specific silicon region 118 may be located between the top of the p-type region 106 and the bottom of the germanium region 112. The specific silicon region 118 is configured to act as an electron channel between the pn junction 110 and the germanium region 112. The bias circuit 150 is configured to apply a bias to the pn junction 110 to apply a voltage greater than the avalanche yield voltage to the SPAD device 100, and is also configured to suppress the SPAD device 100 after an avalanche occurs. The bias circuit 150 can be implemented using a transistor and / or other active or passive elements located on or in the silicon substrate 102, or in another substrate.

[0011] In some cases, the germanium region 112 contacts the silicon substrate 102 at the Ge-Si interface region 117. The Ge-Si interface region 117 is defined where the outer wall and lower surface of the germanium region 112 contact the inner side wall and recessed upper surface of the silicon substrate 102, respectively. This Ge-Si interface region 117 is composed of a Ge-Si alloy having a lattice constant in the range of 56.6 nm to 54.3 nm. In some cases, the Ge-Si alloy can have a thickness in the range of 1 angstrom to 20 nm and can have a U-shaped cross-section.

[0012] The n-type lateral connection region 114 extends laterally from the outer edge of the pn junction 110, passing through the outer wall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116 laterally surrounds the germanium region 112 when viewed from above, so the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as "guard rings". In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116, when viewed in cross-section, typically form a U-shaped cross-sectional contour that encloses the p-type region 106 and the germanium region 112.

[0013] During operation, the bias circuit 150 biases the pn junction 110 above the avalanche breakdown voltage. Under this bias condition, when an incident photon 152 (e.g., from a laser pulse) is absorbed in the absorption region 113 corresponding to the germanium region 112, an electron-hole pair is generated, and electrons flow through the intrinsic silicon region 118 into the multiplication region 115, which includes the pn junction 110. The electrons are then accelerated in the multiplication region 115, gain sufficient kinetic energy, and are collidially ionized, generating a second electron-hole pair. The second electron and second electron-hole pair are similarly accelerated and collidily ionized, generating further electron-hole pairs in the multiplication region 115. Further collidily ionization of holes and electrons rapidly generates a large avalanche current, allowing the device to stand on its own when biased above the avalanche breakdown voltage. In these situations, a detectable electron signal is obtained that can be time-tuned relative to the initial incident photon 152 (e.g., from the generation of a laser pulse). After detection, the bias circuit 150 briefly biases the SPAD device 100 below the avalanche breakdown voltage to suppress the avalanche, after which the SPAD device 100 returns to its stationary state and is ready to detect further incident photons.

[0014] In particular, by positioning the germanium region 112 in the recess 104 within the upper surface 102u of the silicon substrate 102, the dark current rate (DCR) can be reduced in some respects compared to other methods. Furthermore, the germanium region 112 also improves the absorption (detection) of short-wavelength infrared (SWIR) signals, which do not occur in pure silicon-based SPADs. Therefore, the SPAD device 100 is germanium (Ge) in a silicon (Si)SAM device. In this device, forming the germanium region 112 in the recess 104 of the silicon substrate 102 provides several advantages, rather than simply acting as a plateau on the upper surface of the substrate.

[0015] Figure 2 shows another embodiment of the SPAD device 100 according to several embodiments. The SPAD device 100 similarly includes a silicon substrate 102 with a recess 104 within its upper surface 102u. A p-type region 106 is located in the silicon substrate below the lowest part of the recess 104. An n-type avalanche region 108 is located in the silicon substrate 102 below the p-type region 106 and is in contact with the p-type region 106 at a pn junction 110. A germanium region 112 is located in the recess 104.

[0016] The n-type lateral connection region 114 extends laterally from the outer edge of the pn junction 110 and passes through the outer wall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116 laterally surrounds the germanium region 112 when viewed from above, so the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as "guard rings". In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116 jointly form a U-shaped cross-sectional contour that typically encloses the p-type region 106 and the germanium region 112 when viewed in cross-section.

[0017] In some embodiments, the SPAD device further includes a p-type surface region 120 aligned with the recess 104 and laterally surrounding a specific silicon region 118. The p-type surface region is made of silicon, such as single-crystal silicon. The p-type surface region 120 includes a base portion 120b having a central opening corresponding to the specific silicon region 118, and includes a sidewall portion 120s extending upward along the outer wall of the germanium region 112 (and / or the inner sidewall of the recess 104 in the silicon substrate).

[0018] In some embodiments, the germanium region 112 further includes a bulk region corresponding to the absorption region 113, and both the bulk region and the absorption region 113 are intrinsic (undoped) germanium. The sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112. The sidewall germanium region 126 is also p-type. The p-type surface region 120 and the sidewall germanium region help reduce leakage, thereby mitigating dark currents caused by stresses and shear forces occurring in the Ge-Si interface region.

[0019] The cap 128, for example, a p-type silicon cap, is positioned on the upper surface of the germanium region 112 to limit / prevent oxidation of the top surface of the germanium region 112. In the illustrated example, the cap 128 has an upper surface that is coplanar or horizontal with the upper surface 102u of the silicon substrate; however, in other cases, the upper surface of the cap 128 may be recessed below the upper surface of the silicon substrate, horizontal with the uppermost surface of the silicon substrate, or raised above the upper surface of the silicon substrate. Furthermore, in the illustrated embodiment, the cap 128 has a lower surface that is in direct contact with and coplanar or horizontal with the upper surfaces of the bulk germanium region and the sidewall germanium region 126. However, in another embodiment, the sidewall germanium region 126 is positioned within the outer edge of the recess 104 and extends upward along the outer wall of the cap 128, becoming horizontal with the upper surface 102u of the silicon substrate 102.

[0020] The dielectric structure 132 may be made of, for example, a silicon diode or a low dielectric material and is stretched over the upper surface 102u of the substrate. Conductive contacts 134, for example, metal contacts, are stretched through the dielectric structure 132, and a metal wire or conductive pad 136 is formed on the conductive contacts. The metal wire or conductive pad 13 is operably coupled to a bias circuit (e.g., bias circuit 150 in Figure 1) and may include a semiconductor device formed on the silicon substrate 102 or another silicon substrate. For example, if the semiconductor device is formed on the silicon substrate 102, the semiconductor device may include a transistor with fins and / or gate electrodes located on the upper surface 102u of the substrate, or a transistor with fins and / or gate electrodes located on the lower surface 102l of the substrate, in which case through silicon vias may be stretched through the substrate to facilitate operable coupling.

[0021] Referring to Figure 3A, in some embodiments, the germanium region 112 includes an upper germanium region 122 having a first p-type doping concentration, an intermediate germanium region 124 having a second p-type doping concentration, and a bottom germanium region 130 having a third p-type doping concentration or being intrinsic (undoped) germanium. The second p-type doping concentration is lower than the first p-type doping concentration, and if non-zero dopant levels are present, the third p-type doping concentration is lower than the second p-type doping concentration. In some cases, the first, second, and / or third p-type doping concentrations are substantially uniform / constant over their respective depths in the upper germanium region 122, the intermediate germanium region 124, and the bottom germanium region 130, but in other cases, these doping concentrations exhibit a clear "kink" or discontinuity at the upper and lower edges of each region shown in Figure 3A. In other cases, the change in doping concentration is more stepwise and / or continuous over the entire depth of the germanium region 112. In some embodiments, the sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112 and crosses the upper germanium region 122, the intermediate germanium region 124, and the bottom germanium region 130. By using these doping regions shown in Figure 3A, carriers flow more efficiently into the pn junction 110, which helps to facilitate the lensing function of the SPAD device and improve jitter performance.

[0022] Figure 3B shows an example of a band diagram consistent with several embodiments of the SPAD device in Figure 3A. The band diagram includes the conduction band 350 and the valence band 352, with the left portion of the band diagram corresponding to n-type materials (e.g., n-type avalanche region 108) and the right portion corresponding to p-type materials (e.g., p+ germanium). The Fermi level of the device is indicated by line 354. As shown in the figure, at the interface between the absorption region 113 and the multiplication region 115, interface states and / or deep traps are located near the silicon / germanium heterojunction, and these traps cause discontinuities in the valence and conduction bands. In particular, the valence band exhibits an S-shaped curve in the multiplication region 115, showing a steep (e.g., vertical) rise at the interface between the absorption region 113 and the multiplication region 115, and then having a “dip” within the absorption region before returning to the maximum valence band energy. The conduction band also includes an S-shaped curve in the multiplication region 115, but in this case, the uppermost part of the S-shaped curve corresponds to a peak or apex, and before returning to the maximum conduction band energy, it corresponds to a "dip" in the absorption region.

[0023] Figures 4 and 5 show several embodiments in which the first and second SPAD devices are arranged side-by-side with the silicon substrate. In Figures 4 and 5, the first SPAD device 100a and the second SPAD device 100b each have the features described in Figure 2, and the features shown in a and b have the same or similar structures and functions as those described in Figure 2 (for example, 102a and 102b in Figures 4 and 5 correspond to 102 in Figure 2, and 106a and 106b in Figures 4 and 5 correspond to 106 in Figure 2). Therefore, in Figures 4 and 5, the first n-type vertical connection region 116a laterally surrounds the germanium region 112a of the first SPAD device 100a, and the second n-type vertical connection region 116b laterally surrounds the germanium region 112b of the second SPAD device 100b. A portion of the silicon substrate 402 separates the first n-type vertical connection region 116a from the second n-type vertical connection region 116b. In the embodiment of Figure 4, this portion of the silicon substrate may be intrinsic single-crystal silicon. In Figure 5, an isolation structure 502, for example, a deep trench isolation structure made of a dielectric material or containing p-type silicon, separates the first n-type vertical connection region 116a from the second n-type vertical connection region 116b. It should be understood that any number of SPAD devices can be arranged on the silicon substrate, for example, in an array containing several rows and columns. Also, while Figures 4 and 5 show an example where the first SPAD device 100a and the second SPAD device 100b correspond to the SPAD device 100 of Figure 2, in another embodiment, the first SPAD device 100a and the second SPAD device 100b may correspond to the SPAD device 100 of Figure 1 or Figure 3A, and / or other illustrated embodiments, and / or combinations thereof.

[0024] Figures 6 to 14 show manufacturing flows according to several embodiments. While Figures 6 to 14 will be described in relation to the methods, the structures disclosed in Figures 6 to 14 are not limited to these methods and may be independent structures unrelated to the methods.

[0025] In Figure 6, a base semiconductor substrate 600 is received, and sacrificial oxide 602 is formed on the upper surface of the semiconductor substrate. In some embodiments, the base semiconductor substrate 600 is a single-crystal silicon wafer, but in other embodiments, the semiconductor substrate may be of other shapes. For example, the base semiconductor substrate 600 may be silicon on an insulating substrate, a sapphire substrate, or a III-V substrate. The sacrificial oxide 602 may be silicon dioxide or other silicon oxides, such as silicon oxynitride. The sacrificial oxide 602 can be formed by thermal oxidation, fast thermal annealing, plasma deposition, chemical deposition, spin-on, or other techniques. In some embodiments, the sacrificial oxide 602 has a thickness in the range of 30 angstroms to 300 angstroms or 75 angstroms to 120 angstroms, or about 90 angstroms.

[0026] In Figure 7, a blanket p-type implantation, such as boron, aluminum, or indium, is performed to form a p-type region 138 embedded in the semiconductor substrate. Then, with the first photoresist mask in a predetermined position, an n-type implantation, such as phosphorus, arsenic, or antimony, is performed to form an n-type avalanche region 108 and an n-type lateral connection region 114.

[0027] In Figure 8, in some cases, sacrificial oxides are removed and an epitaxial single-crystal silicon region 900 is epitaxially formed on the upper surface of the base semiconductor substrate 600, thereby providing a single-crystal silicon substrate. In some embodiments, the removal of sacrificial oxides and the epitaxial formation of the epitaxial single-crystal silicon region 900 are performed in situ. In situ processing helps to ensure that there are no oxides on the semiconductor substrate, thus promoting high-quality crystal growth with few or no defects. Then, another sacrificial oxide layer 902 is formed on the epitaxial single-crystal silicon region 900. In some cases, the sacrificial oxide layer 902 is formed by an in-situ steam generation (ISSG) process, but it may also be formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In some embodiments, the sacrificial oxide layer 902 has a thickness in the range of 30 angstroms to 300 angstroms or 75 angstroms to 120 angstroms, or about 90 angstroms.

[0028] Subsequently, as shown in Figure 8, a second photoresist mask 1002 is formed on the sacrificial oxide layer 902, and with the second photoresist mask in a predetermined position, n-type implantation, for example, phosphorus, arsenic, or antimony implantation is performed to form an n-type vertical connection region 116. Figure 8 shows the case where the outer edge of the n-type vertical connection region 116 is aligned with the outer edge of the n-type lateral connection region 114, but in another embodiment, there may be a slight misalignment between these outer edges, so the edge of the n-type lateral connection region 114 may be shifted to the left or right relative to the outer edge of the n-type vertical connection region 116.

[0029] In Figure 9, for example, an un-doped silicate glass (USG) region having a thickness in the range of 200 angstroms to 1200 angstroms is formed. Then, a third photoresist mask (not shown) is formed, and etching is performed with the third photoresist mask in a predetermined position to form a recess 104 in the upper surface of the silicon substrate 102. In some cases, the recess 104 may have a depth d of about 1 μm. For example, another oxide layer 1102 having a thickness in the range of 500 angstroms to 1000 angstroms may be formed by in-situ water vapor generation (ISSG), which is aligned with the lower surface and sidewalls of the recess 104 and extends onto the upper surface of the semiconductor substrate.

[0030] In Figure 10, a fourth photomask 1202 is formed to create a p-type region 106. The p-type region 106 is formed at a depth d below the recessed surface, and because it leaves a gap below the recessed surface, a unique silicon region can be left between the p-type region and the recessed surface.

[0031] In Figure 11, a p-type surface region 120 is formed within the semiconductor substrate, leaving a unique silicon region 118 above the p-type region 106. Furthermore, a germanium region 112 is formed, for example, by epitaxial growth. The germanium region 112 is formed to have a recessed upper surface below the upper surface of the silicon substrate 102. However, in another embodiment, the germanium region 112 may be formed to have an upper surface that is horizontal to or raised above the upper surface of the silicon substrate 102. In some cases, as the germanium grows, the germanium region 112 forms a thin alloy on the silicon substrate, so the germanium region contacts the silicon substrate 102 at the Ge-Si interface region. The Ge-Si interface region is defined where the outer wall and lower surface of the germanium region contact the inner side wall and recessed upper surface of the silicon substrate, respectively.

[0032] In Figure 12, a cap 128 is formed on the germanium region 112. The formation of the cap 128 can be carried out by an epitaxial growth process, which can be completed in situ (for example, with the same tools used to form the germanium region 112, in a controlled environment such as vacuum or nitrogen) to limit the oxidation of the germanium region 112. In some cases, the cap 128 may be epitaxially grown p-type single-crystal silicon and have a raised upper surface above the upper surface of the substrate, although the upper surface of the cap may be horizontal to or below the upper surface of the substrate. Then, an oxide 1502 can be formed on the cap 128, for example, via fast thermal annealing or as a native oxide.

[0033] In Figure 13, a different ion implantation process is performed to form the p-type sidewall germanium region 126. In some cases, a different photomask is formed before this ion implantation, and then, with the photomask in place, this ion implantation is performed to form the p-type sidewall germanium region 126.

[0034] In Figure 14, a dielectric structure 132 is formed on the upper surface of the silicon substrate 102. Contact openings are formed through the dielectric structure 132 and conductive contacts 134 such as metal contacts, and a metal wire or conductive pad 136 is formed on the conductive contacts. The metal wire or conductive pad 136 may be operably coupled to a bias circuit, which may include a semiconductor device formed on the silicon substrate 102 or on another semiconductor substrate. For example, when the semiconductor device is formed on a semiconductor substrate, the semiconductor device may include a transistor with fins and / or gate electrodes located on the upper surface of the substrate, or a transistor with fins and / or gate electrodes located on the lower surface of the substrate, in which case through-silicon electrodes can be extended through the substrate to facilitate operable coupling.

[0035] Figures 15 to 21 show alternative manufacturing flows according to several embodiments. In contrast to Figures 6 to 14, which show the formation of a single SPAD device, Figures 15 to 21 show first and second SPAD devices formed directly adjacent to each other. The structures disclosed in Figures 15 to 21 are not limited to these methods and may be independent structures unrelated to the methods.

[0036] In Figure 15 (corresponding in some respects to Figures 6-8), a base semiconductor substrate 600 is received, and a p-type region 138 embedded in the semiconductor substrate is formed using blanket p-type implantation. For example, an n-type lateral connection region 114 is also formed by forming a photomask and performing ion implantation. An epitaxial single-crystal silicon region 900 is formed on the upper surface of the base semiconductor substrate 600, and an n-type vertical connection region 116 is formed. In this example, the first and second n-type vertical connection regions 116a and 116b are separated laterally by isolation regions of the semiconductor substrate. A sacrificial oxide 1802 is formed on the upper surface of the epitaxial single-crystal silicon region 900.

[0037] In Figure 16 (which in some respects corresponds to Figure 9), an undoped silicate glass (USG) region having a thickness in the range of 200 angstroms to 1200 angstroms is formed. Then, a third photoresist mask 1902 is formed, and etching is performed with the third photoresist mask in a predetermined position to form a recess 104 in the upper surface of the silicon substrate. In some cases, the recess may have a depth d of about 1 μm. For example, another oxide layer 1102 aligned in a line with the lower surface and sidewalls of the recess may be formed by in-situ water vapor generation (ISSG).

[0038] In Figure 17 (which in some respects corresponds to Figure 11), p-type regions 106a and 106b, a p-type sidewall portion 120a, and a p-type base portion 120b are formed within the semiconductor substrate. The p-type regions 106a and 106b are formed at a depth d below the recessed surface, thereby leaving intrinsic silicon regions 118a and 118b between the p-type regions and the recessed surface.

[0039] In Figure 18 (which in some respects corresponds again to Figure 11), for example, germanium regions 112a and 112b are formed by epitaxial growth. The germanium regions are formed to have an upper surface recessed below the upper surface of the silicon substrate. However, in another embodiment, the germanium regions may be formed to have an upper surface that is horizontal to or raised above the upper surface of the silicon substrate. In some cases, as the germanium grows, the germanium regions 112a and 112b form a thin alloy on the silicon substrate, so the germanium regions contact the silicon substrate 102 in the Ge-Si interface region. The Ge-Si interface region is defined where the outer wall and lower surface of the germanium region contact the inner side wall and recessed upper surface of the silicon substrate, respectively.

[0040] In Figure 19 (which in some respects corresponds to Figure 12), silicon caps 128a and 128b are formed on germanium regions 112a and 112b, respectively. The formation of the silicon caps can be carried out by an epitaxial growth process, which can be completed in situ (for example, in a controlled environment such as vacuum or nitrogen, in the same way as when the germanium regions were formed), thereby limiting the oxidation of the germanium regions. In some cases, the epitaxially grown silicon caps are p-type. Then, oxides can be formed on the silicon caps, for example, via fast thermal annealing or as native oxides.

[0041] In Figure 20 (which in some respects corresponds to Figure 13), another ion implantation process is performed to form p-type germanium regions 126a and 126b. In some cases, a separate photomask is formed before this ion implantation, and then the ion implantation is performed with the photomask in a predetermined position.

[0042] In Figure 21 (which in some respects corresponds to Figure 14), a dielectric is formed on the upper surface of the substrate. Contact openings are formed via the dielectric and conductive contacts 134, for example, metal contacts, and a metal wire or conductive pad 136 is formed on the conductive contacts. The metal wire or conductive pad may be operably coupled to bias and quench circuits, and these may include semiconductor devices formed on a silicon substrate or on other semiconductor substrates. For example, when a semiconductor device is formed on a semiconductor substrate, the semiconductor device may include transistors with fins and / or gate electrodes located on the upper surface of the substrate, or transistors with fins and / or gate electrodes located on the lower surface of the substrate, in which case through-silicon electrodes can be extended through the substrate to facilitate operable coupling. Thus, in Figure 21, the outer walls of the first and second n-type vertical connection regions 116a, 116b (e.g., guard rings) can be spaced apart from each other by isolation regions corresponding to parts of the semiconductor substrate, in the case of Figure 21, single-crystal silicon.

[0043] Figures 22 to 29 show alternative manufacturing flows according to several embodiments. Although Figures 22 to 29 will be described in relation to the methods, the structures disclosed in Figures 22 to 29 are not limited to these methods and may be independent structures unrelated to the methods.

[0044] Figures 22 to 28 roughly correspond to Figures 15 to 21 described above and show adjacent SPAD devices. However, in Figure 29 (continuing from Figure 28), an isolation structure 502 is formed from the lower surface of the semiconductor substrate to isolate adjacent SPAD devices from each other. In some cases, the isolation structure 502 can be formed by forming a photomask on the lower surface of the semiconductor substrate, then etching to form a trench on the lower surface of the semiconductor substrate, and then filling the trench with a dielectric material. In other cases, the isolation structure 502 can be formed by implanting ions (e.g., p-type dopants) into the lower surface of the substrate.

[0045] Figure 30 is a flowchart of the manufacturing flow relating to several embodiments. Although Method 3300 is shown and described as a series of operations and events, it should be understood that the order of these operations and events is not limiting. For example, some operations may occur in a different order than those shown and / or described herein, and / or simultaneously with other operations or events. Also, not all operations shown are necessarily required to carry out one or more aspects or embodiments of this specification. Furthermore, one or more operations described herein may be performed in one or more separate operations and / or stages.

[0046] In operation 3302, the semiconductor substrate is received.

[0047] In operation 3304, ion implantation is performed to form a lateral connection region beneath the upper surface of the semiconductor substrate.

[0048] In operation 3306, ion implantation is performed to form a vertical connection region. The vertical connection region and the lateral connection region come into contact with each other to form a guard ring.

[0049] In operation 3308, a recess is formed within the upper surface of the semiconductor substrate, the recess being laterally surrounded by a guard ring and defined by the recessed upper surface of the semiconductor substrate and the inner sidewall of the semiconductor substrate.

[0050] In operation 3310, a germanium region is formed in the recess.

[0051] Therefore, some embodiments provide single-photon avalanche detector (SPAD) devices. The device includes a silicon substrate with a recess in its upper surface. A p-type region is located in the silicon substrate below the lower surface of the recess. An n-type avalanche region is located in the silicon substrate below the p-type region and is in contact with the p-type region at the pn junction. A germanium region is located in the recess above the pn junction.

[0052] Another embodiment provides a semiconductor structure. The semiconductor structure includes a silicon substrate and a silicon-based multiplier region embedded in the semiconductor substrate. A germanium-based absorption region is embedded in the semiconductor substrate. The germanium-based absorption region is located above the silicon-based multiplier region. An electron channel is located between the silicon-based multiplier region and the germanium-based absorption region.

[0053] Another embodiment provides a method. A semiconductor substrate is received. Ion implantation is performed to form a lateral connection region beneath the upper surface of the semiconductor substrate. Ion implantation is performed to form a vertical connection region. The vertical and lateral connection regions are in contact with each other to form a guard ring. A recess is formed within the upper surface of the semiconductor substrate, the recess is laterally surrounded by the guard ring and defined by the recessed upper surface of the semiconductor substrate and the inner sidewall of the semiconductor substrate. A germanium region is formed in the recess.

[0054] Furthermore, spatially relative terms such as “down,” “below,” “in a lower position,” “up,” and “above” may be used here to facilitate explanation and describe the relationship between one element or feature and another, as shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figure. The device may be oriented in other directions (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein may be interpreted accordingly. [Industrial applicability]

[0055] The semiconductor structure and method of the present invention can be applied to single-photon avalanche detector (SPAD) devices. [Explanation of Symbols]

[0056] 100 SPAD devices 100a First SPAD device 100b Second SPAD device 102 Silicon structure 102l lower surface 102u top surface 104 recess 106, 106a, 106b p-type region 108, 108a, 108b n-type avalanche regions 110, 110a, 110b pn junction 112, 112a, 112b Germanium region 112ua, 112ub, 112ul top surface 113 Absorption region 114, 114a, 114b n-type lateral connection area 115 Multiplication region 116 n-type vertical connection region 116a Type 1n Vertical Connection Region 116b 2nd n type vertical connection area 117 Ge-S interface region 118, 118a, 118b are unique silicon regions. 120 p-type surface area 120a p type side wall part 120b p-type base section 120s side wall part 122 Upper germanium region 124 Intermediate Germanium Region 126 p-type sidewall germanium region 126a, 126b p-type germanium region 128 caps 128a, 128b Silicone caps 130 Bottom germanium region 132 Dielectric Structure 134 Conductive Contacts 136 Metal wire or conductive pad 138 Buried p-type region 150 Bias Circuit 152 incident photon 350 Conduction band 352 valence band 354 Fermi level 402 Silicon structure 502 Isolation structure 600 Semiconductor Structures 602, 1802 sacrificial oxides 900 Epitaxial single-crystal silicon region 902 Sacrificial Oxide Layer 1002 Second Photoresist Mask 1102 Oxide layer 1202 4th Photomask 1502 Oxides 1902 Third Photoresist Mask 3300 method 3302, 3304, 3306, 3308, 3310 operation d depth h height

Claims

1. a silicon substrate including a recess in an upper surface; a p-type region disposed within the silicon substrate below a lower surface of the recess; an n-type avalanche region disposed in the silicon substrate below the p-type region and contacting the p-type region at a pn junction; a germanium region disposed in the recess overlying the pn junction; Including, A single photon avalanche detector (SPAD) device further comprising disposing an intrinsic silicon region between an uppermost portion of the p-type region and a lower surface of the germanium region, the intrinsic silicon region being an undoped silicon region.

2. 2. The SPAD device of claim 1, wherein the germanium region contacts the silicon substrate at a Ge-Si interface region comprised of a Ge-Si alloy, the Ge-Si interface region being defined where an outer sidewall and a lower surface of the germanium region contact an inner sidewall and a recessed upper surface of the silicon substrate, respectively.

3. an n-type lateral connection region extending laterally from an outer edge of the n-type avalanche region past an outer wall of the germanium region; an n-type vertical connection region extending upwardly from an outer edge of the n-type lateral connection region to an upper surface of the silicon substrate; The SPAD device of claim 1 further comprising:

4. The SPAD device of claim 1 , wherein the intrinsic silicon region is configured to act as an electron channel extending the entire distance between the pn junction and the germanium region.

5. The germanium region is an upper germanium region having a first p-type doping concentration; a lower germanium region having a second p-type doping concentration; 2. The SPAD device of claim 1, comprising: