Semiconductor device

Abstract

To provide a semiconductor device with high reliability and excellent electric characteristics.SOLUTION: In a transistor 100, a semiconductor layer 108, a second insulating layer 110, a metal oxide layer 114, and a conductive layer 112 are stacked in this order on a first insulating layer 103. An end part of the second insulating layer exists on the inside relative to an end part of the semiconductor layer. An end part of each of the conductive layer and the metal oxide layer exists on the inside relative to the end part of the second insulating layer. A third insulating layer 116 is in contact with an upper surface of the first insulating layer, an upper surface and a side surface of the semiconductor layer, an upper surface and a side surface of the second insulating layer, a side surface of the metal oxide layer, and an upper surface and a side surface of the conductive layer. A first region 108C of the semiconductor layer overlaps with the first insulating layer and the metal oxide layer. A second region 108L holds the first region, overlaps with the second insulating layer, and does not overlap with the metal oxide layer. A third region 108N holds the first region and a pair of the second regions, does not overlap with the second insulating layer, and includes a part with lower resistance than that of the first region in contact with the third insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. 2. Description of the Related Art One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility than those using amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized.

[0005] Display devices are becoming larger in screen size, with development being carried out with screen sizes of 60 inches or more diagonally, and even 120 inches or more in mind. In addition, screen resolution is also tending to become higher, from full high vision (1920 x 1080 pixels, also known as "2K"), to ultra high vision (3840 x 2160 pixels, also known as "4K"), to super high vision (7680 x 4320 pixels, also known as "8K").

[0006] Larger screen sizes and higher definitions tend to increase the wiring resistance in the display section. Patent Document 2 discloses a technology for forming a low-resistance wiring layer using copper (Cu) in order to suppress the increase in wiring resistance in a liquid crystal display device using amorphous silicon transistors. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2004-163901 A Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the second insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the first insulating layer. In a cross section in the channel length direction, an end of the second insulating layer is located inside an end of the semiconductor layer, and ends of the conductive layer and the metal oxide layer are each located inside an end of the second insulating layer. The third insulating layer is in contact with a top surface of the first insulating layer, a top surface and a side surface of the semiconductor layer, a top surface and a side surface of the second insulating layer, a side surface of the metal oxide layer, and a top surface and a side surface of the conductive layer. The semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the first insulating layer and the metal oxide layer. The second region sandwiches the first region, overlaps with the second insulating layer, and does not overlap with the metal oxide layer. The third region sandwiches the first region and the pair of second regions and does not overlap the second insulating layer. The third region contacts the third insulating layer and includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

[0011] In the above-described semiconductor device, the second insulating layer preferably has a portion where the thickness of a region not overlapping with the metal oxide layer is thinner than the thickness of a region overlapping with the metal oxide layer.

[0012] In the above-mentioned semiconductor device, the second region has a sheet resistance of 1×10 3 Ω / □ or more 1×10 9 It is preferable that the resistance of the piezoelectric film contains a portion having a resistance of Ω / □ or less.

[0013] In the above-mentioned semiconductor device, the electrical resistance of the first region is 1×10 times that of the second region. 0 1×10 times more 9 It is preferable that the ratio is equal to or less than twice the normal ratio.

[0014] In the above-mentioned semiconductor device, the electrical resistance of the second region is 1×10 times that of the third region. 0 1×10 times more 9It is preferable that the ratio is equal to or less than twice the normal ratio.

[0015] In the above-described semiconductor device, the width of the second region in a cross section in the channel length direction is preferably 100 nm or more and 2 μm or less.

[0016] In the above-described semiconductor device, it is preferable that the first insulating layer contains a nitride, and the third insulating layer contains a nitride.

[0017] The aforementioned semiconductor device preferably further comprises a fourth insulating layer, which is in contact with an upper surface of the third insulating layer and preferably contains a nitride.

[0018] In the above-described semiconductor device, the third insulating layer preferably has a region having a lower hydrogen concentration than the fourth insulating layer.

[0019] In the above-described semiconductor device, the third insulating layer preferably has a region having a higher film density than the fourth insulating layer.

[0020] In the above-described semiconductor device, it is preferable that the conductive layer and the metal oxide layer have substantially the same top surface shape, or that the end of the conductive layer is located inside the end of the metal oxide layer.

[0021] In the above-described semiconductor device, it is preferable that the end of the second insulating layer and the end of the metal oxide layer each have a tapered shape.

[0022] In the above-described semiconductor device, the semiconductor layer and the metal oxide layer each preferably contain the same metal element.

[0023] In the above-described semiconductor device, the metal element is preferably at least one of indium and zinc. Effect of the Invention

[0024] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a highly reliable semiconductor device, or a novel semiconductor device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0026] [Figure 1] Fig. 1A is a top view of the semiconductor device, and Fig. 1B and Fig. 1C are cross-sectional views of the semiconductor device. [Diagram 2] 2A, 2B, and 2C are cross-sectional views of a semiconductor device. [Diagram 3] 3A, 3B, and 3C are cross-sectional views of a semiconductor device. [Figure 4] 4A, 4B, and 4C are cross-sectional views of a semiconductor device. [Diagram 5] Fig. 5A is a top view of the semiconductor device, and Fig. 5B and Fig. 5C are cross-sectional views of the semiconductor device. [Figure 6] 6A and 6B are cross-sectional views of a semiconductor device. [Figure 7] Fig. 7A is a top view of the semiconductor device, and Fig. 7B and Fig. 7C are cross-sectional views of the semiconductor device. [Figure 8] 8A, 8B, and 8C are cross-sectional views of a semiconductor device. [Figure 9] Fig. 9A is a top view of the semiconductor device, and Fig. 9B and Fig. 9C are cross-sectional views of the semiconductor device. [Figure 10] 10A, 10B, 10C, and 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 11] 11A, 11B, and 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 12] 12A, 12B, and 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 13] 13A, 13B, and 13C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 15] 15A, 15B, and 15C are top views of the display device. [Figure 16] FIG. 16 is a cross-sectional view of the display device. [Figure 17] FIG. 17 is a cross-sectional view of the display device. [Figure 18] FIG. 18 is a cross-sectional view of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] Fig. 20A is a block diagram of a display device, and Fig. 20B and Fig. 20C are circuit diagrams of the display device. [Figure 21] 21A, 21C, and 21D are circuit diagrams of the display device, and FIG. 21B is a timing chart of the display device. [Figure 22] Fig. 22A shows a configuration example of a display module, and Fig. 22B is a schematic cross-sectional view of the display module. [Diagram 23] Fig. 23A shows a configuration example of an electronic device, and Fig. 23B is a schematic cross-sectional view of the electronic device. [Figure 24] 24A, 24B, 24C, 24D, and 24E show configuration examples of electronic devices. [Diagram 25] 25A, 25B, 25C, 25D, 25E, 25F, and 25G show configuration examples of electronic devices. [Figure 26] 26A, 26B, 26C, and 26D show configuration examples of electronic devices. [Figure 27] FIG. 27 is a diagram showing the Id-Vd characteristics of a transistor. [Figure 28] FIG. 28 is a diagram showing the Id-Vd characteristics of a transistor. [Figure 29] FIG. 29 is a diagram showing the resistance of a metal oxide film. [Diagram 30] 30A and 30B are cross-sectional STEM images. [Diagram 31] FIG. 31 is a diagram showing the Id-Vg characteristics of a transistor. [Diagram 32] FIG. 32 is a diagram showing the Id-Vg characteristics of a transistor. [Diagram 33] FIG. 33 is a diagram showing the Id-Vg characteristics of a transistor. [Diagram 34] FIG. 34 is a diagram showing the Id-Vg characteristics of a transistor. [Diagram 35] FIG. 35 is a diagram showing the reliability evaluation results of a transistor. [Diagram 36] FIG. 36 is a diagram showing the resistance of a metal oxide film. [Figure 37] FIG. 37 is a diagram showing the Id-Vd characteristics of a transistor. [Figure 38] FIG. 38 is a diagram showing the operation result of the gate driver. [Figure 39] 39A, 39B, 39C, 39D, and 39E are cross-sectional views showing sample structures. [Diagram 40] 40A and 40B are cross-sectional views showing a sample structure. [Diagram 41] FIG. 41 is a cross-sectional view showing the sample structure. [Diagram 42] FIG. 42 shows the results of TDS measurements. [Diagram 43] FIG. 43 shows the results of TDS measurements. [Diagram 44] FIG. 44 shows the results of TDS measurements. [Diagram 45] FIG. 45 shows the results of TDS measurements. [Diagram 46] FIG. 46 shows the results of TDS measurements. [Figure 47] FIG. 47 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 48] FIG. 48 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 49] FIG. 49 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 50] FIG. 50 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 51] FIG. 51 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 52] FIG. 52 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 53] FIG. 53 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 54] 54A and 54B are diagrams showing the reliability evaluation results of a transistor. [Figure 55] 55A and 55B are TEM images of the cross section of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0028] In each figure described in this specification, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0029] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and do not limit the numbers.

[0030] In this specification, the terms "above" and "below" indicating the position are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0031] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, the terms source and drain can be used interchangeably.

[0032] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of a current flowing through a semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined to be one.

[0033] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0034] In this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchangeable with the terms "conductive film" and "insulating film".

[0035] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the edge of the upper layer may be located inside the edge of the lower layer, or the edge of the upper layer may be located outside the edge of the lower layer. In this case, the phrase "top surface shapes roughly match" is also used.

[0036] In this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state) when the voltage V gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0037] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0038] In this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0039] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0040] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0041] In this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0042] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. As an example of the semiconductor device, a structure example of a transistor and a manufacturing method thereof will be described below.

[0043] One embodiment of the present invention is a semiconductor device including a semiconductor layer in which a channel is formed, a second insulating layer functioning as a gate insulating layer, and a conductive layer functioning as a gate electrode, over a first insulating layer. The semiconductor layer preferably contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0044] A metal oxide layer is provided between the second insulating layer and the conductive layer. The metal oxide layer is preferably conductive, and in this case, the metal oxide layer functions as a part of the gate electrode.

[0045] In a cross section in the channel length direction, the edge (contour) of the second insulating layer is preferably located inside the edge (contour) of the semiconductor layer. Furthermore, in a cross section in the channel length direction, the edges (contours) of the conductive layer and the metal oxide layer are preferably located inside the edge (contour) of the second insulating layer.

[0046] The semiconductor device according to one embodiment of the present invention further includes a third insulating layer. The third insulating layer is preferably provided so as to be in contact with a top surface of the first insulating layer, a top surface and a side surface of the semiconductor layer, a top surface and a side surface of the second insulating layer, a side surface of the metal oxide layer, and a top surface and a side surface of the conductive layer. The first insulating layer and the third insulating layer are preferably made of a material that suppresses diffusion of impurities. For example, a nitride can be used for each of the first insulating layer and the third insulating layer. Furthermore, by providing a region where the first insulating layer and the third insulating layer are in contact with each other, diffusion of impurities into the transistor can be suppressed, resulting in a highly reliable transistor.

[0047] The semiconductor layer has a first region where a channel is formed, a pair of second regions sandwiching the first region, and a pair of third regions sandwiching the first and second regions and functioning as a source region and a drain region. The first region is a region overlapping with the first insulating layer and the metal oxide layer. The second region is a region overlapping with the second insulating layer but not overlapping with the metal oxide layer. The third region is a region not overlapping with the second insulating layer. The third region is preferably in contact with the third insulating layer and includes a portion having a lower resistance than the first region. The second region is preferably included in a portion having a higher resistance than the third region.

[0048] The second region functions as an LDD (Lightly Doped Drain) region. The presence of the second region can reduce the drain electric field, resulting in a highly reliable transistor even when driven at a high voltage.

[0049] A more specific example will be described below with reference to the drawings.

[0050] <Configuration example 1> FIG 1A is a top view of a transistor 100, FIG 1B corresponds to a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG 1A, and FIG 1C corresponds to a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG 1A. Note that FIG 1A omits some of the components of the transistor 100 (such as a protective layer). The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Note that, as with FIG 1A, the top views of the transistors in the following drawings will be illustrated with some of the components omitted.

[0051] The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided over the insulating layer 103. The insulating layer 110 is provided to cover part of an upper surface of the insulating layer 103 and part of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order over the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. FIG. 2A shows an enlarged view of a region P surrounded by a dashed line in FIG. 1B.

[0052] The ends of the conductive layer 112 and the metal oxide layer 114 are located inside the ends of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the ends of the conductive layer 112 and the metal oxide layer 114 at least on the semiconductor layer 108.

[0053] The semiconductor layer 108 has a region 108C that functions as a channel formation region, a pair of regions 108L that sandwich the region 108C, and a pair of regions 108N that are located outside the region 108C. The region 108L is a region of the semiconductor layer 108 that overlaps with the insulating layer 110 but does not overlap with the conductive layer 112. In FIG. 2A, the width of the region 108C in the channel length direction of the transistor 100 is indicated as L1, and the width of the region 108L is indicated as L2.

[0054] The region 108C functions as a channel formation region. When the metal oxide layer 114 has conductivity, it functions as a part of the gate electrode, and an electric field is applied from the gate electrode to the region 108C through the insulating layer 110, which functions as a gate insulating layer, to form a channel.

[0055] The region 108L functions as a buffer region for reducing a drain electric field. The region 108L does not overlap with the conductive layer 112 and the metal oxide layer 114, and therefore, a channel is hardly formed in the region 108L even when a gate voltage is applied to the conductive layer 112. The region 108L preferably has a higher carrier concentration than the region 108C. This allows the region 108L to function as an LDD region.

[0056] Region 108L can also be said to be a region having the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen defect density, or the same or higher impurity concentration compared to region 108C.

[0057] Region 108L can also be said to be a region having the same or higher resistance, the same or lower carrier concentration, the same or lower oxygen defect density, or the same or lower impurity concentration compared to region 108N.

[0058] In this manner, by providing the region 108L functioning as an LDD region between the region 108C which is a channel formation region and the region 108N which is a source or drain region, a highly reliable transistor having both a high drain withstand voltage and a high on-current can be realized.

[0059] Region 108N functions as a source region or a drain region, and is the region with the lowest resistance compared to other regions of semiconductor layer 108. Alternatively, region 108N can be said to be the region with the highest carrier concentration, the region with the highest oxygen defect density, or the region with the highest impurity concentration compared to other regions of semiconductor layer 108.

[0060] The lower the electrical resistance of the region 108N, the more preferable. For example, the sheet resistance of the region 108N is 1 Ω / □ or more and 1×10 3 Less than Ω / □, preferably 1Ω / □ or more 8×10 2 It is preferable to set it to Ω / □ or less.

[0061] The higher the electrical resistance of the region 108C in a state where no channel is formed, the more preferable it is. For example, the sheet resistance of the region 108C is 1×10 9 Ω / □ or more, preferably 5×10 9 Ω / □ or more, preferably 1×10 10 It is preferable that the resistance is Ω / □ or more.

[0062] Since the electrical resistance of the region 108C in a state where no channel is formed is preferably as high as possible, there is no need to set an upper limit. However, if an upper limit is set, the sheet resistance of the region 108C may be set to, for example, 1×10 9 Ω / □ or more 1×10 12 Ω / □ or less, preferably 5×10 9 Ω / □ or more 1×10 12 Ω / □ or less, more preferably 1×10 10 Ω / □ or more 1×10 12 It is preferable that the resistance is Ω / □ or less.

[0063] The sheet resistance value of the region 108L is, for example, 1×10 3 Ω / □ or more 1×10 9 Ω / □ or less, preferably 1×10 3 Ω / □ or more 1×10 8 Ω / □ or less, more preferably 1×10 3 Ω / □ or more 1×10 7 Ω / □. By setting the resistance in this range, a transistor with good electrical characteristics and high reliability can be obtained. The sheet resistance can be calculated from the resistance value. By providing such region 108L between region 108N and region 108C, the source-drain breakdown voltage of transistor 100 can be increased.

[0064] The electrical resistance of region 108C in a state where no channel is formed is 1×10 6 more than 1x10 12 times or less, preferably 1×10 6 more than 1x10 11 times or less, more preferably 1×10 6 more than 1x10 10 It can be up to twice as much.

[0065] When no channel is formed, the electrical resistance of region 108C is 1×10 0 more than 1x10 9 times or less, preferably 1×10 1 more than 1x10 8times or less, more preferably 1×10 2 more than 1x10 7 It can be up to twice as much.

[0066] The electrical resistance of region 108L is 1×10 0 more than 1x10 9 times or less, preferably 1×10 1 more than 1x10 8 times or less, more preferably 1×10 1 more than 1x10 7 It can be up to twice as much.

[0067] By providing the region 108L having the above-mentioned resistance between the region 108N and the channel formation region, the source-drain breakdown voltage of the transistor 100 can be increased.

[0068] The semiconductor layer 108 preferably has a distribution in which the carrier concentration is lowest in region 108C, and increases in the order of region 108L and region 108N. By providing region 108L between region 108C and region 108N, the carrier concentration in region 108C can be kept extremely low even if impurities such as hydrogen diffuse from region 108N during a manufacturing process, for example.

[0069] The carrier concentration in the region 108C functioning as a channel formation region is preferably as low as possible. 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is 1×10 16 cm -3 More preferably, it is 1×10 13 cm -3 More preferably, it is 1×10 12 cm -3 The lower limit of the carrier concentration in the region 108C is not particularly limited, but is preferably 1×10 -9 cm -3 It can be said that:

[0070] On the other hand, the carrier concentration in the region 108N is, for example, 5×10 18 cm -3 More than 1×10 19 cm -3 More preferably, 5×10 19 cm -3 The upper limit of the carrier concentration in the region 108N is not particularly limited, but may be, for example, 5×10 21 cm -3 , or 1 × 10 22 cm -3 etc.

[0071] The carrier concentration in region 108L may be a value between regions 108C and 108N. For example, 1×10 14 cm -3 More than 1×10 20 cm -3 It is sufficient to set the value to a range less than .

[0072] The carrier concentration in the region 108L may not be uniform, and may have a gradient such that the carrier concentration decreases from the region 108N side to the channel formation region. For example, either one or both of the hydrogen concentration and the oxygen vacancy concentration in the region 108L may have a gradient such that the concentration decreases from the region 108N side to the channel formation region side.

[0073] The semiconductor layer 108 preferably contains a metal oxide. The insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are preferably formed using an oxide film. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. In this way, oxygen desorbed from the insulating layer 103 or the insulating layer 110 during heat treatment or the like in the manufacturing process of the transistor 100 can be supplied to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies in the semiconductor layer 108.

[0074] A portion of an end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 has a portion that overlaps with the conductive layer 112 and functions as a gate insulating layer, and a portion that does not overlap with the conductive layer 112 and the metal oxide layer 114 (i.e., a portion that overlaps with the region 108L).

[0075] The insulating layer 110 may have a laminated structure of two or more layers. FIG. 1B, FIG. 1C, and FIG. 2A show an example in which the insulating layer 110 has a three-layer structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. Since the insulating layers 110a, 110b, and 110c can be made of insulating films of the same material, the interfaces of the insulating layers 110a, 110b, and 110c may not be clearly visible. Therefore, in this embodiment, the interfaces of the insulating layers 110a, 110b, and 110c are shown by dashed lines.

[0076] The insulating layer 110a has a region in contact with the channel formation region of the semiconductor layer 108. The insulating layer 110c has a region in contact with the metal oxide layer 114. The insulating layer 110b is located between the insulating layer 110a and the insulating layer 110c.

[0077] The insulating layers 110a, 110b, and 110c are preferably insulating films containing oxide. In this case, the insulating layers 110a, 110b, and 110c are preferably formed successively using the same film formation apparatus.

[0078] For example, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0079] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the insulating layer 110 after film formation in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0080] For example, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Also, the CVD method includes a plasma enhanced CVD (PECVD) method, a thermal CVD method, etc.

[0081] In particular, it is preferable that the insulating layers 110a, 110b, and 110c are formed by a plasma CVD method.

[0082] Since the insulating layer 110a is formed over the semiconductor layer 108, it is preferable that the insulating layer 110a be formed under conditions that minimize damage to the semiconductor layer 108. For example, the insulating layer 110a can be formed under conditions where the film formation rate (also referred to as the film formation rate) is sufficiently low.

[0083] For example, when the insulating layer 110a is formed by plasma CVD, damage to the semiconductor layer 108 can be made extremely small by forming the insulating layer 110a under low power conditions.

[0084] When silicon oxynitride films are used as the insulating layers 110a, 110b, and 110c, a deposition gas used to deposit the silicon oxynitride films can be a source gas containing a deposition gas containing silicon, such as silane or disilane, and an oxidizing gas, such as oxygen, ozone, nitrous oxide, or nitrogen dioxide. In addition to the source gas, a dilution gas, such as argon, helium, or nitrogen, can be used.

[0085] For example, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as the flow rate ratio), the film-forming rate can be reduced, and a dense film with few defects can be formed.

[0086] It is preferable that the insulating layer 110b is a film formed under conditions that provide a faster film formation rate than the insulating layer 110a, which can improve productivity.

[0087] For example, the insulating layer 110b can be formed under conditions in which the flow rate ratio of the deposition gas is made higher than that of the insulating layer 110a, thereby increasing the film formation rate.

[0088] The insulating layer 110c is preferably an extremely dense film with reduced surface defects and low adsorption of impurities such as water contained in the air. For example, like the insulating layer 110a, the insulating layer 110c can be formed under conditions where the film formation rate is sufficiently low.

[0089] Since the insulating layer 110c is formed on the insulating layer 110b, the insulating layer 110c has a smaller effect on the semiconductor layer 108 during its formation than the insulating layer 110a. Therefore, the insulating layer 110c can be formed under higher power conditions than the insulating layer 110a. By reducing the flow rate ratio of the deposition gas and forming the insulating layer 110c at relatively high power, a dense film with reduced surface defects can be obtained.

[0090] That is, a stacked film formed under conditions in which the order of film formation rate is insulating layer 110b, insulating layer 110a, and insulating layer 110c can be used as insulating layer 110. Moreover, in insulating layer 110, the etching rates of insulating layer 110b, insulating layer 110a, and insulating layer 110c are highest under the same wet etching or dry etching conditions.

[0091] The insulating layer 110b is preferably formed thicker than the insulating layers 110a and 110c. By forming the insulating layer 110b, which has the fastest film formation speed, thick, the time required for the film formation process of the insulating layer 110 can be shortened.

[0092] Here, the boundary between insulating layer 110a and insulating layer 110b, and the boundary between insulating layer 110b and insulating layer 110c may be unclear, and therefore these boundaries are illustrated by dashed lines in Fig. 1A and the like. Note that insulating layer 110a and insulating layer 110b have different film densities, and therefore these boundaries may be observable as differences in contrast in a transmission electron microscope (TEM) image of a cross section of insulating layer 110. Similarly, the boundary between insulating layer 110b and insulating layer 110c may also be observable.

[0093] When the conductive layer 112 and the metal oxide layer 114 are formed, the thickness of the insulating layer 110 in the region not overlapping with the conductive layer 112 may be reduced. Figures 1B, 1C, and 2A show a configuration in which the insulating layer 110c in the region not overlapping with the conductive layer 112 is removed, and the insulating layer 110a and the insulating layer 110b remain. Furthermore, the thickness of the insulating layer 110b in the region not overlapping with the conductive layer 112 may be reduced compared to the insulating layer 110b in the region overlapping with the conductive layer 112.

[0094] By reducing the thickness of the insulating layer 110 in the region not overlapping with the conductive layer 112, more hydrogen is supplied from the insulating layer 116, and the resistance of the region 108L can be reduced. In addition, by adjusting the thickness of the insulating layer 110 in the region not overlapping with the conductive layer 112, the amount of hydrogen supplied from the insulating layer 116 can be adjusted, and the resistance of the region 108L can be controlled.

[0095] By reducing the thickness of the insulating layer 110 in the area that does not overlap with the conductive layer 112, the step at the end of the insulating layer 110 is reduced, the step coverage of the layer formed on the insulating layer 110 (e.g., insulating layer 116) is improved, and defects such as discontinuities and voids in the layer can be suppressed.

[0096] FIG. 2B shows a configuration in which the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c remain in the region not overlapping with the conductive layer 112. In addition, the thickness of the insulating layer 110c in the region not overlapping with the conductive layer 112 may be thinner than that of the insulating layer 110c in the region overlapping with the conductive layer 112. As shown in FIG. 2B, it is particularly preferable that the insulating layer 110c remains in the region not overlapping with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region not overlapping with the conductive layer 112, it is possible to suppress water adsorption to the insulating layer 110. The thickness of the insulating layer 110c in the region overlapping with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less.

[0097] Figure 2C shows an example in which insulating layers 110a, 110b, and 110c remain in areas that do not overlap with conductive layer 112, and the thickness of insulating layer 110c in the area that overlaps with conductive layer 112 is approximately equal to the thickness of insulating layer 110c in the area that does not overlap with conductive layer 112.

[0098] The insulating layer 110 may have a two-layer structure of an insulating layer 110a and an insulating layer 110c on the insulating layer 110a. Alternatively, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the insulating layers 110a, 110b, and 110c described above can be appropriately selected depending on the purpose.

[0099] The insulating layer 116 is provided to cover the top surface and side surfaces of the conductive layer 112, the side surfaces of the metal oxide layer 114, the top surface and side surfaces of the insulating layer 110, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116. The insulating layer 116 and the insulating layer 118 function as protective layers and can suppress diffusion of impurity elements from the outside.

[0100] The insulating layer 116 has a function of suppressing diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108. The insulating layer 116 also has a function of reducing the resistance of the semiconductor layer 108 in contact with the insulating layer 116 during deposition. The insulating layer 116 is provided in contact with the upper surface and side surfaces of the region 108N. The insulating layer 116 can be an insulating film that can supply impurities into the region 108N by heating during or after the deposition of the insulating layer 116. Alternatively, an insulating film that can cause oxygen vacancies in the region 108N by heating during or after the deposition of the insulating layer 116 can be used.

[0101] The insulating layer 116 is preferably formed using a gas containing an impurity element such as hydrogen as a deposition gas. For example, silane, ammonia, or the like can be used as the gas containing hydrogen. In addition, by lowering the deposition temperature of the insulating layer 116, a large amount of impurity elements can be effectively supplied to the semiconductor layer 108. The deposition temperature of the insulating layer 116 is preferably, for example, from 200° C. to 500° C., more preferably from 220° C. to 450° C., further preferably from 230° C. to 430° C., and further preferably from 250° C. to 400° C.

[0102] Deposition of the insulating layer 116 under reduced pressure and by heating can promote desorption of oxygen from a region that will become the region 108N in the semiconductor layer 108. Supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen vacancies have been formed increases the carrier concentration in the region 108N, and can more effectively reduce the resistance of the region 108N.

[0103] For the insulating layer 116, for example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be suitably used. In particular, silicon nitride has a blocking property against hydrogen and oxygen, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer 108 and elimination of oxygen from the semiconductor layer 108 to the outside, thereby realizing a highly reliable transistor.

[0104] The insulating layer 116 may be an insulating film having a function of absorbing oxygen in the semiconductor layer 108 and generating oxygen vacancies. In particular, the insulating layer 116 is preferably formed using a metal nitride such as aluminum nitride.

[0105] When a metal nitride is used for the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to use aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using aluminum as a sputtering target and a gas containing nitrogen as a deposition gas can have extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. Therefore, by providing an insulating film containing such a metal nitride in contact with the semiconductor layer 108, not only can the resistance of the semiconductor layer 108 be reduced, but also oxygen can be prevented from being released from the semiconductor layer 108 and hydrogen can be prevented from diffusing into the semiconductor layer 108.

[0106] When aluminum nitride is used as the metal nitride, the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even with such a thin film, it is possible to achieve both high blocking properties against hydrogen and oxygen and a function of reducing the resistance of the semiconductor layer. There is no particular upper limit to the thickness of the insulating layer, but in consideration of productivity, it is preferable to set it to 500 nm or less, preferably 200 nm or less, and more preferably 50 nm or less.

[0107] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is a real number greater than 0 and equal to or less than 2, preferably, x is a real number greater than 0.5 and equal to or less than 1.5) is preferably used. This allows the film to have excellent insulating properties and excellent thermal conductivity, thereby improving the dissipation of heat generated when the transistor 100 is driven.

[0108] Alternatively, the insulating layer 116 can be an aluminum titanium nitride film, a titanium nitride film, or the like.

[0109] By providing such an insulating layer 116 in contact with the region 108N, the insulating layer 116 can absorb oxygen in the region 108N and form oxygen vacancies in the region 108N. In addition, by performing heat treatment after forming such an insulating layer 116, more oxygen vacancies can be formed in the region 108N, and the resistance can be reduced. In addition, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 may absorb oxygen in the semiconductor layer 108, and as a result, a layer containing an oxide of a metal element (e.g., aluminum) contained in the insulating layer 116 may be formed between the insulating layer 116 and the region 108N.

[0110] Since the insulating layer 110 is present between the region 108L and the insulating layer 116, the region 108L receives less hydrogen from the insulating layer 116 than the region 108N. Furthermore, the impurity concentration of the region 108L is smaller than that of the region 108N, so the region 108L can be made to have a higher resistance than the region 108N.

[0111] As described later, since the region 108L can be formed in a self-aligned manner, a photomask for forming the region 108L is not required, and the manufacturing cost can be reduced. Furthermore, since the region 108L is formed in a self-aligned manner, the relative positional deviation between the region 108L and the conductive layer 112 does not occur, and the width of the region 108L in the semiconductor layer 108 can be approximately the same.

[0112] A region 108L that functions as an offset region to which the electric field of the gate is not applied (or is applied less than the channel formation region) can be formed stably and without variation between the channel formation region and the low-resistance region 108N in the semiconductor layer 108. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized.

[0113] The width L2 of the region 108L is preferably 100 nm or more and 2 μm or less, more preferably 150 nm or more and 1 μm or less, and even more preferably 200 nm or more and 1 μm or less. By providing the region 108L, the concentration of the electric field near the drain is alleviated, and the deterioration of the transistor can be suppressed, especially when the drain voltage is high. In particular, by making the width L2 of the region 108L larger than the thickness of the insulating layer 110, the concentration of the electric field near the drain can be effectively suppressed. On the other hand, if the width L2 is longer than 2 μm, the source-drain resistance increases, and the driving speed of the transistor may become slow. By setting the width L2 in the above-mentioned range, a transistor and a semiconductor device with high reliability and high driving speed can be obtained. The width L2 of the region 108L can be determined according to the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and drain when driving the transistor 100.

[0114] By providing region 108L between the channel formation region and low-resistance region 108N, the current density at the boundary between the channel formation region and region 108N can be alleviated, and heat generation at the boundary between the channel and the source or drain can be suppressed, resulting in a highly reliable transistor or semiconductor device.

[0115] The insulating layer 103 can have a stacked structure. Fig. 1 shows an example in which the insulating layer 103 has a structure in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are stacked in this order from the substrate 102 side. The insulating layer 103a is in contact with the substrate 102. The insulating layer 103d is in contact with the semiconductor layer 108.

[0116] It is preferable that the insulating layer 103 satisfy one or more of the following requirements: high breakdown voltage, low film stress, low resistance to hydrogen and water release, few defects in the film, and suppression of diffusion of impurities contained in the substrate 102, and it is most preferable that the insulating layer 103 satisfy all of these requirements.

[0117] Of the four insulating films included in the insulating layer 103, insulating layers 103a, 103b, and 103c located on the substrate 102 side are preferably made of insulating films containing nitrogen. On the other hand, insulating layer 103d in contact with the semiconductor layer 108 is preferably made of an insulating film containing oxygen. In addition, the four insulating films included in the insulating layer 103 are preferably formed successively without exposure to air using a plasma CVD apparatus.

[0118] For the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c, an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film, can be suitably used. For the insulating layer 103d, the description of the insulating film that can be used for the insulating layer 110 can be cited.

[0119] The insulating layers 103a and 103c are preferably dense films capable of preventing diffusion of impurities from below. The insulating layer 103a is preferably a film capable of blocking impurities contained in the substrate 102, and the insulating layer 103c is preferably a film capable of blocking hydrogen and water contained in the insulating layer 103b. For this reason, the insulating layer 103a and the insulating layer 103c can be formed using insulating films formed at a lower deposition rate than the insulating layer 103b.

[0120] On the other hand, the insulating layer 103b is preferably an insulating film formed under conditions of low stress and high deposition rate. The insulating layer 103b is preferably formed thicker than the insulating layers 103a and 103c.

[0121] For example, even if the insulating layers 103a, 103b, and 103c are each made of a silicon nitride film formed by a plasma CVD method, the insulating layer 103b has a lower film density than the other two insulating films. Therefore, in a transmission electron microscope image of a cross section of the insulating layer 103, this may be observed as a difference in contrast. Note that the boundaries between the insulating layers 103a and 103b, and between the insulating layers 103b and 103c may be unclear, and therefore these boundaries are shown by dashed lines in FIG. 1 and other figures.

[0122] The insulating layer 103d in contact with the semiconductor layer 108 is preferably a dense insulating film that is unlikely to adsorb impurities such as water to its surface. In addition, it is preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced. For example, the insulating layer 103d can be an insulating film similar to the insulating layer 110c of the insulating layer 110.

[0123] By using the insulating layer 103 having such a stacked structure, a highly reliable transistor can be realized.

[0124] 1B and 1C, the transistor 100 preferably has a region where the insulating layer 103c is in contact with the insulating layer 116. Fig. 3A shows an enlarged view of a region Q surrounded by a dashed line in Fig. 1B, and Fig. 3B shows an enlarged view of a region R surrounded by a dashed line in Fig. 1C.

[0125] 1B and 3A, the insulating layer 116 in a region that does not overlap with the semiconductor layer 108 in the channel length direction is provided in contact with the insulating layer 103c.

[0126] 3B, in the channel width direction, the insulating layer 116 is provided in contact with the insulating layer 103c in a region that does not overlap with the insulating layer 110. In addition, an end of the insulating layer 103d roughly coincides with an end of the insulating layer 110. For example, when forming the insulating layer 110, the insulating film that becomes the insulating layer 103d in a region that does not overlap with the insulating layer 110 can also be removed, so that the end of the insulating layer 103d roughly coincides with the end of the insulating layer 110.

[0127] The insulating layer 103c and the insulating layer 116 have a region in contact with each other, which can suppress diffusion of impurities from outside the transistor 100 into the transistor 100. In particular, an insulating film containing nitrogen can be preferably used as each of the insulating layer 116 and the insulating layer 103c.

[0128] 3C, the end of the insulating layer 103d may be configured to roughly coincide with the end of the semiconductor layer 108. For example, when forming the semiconductor layer 108, the insulating film that becomes the insulating layer 103d in the region that does not overlap with the semiconductor layer 108 may also be removed, so that the end of the insulating layer 103d and the end of the semiconductor layer 108 can roughly coincide with each other.

[0129] In the channel length direction, the thickness of the insulating layer 103c in a region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 103c in a region that overlaps with the semiconductor layer 108. Fig. 4A shows an enlarged view of a region Q surrounded by a dashed line in Fig. 1B. Fig. 4A shows an example where the thickness of the insulating layer 103c in a region that does not overlap with the semiconductor layer 108 is thinner than the thickness of the insulating layer 103c in a region that overlaps with the semiconductor layer 108, and where the insulating layer 103c and the insulating layer 116 are in contact with each other in the region where the thickness of the insulating layer 103c is thinner.

[0130] In the channel width direction, the thickness of the insulating layer 103c in the region not overlapping the insulating layer 110 may be thinner than the thickness of the insulating layer 103c in the region overlapping the insulating layer 110. FIGS. 4B and 4C show enlarged views of the region R surrounded by a dashed line in FIG. 1C. FIGS. 4B and 4C show an example in which the thickness of the insulating layer 103c in the region not overlapping the insulating layer 110 is thinner than the thickness of the insulating layer 103c in the region overlapping the insulating layer 110, and the insulating layer 103c and the insulating layer 116 are in contact in the region where the thickness of the insulating layer 103c is thin. In FIG. 4B, the end of the insulating layer 103d roughly coincides with the end of the insulating layer 110. In FIG. 4C, the end of the insulating layer 103d roughly coincides with the end of the semiconductor layer 108.

[0131] 4A, 4B, and 4C show an example in which the insulating layer 103c is in contact with the insulating layer 116; however, one embodiment of the present invention is not limited to this. The insulating layer 103b may be exposed and in contact with the insulating layer 116. Alternatively, the insulating layer 103a may be exposed and in contact with the insulating layer 116.

[0132] It is preferable that the end of the insulating layer 110 and the end of the metal oxide layer 114 each have a tapered shape. With such a structure, the coverage of a layer (for example, the insulating layer 116) formed on the insulating layer 110 and the metal oxide layer 114 can be improved, and defects such as discontinuities and voids in the layer can be suppressed.

[0133] A part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer .

[0134] 1A and 1B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over an insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108N through an opening 141a and an opening 141b provided in the insulating layer 118 and the insulating layer 116, respectively.

[0135] The semiconductor layer 108 preferably comprises a metal oxide.

[0136] For example, the semiconductor layer 108 preferably contains indium, an element M (wherein the element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0137] In particular, it is preferable to use an oxide containing indium, gallium, and zinc for the semiconductor layer 108.

[0138] The semiconductor layer 108 may have a stacked structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0139] It is preferable to use a low-resistance material for the conductive layer 112. By using a low-resistance material for the conductive layer 112, parasitic resistance can be reduced, and a transistor having high on-state current can be obtained, thereby making it possible to provide a semiconductor device with high on-state current. Furthermore, by reducing the wiring resistance in a large display device or a high-definition display device, signal delay can be suppressed and high-speed driving can be achieved. Copper, silver, gold, aluminum, aluminum, or the like can be used for the conductive layer 112. In particular, copper is preferable because it has low resistance and is excellent in mass productivity.

[0140] The conductive layer 112 may have a stacked structure. When the conductive layer 112 has a stacked structure, a second conductive layer is provided above or below, or both of, the first conductive layer having low resistance. The second conductive layer is preferably made of a conductive material that is less likely to be oxidized (has oxidation resistance) than the first conductive layer. In addition, the second conductive layer is preferably made of a material that suppresses the diffusion of components of the first conductive layer. As the second conductive layer, for example, metal oxides such as indium oxide, indium zinc oxide, indium tin oxide (ITO), indium tin oxide containing silicon (ITSO), and zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, and tungsten nitride can be suitably used.

[0141] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. The metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. The metal oxide layer 114 can be made of a material that is less permeable to oxygen and hydrogen than the insulating layer 110, for example.

[0142] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0143] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, it functions as a part of the gate electrode.

[0144] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0145] A metal oxide can be used as the metal oxide layer 114. For example, an oxide containing indium, such as indium oxide, indium zinc oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO), can be used. A conductive oxide containing indium is preferable because of its high conductivity. In addition, ITSO is less likely to crystallize due to the inclusion of silicon, and has high flatness, so that the adhesion to a film formed on ITSO is high. A metal oxide, such as zinc oxide or zinc oxide containing gallium, can be used as the metal oxide layer 114. Alternatively, a structure in which these are stacked may be used as the metal oxide layer 114.

[0146] For the metal oxide layer 114, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that of the semiconductor layer 108 for the metal oxide layer 114, because this allows the use of a common device.

[0147] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material with a higher gallium composition (content) than the semiconductor layer 108 because the blocking property against oxygen can be further improved. In this case, by using a material with a higher indium composition than the metal oxide layer 114 for the semiconductor layer 108, the field-effect mobility of the transistor 100 can be increased.

[0148] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0149] The semiconductor layer 108 has a channel formation region overlapping with the conductive layer 112 with the insulating layer 110 interposed therebetween. The semiconductor layer 108 also has a pair of regions 108N that sandwich the channel formation region. The region 108N is a region of the semiconductor layer 108 that does not overlap with either the conductive layer 112 or the insulating layer 110 and is in contact with the insulating layer 116.

[0150] The region 108N can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a high density of oxygen defects, a region having a high impurity concentration, or an n-type region.

[0151] The region 108N is a region containing an impurity element (first element). Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable that the region 108N contains boron, phosphorus, magnesium, or aluminum. The region 108N may contain two or more of these elements.

[0152] Here, it is preferable that the impurity concentration in the region 108N has a concentration gradient such that the concentration becomes higher closer to the insulating layer 116. This makes it possible to reduce the total amount of impurity elements in the region 108N compared to a case where the concentration is uniform throughout the region 108N, and therefore the amount of impurities that may diffuse into the channel formation region due to the influence of heat during the manufacturing process can be kept low. In addition, since the resistance becomes lower toward the upper part of the region 108N, the contact resistance with the conductive layer 120a (or conductive layer 120b) can be reduced more effectively.

[0153] As described later, the process of adding an impurity element to the region 108N can be performed using the insulating layer 110 as a mask, thereby allowing the region 108N to be formed in a self-aligned manner.

[0154] The region 108N has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0155] The concentration of impurities contained in the region 108N can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or rear side with XPS analysis.

[0156] In the region 108N, the impurity element is preferably present in an oxidized state. For example, it is preferable to use an element that is easily oxidized, such as boron, phosphorus, magnesium, aluminum, or silicon, as the impurity element. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, desorption is suppressed even when a high temperature (e.g., 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process. In addition, the impurity element removes oxygen from the semiconductor layer 108, causing many oxygen vacancies (V O ) is generated. This oxygen vacancy (V O ) is a defect caused by hydrogen entering the film (hereafter referred to as VO H) serves as a carrier supply source, so that the region 108N has an extremely low resistance.

[0157] In addition, when a high-temperature process is performed in a later step, if a large amount of oxygen is supplied to region 108N from the outside or a film in the vicinity of region 108N, the resistance may increase. Therefore, when performing a high-temperature process, it is preferable to perform the process in a state where semiconductor layer 108 is covered with insulating layer 116 that has a high barrier property against oxygen.

[0158] The insulating layer 116 is provided in contact with a region 108N of the semiconductor layer 108.

[0159] The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen when heated. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance.

[0160] The insulating layer 116 is preferably formed by using a deposition gas containing hydrogen, so that hydrogen can be effectively supplied to the region 108N during the deposition of the insulating layer 116.

[0161] The insulating layer 116 can be, for example, an insulating film made of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.

[0162] As described above, the region 108N is in a state where it contains many oxygen vacancies due to the addition of the impurity element, and therefore, by supplying hydrogen from the insulating layer 116 in addition to the hydrogen contained in the semiconductor layer 108, the carrier concentration can be further increased.

[0163] The insulating layer 118 functions as a protective layer that protects the transistor 100. For the insulating layer 118, for example, an inorganic insulating material such as an oxide or a nitride can be used. More specifically, for example, an inorganic insulating material such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used. The insulating layer 118 can also be used as a planarization layer. In that case, an organic resin material can be used for the insulating layer 118.

[0164] Although the protective layer has a stacked structure of the insulating layer 116 and the insulating layer 118 in this embodiment, the insulating layer 118 does not have to be provided if it is not necessary. The insulating layer 118 may have a stacked structure of two or more layers.

[0165] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described.

[0166] Oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect transistor characteristics and are therefore problematic. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen enters the oxygen vacancies and can become a carrier supply source. When a carrier supply source is generated in the channel formation region, the electrical characteristics of the transistor 100 fluctuate, typically causing a shift in the threshold voltage. Therefore, it is preferable to have fewer oxygen vacancies in the channel formation region.

[0167] Therefore, in one embodiment of the present invention, an insulating film in the vicinity of a channel formation region of the semiconductor layer 108, specifically, the insulating layer 110 located above the channel formation region and the insulating layer 103 located below the channel formation region, includes an oxide film. By transferring oxygen from the insulating layer 103 and the insulating layer 110 to the channel formation region by heat or the like during a manufacturing process, oxygen vacancies in the channel formation region can be reduced.

[0168] The semiconductor layer 108 preferably has a region in which the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0169] Here, in the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is weaker than that between Ga and oxygen, so oxygen vacancies are likely to be formed in the metal oxide film when the In content is high. The same tendency is observed when a metal element represented by M is used instead of Ga. If many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are degraded.

[0170] However, in one embodiment of the present invention, a metal oxide material with a high In content can be used because an extremely large amount of oxygen can be supplied to the channel formation region of the semiconductor layer 108 containing a metal oxide. As a result, a transistor having extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0171] For example, metal oxides in which the atomic ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be suitably used.

[0172] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is preferably In:M:Zn=4:2:3 or close to it. Alternatively, the atomic ratio of In, M, and Zn is preferably In:M:Zn=5:1:6 or close to it. Furthermore, the composition of the semiconductor layer 108 may be such that the atomic ratio of In, element M, and Zn in the semiconductor layer 108 is approximately equal. That is, the semiconductor layer 108 may contain a material in which the atomic ratio of In, element M, and Zn is In:M:Zn=1:1:1 or close to it.

[0173] For example, by using the transistor with high field-effect mobility in a gate driver that generates a gate signal, a display device with a narrow frame width (also called a narrow frame) can be provided. In addition, by using the transistor with high field-effect mobility in a source driver (particularly, a demultiplexer connected to an output terminal of a shift register of the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0174] Even if the semiconductor layer 108 has a region in which the atomic ratio of In to the element M is greater than 1, the field-effect mobility may be reduced if the semiconductor layer 108 has high crystallinity. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD) or a transmission electron microscope (TEM).

[0175] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect state density (reduced oxygen vacancies), so that the carrier concentration in the film can be reduced. A transistor using such a metal oxide film for a channel formation region of the semiconductor layer rarely has electrical characteristics in which the threshold voltage is negative (also called normally on). In addition, a transistor using such a metal oxide film can have a significantly small off-current.

[0176] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during deposition of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, when a metal oxide film with relatively low crystallinity is used for the semiconductor layer 108, electrical conductivity is improved, and a transistor with high field-effect mobility can be realized.

[0177] The semiconductor layer 108 is preferably made of a metal oxide film having a c-axis aligned crystal (CAAC) structure, a metal oxide film having a nano crystal (nc) structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure, as described below.

[0178] The semiconductor layer 108 may have a laminated structure of two or more layers.

[0179] For example, a semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used. For example, when an In-M-Zn oxide is used, it is preferable to stack two or more films formed from a sputtering target in which the atomic ratio of In, element M, and Zn is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn=1:3:2, or a ratio close to these values.

[0180] A stack of two or more metal oxide films having different crystallinity can be used for the semiconductor layer 108. In that case, it is preferable to use the same oxide target and to form the films under different film formation conditions in succession without exposure to air.

[0181] In this case, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Note that the function or material configuration of a metal oxide that can be suitably used for the metal oxide film can be described with reference to the description of CAC (Cloud-Aligned Composite) described later.

[0182] For example, the oxygen flow ratio during the formation of the first metal oxide film is set to be smaller than the oxygen flow ratio during the formation of the second metal oxide film. Alternatively, oxygen is not allowed to flow during the formation of the first metal oxide film. This allows oxygen to be effectively supplied during the formation of the second metal oxide film. In addition, the first metal oxide film can be a film with lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, by making the second metal oxide film provided on the upper portion a film with higher crystallinity than the first metal oxide film, damage during processing of the semiconductor layer 108 and during the formation of the insulating layer 110 can be suppressed.

[0183] More specifically, the oxygen flow ratio during deposition of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow ratio during deposition of the second metal oxide film is 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, further preferably 90% or more and 100% or less, and typically 100%. Although the conditions during deposition of the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different, it is preferable to make the conditions other than the oxygen flow ratio the same, since this shortens the time required for the deposition process.

[0184] With this structure, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0185] The following describes a configuration example of a transistor that is partially different from the above-mentioned configuration example 1. Note that, in the following, the description of parts that overlap with the above-mentioned configuration example 1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-mentioned configuration examples may be indicated with the same hatching pattern and may not be assigned reference numerals.

[0186] <Configuration example 2> Fig. 5A is a top view of the transistor 100A, Fig. 5B is a cross-sectional view of the transistor 100A in the channel length direction, and Fig. 5C is a cross-sectional view of the transistor 100A in the channel width direction. Fig. 6A shows an enlarged view of a region P surrounded by a dashed line in Fig. 5B. Fig. 6B shows an enlarged view of a region R surrounded by a dashed line in Fig. 5C.

[0187] The transistor 100A differs from the transistor 100 mainly in that an end of the conductive layer 112 is located inside an end of the metal oxide layer 114. In addition, an insulating layer 116 is provided in contact with the top surface and side surfaces of the metal oxide layer.

[0188] In the transistor 100A, an end of the conductive layer 112 is located inside an end of the metal oxide layer 114. In other words, the metal oxide layer 114 has a portion that protrudes outside the end of the conductive layer 112 at least on the insulating layer 110.

[0189] By positioning the end of the conductive layer 112 inside the end of the metal oxide layer 114, the steps on the side surfaces of the conductive layer 112 and the metal oxide layer 114 are gentler, improving the step coverage of the layer (e.g., the insulating layer 116) formed on the conductive layer 112 and the metal oxide layer 114, and suppressing defects such as discontinuities and porosity in the layer.

[0190] A wet etching method can be suitably used for forming the conductive layer 112 and the metal oxide layer 114. In addition, by using a material having an etching rate slower than that of the conductive layer 112 for the metal oxide layer 114, the end of the conductive layer 112 can be located inside the end of the metal oxide layer 114. Furthermore, the metal oxide layer 114 and the conductive layer 112 can be formed in the same process, thereby improving productivity.

[0191] This concludes the description of configuration example 2.

[0192] <Configuration example 3> Fig. 7A is a top view of the transistor 100B, Fig. 7B is a cross-sectional view of the transistor 100B in the channel length direction, and Fig. 7C is a cross-sectional view of the transistor 100B in the channel width direction. Fig. 8A shows an enlarged view of a region P surrounded by a dashed line in Fig. 7B. Fig. 8B shows an enlarged view of a region Q surrounded by a dashed line in Fig. 7B. Fig. 8C shows an enlarged view of a region R surrounded by a dashed line in Fig. 7C.

[0193] The transistor 100B differs from the transistor 100A mainly in that the insulating layer 116 has a stacked structure. The insulating layer 116 can have a stacked structure of two or more layers. When the insulating layer 116 has a stacked structure, it is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0194] 7B, 7C, 8A, 8B, and 8C show an example in which the insulating layer 116 has a two-layer structure of an insulating layer 116a and an insulating layer 116b on the insulating layer 116a. The insulating layer 116a and the insulating layer 116b can be made of a material that can be used for the insulating layer 116. The insulating layer 116a and the insulating layer 116b can be made of the same material or different materials. Note that since the insulating layer 116a and the insulating layer 116b can be made of insulating films made of the same material, the interfaces between the insulating layer 116a and the insulating layer 116b may not be clearly identified. Therefore, in this embodiment, the interface between the insulating layer 116a and the insulating layer 116b is illustrated by a broken line.

[0195] 8A and 8B, the insulating layer 116 is in contact with the region 108N and functions as a hydrogen source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen when heat is applied thereto.

[0196] The insulating layer 116 can be formed in an atmosphere containing hydrogen. For example, the insulating layer 116 is preferably formed by a plasma CVD method using a deposition gas containing hydrogen. For example, a silicon nitride film can be formed as the insulating layer 116 using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the insulating layer 116. Also, hydrogen can be supplied to an exposed portion of the semiconductor layer 108 during the deposition of the insulating layer 116.

[0197] However, when the insulating layer 116 is formed in an atmosphere containing hydrogen, the exposed region of the semiconductor layer 108 may be reduced during the formation of the insulating layer 116. When the surface of the semiconductor layer 108 is reduced, the roughness of the surface of the semiconductor layer 108 increases, and defects such as discontinuities and voids may occur in layers (such as the insulating layer 116) formed on the semiconductor layer 108.

[0198] Therefore, the amount of hydrogen contained in the atmosphere used to form the insulating layer 116a located on the semiconductor layer 108 side is preferably less than the amount of hydrogen contained in the atmosphere used to form the insulating layer 116b. For example, a mixed gas of silane, nitrogen, and ammonia can be used to form each of the insulating layers 116a and 116b, and the flow rate of ammonia used to form the insulating layer 116a can be less than the flow rate of ammonia used to form the insulating layer 116b. Alternatively, a mixed gas of silane and nitrogen can be used to form the insulating layer 116a, and a mixed gas of silane, nitrogen, and ammonia can be used to form the insulating layer 116b. Furthermore, it is preferable that the insulating layer 116a has a region with a lower hydrogen concentration than the insulating layer 116b. With such a structure, reduction of the surface of the semiconductor layer 108 can be suppressed.

[0199] For example, even if the insulating layers 116a and 116b are made of silicon nitride films formed by plasma CVD, their film densities are different, and therefore their boundaries may be observed as differences in contrast in a transmission electron microscope (TEM) image of the cross section of the insulating layer 110. For example, the insulating layer 116a may have a region with a higher film density than the insulating layer 116b. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, the insulating layer 116a may have a darker image than the insulating layer 116b in the transmission electron (TE) image. Also, the insulating layer 116a may have a region with a lower hydrogen concentration than the insulating layer 116b. The difference in hydrogen concentration between the insulating layers 116a and 116b may be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0200] The insulating layer 116b is preferably made of a material that has a blocking property against hydrogen, water, and oxygen. The insulating layer 116b preferably has a blocking property against hydrogen, water, and oxygen higher than that of the insulating layer 116a. When the insulating layer 116b provided over the insulating layer 116a has a blocking property against hydrogen, water, and oxygen, the insulating layer 116b can suppress diffusion of hydrogen and water from the outside to the semiconductor layer 108 and can suppress desorption of oxygen from the semiconductor layer 108 to the outside, thereby realizing a highly reliable transistor.

[0201] It is preferable that the insulating layer 116 in contact with the semiconductor layer 108 has few defects in the film. For example, when silicon nitride is used as the insulating layer 116, a typical defect in the silicon nitride film is a K center. The K center is caused by a dangling bond of silicon, and can be evaluated by electron spin resonance (ESR).

[0202] When the amount of hydrogen contained in the atmosphere used to form the insulating layer 116a is less than the amount of hydrogen contained in the atmosphere used to form the insulating layer 116b, the insulating layer 116a may have more defects than the insulating layer 116b. Therefore, when the insulating layer 116 has a single-layer structure including only the insulating layer 116a, the insulating layer 116 as a whole has more defects. Therefore, when the insulating layer 116 has a stacked structure including the insulating layers 116a and 116b, the insulating layer 116 as a whole can have fewer defects.

[0203] The thickness of the insulating layer 116b is preferably 0.5 to 30 times the thickness of the insulating layer 116a, more preferably 1 to 25 times, further preferably 2 to 20 times, further preferably 3 to 10 times, and further preferably 4 to 5 times. By forming the insulating layer 116 with a stacked structure, the insulating layer 116 has blocking properties against hydrogen, water, and oxygen, and can suppress reduction of the surface of the semiconductor layer 108 during the formation of the insulating layer 116, and can reduce the amount of defects in the insulating layer 116.

[0204] The insulating layer 116a and the insulating layer 116b are preferably successively formed using a plasma CVD apparatus without exposure to the air. By successively forming the layers, it is possible to prevent impurities from adhering to the interface between the insulating layer 116a and the insulating layer 116b. Furthermore, the insulating layer 116a, the insulating layer 116b, and the insulating layer 118 are preferably successively formed using a plasma CVD apparatus without exposure to the air. By successively forming the layers, it is possible to prevent impurities from adhering to the interface between the insulating layer 116a and the insulating layer 116b, and the interface between the insulating layer 116b and the insulating layer 118.

[0205] This concludes the description of configuration example 3.

[0206] <Configuration Example 4> 9A is a top view of the transistor 100C, FIG. 9B is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 9C is a cross-sectional view of the transistor 100C in the channel width direction.

[0207] The transistor 100C differs from the transistor 100 mainly in that a conductive layer 106 is provided between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with a channel formation region of the semiconductor layer 108, a metal oxide layer 114, and a conductive layer 112.

[0208] In the transistor 100C, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 103 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

[0209] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 108 overlapping with the conductive layer 112 may be referred to as a channel formation region hereinafter; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (a portion including a region 108N).

[0210] 9A and 9C, the conductive layer 106 may be electrically connected to the conductive layer 112 through the metal oxide layer 114, the insulating layer 110, and the opening 142 provided in the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be applied with the same potential.

[0211] The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because the wiring resistance can be reduced. Furthermore, if a material containing a high melting point metal such as tungsten or molybdenum is used for the conductive layer 106, processing can be performed at a high temperature in a later step.

[0212] 9A and 9C, in the channel width direction, the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portion of the semiconductor layer 108. In this case, as shown in FIG. 9C, the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0213] With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This makes it possible to effectively apply an electric field for inducing a channel in the semiconductor layer 108, thereby increasing the on-state current of the transistor 100C. This also enables miniaturization of the transistor 100C.

[0214] Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 100C may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 100C is driven by the other electrode can also be controlled by the potential applied to one electrode.

[0215] The insulating layer 103 may have a layered structure. 9B and 9C show an example in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are layered in this order from the conductive layer 106 side. The insulating layer 103a is in contact with the conductive layer 106. The insulating layer 103a is preferably a film capable of blocking a metal element contained in the conductive layer 106. The insulating layer 103a, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d can be described above, and detailed description thereof will be omitted.

[0216] In the case where a metal film or an alloy film that is not likely to diffuse into the insulating layer 103 is used as the conductive layer 106, the insulating layer 103a may not be provided, and three insulating films, that is, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d, may be stacked.

[0217] By using the insulating layer 103 having such a stacked structure, a highly reliable transistor can be realized.

[0218] This concludes the description of configuration example 4.

[0219] <Production method example 1> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100C given as an example in the above structure example will be described.

[0220] The thin films (insulating film, semiconductor film, conductive film, etc.) that constitute the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0221] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0222] The thin film constituting the semiconductor device can be processed by photolithography or the like. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Also, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0223] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0224] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0225] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0226] 10 to 14 show cross sections of the transistor 100C at various stages in a manufacturing process thereof. In each of the drawings, a cross section in the channel length direction is shown on the left side of a dashed line in the center, and a cross section in the channel width direction is shown on the right side.

[0227] [Formation of Conductive Layer 106] A conductive film is formed on a substrate 102 and processed by etching to form a conductive layer 106 that functions as a first gate electrode (FIG. 10A).

[0228] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 10B). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0229] Here, insulating layer 103a, insulating layer 103b, insulating layer 103c, and insulating layer 103d are stacked to form insulating layer 103. In particular, each insulating layer constituting insulating layer 103 is preferably formed by PECVD.

[0230] The insulating layer 103a preferably has a function of blocking impurities. By providing the insulating layer 103a, it is possible to suppress the diffusion of impurities from layers below the insulating layer 103 to layers above the insulating layer 103. It is preferable that the insulating layer 103b has low stress and high withstand voltage. By providing the insulating layer 103b, the insulating layer 103 can be made to have low stress and high withstand voltage. It is preferable that the insulating layer 103c releases little impurities containing hydrogen and has a function of blocking impurities containing hydrogen. By providing the insulating layer 103c, it is possible to suppress the diffusion of hydrogen to a channel formation region. It is preferable that the insulating layer 103d has low defect density and releases little impurities containing hydrogen.

[0231] A case where silicon nitride films are used for the insulating layers 103a, 103b, and 103c, and a silicon oxynitride film is used for the insulating layer 103d will be described. The insulating layer 103a is formed by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia. Next, the insulating layer 103b, which has low stress and high dielectric strength, is formed using a mixed gas with a higher ammonia flow rate than the insulating layer 103a. Next, the insulating layer 103c, which releases less impurities containing hydrogen and has a function of blocking impurities containing hydrogen, is formed using a mixed gas with a lower ammonia flow rate than the insulating layer 103b. Next, the insulating layer 103d, which has low defect density and releases less impurities containing hydrogen, is formed using a mixed gas of silane and dinitrogen monoxide, so that the insulating layer 103 can be formed. Furthermore, by switching the film formation conditions in the same chamber, the insulating layers 103a, 103b, 103c, and 103d can be successively formed in a vacuum, and the insulating layer 103 can be formed with high productivity.

[0232] Alternatively, after the insulating layer 103c is formed, a plasma treatment is performed in an atmosphere containing oxygen to oxidize the surface of the insulating layer 103c, whereby the insulating layer 103d can be formed on the insulating layer 103c.

[0233] The insulating layer 103b may have a lower film density than the insulating layers 103a and 103c. The difference in film density between the insulating layers 103a, 103b, and 103c may be evaluated by, for example, the density (brightness) of a TEM image. Furthermore, the insulating layer 103b may have a higher hydrogen concentration in the film than the insulating layers 103a and 103c. The difference in hydrogen concentration between the insulating layers 103a, 103b, and 103c may be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0234] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, a plasma treatment or a heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method, an ion implantation method, or the like.

[0235] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f that will become the semiconductor layer 108 is formed on the insulating layer 103 (FIG. 10C).

[0236] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0237] When forming the metal oxide film 108f, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed with oxygen gas. Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter, also referred to as oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with increased on-current can be obtained.

[0238] When the semiconductor layer 108 has a stacked structure, it is preferable to deposit the films successively in the same deposition chamber using the same sputtering target, since this can improve the interface. In particular, the deposition conditions for each metal oxide film may be different in terms of pressure, temperature, power, and the like during deposition, but it is preferable to keep the conditions other than the oxygen flow rate the same, since this can shorten the time required for the deposition process. In addition, when metal oxide films with different compositions are stacked, it is preferable to deposit the films successively without exposing them to the air.

[0239] It is preferable to set the deposition conditions so that the metal oxide film 108f is a metal oxide film having a CAAC structure, a metal oxide film having an nc structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure. Since the deposition conditions under which the metal oxide film to be deposited has a CAAC structure and the deposition conditions under which the metal oxide film has an nc structure vary depending on the composition of the sputtering target used, the substrate temperature, oxygen flow rate ratio, pressure, power, and the like may be appropriately set according to the composition.

[0240] The metal oxide film 108f may be formed at a substrate temperature between room temperature and 450° C., preferably between room temperature and 300° C., more preferably between room temperature and 200° C., and further preferably between room temperature and 140° C. For example, when a large glass substrate or a resin substrate is used as the substrate 102, it is preferable to set the film formation temperature between room temperature and less than 140° C., since this increases productivity. In addition, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0241] Before forming the metal oxide film 108f, it is preferable to perform a treatment for removing water, hydrogen, organic components, and the like adsorbed on the surface of the insulating layer 103, and a treatment for supplying oxygen into the insulating layer 103. For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Furthermore, if a plasma treatment containing nitrous oxide gas is performed, organic substances on the surface of the insulating layer 103 can be suitably removed. After such a treatment, it is preferable to continuously form a metal oxide film without exposing the surface of the insulating layer 103 to the air.

[0242] Next, the metal oxide film 108f is processed to form island-shaped semiconductor layers 108 (FIG. 10D).

[0243] The metal oxide film may be processed by using either or both of a wet etching method and a dry etching method. At this time, a part of the insulating layer 103d that does not overlap with the semiconductor layer 108 may be etched and removed. By removing the part of the insulating layer 103d, the semiconductor layer 108 and the insulating layer 103d have roughly the same top surface shape. By removing the part of the insulating layer 103d, a part of the insulating layer 103c is exposed, and a structure can be formed in which the insulating layer 116, which will be formed later, and the insulating layer 103c are in contact with each other.

[0244] After the metal oxide film is formed or after it is processed into the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment can be typically set to 150° C. or higher and lower than the distortion point of the substrate, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower. Note that the heat treatment does not have to be performed after the metal oxide film is formed or after it is processed into the semiconductor layer 108. The heat treatment may be performed at any stage after the metal oxide film is formed. Alternatively, the heat treatment may be performed together with a later heat treatment or a step in which heat is applied.

[0245] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the heat treatment can be performed in the atmosphere containing a rare gas or nitrogen, and then in an atmosphere containing oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, ultra dry air (CDA: Clean Dry Air) can be used. Note that it is preferable that the atmosphere for the heat treatment does not contain hydrogen, water, or the like. By using a gas that has been highly purified to a dew point of −60° C. or less, preferably −100° C. or less, it is possible to prevent hydrogen, water, or the like from being taken into the semiconductor layer 108 as much as possible. The heat treatment can be performed using an electric furnace, a rapid thermal annealing (RTA: Rapid Thermal Annealing) device, or the like. By using an RTA device, the heat treatment time can be shortened.

[0246] It is preferable to form the insulating film 110f promptly after forming the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed onto the surface of the semiconductor layer 108. When water is adsorbed onto the surface of the semiconductor layer 108, hydrogen is diffused into the semiconductor layer 108 by a subsequent heat treatment or the like, and V O H may be formed. V O Since H can be a carrier generation source, it is preferable that the amount of adsorbed water in the semiconductor layer 108 is small.

[0247] [Formation of insulating film 110f] Subsequently, an insulating film 110f is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 11A).

[0248] The insulating film 110f is a film that will later become the insulating layer 110. The insulating film 110f is preferably formed by forming an oxide film, such as a silicon oxide film or a silicon oxynitride film, using a plasma enhanced chemical vapor deposition apparatus (PECVD apparatus, or simply called a plasma CVD apparatus). Alternatively, the insulating film 110f may be formed by using a PECVD method using microwaves.

[0249] Here, an insulating film 110A that will become the insulating layer 110a, an insulating film 110B that will become the insulating layer 110b, and an insulating film 110C that will become the insulating layer 110c are laminated in this order to form the insulating film 110f. In particular, each insulating film that constitutes the insulating film 110f is preferably formed by the PECVD method.

[0250] A case where a silicon oxynitride film is used for the insulating film 110A, the insulating film 110B, and the insulating film 110C will be described. For example, the insulating film 110A is formed by a plasma CVD method using a mixed gas of silane and dinitrogen monoxide. Next, the insulating film 110B is formed under high power conditions using a mixed gas having a higher silane flow rate ratio to dinitrogen monoxide flow rate than the insulating film 110A. Next, the insulating film 110C is formed under low pressure conditions using a mixed gas having a lower silane flow rate ratio to dinitrogen monoxide flow rate than the insulating film 110B, thereby forming the insulating film 110f. Also, by switching the film formation conditions in the same chamber, the insulating film 110A, the insulating film 110B, and the insulating film 110C can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity.

[0251] After the insulating film 110f is formed, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas. Note that the heat treatment does not necessarily have to be performed after the insulating film 110f is formed. The heat treatment may be performed at any stage after the insulating film 110f is formed. The heat treatment may also be performed together with a later heat treatment or a process in which heat is applied.

[0252] It is preferable to perform plasma treatment on the surface of the semiconductor layer 108 before forming the insulating film 110f. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. As a result, impurities at the interface between the semiconductor layer 108 and the insulating film 110f can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating film 110f. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. It is also preferable to perform the plasma treatment and the formation of the insulating film 110f consecutively without exposure to the air.

[0253] Here, after the insulating film 110f is formed, heat treatment is preferably performed. The heat treatment can remove hydrogen or water contained in the insulating film 110f or adsorbed on the surface of the insulating film 110f and can reduce defects in the insulating film 110f.

[0254] The heat treatment conditions may be as described above.

[0255] After the insulating film 110f is formed, or after the above-mentioned heat treatment for removing hydrogen or water is performed, a treatment for supplying oxygen to the insulating film 110f may be performed. For example, a plasma treatment or a heat treatment may be performed in an atmosphere containing oxygen. Alternatively, oxygen may be supplied to the insulating film 110f by a plasma ion doping method or an ion implantation method. For example, a PECVD apparatus may be suitably used for the plasma treatment. When the insulating film 110f is formed using a PECVD apparatus, it is preferable to perform a plasma treatment in a vacuum successively after the formation of the insulating film 110f. By performing the formation of the insulating film 110f and the plasma treatment in a vacuum successively, productivity can be increased.

[0256] When the heat treatment is performed after the treatment of supplying oxygen to the insulating film 110f, it is preferable to perform the heat treatment after a film (e.g., the metal oxide film 114f) is formed on the insulating film 110f. If the heat treatment is performed in a state where the insulating film 110f is exposed, the oxygen supplied to the insulating film 110f may be desorbed to the outside of the insulating film 110f. By performing the heat treatment after a film (e.g., the metal oxide film 114f) is formed on the insulating film 110f, it is possible to prevent the oxygen supplied to the insulating film 110f from being desorbed to the outside of the insulating film 110f.

[0257] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed to cover the insulating film 110f (FIG. 11B).

[0258] The metal oxide film 114f is a film that will later become the metal oxide layer 114. The metal oxide film 114f is preferably formed by, for example, a sputtering method in an atmosphere containing oxygen, which allows oxygen to be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0259] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that of the semiconductor layer 108, the above method can be applied.

[0260] The metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0261] During the formation of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the film formation chamber, the more oxygen can be supplied to the insulating layer 110, which is preferable. The oxygen flow rate ratio or oxygen partial pressure is, for example, higher than 0% and lower than 100%, preferably 10% to 100%, more preferably 20% to 100%, further preferably 30% to 100%, and further preferably 40% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0262] In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating film 110f. As a result, an extremely large amount of oxygen can be trapped in the insulating film 110f. Then, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108 by a subsequent heat treatment, and oxygen vacancies in the channel formation region can be reduced, thereby realizing a highly reliable transistor.

[0263] The metal oxide film 114f may be formed at a substrate temperature between room temperature and 450° C., preferably between room temperature and 300° C., more preferably between room temperature and 200° C., and further preferably between room temperature and 140° C. For example, when a large glass substrate or a resin substrate is used as the substrate 102, it is preferable to set the film formation temperature to between room temperature and 140° C., since this increases productivity. Furthermore, when the film formation temperature of the metal oxide film 114f is high, the crystallinity of the metal oxide film 114f may become high, and the etching rate may become slow. When the film formation temperature of the metal oxide film 114f is low, the crystallinity of the metal oxide film 114f may become low, and the etching rate may become fast. The film formation temperature of the metal oxide film 114f may be appropriately selected so as to obtain a desired etching rate for an etchant used for processing the metal oxide film 114f.

[0264] After the metal oxide film 114f is formed, heat treatment may be performed so that oxygen is supplied from the insulating film 110f to the semiconductor layer 108. The heat treatment may be performed in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas at a temperature of 200° C. to 400° C. Note that the heat treatment does not necessarily have to be performed after the metal oxide film 114f is formed. The heat treatment may be performed at any stage after the formation of the metal oxide film 114f. Alternatively, the heat treatment may be performed together with a later heat treatment or a step in which heat is applied.

[0265] [Formation of Conductive Film 112f] Next, the metal oxide film 114f, the insulating film 110f, and a part of the insulating layer 103 are etched to form an opening 142 that reaches the conductive layer 106. This allows the conductive layer 112, which will be formed later, and the conductive layer 106 to be electrically connected to each other through the opening 142.

[0266] Subsequently, a conductive film 112f which will become the conductive layer 112 is formed on the metal oxide film 114f (FIG. 11C). The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or alloy.

[0267] [Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112] Next, a resist mask 115 is formed over the conductive film 112f (FIG. 12A). After that, the conductive film 112f and the metal oxide film 114f are removed in a region not covered with the resist mask 115, and the conductive layer 112 and the metal oxide layer 114 are formed (FIG. 12B).

[0268] A wet etching method can be preferably used to form the conductive layer 112 and the metal oxide layer 114. For example, an etchant containing hydrogen peroxide can be used for the wet etching method. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be preferably used.

[0269] The conductive layer 112 and the metal oxide layer 114 are processed so that their ends are located inside the contour of the resist mask 115. A wet etching method is preferably used to form the conductive layer 112 and the metal oxide layer 114. The width L2 of the region 108L can be controlled by adjusting the etching time.

[0270] The conductive layer 112 and the metal oxide layer 114 may be formed by first etching the conductive film 112f and the metal oxide film 114f by anisotropic etching, and then etching the side surfaces of the conductive film 112f and the metal oxide film 114f by isotropic etching to recess the end faces (also referred to as side etching). In this way, the conductive layer 112 and the metal oxide layer 114 can be formed to be located inside the insulating layer 110 in a plan view.

[0271] As shown in FIG. 12B, when the conductive layer 112 and the metal oxide layer 114 are formed, the thickness of the insulating film 110f in the region that does not overlap with the conductive layer 112 may be thinner than the thickness of the insulating film 110f in the region that overlaps with the conductive layer 112.

[0272] Note that the conductive layer 112 and the metal oxide layer 114 may be formed by etching at least two times using different etching conditions or techniques. For example, the conductive film 112f may be etched first, and then the metal oxide film 114f may be etched under different etching conditions.

[0273] Next, the insulating film 110f is removed from the region not covered by the resist mask 115 to form the insulating layer 110 (FIG. 12C). The insulating layer 110 can be formed by using either or both of a wet etching method and a dry etching method. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can prevent the conductive layer 112 from becoming thin. When forming the insulating layer 110, the insulating layer 103d from the region not covered by the resist mask 115 may also be removed.

[0274] The width L2 of the region 108L can be controlled by adjusting the conditions for forming the insulating layer 110. For example, the width of the resist mask 115 is reduced by using conditions that cause the resist mask 115 to recede when forming the insulating layer 110. By reducing the width of the resist mask 115, the distance between the end of the resist mask 115 and the end of the conductive layer 112 becomes closer, and as a result, the width L2 of the region 108L can be reduced.

[0275] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0276] Here, cleaning may be performed to remove impurities. By performing cleaning, impurities attached to the exposed regions of the insulating layer 110 and the semiconductor layer 108 can be removed, and degradation of the electrical characteristics and reliability of the transistor can be suppressed. Examples of impurities include components of an etching gas or an etchant that are attached during etching of the insulating film 110f, components of the conductive film 112f, and components of the metal oxide film 114f.

[0277] The cleaning method may be wet cleaning using a cleaning solution or plasma treatment. These cleaning methods may also be combined as appropriate. For wet cleaning, a cleaning solution containing oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like may be used.

[0278] [Formation of insulating layer 116 and region 108N (hydrogen supply process)] Next, a process is performed to supply hydrogen to the exposed region of the semiconductor layer 108. Here, hydrogen is supplied by forming an insulating layer 116 containing hydrogen in contact with the exposed region of the semiconductor layer 108 (FIG. 13A).

[0279] The insulating layer 116 is preferably formed by a plasma CVD method using a deposition gas containing hydrogen. For example, a silicon nitride film is formed using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the film. Also, hydrogen can be supplied to the exposed portion of the semiconductor layer 108 during the film formation.

[0280] After the insulating layer 116 is formed, heat treatment is preferably performed so that part of hydrogen released from the insulating layer 116 is supplied to part of the semiconductor layer 108. The heat treatment is preferably performed in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas at a temperature of 150° C. to 450° C., preferably 200° C. to 400° C.

[0281] By supplying hydrogen in this manner, an extremely low resistance region 108N can be formed in the semiconductor layer 108.

[0282] By the heat treatment, oxygen can be supplied from the insulating layer 110 to the channel formation region of the semiconductor layer .

[0283] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed on the insulating layer 116 (FIG. 13B).

[0284] When the insulating layer 118 is formed by the plasma CVD method, if the deposition temperature is too high, depending on the impurities contained in the region 108N, etc., the impurities may diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108. As a result, the resistance of the channel formation region may decrease, or the resistance of the region 108N may increase. The deposition temperature of the insulating layer 116 or the insulating layer 118 is preferably, for example, 150° C. or more and 400° C. or less, preferably 180° C. or more and 360° C. or less, and more preferably 200° C. or more and 250° C. or less. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0285] After the insulating layer 118 is formed, a heat treatment may be performed.

[0286] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at desired positions on the insulating layer 118, and then the insulating layer 118 and the insulating layer 116 are partially etched to form the opening 141a and the opening 141b that reach the region 108N.

[0287] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 13C).

[0288] Through the above steps, the transistor 100C can be manufactured.

[0289] <Production method example 2> In the following, a configuration in which the end of the conductive layer 112 is located inside the end of the metal oxide layer 114, as exemplified in the transistor 100A of the above-described configuration example, will be described as an example.

[0290] The steps up to forming the resist mask 115 over the conductive film 112f are similar to those in the above-described <Manufacturing method example 1> (see FIG. 12A).

[0291] [Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112] Next, the conductive film 112f and the metal oxide film 114f are removed in the region not covered with the resist mask 115, to form the conductive layer 112 and the metal oxide layer 114 (FIG. 14A).

[0292] A wet etching method can be suitably used for forming the conductive layer 112 and the metal oxide layer 114. At this time, the metal oxide layer 114 is processed so that an end of the metal oxide layer 114 is located inside the contour of the resist mask 115, and an end of the conductive layer 112 is located inside the contour of the metal oxide layer 114. In addition, the width L2 of the region 108L can be controlled by adjusting the etching time.

[0293] The conductive layer 112 and the metal oxide layer 114 may be formed by first etching the conductive film 112f and the metal oxide film 114f using an anisotropic etching method, and then etching the side surfaces of the conductive film 112f and the metal oxide film 114f using an isotropic etching method to recess the end faces.

[0294] As shown in FIG. 14A, when the conductive layer 112 and the metal oxide layer 114 are formed, the thickness of the insulating film 110f in the region that does not overlap with the metal oxide layer 114 may be thinner than the thickness of the insulating film 110f in the region that overlaps with the metal oxide layer 114.

[0295] When forming the conductive layer 112 and the metal oxide layer 114, the ends of the conductive layer 112 may be recessed from the ends of the metal oxide layer 114, and the thickness of the metal oxide layer 114 in areas that do not overlap with the conductive layer 112 may be thinner than the thickness of the metal oxide layer 114 in areas that overlap with the conductive layer 112.

[0296] Next, the insulating film 110f is removed from the region not covered with the resist mask 115 to form the insulating layer 110 (FIG. 14B). Either or both of a wet etching method and a dry etching method can be used to form the insulating layer 110. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but by leaving the resist mask 115, the thickness of the conductive layer 112 can be prevented from becoming thin.

[0297] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0298] Since the steps after the formation of the insulating layer 116 can be referred to in the description of <Fabrication Method Example 1>, detailed description will be omitted.

[0299] <Components of Semiconductor Device> Next, components included in the semiconductor device of this embodiment will be described in detail.

[0300] 〔substrate〕 There are no significant limitations on the material of the substrate 102, but the substrate must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may be used as the substrate 102.

[0301] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device that is partially or entirely completed thereon from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0302] [Insulating layer 103] The insulating layer 103 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like as appropriate. The insulating layer 103 can be formed, for example, by using a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve the interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 103 that is in contact with the semiconductor layer 108 is preferably formed of an oxide insulating film. The insulating layer 103 is preferably formed using a film that releases oxygen when heated.

[0303] The insulating layer 103 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like, and may be formed as a single layer or a stacked layer.

[0304] In the case where a film other than an oxide film, such as a silicon nitride film, is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform a pretreatment such as an oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0305] [Conductive Film] The conductive layer 106, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements.

[0306] The conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be formed of an oxide conductor or a metal oxide film, such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0307] Here, an oxide conductor (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0308] The conductive layer 106 or the like may have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0309] The conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably contain one or more of the above-mentioned metal elements selected from titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferably used. The tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, and therefore can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0310] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film of the transistor 100 or the like, can be formed by a PECVD method, a sputtering method, or the like. The insulating layer 110 can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.

[0311] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed insulating layer 110 in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0312] A material such as hafnium oxide, which has a higher dielectric constant than silicon oxide or silicon oxynitride, can be used as the insulating layer 110. This allows the insulating layer 110 to be thicker and suppresses leakage current due to tunnel current. In particular, crystalline hafnium oxide is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

[0313] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used for depositing the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. Examples of atomic ratios of metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and the like.

[0314] It is preferable to use a target containing a polycrystalline oxide as the sputtering target because it is easy to form the semiconductor layer 108 having crystallinity. The atomic ratio of the semiconductor layer 108 to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0315] When the atomic ratio is described as In:Ga:Zn=4:2:3 or thereabout, this includes the case where, when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:Ga:Zn=5:1:6 or thereabout, this includes the case where, when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is greater than 5 and 7 or less. When the atomic ratio is described as In:Ga:Zn=1:1:1 or thereabout, this includes the case where, when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0316] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon in this manner, the off-state current of the transistor can be reduced.

[0317] It is preferable to use a metal oxide having a low carrier concentration for the semiconductor layer 108. In the case of lowering the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0318] In particular, hydrogen contained in metal oxide reacts with oxygen that bonds to metal atoms to form water, which may cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region in the metal oxide, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to have normally-on characteristics.

[0319] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0320] Therefore, it is preferable to reduce hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0321] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0322] The semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0323] In the following, we explain about CAAC (c-axis aligned crystal). CAAC is an example of a crystal structure.

[0324] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0325] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0326] In crystallography, it is common to take a unit cell with a specific axis as the c-axis out of the three axes (crystal axes) that make up the unit cell: the a-axis, the b-axis, and the c-axis. In particular, in crystals with a layered structure, it is common to take the two axes parallel to the plane direction of the layers as the a-axis and the b-axis, and the axis that intersects the layers as the c-axis. A typical example of a crystal with such a layered structure is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, YbFe 2 O 4 InGaZnO with a type crystal structure 4 The crystals can be classified as hexagonal, with the a-axis and b-axis of the unit cell being parallel to the plane of the layers and the c-axis being perpendicular to the layers (i.e., the a-axis and b-axis).

[0327] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly identified in an image observed by TEM. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, for example, in an nc-OS film, crystal grain boundaries may not be clearly identified.

[0328] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus using X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane analysis. In addition, when the nc-OS film is subjected to electron beam diffraction (also called selected area electron beam diffraction) using an electron beam with a probe diameter larger than that of the crystal parts (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (for example, 1 nm to 30 nm) that is close to or smaller than the size of the crystal part, a circular (ring-shaped) area of ​​high brightness is observed, and multiple spots may be observed within that area.

[0329] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier concentration and higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0330] The nc-OS film can be formed by lowering the oxygen flow rate ratio during film formation compared to the CAAC-OS film. Also, the nc-OS film can be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (for example, 130°C or lower) or without heating the substrate, making it suitable for use on large glass substrates or resin substrates, and improving productivity.

[0331] An example of the crystal structure of a metal oxide will be described. In the following, a metal oxide film formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) will be described as an example. A metal oxide formed by a sputtering method using the above target and with a substrate temperature of 100°C to 130°C tends to have either a crystalline structure of nc (nano crystal) structure or a CAAC structure, or a mixed structure of these. On the other hand, a metal oxide formed by a sputtering method with a substrate temperature of room temperature (RT) tends to have an nc crystalline structure. Note that room temperature (RT) here includes the temperature when the substrate is not heated.

[0332] <Metal oxide composition> A structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0333] In this specification, etc., the term CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be used. CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0334] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole has a function as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) that become carriers, and the insulating function is a function of not flowing electrons that become carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0335] CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0336] In the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0337] CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are made to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0338] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0339] The above is a description of the components.

[0340] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0341] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0342] <Configuration example> 15A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0343] An FPC terminal portion 708 to which an FPC 716 (Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716 via the FPC terminal portion 708 and signal lines 710.

[0344] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0345] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be the transistors that are the semiconductor device of one embodiment of the present invention.

[0346] Examples of the display element provided in the pixel unit 702 include a liquid crystal element and a light-emitting element. The liquid crystal element may be a transmissive liquid crystal element, a reflective liquid crystal element, or a semi-transmissive liquid crystal element. Examples of the light-emitting element may be a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), or a semiconductor laser. In addition, a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, or a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type may also be used.

[0347] A display device 700A shown in FIG. 15B is an example of a display device in which a flexible resin layer 743 is applied instead of the first substrate 701 and which can be used as a flexible display.

[0348] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 15B, the pixel section 702 and the resin layer 743 have cutouts formed by cutting out parts of them. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are provided at the corners of the pixel section 702 along the arc-shaped contour.

[0349] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. A portion of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in an area P2 in Fig. 15B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 overlapping the rear side of the pixel portion 702, thereby saving space in the electronic device.

[0350] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0351] 15C is a display device that can be suitably used in electronic devices having a large screen. The display device 700B can be suitably used in, for example, a television device, a monitor device, a personal computer (including a notebook type or a desktop type), a tablet terminal, a digital signage, and the like.

[0352] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0353] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0354] On the other hand, the gate driver circuit portion 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0355] With this configuration, a large-sized, high-resolution display device can be realized. For example, a display device with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K resolution can be realized.

[0356] <Cross-section configuration example> A configuration using liquid crystal elements as display elements and a configuration using EL elements will be described below with reference to Figs. 16 to 19. Figs. 16 to 18 are cross-sectional views taken along dashed line QR in Fig. 15A. Fig. 19 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 15B. Figs. 16 and 17 show configurations using liquid crystal elements as display elements, and Figs. 18 and 19 show configurations using EL elements.

[0357] [Description of common parts of the display device] 16 to 19 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 17 illustrates a case where the capacitor 790 is not included.

[0358] The transistors described in Embodiment 1 can be used as the transistors 750 and 752.

[0359] The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be reduced. Thus, the retention time of an electric signal such as an image signal can be increased, and the writing interval of the image signal can be set to be long. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0360] The transistor used in this embodiment mode can achieve high-speed driving because it has a relatively high field-effect mobility. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed on the same substrate. That is, a configuration without using a driver circuit formed from a silicon wafer or the like is possible, and the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0361] The capacitor 790 shown in FIG. 16, FIG. 18, and FIG. 19 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a low resistance like the source and drain regions of the transistor 750. In addition, a part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. In addition, a wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0362] A planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0363] The transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the gate driver circuit portion 706 is similar to the source driver circuit portion 704.

[0364] The signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because signal delays caused by wiring resistance are small and display on a large screen is possible.

[0365] The FPC terminal portion 708 has a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0366] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0367] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0368] [Example of the configuration of a display device using a liquid crystal element] A display device 700 shown in FIG. 16 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0369] A material that transmits or reflects visible light can be used for the conductive layer 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0370] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0371] 17 shows an example of a display device 700 using a horizontal electric field (for example, FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0372] 17, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0373] 16 and 17, an alignment film may be provided in contact with the liquid crystal layer 776. In addition, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0374] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0375] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0376] A scattering type liquid crystal using a polymer dispersed type liquid crystal or a polymer network type liquid crystal can be used for the liquid crystal layer 776. In this case, a configuration for performing black and white display without providing the colored film 736, or a configuration for performing color display using the colored film 736 can be used.

[0377] A time-division display method (also called a field sequential driving method) that performs color display based on a time-sequential additive color mixing method may be applied as a driving method for the liquid crystal element. In this case, the color film 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0378] [Display device using light-emitting element] 18 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0379] Examples of materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, while examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0380] 18, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that has a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0381] The colored film 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided at a position overlapping with the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

[0382] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 19. Fig. 19 is a cross-sectional view of the display device 700A shown in Fig. 15B taken along dashed line ST.

[0383] 19 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 instead of the first substrate 701 shown in FIG. 19. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0384] The support substrate 745 is a substrate containing an organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide resin or acrylic resin. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are attached to each other by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0385] A display device 700 shown in Fig. 19 has a protective layer 740 instead of the substrate 705 shown in Fig. 18. The protective layer 740 is attached to a sealing film 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. In addition, an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be used as the protective layer 740.

[0386] An EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By creating the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored film 736. A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. Moreover, a layered structure including at least one inorganic insulating film and at least one organic insulating film is more preferably used.

[0387] FIG. 19 shows a bendable region P2. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0388] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display devices shown in Figures 16 to 19. Examples of the input device include a touch sensor.

[0389] For example, the sensor may be of various types, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0390] The touch panel may have a configuration such as an in-cell type touch panel in which an input device is formed between a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on a display device, or an out-cell type touch panel in which the input device is attached to a display device.

[0391] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0392] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0393] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0394] 20A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0395] The transistor of one embodiment of the present invention can be applied to the transistors in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0396] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0397] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the scan lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include, for example, a plurality of analog switches. The source driver 504b may also include a shift register.

[0398] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0399] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 20A is connected to various wirings such as the scanning lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or the data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501.

[0400] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0401] The pixel circuits 501 shown in FIG. 20A can have the configurations shown in FIGS. 20B and 20C, for example.

[0402] 20B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL, and the like.

[0403] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0404] 20C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0405] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0406] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0407] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0408] (Embodiment 4) In the following, a pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described. The transistors exemplified in the first embodiment can be applied to the transistors used in the pixel circuits exemplified below.

[0409] <Circuit configuration> 21A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0410] The transistor M1 has a gate connected to the wiring G1, one of its source and drain connected to the wiring S1, and the other of its source and drain connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of its source and drain connected to the wiring S2, and the other of its source and drain connected to the other electrode of the capacitor C1 and the circuit 401.

[0411] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0412] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0413] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0414] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistor M1 and the transistor M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potentials of the nodes are held is short (specifically, when the frame frequency is 30 Hz or more), a transistor including a semiconductor such as silicon may be used.

[0415] <Driving method example> Next, an example of an operation method of the pixel circuit 400 will be described with reference to Fig. 21B. Fig. 21B is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0416] 21B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0417] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0418] The node N1 is connected to a potential V ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0419] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0420] The node N1 receives a second data potential V data At this time, the second data potential V data In response to the change in potential, the potential of the node N2 changes by a potential dV. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that although the potential dV is shown to be a positive value in FIG. 21B, it may be a negative value. That is, the potential of the second data potential V data is the potential V ref It may be lower.

[0421] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0422] In this manner, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals. Therefore, it is possible to perform gray scale correction within the pixel circuit 400.

[0423] The pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0424] <Application Examples> [Example using liquid crystal element] The pixel circuit 400LC shown in Fig. 21C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0425] The liquid crystal element LC has one electrode connected to the other electrode of the capacitance C1, the other electrodes of the source and drain of the transistor M2, and one electrode of the capacitance C2, and the other electrode is connected to a potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0426] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0427] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, it can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0428] [Example using light-emitting element] The pixel circuit 400EL shown in Fig. 21D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0429] The transistor M3 has a gate connected to one electrode of the capacitor C2, a source and a drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL. com The light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0430] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0431] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L You can change the value as appropriate.

[0432] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, thereby realizing, for example, HDR display, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0433] Note that the circuits are not limited to those illustrated in FIGS. 21C and 21D, and may be configured to include additional transistors, capacitors, and the like.

[0434] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0435] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0436] A display module 6000 shown in FIG. 22A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0437] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0438] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0439] The display device 6006 may have a function as a touch panel.

[0440] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0441] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0442] FIG. 22B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0443] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0444] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0445] Light 6018 emitted from a light-emitting unit 6015 passes through a light-guiding unit 6017a, an upper portion of the display device 6006, and a light-guiding unit 6017b to reach a light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0446] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation has been performed.

[0447] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0448] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0449] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0450] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0451] Electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone.

[0452] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0453] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0454] FIG. 23B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0455] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0456] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0457] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0458] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0459] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0460] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0461] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0462] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0463] Examples of electronic devices include electronic devices with relatively large screens, such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0464] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0465] FIG. 24A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0466] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0467] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0468] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0469] The housing 8001 has a mount having electrodes, and can be connected to a strobe device and the like in addition to the finder 8100 .

[0470] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0471] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0472] The button 8103 has a function such as a power button.

[0473] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0474] FIG. 24B is a diagram showing the external appearance of the head mounted display 8200.

[0475] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0476] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0477] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes capable of detecting a current flowing with the movement of the user's eyeball at positions that come into contact with the user. The wearing unit 8201 may also have a function of monitoring the user's pulse rate by the current flowing through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0478] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0479] 24C, 24D, and 24E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0480] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0481] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG. 24E, and a more realistic image can be displayed.

[0482] The electronic device shown in Figures 25A to 25G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0483] The electronic device shown in FIG. 25A to FIG. 25G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, etc. The functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have multiple display units. In addition, the electronic device may have a function of providing a camera or the like to capture still images and videos and store them on a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, etc.

[0484] The electronic device shown in FIGS. 25A to 25G will be described in detail below.

[0485] 25A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0486] FIG. 25B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 25B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mails, SNS, and phone calls, titles of e-mails and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, icons 9050 and the like may be displayed at the position where the information 9051 is displayed.

[0487] 25C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

[0488] FIG. 25D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. The charging operation may be performed by wireless power supply.

[0489] 25E, 25F, and 25G are perspective views showing a foldable mobile information terminal 9201. FIG. 25E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 25G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 25F is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 25E and FIG. 25G to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0490] 26A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0491] 26A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television device 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0492] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0493] 26B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display unit 7500 is incorporated in the housing 7211.

[0494] 26C and 26D show an example of digital signage.

[0495] 26C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0496] 26D shows a digital signage 7400 attached to a cylindrical pole 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pole 7401.

[0497] The larger the display unit 7500, the more information can be provided at one time, and the larger the display area, the more easily it catches people's attention, which has the effect of increasing the effectiveness of advertising, for example.

[0498] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes, but also for providing users with information they require, such as route information, traffic information, and commercial facility guidance information.

[0499] 26C and 26D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly communicate with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0500] A game using the information terminal 7311 as an operation means (controller) can also be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0501] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 26A to 26D.

[0502] Although the electronic device in this embodiment has a display portion, one embodiment of the present invention can also be applied to an electronic device that does not have a display portion.

[0503] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. EXAMPLES

[0504] In this example, samples (sample A1 to sample A6) corresponding to the transistor 100C shown in FIG. 9 were fabricated, and the drain current-drain voltage characteristics (Id-Vd characteristics) of the transistors were evaluated.

[0505] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0506] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order.

[0507] The first silicon nitride film and the third silicon nitride film were each formed by PECVD using a mixed gas of silane gas at a flow rate of 200 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 100 Pa, the film formation power was 2000 W, and the substrate temperature was 350° C. The first silicon nitride film corresponds to the insulating layer 103a shown in the first embodiment, and the third silicon nitride film corresponds to the insulating layer 103c shown in the first embodiment.

[0508] The second silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 290 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 2000 sccm. The pressure during film formation was 200 Pa, the film formation power was 3000 W, and the substrate temperature was 350° C. The second silicon nitride film corresponds to the insulating layer 103b shown in the first embodiment.

[0509] The first silicon oxynitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 20 sccm and nitrous oxide gas at a flow rate of 3000 sccm. The pressure during film formation was 40 Pa, the film formation power was 3000 W, and the substrate temperature was 350° C. The first silicon oxynitride film corresponds to the insulating layer 103d described in the first embodiment.

[0510] Next, a first metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.3 Pa, the power source was 4.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the ratio of the flow rate of oxygen gas to the total flow rate of the film formation gas (hereinafter referred to as the oxygen flow rate ratio) was 10%. The film composition of the sample formed using a target with a composition of In:Ga:Zn=4:2:4.1 [atomic ratio] was approximately In:Ga:Zn=4:2:3 [atomic ratio].

[0511] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0512] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0513] Subsequently, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order as a second gate insulating layer.

[0514] The second silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 24 sccm and nitrous oxide gas with a flow rate of 18,000 sccm. The pressure during film formation was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350° C. The second silicon oxynitride film corresponds to the insulating layer 110a described in the first embodiment.

[0515] The third silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm and nitrous oxide gas with a flow rate of 10,000 sccm. The pressure during film formation was 300 Pa, the film formation power was 750 W, and the substrate temperature was 350° C. The third silicon oxynitride film corresponds to the insulating layer 110b described in the first embodiment.

[0516] The fourth silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and nitrous oxide gas with a flow rate of 3000 sccm. The pressure during film formation was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350° C. The fourth silicon oxynitride film corresponds to the insulating layer 110c described in the first embodiment.

[0517] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0518] Next, a second metal oxide film having a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the source power was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.

[0519] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0520] Next, an ITSO film having a thickness of 10 nm and a copper film having a thickness of 100 nm were formed in this order on the second metal oxide film. The ITSO film and the copper film were formed by a sputtering method. The ITSO film was formed using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 = 85:10:5 [weight ratio]) was used. A Cu target was used for depositing the copper film.

[0521] Next, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. A wet etching method was used for the processing. As an etchant, two chemical solutions, chemical solution A and chemical solution B, were mixed at a volume ratio of 5:1 just before use and used. Chemical solution A was an aqueous solution of phosphoric acid (less than 5 weight%), hydrofluoric acid (less than 1 weight%), nitric acid (less than 10 weight%), and additives (less than 22 weight%). Chemical solution B was an aqueous solution of hydrogen peroxide (31 weight%). The etchant temperature during etching was 30°C.

[0522] The wet etching treatment time was different for each of samples A1 to A6, and the width L2 of the region 108L was different. The wet etching treatment time for sample A1 was 60 seconds, the wet etching treatment time for sample A2 was 75 seconds, the wet etching treatment time for sample A3 was 90 seconds, the wet etching treatment time for sample A4 was 105 seconds, the wet etching treatment time for sample A5 was 120 seconds, and the wet etching treatment time for sample A6 was 135 seconds.

[0523] Next, cleaning was performed. For cleaning, an aqueous solution of 85 weight % phosphoric acid diluted 500 times was used. The etchant temperature during etching was room temperature, and the processing time was 15 seconds.

[0524] Next, the second to fourth silicon oxynitride films were processed using the resist mask described above as a mask to form a second gate insulating layer. When the second gate insulating layer was formed, the first silicon oxynitride film was removed from a region that did not overlap with the resist mask to expose a part of the third silicon nitride film. A dry etching method was used for the processing. After this, the resist mask was removed.

[0525] Subsequently, a fourth silicon nitride film having a thickness of 100 nm and a fifth silicon oxynitride film having a thickness of 300 nm were formed in this order as protective layers covering the transistors.

[0526] The fourth silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0527] The fifth silicon oxynitride film was formed by a PECVD method using a mixed gas of silane gas at a flow rate of 290 sccm and dinitrogen monoxide gas at a flow rate of 4000 sccm under a pressure of 133 Pa, a film-forming power of 1000 W, and a substrate temperature of 350° C.

[0528] Next, a part of the protective layer covering the transistor was opened, and a 30 nm thick titanium film, a 100 nm thick copper film, and a 50 nm thick titanium film were formed in that order by sputtering, and then processed to obtain source and drain electrodes. After that, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarizing layer, and a heat treatment was performed under conditions of a nitrogen atmosphere at a temperature of 250°C for 1 hour.

[0529] Transistors (sample A1 to sample A6) formed on the glass substrate were obtained through the above processes.

[0530] <Id-Vd Characteristic Evaluation> Subsequently, the Id-Vd characteristics of the transistors fabricated above were measured.

[0531] The Id-Vd characteristics of the transistors were measured by setting the source potential to the ground potential (GND) and sweeping the drain voltage (Vd) in the range from 0 V to 30 V at intervals of 0.25 V. The Id-Vd measurements were continuously performed using the same transistors under four conditions of gate voltage (Vg) being 0 V, 2 V, 4 V, and 6 V. The transistors had a channel length of 3 μm and a channel width of 10 μm.

[0532] The Id-Vd characteristics of sample A1 to sample A6 are shown in FIGS. 27 and 28. In FIGS. 27 and 28, the horizontal axis represents the drain voltage (Vd), and the vertical axis represents the drain current (Id).

[0533] In FIGS. 27 and 28, the results of sample A1 to sample A6 are shown horizontally. Note that for sample A1, the width L2 was approximately 200 nm, for sample A2, the width L2 was approximately 300 nm, for sample A3, the width L2 was approximately 400 nm, for sample A4, the width L2 was approximately 500 nm, for sample A5, the width L2 was approximately 600 nm, and for sample A6, the width L2 was approximately 700 nm.

[0534] 27 and 28 show conditions where the transistor structure is different in the vertical direction. "Single Gate" indicates the result of Id-Vd measurement performed by applying a gate voltage (Vg) to the conductive layer 112 in a transistor that does not have a conductive layer 106. "Source Sync." indicates the result of Id-Vd measurement performed by applying a gate voltage (Vg) to the conductive layer 112 (top gate electrode) in a transistor that has a conductive layer 106, with the conductive layer 106 (bottom gate electrode) electrically connected to the source electrode (GND). "Top Gate Sync." indicates the result of Id-Vd measurement performed by applying a gate voltage (Vg) to the conductive layer 112 (top gate electrode) in a transistor that has a conductive layer 106, with the conductive layer 106 (bottom gate electrode) electrically connected to the conductive layer 112 (top gate electrode).

[0535] As shown in Figures 27 and 28, the Single Gate showed good Id-Vd characteristics under all conditions. For the Source Sync. and Top Gate Sync., a decrease in on-current was confirmed when the width L2 was approximately 200 nm, approximately 300 nm, and approximately 400 nm, but no decrease in on-current was confirmed when the width L2 was approximately 500 nm or more, showing good Id-Vd characteristics. It was confirmed that by increasing the width L2, the decrease in on-current when a high drain voltage is applied can be suppressed. EXAMPLES

[0536] In this example, samples (samples B1 to B3) corresponding to the regions 108C, 108L, and 108N shown in Fig. 2 were fabricated, and the resistances of the regions 108C, 108L, and 108N were evaluated. Sample B1 corresponds to the region 108C, sample B2 corresponds to the region 108L, and sample B3 corresponds to the region 108N.

[0537] <Sample preparation: Sample B1> First, a first metal oxide film having a thickness of 25 nm was formed on a glass substrate. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 10%.

[0538] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0539] Subsequently, a first silicon oxynitride film having a thickness of 5 nm, a second silicon oxynitride film having a thickness of 130 nm, and a third silicon oxynitride film having a thickness of 5 nm were formed in this order.

[0540] The first silicon oxynitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 24 sccm and dinitrogen monoxide gas at a flow rate of 18,000 sccm under a pressure of 200 Pa, a power of 130 W, and a substrate temperature of 350° C.

[0541] The second silicon oxynitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 200 sccm and dinitrogen monoxide gas at a flow rate of 10,000 sccm under a pressure of 300 Pa, a power of 750 W, and a substrate temperature of 350° C.

[0542] The third silicon oxynitride film was formed by a PECVD method using a mixed gas of silane gas at a flow rate of 20 sccm and dinitrogen monoxide gas at a flow rate of 3000 sccm under a pressure of 40 Pa, a power of 500 W, and a substrate temperature of 350° C.

[0543] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0544] Next, a second metal oxide film having a thickness of 20 nm was formed on the third silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the source power was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.

[0545] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0546] Next, an ITSO film having a thickness of 10 nm and a copper film having a thickness of 100 nm were formed in this order on the second metal oxide film. The ITSO film and the copper film were formed by a sputtering method. The ITSO film was formed using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 = 85:10:5 [weight ratio]) was used. A Cu target was used for depositing the copper film.

[0547] Subsequently, a silicon nitride film was formed to a thickness of 100 nm.

[0548] The silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0549] Subsequently, the silicon nitride film, the copper film, the ITSO film and the second metal oxide film were removed to expose the third silicon oxynitride film.

[0550] Subsequently, openings reaching the first metal oxide film were formed in the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film, and terminals were provided.

[0551] <Sample preparation: Sample B2> First, a first metal oxide film, a first silicon oxynitride film, a second silicon oxynitride film, a third silicon oxynitride film, a second metal oxide film, an ITSO film, and a copper film were formed on a glass substrate. Since the description of <Sample B1> can be referred to for the formation of the copper film, detailed description is omitted.

[0552] Subsequently, the copper film, the ITSO film and the second metal oxide film were removed to expose the third silicon oxynitride film.

[0553] Subsequently, a silicon nitride film was formed to a thickness of 100 nm.

[0554] The silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0555] Subsequently, openings reaching the first metal oxide film were formed in the first silicon oxynitride film, the second silicon oxynitride film, the third silicon oxynitride film, and the silicon nitride film, and terminals were provided.

[0556] <Sample preparation: Sample B3> First, a first metal oxide film, a first silicon oxynitride film, a second silicon oxynitride film, a third silicon oxynitride film, a second metal oxide film, an ITSO film, and a copper film were formed on a glass substrate. Since the description of <Sample B1> can be referred to for the formation of the copper film, detailed description is omitted.

[0557] Subsequently, the copper film, the ITSO film, the second metal oxide film, the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film were removed to expose the first metal oxide film.

[0558] Subsequently, a silicon nitride film was formed to a thickness of 100 nm.

[0559] The silicon nitride film was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 350°C.

[0560] Subsequently, an opening reaching the first metal oxide film was formed in the silicon nitride film, and a terminal was provided therein.

[0561] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the first metal oxide film.

[0562] The sheet resistance values ​​of samples B1 to B3 are shown in Fig. 29. In Fig. 29, the horizontal axis indicates the sample name, and the vertical axis indicates the sheet resistance Rs.

[0563] As shown in FIG. 29, the sheet resistance of sample B1 corresponding to region 108C is about 1.5×10 11 The sheet resistance of sample B2, which corresponds to the area 108L, was 4.6×10 5 The sheet resistance of sample B3, which corresponds to an area of ​​108N, was 8.0×10 2 It was Ω / □. EXAMPLES

[0564] In this example, samples (sample C1 and sample C2) corresponding to the transistor 100A shown in FIG. 5 were fabricated, and their cross-sectional shapes were evaluated.

[0565] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0566] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order. The first to third silicon nitride films and the first silicon oxynitride film can be referred to in the description of Example 1, and therefore detailed description thereof will be omitted.

[0567] Subsequently, a first metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride film. Since the description of the first metal oxide film can be referred to in Example 1, a detailed description thereof will be omitted.

[0568] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0569] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0570] Subsequently, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order as a second gate insulating layer. Since the description of Example 1 can be referred to for the second to fourth silicon oxynitride films, detailed description thereof will be omitted.

[0571] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0572] Subsequently, a second metal oxide film having a thickness of 20 nm was formed on the fourth silicon oxynitride film. Since the description of the second metal oxide film can be referred to in Example 1, detailed description thereof will be omitted.

[0573] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0574] Next, a 10 nm thick ITSO film and a 100 nm thick copper film were formed in this order on the second metal oxide film. The ITSO film and the copper film can be described in Example 1, so detailed description is omitted.

[0575] Next, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. A wet etching method was used for the processing. The etchant can be referred to in the description of Example 1, so a detailed description is omitted. The wet etching time was 60 seconds.

[0576] Next, the second to fourth silicon oxynitride films were processed using the resist mask as a mask to form a second gate insulating layer. A dry etching method was used for the processing. Here, the dry etching conditions were different between sample C1 and sample C2.

[0577] Sample C1 is an etching gas containing C 4 F 8 The ICP RF power was 6000W, the Bias RF power was 1000W, the pressure was 0.67Pa, and the C 4 F 8 The gas flow rate was 100 sccm, the etching time was 140 seconds, and the lower electrode temperature was 10°C.

[0578] Sample C2 uses CF as the etching gas. 4 The ICP RF power was 6000W, the Bias RF power was 750W, the pressure was 0.67Pa, and the CF 4 The gas flow rate was 100 sccm, the etching time was 112 seconds, and the lower electrode temperature was 10°C.

[0579] Then, the resist mask was removed.

[0580] Subsequently, a fourth silicon nitride film having a thickness of 100 nm and a fifth silicon oxynitride film having a thickness of 300 nm were formed in this order as a protective layer covering the transistor. The fourth silicon nitride film and the fifth silicon oxynitride film can be referred to in the description of Example 1, and therefore detailed description thereof will be omitted.

[0581] Next, a part of the protective layer covering the transistor was opened, and a 30 nm thick titanium film, a 100 nm thick copper film, and a 50 nm thick titanium film were deposited in that order by sputtering, and then processed to obtain source and drain electrodes. After that, an acrylic resin with a thickness of about 1.5 μm was applied as a planarizing layer, and a heat treatment was performed under conditions of a nitrogen atmosphere at a temperature of 250°C for 1 hour.

[0582] Through the above steps, transistors (samples C1 and C2) formed on glass substrates were obtained.

[0583] <Cross-section observation> Next, sample C1 and sample C2 were sliced ​​by a focused ion beam (FIB), and the cross sections of sample C1 and sample C2 were observed by STEM.

[0584] <Etching rate evaluation> In the preparation of sample C1 and sample C2, the etching rate was evaluated for the dry etching conditions used in etching the second silicon oxynitride film to the fourth silicon oxynitride film.

[0585] The etching rates are shown in Table 1. In Table 1, the upper row shows the C 4 F 8 The etching rate by gas is shown in the lower part. 4The etching rate by gas is shown. The type of film to be etched is shown horizontally. SiON stands for silicon oxynitride film, SiN stands for silicon nitride film, IGZO stands for metal oxide film, and PR stands for resist film.

[0586] [Table 1]

[0587] A STEM image of the cross section of sample C1 is shown in Figure 30A, and a STEM image of the cross section of sample C2 is shown in Figure 30B. Figures 30A and 30B are transmission electron images (TE images) at a magnification of 80,000 times. In Figures 30A and 30B, the silicon oxynitride layer is indicated as SiON, the silicon nitride layer as SiN, the metal oxide layer as IGZO, the ITSO layer as ITSO, and the copper layer as Cu.

[0588] As shown in Fig. 30A, the width L2 of the region 108L was 233 nm in sample C1, and as shown in Fig. 30B, the width L2 of the region 108L was 157 nm in sample C2.

[0589] As shown in Table 1, the C1 used for the preparation of sample C1 4 F 8 The CF gas used to prepare sample C2 was compared with the 4 It is presumed that the etching rate of the resist film is high, and the amount of retreat of the resist used in forming the second gate insulating layer is large. CF 4 It is believed that the width L2 of sample C2 was small because the amount of resist recession was large in the etching using gas. In other words, it was found that the width L2 of region 108L can be controlled by adjusting the formation conditions of the second gate insulating layer. EXAMPLES

[0590] In this example, samples (samples D1 to D4) corresponding to the transistor 100C shown in FIG. 9 were fabricated, and the drain current-drain voltage characteristics (Id-Vd characteristics) and reliability of the transistors were evaluated. In this example, an indium zinc oxide layer was used as the metal oxide layer 114. In addition, a sample using a copper layer as the conductive layer 112 and a sample using a stacked structure of a copper layer and an indium zinc oxide layer on the copper layer were fabricated.

[0591] In this embodiment, a transistor was fabricated in which the conductive layer 106 (bottom gate electrode) was electrically connected to the conductive layer 112 (top gate electrode).

[0592] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0593] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order. The first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the first silicon oxynitride film can be referred to in the description of Example 1, and therefore detailed description thereof will be omitted.

[0594] Next, a first metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.3 Pa, the source power was 4.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 10%.

[0595] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0596] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0597] Subsequently, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order as a second gate insulating layer. Since the description of Example 1 can be referred to for the second gate insulating layer, the third silicon oxynitride film, and the fourth silicon oxynitride film, detailed description thereof will be omitted.

[0598] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0599] Next, a second metal oxide film having a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an indium zinc oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.

[0600] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0601] Next, in sample D1 and sample D2, a copper film having a thickness of 100 nm was formed on the second metal oxide film as a conductive film. In sample D3 and sample D4, a copper film having a thickness of 100 nm and an indium zinc oxide film having a thickness of 30 nm were formed on the second metal oxide film as a conductive film in this order. The copper film and the indium zinc oxide film were formed by a sputtering method. A Cu target was used for forming the copper film. The indium zinc oxide film was formed by a sputtering method using an indium zinc oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power supply power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%.

[0602] Next, a resist mask was formed on the conductive film, and the second metal oxide film and the conductive film were processed to form a second metal oxide layer and a conductive layer. A wet etching method was used for the processing. The etchant can be referred to in the description of Example 1, so a detailed description is omitted. The wet etching process time was 55 seconds for all samples.

[0603] Next, the second to fourth silicon oxynitride films were processed using the resist mask described above as a mask to form a second gate insulating layer. When the second gate insulating layer was formed, the first silicon oxynitride film was removed from a region that did not overlap with the resist mask to expose a part of the third silicon nitride film. A dry etching method was used for the processing. After this, the resist mask was removed.

[0604] Next, sample D2 and sample D4 were washed. For washing, an aqueous solution of 85 weight % phosphoric acid diluted 500 times was used. The etchant temperature during etching was room temperature, and the treatment time was 15 seconds. Sample D1 and sample D3 were not washed.

[0605] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a fifth silicon oxynitride film with a thickness of 300 nm were formed in this order. For the fourth silicon nitride film and the fifth silicon oxynitride film, since the description in Example 1 can be referred to, detailed explanations are omitted.

[0606] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm, a copper film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were formed in this order by sputtering, and then this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin with a thickness of about 1.5 μm was applied as a planarization layer, and heat treatment was performed under a nitrogen atmosphere at a temperature of 250 °C for 1 hour.

[0607] Transistors (sample D1 to sample D4) formed on the glass substrate were obtained through the above steps.

[0608] <Id-Vg characteristic evaluation> Subsequently, the Id-Vg characteristics of the transistor fabricated above were measured.

[0609] The Id-Vg characteristics of the transistor were measured by applying the voltage applied to the first gate electrode (hereinafter also referred to as gate voltage (Vg)) and the voltage applied to the second gate electrode (hereinafter also referred to as gate voltage (Vbg)) in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as source voltage (Vs)) was set to 0 V (common), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and 5.1 V.

[0610] The Id-Vg characteristics of the transistors of sample E1 to sample E4 are shown in Figs. 31 to 34, respectively. In Figs. 31 to 34, the conditions of the transistor channel length differing in the vertical direction are shown, and three types of transistors with channel lengths of 2 μm, 3 μm, and 6 μm and channel widths of 3 μm are shown. In Figs. 31 to 34, the horizontal axis shows the gate voltage (Vg), the left vertical axis shows the drain current (Id), and the right vertical axis shows the saturation mobility (μFE) at Vd=5.1 V. The Id-Vg characteristics of 20 transistors were measured for each sample. In Figs. 31 to 34, the Id-Vg characteristic results of the 20 transistors are shown overlapping each other.

[0611] 31 to 34 also show the difference (2ΔL) between the design channel length and the effective channel length. The effective channel length was obtained by a TLM (Transmission Line Model) analysis.

[0612] As shown in FIGS. 31 to 34, good electrical characteristics were obtained in all the samples.

[0613] <Reliability evaluation> Next, the reliability of the transistor fabricated above was evaluated. In this example, a PBTS (Positive Bias Temperature Stress) test was performed in which a positive potential was applied to the gate relative to the source potential and drain potential, and the transistor was held at high temperature, and an NBTIS (Negative Bias Temperature Illumination Stress) test was performed in which a negative potential was applied to the gate in a light irradiation environment and the transistor was held at high temperature.

[0614] In the PBTS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 0.1 V is applied to the drain of the transistor, and a voltage of 20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a dark environment.

[0615] In the NBTIS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 10 V is applied to the drain of the transistor, and a voltage of -20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a light irradiation environment (irradiating light of about 3400 lux with a white LED).

[0616] In the reliability test, a transistor with a channel length of 2 μm and a channel width of 3 μm was used, and the variation in threshold voltage (ΔVth) before and after the gate bias stress test was evaluated.

[0617] FIG. 35 shows the variation (ΔVth) of the threshold voltage of samples E1 to E4.

[0618] As shown in Figure 35, it was confirmed that sample D2 and sample D4, which were washed, had smaller threshold voltage fluctuations (ΔVth) in the PBTS test compared to sample D1 and sample D3, which were not washed before forming the protective layer. It was confirmed that washing before forming the protective layer removes impurities attached to the gate insulating layer and semiconductor layer, improving the reliability of the transistor. EXAMPLES

[0619] In this example, a semiconductor film and an insulating film on the semiconductor film were subjected to plasma treatment in an atmosphere containing oxygen, and the resistance of the semiconductor film was evaluated. In this example, samples (samples E1 to 7) were fabricated with different conditions for the plasma treatment and the heat treatment after the plasma treatment.

[0620] <Sample preparation> First, a metal oxide film with a thickness of 25 nm was formed as a semiconductor film on a glass substrate. The metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 10%.

[0621] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0622] Subsequently, a first silicon oxynitride film having a thickness of 5 nm, a second silicon oxynitride film having a thickness of 130 nm, and a third silicon oxynitride film having a thickness of 5 nm were formed in this order as insulating films. Since the description of Example 2 can be referred to for the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film, detailed description thereof will be omitted.

[0623] Next, plasma treatment was performed. The plasma treatment was performed using a PECVD apparatus, and was performed consecutively after the formation of the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film described above. The plasma treatment was performed using oxygen gas with a flow rate of 3000 sccm, with a pressure of 40 Pa and a power of 3000 W. The substrate temperature during the plasma treatment was 350°C. The plasma treatment time was 15 seconds for samples E2 and E3, 30 seconds for samples E4 and E5, and 60 seconds for samples E6 and E7. Sample E1 was not subjected to plasma treatment.

[0624] Next, samples E1, E3, E5 and E7 were heat-treated at 370° C. for 1 hour in a nitrogen atmosphere. An oven was used for the heat treatment. Samples E2, E4 and E6 were not heat-treated.

[0625] Subsequently, openings reaching the metal oxide film were formed in the first silicon oxynitride film, the second silicon oxynitride film, and the third silicon oxynitride film, and terminals were provided.

[0626] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0627] The sheet resistance values ​​of samples E1 to E7 are shown in Fig. 36. In Fig. 36, the horizontal axis represents the plasma treatment time, and the vertical axis represents the sheet resistance Rs.

[0628] As shown in Figure 36, it was confirmed that the resistance of the metal oxide film increases by performing plasma treatment in an atmosphere containing oxygen. In addition, the resistance of the metal oxide film increases as the plasma treatment time increases, and the resistance of the metal oxide film tends to increase when a heat treatment is performed after the plasma treatment. It was found that by performing a plasma treatment in an atmosphere containing oxygen after forming an insulating film on the metal oxide film, oxygen is supplied to the metal oxide film, and the resistance of the metal oxide film can be increased. EXAMPLES

[0629] In this example, transistors (samples F1 to F3) fabricated by a fabrication method different from that of the above-described Example 1 were evaluated.

[0630] In this embodiment, a transistor was fabricated in which the conductive layer 106 (bottom gate electrode) was electrically connected to the conductive layer 112 (top gate electrode).

[0631] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0632] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order. The first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the first silicon oxynitride film can be referred to in the description of Example 1, and therefore detailed description thereof will be omitted.

[0633] Next, a first metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.3 Pa, the source power was 4.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 10%.

[0634] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0635] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0636] Subsequently, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order as a second gate insulating layer. Since the description of Example 1 can be referred to for the second gate insulating layer, the third silicon oxynitride film, and the fourth silicon oxynitride film, detailed description thereof will be omitted.

[0637] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0638] Subsequently, a second metal oxide film was formed on the fourth silicon oxynitride film. The second metal oxide film had a laminated structure of a 20 nm thick In-Ga-Zn oxide film and a 10 nm thick silicon-containing indium tin oxide (ITSO) film. The In-Ga-Zn oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the source power was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas. The ITSO film was formed by sputtering using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 The film was formed by a sputtering method using a mixture of 1000 and 10000 sulphuric acid (weight ratio: 85:10:5). The pressure during film formation was 0.15 Pa, the power source was 1 kW (DC), and the substrate temperature was 80° C. Argon gas was used as the film formation gas.

[0639] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0640] Next, a copper film having a thickness of 100 nm was formed on the second metal oxide film by sputtering using a Cu target.

[0641] Next, a resist mask was formed on the conductive film, and the second metal oxide film and the conductive film were processed to form a second metal oxide layer and a conductive layer. A wet etching method was used for the processing. The description of Example 1 can be referred to for the etchant, so a detailed description is omitted. Here, the wet etching processing time was made different for each of samples F1 to F3, and the width L2 of the region 108L was made different. The width L2 of sample F1 was about 200 nm, the width L2 of sample F2 was about 300 nm, and the width L2 of sample F3 was about 400 nm.

[0642] Subsequently, using the aforementioned resist mask as a mask, the second to fourth silicon oxynitride films were processed to form a second gate insulating layer. Also, when forming the second gate insulating layer, the first silicon oxynitride film in the region that does not overlap with the resist mask was removed to expose a part of the third silicon nitride film. Dry etching was used for the processing. After that, the resist mask was removed.

[0643] Subsequently, washing was performed. For the washing, an aqueous solution obtained by diluting 85 weight% phosphoric acid 500 times was used. The etchant temperature during etching was room temperature, and the treatment time was 15 seconds.

[0644] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a fifth silicon oxynitride film with a thickness of 300 nm were formed in this order. Since the description of Example 1 can be referred to for the fourth silicon nitride film and the fifth silicon oxynitride film, detailed explanations are omitted.

[0645] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm were formed in this order by sputtering, and then this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin with a thickness of about 1.5 μm was applied as a planarization layer, and heat treatment was performed under a nitrogen atmosphere at a temperature of 250 °C for 1 hour.

[0646] Transistors (sample F1 to sample F3) formed on the glass substrate were obtained through the above steps.

[0647] <Id-Vd characteristic evaluation> Subsequently, the Id-Vd characteristics of the transistors fabricated above were measured.

[0648] The Id-Vd characteristics of the transistor were measured by sweeping the drain voltage (Vd) in the range of 0 V to 30 V at 0.25 V intervals, with the source potential set to ground potential (GND). Id-Vd measurements were performed consecutively using the same transistor under four gate voltage (Vg) conditions: 0 V, 2 V, 4 V, and 6 V. The transistor had a channel length of 6 μm and a channel width of 10 μm.

[0649] The Id-Vd characteristics of samples F1 to F3 are shown in Fig. 37. In Fig. 37, the horizontal axis represents the drain voltage (Vd) and the vertical axis represents the drain current (Id).

[0650] As shown in FIG. 37, similarly to Example 1, the larger the width L2, the more the decrease in the on-current tends to be suppressed, and good Id-Vd characteristics were exhibited.

[0651] <Evaluation of continuous operation of gate driver circuits> A gate driver circuit that can be used in a display device was fabricated and evaluated in continuous operation. The gate driver circuit used had transistors fabricated under the same conditions as the aforementioned sample F3 (width L2 = approximately 400 nm).

[0652] First, the gate driver circuit was operated at a drive voltage of 25V (high power supply voltage VDD = +19V, low power supply voltage = -6V). Next, the gate driver circuit was operated at a drive voltage of 40V (high power supply voltage VDD = +20V, low power supply voltage = -20V). Next, it was operated continuously for 57 hours at a drive voltage of 40V (high power supply voltage VDD = +20V, low power supply voltage = -20V). Next, the gate driver circuit was operated at a drive voltage of 25V (high power supply voltage VDD = +19V, low power supply voltage = -6V).

[0653] The input and output waveforms of the gate driver circuit are shown in Figure 38. In Figure 38, the vertical axis represents voltage and the horizontal axis represents time. Also, the upper part of each figure shows the waveform of the input signal, and the lower part shows the waveform of the output signal.

[0654] As shown in FIG. 38, it was possible to confirm that a gate driver circuit including a transistor according to one embodiment of the present invention operated normally even when continuously operated at a high driving voltage of 40 V. EXAMPLES

[0655] In this example, the amount of released hydrogen and the like were evaluated for a silicon nitride film that can be used for the insulating layer 116 described in Embodiment 1.

[0656] <Sample preparation 1> Samples (sample G1 to sample G6) having a silicon nitride film were fabricated, and hydrogen desorption from the silicon nitride film was evaluated. The sample structures of sample G1 to sample G6 are shown in FIG. 39A. In sample G1 to sample G6, a first silicon nitride film 201 having a thickness of 100 nm was formed on a glass substrate 200.

[0657] In this example, the film-forming gas used for forming the first silicon nitride film 201 and the substrate temperature during film formation were made different among samples G1 to G6.

[0658] The first silicon nitride film 201 of sample G1 was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The substrate temperature during film formation was set to 240°C.

[0659] The first silicon nitride film 201 of sample G2 was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm and nitrogen gas at a flow rate of 5000 sccm. The substrate temperature during film formation was set to 240°C.

[0660] The first silicon nitride film 201 of sample G3 was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The substrate temperature during film formation was set to 300°C.

[0661] The first silicon nitride film 201 of sample G4 was formed by the PECVD method using a mixed gas of silane gas at a flow rate of 150 sccm and nitrogen gas at a flow rate of 5000 sccm. The substrate temperature during film formation was set to 300°C.

[0662] The first silicon nitride film 201 of sample G5 was formed by PECVD using a mixed gas of silane gas at a flow rate of 150 sccm, nitrogen gas at a flow rate of 5000 sccm, and ammonia gas at a flow rate of 100 sccm. The substrate temperature during film formation was 350°C.

[0663] The first silicon nitride film 201 of sample G6 was formed by the PECVD method using a mixed gas of silane gas at a flow rate of 150 sccm and nitrogen gas at a flow rate of 5000 sccm. The substrate temperature during film formation was set to 350°C.

[0664] In each of samples G1 to G6, the pressure during deposition of the first silicon nitride film 201 was set to 200 Pa and the deposition power was set to 2000 W.

[0665] <Sample preparation 2> Samples (sample H1 to sample H6) having silicon nitride films were prepared, and the hydrogen blocking properties of the silicon nitride films were evaluated. The sample structures of sample H1 to sample H6 are shown in FIG. 39B. In sample H1 to sample H6, a second silicon nitride film 203 having a thickness of 300 nm and a first silicon nitride film 201 having a thickness of 100 nm were formed on a glass substrate 200. In addition, as a reference sample, a sample (sample J) was prepared in which a second silicon nitride film 203 having a thickness of 300 nm was formed on a glass substrate 200. The sample structure of sample J is shown in FIG. 39C.

[0666] First, for sample H1 to sample H6 and sample J, a second silicon nitride film 203 was formed on a glass substrate 200. The second silicon nitride film 203 was formed by a PECVD method using a mixed gas of silane gas at a flow rate of 200 sccm, nitrogen gas at a flow rate of 2000 sccm, and ammonia gas at a flow rate of 2000 sccm. The pressure during film formation was 200 Pa, the film formation power was 1000 W, and the substrate temperature was 220° C. Note that the second silicon nitride film 203 was formed under conditions that released a large amount of hydrogen when heat was applied.

[0667] Next, for samples H1 to H6, a first silicon nitride film 201 was formed on the second silicon nitride film 203. The first silicon nitride film 201 was formed on the second silicon nitride film 203, which releases hydrogen when heat is applied, and the blocking ability of the first silicon nitride film 201 against hydrogen was evaluated. In this example, the film formation gas used for forming the first silicon nitride film 201 and the substrate temperature during film formation were made different for samples H1 to H6.

[0668] The first silicon nitride film 201 of sample H1 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G1 described above.

[0669] The first silicon nitride film 201 of sample H2 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G2 described above.

[0670] The first silicon nitride film 201 of sample H3 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G3 described above.

[0671] The first silicon nitride film 201 of sample H4 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G4 described above.

[0672] The first silicon nitride film 201 of sample H5 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G5 described above.

[0673] The first silicon nitride film 201 of sample H6 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G6 described above.

[0674] <Sample preparation 3> Samples (sample K1 to sample K4) having a silicon nitride film were prepared, and the water blocking properties of the silicon nitride film were evaluated. The sample structures of sample K1 to sample K4 are shown in FIG. 39D. In sample K1 to sample K4, a first silicon oxynitride film 205 having a thickness of 300 nm and a first silicon nitride film 201 having a thickness of 100 nm were formed on a glass substrate 200. In addition, as a reference sample, a sample (sample L) was prepared in which a first silicon oxynitride film 205 having a thickness of 300 nm was formed on a glass substrate 200. The sample structure of sample L is shown in FIG. 39E.

[0675] First, for sample K1 to sample K4 and sample L, a first silicon oxynitride film 205 was formed on a glass substrate 200. The first silicon oxynitride film 205 was formed by a PECVD method using a mixed gas of silane gas with a flow rate of 160 sccm and nitrous oxide gas with a flow rate of 4000 sccm. The pressure during film formation was 200 Pa, the film formation power was 1500 W, and the substrate temperature was 220° C. Note that the first silicon oxynitride film 205 was formed under film formation conditions that released a large amount of water when heat was applied.

[0676] Next, for sample K1 to sample K4, the first silicon nitride film 201 was formed on the first silicon oxynitride film 205. The first silicon nitride film 201 was formed on the first silicon oxynitride film 205, which releases water when heat is applied, and the blocking property of the first silicon nitride film 201 against water was evaluated. In this example, the film formation gas used for forming the first silicon nitride film 201 and the substrate temperature during film formation were made different for sample K1 to sample K4.

[0677] The first silicon nitride film 201 of sample K1 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G1 described above.

[0678] The first silicon nitride film 201 of sample K2 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G2 described above.

[0679] The first silicon nitride film 201 of sample K3 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G5 described above.

[0680] The first silicon nitride film 201 of sample K4 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G6 described above.

[0681] <Sample preparation 4> Samples (sample M1 to sample M4) having silicon nitride films were fabricated, and the oxygen blocking properties of the silicon nitride films were evaluated. The sample structures of sample M1 to sample M4 are shown in FIG. 40A. In sample M1 to sample M4, a second silicon oxynitride film 207 having a thickness of 100 nm and a first silicon nitride film 201 having a thickness of 100 nm were formed on a glass substrate 200. In addition, as a reference sample, a sample (sample N) was fabricated in which a second silicon oxynitride film 207 having a thickness of 100 nm was formed on a glass substrate 200. The sample structure of sample N is shown in FIG. 40B.

[0682] First, for sample M1 to sample M4 and sample N, a second silicon oxynitride film 207 was formed on a glass substrate 200. The second silicon oxynitride film 207 was formed by a PECVD method using a mixed gas of silane gas with a flow rate of 20 sccm and nitrous oxide gas with a flow rate of 18000 sccm. The pressure during film formation was 200 Pa, the film formation power was 100 W, and the substrate temperature was 350°C.

[0683] Next, in each of Sample M1 to Sample M4 and Sample N, a 100-nm-thick oxide conductive film 209 was formed over the second silicon oxynitride film 207. The oxide conductive film 209 was formed by a sputtering method using an indium tin oxide target containing silicon.

[0684] Next, the samples M1 to M4 and sample N were subjected to oxygen radical doping treatment using an ashing apparatus. The oxygen radical doping treatment was performed under the following conditions: ICP power: 0 W, bias power: 4500 W, pressure: 15 Pa, oxygen flow rate ratio: 100%, lower electrode temperature: 40° C., and treatment time: 120 seconds. By performing the oxygen radical doping treatment after the oxide conductive film 209 was formed, oxygen was supplied to the second silicon oxynitride film 207 through the oxide conductive film 209.

[0685] Next, from samples M1 to M4 and sample N, the oxide conductive film 209 was removed.

[0686] Next, in the samples M1 to M4 and sample N, a metal oxide film 211 having a thickness of 20 nm was formed on the second silicon oxynitride film 207. The metal oxide film 211 was formed by a sputtering method using an In-Zn oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.3 Pa, the source power was 4.5 kW, and the substrate temperature was room temperature. Oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas. By forming the metal oxide film 211 having a thickness of 20 nm on the second silicon oxynitride film 207, oxygen was supplied to the second silicon oxynitride film 207. The oxygen was desorbed from the second silicon oxynitride film 207 by applying heat.

[0687] Next, from samples M1 to M4 and sample N, the metal oxide film 211 was removed.

[0688] Next, for samples M1 to M4, the first silicon nitride film 201 was formed on the second silicon oxynitride film 207. The first silicon nitride film 201 was formed on the second silicon oxynitride film 207, which releases oxygen when heated, and the blocking property of the first silicon nitride film 201 against oxygen was evaluated. In this example, the film formation gas used for forming the first silicon nitride film 201 and the substrate temperature during film formation were made different for samples M1 to M4.

[0689] The first silicon nitride film 201 of sample M1 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G1 described above.

[0690] The first silicon nitride film 201 of sample M2 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G2 described above.

[0691] The first silicon nitride film 201 of sample M3 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G5 described above.

[0692] The first silicon nitride film 201 of sample M4 was formed under the same film forming conditions as those for the first silicon nitride film 201 of sample G6 described above.

[0693] <Sample preparation 5> Samples (sample P1 to sample P4) were prepared to evaluate the desorption of oxygen from the lower layer due to the formation of the silicon nitride film. The sample structures of sample P1 to sample P4 are shown in FIG. 41. In sample P1 to sample P4, a second silicon oxynitride film 207 having a thickness of 100 nm was formed on a glass substrate 200.

[0694] First, in the samples P1 to P4, the second silicon oxynitride film 207 was formed on the glass substrate 200. The above description can be referred to for the second silicon oxynitride film 207, and therefore detailed description thereof will be omitted.

[0695] Next, in samples P1 to P4, an oxide conductive film 209 was formed over the second silicon oxynitride film 207. The above description can be referred to for the oxide conductive film 209, and therefore detailed description thereof will be omitted.

[0696] Next, samples P1 to P4 were subjected to an oxygen radical doping process using an ashing device. Since the above description can be referred to for the oxygen radical doping process, a detailed description thereof will be omitted.

[0697] Next, the oxide conductive film 209 was removed from the samples P1 to P4.

[0698] Next, in samples P1 to P4, a metal oxide film 211 having a thickness of 20 nm was formed on the second silicon oxynitride film 207. Since the above description can be referred to for the metal oxide film 211, detailed description thereof will be omitted.

[0699] Next, the metal oxide film 211 was removed from samples P1 to P4.

[0700] Next, a first silicon nitride film 201 was formed on the second silicon oxynitride film 207 for samples P1 to P4. In this example, for samples P1 to P4, the film-forming gas used for forming the first silicon nitride film 201 and the substrate temperature during film formation were varied.

[0701] For the formation of the first silicon nitride film 201 of sample P1, the same film-forming conditions as those of the first silicon nitride film 201 of sample G1 described above were used.

[0702] For the formation of the first silicon nitride film 201 of sample P2, the same film-forming conditions as those of the first silicon nitride film 201 of sample G2 described above were used.

[0703] For the formation of the first silicon nitride film 201 of sample P3, the same film-forming conditions as those of the first silicon nitride film 201 of sample G5 described above were used.

[0704] For the formation of the first silicon nitride film 201 of sample P4, the same film-forming conditions as those of the first silicon nitride film 201 of sample G6 described above were used.

[0705] Next, the first silicon nitride film 201 was removed from samples P1 to P4. Here, oxygen may desorb from the second silicon oxynitride film 207 due to the heat during the formation of the first silicon nitride film 201 on the second silicon oxynitride film 207. In this example, the desorption of oxygen from the second silicon oxynitride film 207 after the formation of the first silicon nitride film 201 was evaluated.

[0706] <TDS analysis> Thermal desorption spectrometry (TDS) was used to evaluate the desorbed gas from each sample. In the TDS measurement, the substrate temperature was raised from about 50°C to about 520°C at a heating rate of 30°C / min.

[0707] The TDS analysis results of samples G1 to G6 are shown in Figure 42. In Figure 42, the flow rate of ammonia gas during the formation of the first silicon nitride film 201 is shown vertically, and the substrate temperature (Tsub) during the formation of the first silicon nitride film 201 is shown horizontally. In Figure 42, the horizontal axis indicates the substrate temperature (Tsub), and the vertical axis indicates the detection intensity (Intensity) of a mass-to-charge ratio of 2 (m / z=2). The gas with a mass-to-charge ratio of 2 (m / z=2) is mainly hydrogen molecules.

[0708] 42, it was confirmed that the lower the substrate temperature during the formation of the first silicon nitride film 201, the more hydrogen is released. It was also confirmed that the use of ammonia gas for the formation of the first silicon nitride film 201 reduced the amount of hydrogen released.

[0709] The TDS analysis results of samples H1 to H6 and sample J are shown in Figure 43. In Figure 43, the flow rate of ammonia gas during the formation of the first silicon nitride film 201 is shown vertically, and the substrate temperature (Tsub) during the formation of the first silicon nitride film 201 is shown horizontally. In Figure 43, the horizontal axis indicates the substrate temperature (Tsub), and the vertical axis indicates the detection intensity (Intensity) of a mass-to-charge ratio of 2 (m / z=2). The gas with a mass-to-charge ratio of 2 (m / z=2) is mainly hydrogen molecules.

[0710] As shown in Fig. 43, the lower the substrate temperature during the formation of the first silicon nitride film 201, the more hydrogen was released. This indicates that the lower the substrate temperature during the formation of the first silicon nitride film 201, the more easily hydrogen released from the second silicon nitride film 203 permeates the first silicon nitride film 201. In other words, it was confirmed that the lower the substrate temperature during the formation of the first silicon nitride film 201, the lower the blocking ability of the first silicon nitride film 201 against hydrogen tends to be. It was also confirmed that when ammonia gas is used to form the first silicon nitride film 201, the blocking ability of the first silicon nitride film 201 against hydrogen is increased.

[0711] The TDS analysis results of samples K1 to K4 and sample L are shown in Figure 44. In Figure 44, the flow rate of ammonia gas during the formation of the first silicon nitride film 201 is shown vertically, and the substrate temperature (Tsub) during the formation of the first silicon nitride film 201 is shown horizontally. In Figure 44, the horizontal axis indicates the substrate temperature (Tsub), and the vertical axis indicates the detection intensity (Intensity) of a mass-to-charge ratio of 18 (m / z=18). The gas with a mass-to-charge ratio of 18 (m / z=18) is mainly water molecules.

[0712] 44, it was found that all samples released little water, and that the water released from the first silicon oxynitride film 205 was unlikely to permeate the first silicon nitride film 201. In other words, it was found that the first silicon nitride film 201 has a blocking property against water.

[0713] The TDS analysis results of samples M1 to M4 and sample N are shown in Fig. 45. In Fig. 45, the flow rate of ammonia gas during the formation of the first silicon nitride film 201 is shown vertically, and the substrate temperature (Tsub) during the formation of the first silicon nitride film 201 is shown horizontally. In Fig. 45, the horizontal axis indicates the substrate temperature (Tsub), and the vertical axis indicates the detection intensity (Intensity) of a mass-to-charge ratio of 32 (m / z=32). The gas with a mass-to-charge ratio of 32 (m / z=32) is mainly oxygen molecules.

[0714] As shown in Fig. 45, the amount of oxygen released was small for all samples. This indicates that even if the substrate temperature during the formation of the first silicon nitride film 201 was low, the oxygen released from the second silicon oxynitride film 207 was unlikely to pass through the first silicon nitride film 201. In other words, it was confirmed that the first silicon nitride film 201 had a high blocking ability against oxygen even if the substrate temperature during the formation of the first silicon nitride film 201 was low. It was also confirmed that there was no difference in the blocking ability against oxygen of the first silicon nitride film 201 between the case where ammonia gas was used and the case where ammonia gas was not used for the formation of the first silicon nitride film 201.

[0715] The TDS analysis results of samples P1 to P4 and sample N are shown in Fig. 46. In Fig. 46, the flow rate of ammonia gas during the formation of the first silicon nitride film 201 is shown vertically, and the substrate temperature (Tsub) during the formation of the first silicon nitride film 201 is shown horizontally. In Fig. 46, the horizontal axis indicates the substrate temperature (Tsub), and the vertical axis indicates the detection intensity (Intensity) of a mass-to-charge ratio of 32 (m / z=32). The gas with a mass-to-charge ratio of 32 (m / z=32) is mainly oxygen molecules.

[0716] As shown in Fig. 46, the lower the substrate temperature during the formation of the first silicon nitride film 201, the more oxygen was released. This indicates that the lower the substrate temperature during the formation of the first silicon nitride film 201, the less oxygen was released from the second silicon oxynitride film 207 during the formation of the first silicon nitride film 201. In other words, it was confirmed that the lower the substrate temperature during the formation of the first silicon nitride film 201, the more oxygen remained in the second silicon oxynitride film 207. In addition, no difference was observed in the amount of oxygen remaining in the second silicon oxynitride film 207 between the case where ammonia gas was used and the case where ammonia gas was not used during the formation of the first silicon nitride film 201. EXAMPLES

[0717] In this example, samples (samples Q1 to Q7) corresponding to the transistor 100B shown in FIG. 7 were fabricated, and the drain current-drain voltage characteristics (Id-Vd characteristics) and reliability of the transistors were evaluated. In this example, an indium zinc oxide layer was used as the metal oxide layer 114. In addition, a sample using a copper layer as the conductive layer 112 and a sample using a stacked structure of a copper layer and an indium zinc oxide layer on the copper layer were fabricated.

[0718] In this embodiment, a transistor was manufactured in which the conductive layer 106 (bottom gate electrode) shown in FIG. 9 was provided and the conductive layer 106 (bottom gate electrode) was electrically connected to the conductive layer 112 (top gate electrode).

[0719] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by a sputtering method, and then processed to obtain a first gate electrode (bottom gate).

[0720] Next, as a first gate insulating layer, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 150 nm, a third silicon nitride film having a thickness of 100 nm, and a first silicon oxynitride film having a thickness of 3 nm were formed in this order. The first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the first silicon oxynitride film can be referred to in the description of Example 1, and therefore detailed description thereof will be omitted.

[0721] Next, a first metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%.

[0722] Next, the first metal oxide film was processed into islands to form a first metal oxide layer.

[0723] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0724] Subsequently, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order as a second gate insulating layer. Since the description of Example 1 can be referred to for the second gate insulating layer, the third silicon oxynitride film, and the fourth silicon oxynitride film, detailed description thereof will be omitted.

[0725] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0726] Next, a second metal oxide film having a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an indium zinc oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power source was 2.5 kW, and the substrate temperature was room temperature. In this example, the film formation gas conditions used for film formation of the second metal oxide film were different. Samples Q1 to Q4 used oxygen gas (oxygen flow ratio 100%) as the film formation gas. Samples Q5 to Q7 used a mixed gas of oxygen gas and argon gas as the film formation gas, and the oxygen flow ratio was 60%. Compared to samples Q1 to Q4, samples Q5 to Q7 had a lower oxygen flow ratio during film formation of the second metal oxide film, and therefore the amount of oxygen supplied to the second gate insulating layer was reduced.

[0727] Next, a heat treatment was carried out for 1 hour at 370° C. in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate=4:1) using an oven device.

[0728] Subsequently, a copper film having a thickness of 100 nm and an indium zinc oxide film having a thickness of 30 nm were formed in this order on the second metal oxide film as a conductive film. The copper film and the indium zinc oxide film were formed by a sputtering method. A Cu target was used for forming the copper film. The indium zinc oxide film was formed by a sputtering method using an indium zinc oxide target (In:Zn=2:3 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power supply power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%.

[0729] Next, a resist mask was formed on the conductive film, and the second metal oxide film and the conductive film were processed to form a second metal oxide layer and a conductive layer. The processing was performed by a wet etching method. The etchant can be referred to in the description of Example 1, and therefore a detailed description thereof will be omitted.

[0730] Next, the second to fourth silicon oxynitride films were processed using the resist mask described above as a mask to form a second gate insulating layer. When the second gate insulating layer was formed, the first silicon oxynitride film was removed from a region that did not overlap with the resist mask to expose a part of the third silicon nitride film. A dry etching method was used for the processing. After this, the resist mask was removed.

[0731] Next, cleaning was performed. For cleaning, an aqueous solution of 85 weight % phosphoric acid diluted 500 times was used. The etchant temperature during etching was room temperature, and the processing time was 15 seconds.

[0732] Next, a first protective layer having a thickness of 100 nm and a second protective layer having a thickness of 300 nm were deposited in this order as protective layers covering the transistors. In this example, the deposition conditions of the first protective layer were different for sample Q1 to sample Q7. A silicon oxynitride film was used as the second protective layer for all samples.

[0733] The first protective layer of sample Q1 had a laminated structure of a fourth silicon nitride film with a thickness of 20 nm and a fifth silicon nitride film with a thickness of 80 nm on the fourth silicon nitride film. The fourth silicon nitride film of sample Q1 was formed by the PECVD method using a mixed gas of silane gas with a flow rate of 150 sccm and nitrogen gas with a flow rate of 5000 sccm. The pressure during the formation of the fourth silicon nitride film was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 240°C. The fifth silicon nitride film of sample Q1 was formed by the PECVD method using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The substrate temperature during the film formation was 240°C. The pressure during the formation of the fifth silicon nitride film was 200 Pa, the film formation power was 2000 W, and the substrate temperature was 240°C. After the fourth silicon nitride film was formed, a fifth silicon nitride film was formed continuously without exposure to air.

[0734] The first protective layer of sample Q2 and sample Q5 was a single-layer structure of a fourth silicon nitride film with a thickness of 100 nm. The fourth silicon nitride film of sample Q2 and sample Q5 was formed by the PECVD method using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The substrate temperature during film formation was 240°C.

[0735] The first protective layer of sample Q3 and sample Q6 was a single-layer structure of a fourth silicon nitride film with a thickness of 100 nm. The fourth silicon nitride film of sample Q3 and sample Q6 was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The substrate temperature during film formation was 300°C.

[0736] The first protective layers of sample Q4 and sample Q7 were each a single-layer structure of a fourth silicon nitride film with a thickness of 100 nm. The fourth silicon nitride films of sample Q4 and sample Q7 were formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The substrate temperature during film formation was 350 °C.

[0737] For all samples, the second protective layer was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm and dinitrogen monoxide gas with a flow rate of 4000 sccm. The pressure during film formation was 133 Pa, the film formation power was 1000 W, and the substrate temperature was 350 °C.

[0738] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm, a copper film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were formed in this order by sputtering. Then, this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin with a thickness of about 1.5 μm was applied as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0739] Transistors (sample Q1 to sample Q7) formed on a glass substrate were obtained through the above steps.

[0740] <Id-Vg Characteristic Evaluation> Subsequently, the Id-Vg characteristics of the transistors fabricated above were measured.

[0741] The Id-Vg characteristics of the transistors were measured by applying the voltage applied to the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the second gate electrode (hereinafter also referred to as the gate voltage (Vbg)) in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (common), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 5.1 V.

[0742] The Id-Vg characteristics of the transistors of sample Q1 to sample Q7 are shown in Figs. 47 to 53, respectively. Figs. 47 to 53 show the structure of the first protective layer and the substrate temperature (Tsub) during the deposition of the first protective layer. Sample Q1 shows that the first protective layer has a laminated structure of a fourth silicon nitride film and a fifth silicon nitride film, and that ammonia gas is not used in the deposition of the fourth silicon nitride film, but ammonia gas is used in the deposition of the fifth silicon nitride film (SiN(w / o NH3)\SiN(w / NH3)). Samples Q2 to Q7 show that the first protective layer has a single layer structure of a fourth silicon nitride film, and ammonia gas is used in the deposition of the fourth silicon nitride film (SiN(w / NH3)). In addition, the conditions in which the channel length of the transistor is different in the vertical direction are shown, and three types of transistors with channel lengths of 2 μm, 3 μm, and 6 μm and channel widths of 50 μm are shown. 47 to 53, the horizontal axis indicates the gate voltage (Vg), the left vertical axis indicates the drain current (Id), and the right vertical axis indicates the saturation mobility (μFE) at Vd = 5.1 V. Note that the Id-Vg characteristics of 20 transistors were measured for each sample. In Figs. 47 to 53, the Id-Vg characteristic results of the 20 transistors are shown overlapping each other.

[0743] 47 to 53 show the average value (ave) and 3σ of the threshold voltage (Vth) and saturation mobility (μFE) for each transistor size. σ indicates the standard deviation. 47 to 53 also show the difference (2ΔL) between the design channel length and the effective channel length. The effective channel length was obtained by TLM (Transmission Line Model) analysis.

[0744] <Reliability evaluation> Next, the reliability of the transistor fabricated above was evaluated. In this example, a PBTS (Positive Bias Temperature Stress) test was performed in which a positive potential was applied to the gate relative to the source potential and drain potential, and the transistor was held at high temperature, and an NBTIS (Negative Bias Temperature Illumination Stress) test was performed in which a negative potential was applied to the gate in a light irradiation environment and the transistor was held at high temperature.

[0745] In the PBTS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 0.1 V is applied to the drain of the transistor, and a voltage of 20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a dark environment.

[0746] In the NBTIS test, the substrate on which the transistor is formed is kept at 60°C, a voltage of 10 V is applied to the drain of the transistor, and a voltage of -20 V is applied to the gate, and this condition is maintained for one hour. The test was performed in a light irradiation environment (irradiating light of about 3400 lux with a white LED).

[0747] In the reliability test, a transistor with a channel length of 2 μm and a channel width of 3 μm was used, and the variation in threshold voltage (ΔVth) before and after the gate bias stress test was evaluated.

[0748] The variation (ΔVth) of threshold voltage of samples Q1 to Q4 is shown in Fig. 54A. The variation (ΔVth) of threshold voltage of samples Q5 and Q6 is shown in Fig. 54B. Figs. 54A and 54B show the structure of the first protective layer in the horizontal direction and the substrate temperature during deposition of the first protective layer. In Figs. 54A and 54B, the variation (ΔVth) of threshold voltage is shown on the vertical axis.

[0749] As shown in Figures 47 to 50, in sample Q1 to sample Q4 in which the oxygen flow rate ratio during the deposition of the second metal oxide film was 100%, the lower the substrate temperature during the deposition of the first protective layer, the greater the variation in electrical characteristics. It is believed that the lower substrate temperature during the deposition of the first protective layer increases the amount of hydrogen desorbed from the first protective layer, and the greater the variation in electrical characteristics and the amount of change in threshold voltage in the NBTIS test. In addition, it is believed that sample Q1, in which the first protective layer has a stacked structure, was able to suppress the diffusion of hydrogen into the transistor due to the high blocking ability of the fifth silicon nitride film against hydrogen.

[0750] As shown in FIG. 54A, in samples Q1 to Q4 in which the oxygen flow rate ratio during deposition of the second metal oxide film was 100%, the higher the substrate temperature during deposition of the first protective layer, the smaller the threshold voltage fluctuation amount (ΔVth) in the NBTIS test tended to be. As the substrate temperature during deposition of the first protective layer increased, oxygen supplied to the second gate insulating layer diffused into the semiconductor layer, and the V O and V O It is believed that the change in threshold voltage (ΔVth) in the NBTIS test was reduced by reducing H. In addition, it was confirmed that sample Q1, which has a stacked first protective layer, had a small change in threshold voltage (ΔVth) in the NBTIS test.

[0751] As shown in Figs. 51 to 53, in samples Q5 to Q7 in which the oxygen flow rate ratio during deposition of the second metal oxide film was 60%, the higher the substrate temperature during deposition of the first protective layer, the greater the tendency for the variation in electrical characteristics to increase. Compared with samples Q1 to Q4, samples Q5 to Q7 received less oxygen supplied to the second gate insulating layer. Furthermore, the higher the substrate temperature during deposition of the first protective layer, the more oxygen is desorbed from the second gate insulating layer during deposition of the first protective layer, and the less oxygen diffuses into the semiconductor layer, which reduces the V in the semiconductor layer. O and V O It is thought that H became more difficult to decrease.

[0752] As described above, it was found that by adjusting the substrate temperature during deposition of the first protective layer, it is possible to achieve both good electrical characteristics and high reliability. EXAMPLES

[0753] In this example, a sample (sample R) corresponding to the transistor 100B shown in Fig. 7 was fabricated, and the cross-sectional shape of the transistor having a two-layer structure of the insulating layer 116 was evaluated. Note that in this example, the conductive layer 106 (bottom gate electrode) shown in Fig. 9 was provided. The insulating layer 103 had a two-layer structure of an insulating layer 103b and an insulating layer 103c.

[0754] <Sample preparation> First, a tungsten film having a thickness of 100 nm was formed on a glass substrate by sputtering, and then processed to obtain a tungsten layer (first gate electrode).

[0755] Next, as a first gate insulating layer, a first silicon nitride layer having a thickness of 200 nm, a second silicon nitride layer having a thickness of 50 nm, and a first silicon oxynitride layer having a thickness of 100 nm were formed in this order.

[0756] Subsequently, a metal oxide film having a thickness of 25 nm was formed on the first silicon oxynitride layer by a sputtering method.

[0757] Next, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0758] The metal oxide film was then processed to form a metal oxide layer.

[0759] Subsequently, as a second gate insulating layer, a second silicon oxynitride film having a thickness of 5 nm, a third silicon oxynitride film having a thickness of 130 nm, and a fourth silicon oxynitride film having a thickness of 5 nm were formed in this order.

[0760] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0761] Subsequently, a titanium film having a thickness of 10 nm and a copper film having a thickness of 100 nm were formed in this order on the fourth silicon oxynitride film.

[0762] Then, a resist mask was formed on the copper film, and the titanium film and the copper film were processed to form a titanium layer and a copper layer by wet etching.

[0763] Next, the second to fourth silicon oxynitride films were processed using the above-mentioned resist mask as a mask to form second to fourth silicon oxynitride layers (second gate insulating layers) by dry etching.

[0764] Then, the resist mask was removed.

[0765] Subsequently, a third silicon nitride layer having a thickness of 20 nm, a fourth silicon nitride layer having a thickness of 80 nm, and a fifth silicon oxynitride layer having a thickness of 300 nm were formed in this order as protective layers covering the transistor.

[0766] The third silicon nitride layer and the fourth silicon nitride layer were formed by PECVD, and the substrate temperature during film formation was set to 350° C. The third silicon nitride layer was forme...

Claims

1. A semiconductor device having a transistor, A semiconductor layer; a first insulating layer on the semiconductor layer; a second insulating layer provided on the first insulating layer and overlapping the semiconductor layer with the first insulating layer interposed therebetween; a third insulating layer provided on the second insulating layer and overlapping the semiconductor layer via the first insulating layer and the second insulating layer; a metal oxide layer provided on the third insulating layer and overlapping with the semiconductor layer via the first to third insulating layers; a first conductive layer provided on the metal oxide layer and overlapping with the semiconductor layer via the first to third insulating layers and the metal oxide layer; a fourth insulating layer having a region disposed on the first conductive layer; In a cross-sectional view of the transistor in a channel length direction, ends of the first to third insulating layers are located on the semiconductor layer, In the cross-sectional view, each end of the first conductive layer and the metal oxide layer is located on the third insulating layer; the first insulating layer has a film density different from the film density of the second insulating layer; the film density of the second insulating layer is different from the film density of the third insulating layer; the fourth insulating layer has a region in contact with an upper surface and a side surface of the first conductive layer, a region in contact with a side surface of the metal oxide layer, a region in contact with an upper surface and a side surface of the third insulating layer, a region in contact with a side surface of the second insulating layer, a region in contact with a side surface of the first insulating layer, and a region in contact with an upper surface and a side surface of the semiconductor layer; the third insulating layer has a first thickness in a region in contact with the metal oxide layer and a second thickness in a region in contact with the fourth insulating layer; The second film thickness is smaller than the first film thickness.

2. A semiconductor device having a transistor, A semiconductor layer; a first insulating layer on the semiconductor layer; a second insulating layer provided on the first insulating layer and overlapping the semiconductor layer with the first insulating layer interposed therebetween; a third insulating layer provided on the second insulating layer and overlapping the semiconductor layer via the first insulating layer and the second insulating layer; a metal oxide layer provided on the third insulating layer and overlapping with the semiconductor layer via the first to third insulating layers; a first conductive layer provided on the metal oxide layer and overlapping with the semiconductor layer via the first to third insulating layers and the metal oxide layer; a fourth insulating layer having a region disposed on the first conductive layer; In a cross-sectional view of the transistor in a channel length direction, ends of the first to third insulating layers are located on the semiconductor layer, In the cross-sectional view, each end of the first conductive layer and the metal oxide layer is located on the third insulating layer; the first insulating layer has a film density different from the film density of the second insulating layer; the film density of the second insulating layer is different from the film density of the third insulating layer; the fourth insulating layer has a region in contact with an upper surface and a side surface of the first conductive layer, a region in contact with a side surface of the metal oxide layer, a region in contact with an upper surface and a side surface of the third insulating layer, a region in contact with a side surface of the second insulating layer, a region in contact with a side surface of the first insulating layer, and a region in contact with an upper surface and a side surface of the semiconductor layer; the third insulating layer has a first thickness in a region in contact with the metal oxide layer and a second thickness in a region in contact with the fourth insulating layer; The second thickness is smaller than the first thickness, the semiconductor layer has a first region, a pair of second regions, and a pair of third regions; the first region overlaps the metal oxide layer and the first conductive layer; the pair of second regions sandwich the first region and do not overlap the metal oxide layer and the first conductive layer; the pair of third regions sandwich the first region and the pair of second regions, and do not overlap the first to third insulating layers; the pair of third regions each include a portion having a lower resistance than the first region, The pair of second regions includes a portion having a higher resistance than the third region.

3. In claim 1 or 2, The semiconductor device, wherein each of the semiconductor layer and the metal oxide layer contains In.

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