Radio communication apparatus and frequency error calculation method

Abstract

To provide a radio communication apparatus that can accurately estimate a frequency error, and can also simplify an AFC circuit.SOLUTION: In a radio communication apparatus that comprises a second AFC circuit 2 for correcting a frequency error between transmission and reception, the second AFC circuit 2 defines a signal section of a known signal of received signals as a pilot signal section, and a signal section other than the pilot signal section as a data signal section; delays the received signal by a predetermined symbol number in each delay circuit 3 using a signal of the pilot signal section and the data signal section; integrates these delay signals using an adder circuit 4; and multiplies between the integrated value and the received signal using a multiplier 5 to calculate the frequency error in a frequency error conversion section 6.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a wireless communication device equipped with an AFC (Automatic Frequency Control) circuit for correcting a frequency error between a transmitter and a receiver, and a frequency error calculation method for calculating a frequency error between a transmitter and a receiver. [Background technology]

[0002] In wireless systems with local frequency errors between transmitter and receiver, AFC circuits have been used to correct the local frequency errors. For example, in satellite communication systems, in order to assume low CNR (Carrier to Noise Ratio) conditions, an AFC circuit based on a modified L&R algorithm has been applied using only a pilot signal, which is a known signal section (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Non-Patent Document 1] ETSI TR 102 376 V1.1.1(2005-02)“Digital Video Broadcasting(DVB) User guidelines for the second generation system for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications(DVB-S2)“ Summary of the Invention [Problem to be solved by the invention]

[0004] However, the conventional modified L&R algorithm has a problem that the estimation accuracy of the local frequency error is poor in the case of a low symbol rate signal in which the fluctuation of the local frequency error is relatively large.In addition, the conventional modified L&R algorithm has a problem that the circuit configuration becomes complicated because multiplication and accumulation (integration) processes are performed for each delayed symbol (details will be described later).

[0005] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a wireless communication device and a frequency error calculation method that are capable of estimating a frequency error with high accuracy and that enable simplification of the AFC circuit. [Means for solving the problem]

[0006] In order to solve the above problem, the invention recited in claim 1 is a wireless communication device including an AFC circuit for correcting a frequency error between a transmitter and a receiver, wherein the AFC circuit defines a signal section of a known signal in a received signal as a pilot signal section and a signal section other than the pilot signal section as a data signal section, and accumulates a delayed signal obtained by delaying the received signal by a predetermined number of symbols using signals in the pilot signal section and the data signal section, and calculates a frequency error based on a correlation between the accumulated value and the received signal.

[0007] The invention described in claim 2 is characterized in that, in the wireless communication device described in claim 1, the AFC circuit calculates the frequency error by using a signal in the pilot signal section when the frequency is asynchronous, and calculates the frequency error by simultaneously using the signals in the pilot signal section and the data signal section when the frequency is synchronized.

[0008] The invention described in claim 3 is a frequency error calculation method for calculating a frequency error between a transmitter and a receiver, the method comprising: setting a signal section of a known signal in a received signal as a pilot signal section, and a signal section other than the pilot signal section as a data signal section; using the signals in the pilot signal section and the data signal section, accumulating a delayed signal obtained by delaying the received signal by a predetermined number of symbols; and calculating a frequency error based on a correlation between the accumulated value and the received signal. It is characterized by:

[0009] The invention recited in claim 4 is characterized in that, in the frequency error calculation method recited in claim 3, when the frequency is asynchronous, the frequency error is calculated using a signal in the pilot signal section, and when the frequency is synchronized, the frequency error is calculated using simultaneously the signals in the pilot signal section and the data signal section. Effect of the Invention

[0010] According to the inventions of claims 1 and 3, since the frequency error is calculated using many signals including not only the pilot signal section but also the data signal section, it is possible to estimate the frequency error with high accuracy even when the fluctuation of the frequency error is relatively large. In other words, since the number of symbols used for frequency correction increases and frequency correction and updating is possible for each symbol, it is possible to track the frequency fluctuation with high accuracy. In addition, instead of performing multiplication processing or accumulation processing for each delayed signal as in the conventional method, the delayed signal obtained by delaying the received signal by a predetermined number of symbols is accumulated, and the frequency error is calculated based on the correlation between the accumulated value and the received signal, which makes it possible to simplify the AFC circuit.

[0011] According to the inventions of claims 2 and 4, when the frequency is asynchronous, that is, when the frequency error is large, the frequency error is calculated using a known signal without using a signal in the data signal section, so that the frequency error can be estimated with high accuracy. Also, when the frequency is synchronized, that is, when the frequency error is small, the frequency error is calculated using many signals in the pilot signal section and the data signal section at the same time, so that the frequency error can be estimated with high accuracy. And, since such switching (two calculations) can be performed by the same AFC circuit, the circuit configuration can be simplified. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1A is a schematic block diagram of a transmission system of a wireless communication device according to an embodiment of the present invention, and FIG. [Diagram 2] 5A and 5B are diagrams illustrating examples of transmission signal patterns in the embodiment of the present invention. [Diagram 3] FIG. 2 is a schematic block diagram showing a second AFC circuit of FIG. [Figure 4] 1A is a conceptual diagram showing a conventional frequency error calculation method, and FIG. 1B is a conceptual diagram showing a frequency error calculation method according to an embodiment of the present invention. [Diagram 5] FIG. 1 is a schematic block diagram showing a conventional AFC circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the present invention will be described based on the illustrated embodiment.

[0014] 1 is a diagram showing (a) a schematic configuration block diagram of a transmission system of a wireless communication device 1 according to this embodiment, and (b) a schematic configuration block diagram of a reception system. This wireless communication device 1 includes a second AFC circuit (AFC circuit, AFC2 in FIG. 1(b)) 2 for correcting a frequency error between transmission and reception, and since this second AFC circuit 2 has a different configuration from that of conventional wireless communication devices, the second AFC circuit 2 will be mainly described below.

[0015] Here, the wireless communication device 1 in this embodiment is configured to meet the DVB-S.2 standard, which is a transmission path standard for satellite broadcasting, and the transmission signal and reception signal have, for example, a signal pattern as shown in Fig. 2. That is, the signal section of the PL header signal and pilot signal, which are known signals among the transmission signal and reception signal, is called a pilot signal section PB, and the signal section other than the pilot signal section PB (section of an unknown signal including a data signal) is called a data signal section DB. It is assumed that the pilot signal section PB of a predetermined number of symbols and the data signal section DB of a predetermined number of symbols are alternately arranged.

[0016] Furthermore, as shown in FIG. 1(b), upstream (toward the antenna) of the second AFC circuit 2 in the receiving system, as in the conventional system, there is a first AFC circuit (AFC1) for correcting large frequency errors (roughly adjusting the frequency), and the second AFC circuit 2 is a circuit for finely adjusting the frequency (correcting small frequency errors).

[0017] The second AFC circuit 2 uses the signals in the pilot signal section PB and the data signal section DB to accumulate the delayed signal obtained by delaying the received signal by a predetermined number of symbols, and calculates the frequency error based on the correlation between the accumulated value and the received signal. That is, as shown in FIG. 3, each received signal r including (not distinguishing between) the pilot signal section PB and the data signal section DB is iis delayed by a predetermined number of symbols, for example, by the number of symbols in the pilot signal section PB, although Fig. 3 shows a delay of up to two symbols. Similarly, Fig. 4 and Fig. 5, which will be described later, also show a delay of up to two symbols.

[0018] And these delayed signals r * i-k (i = order of the target received signal, k = number of delayed symbols) are accumulated and added by adder 4, and this accumulated value Σ(r * i-k ) and the received signal r i and are multiplied by each other for each "i" in multiplier 5 (to calculate the correlation), and the frequency error is calculated in frequency error conversion unit 6 based on the correlation value. This calculation is performed for each symbol, regardless of whether it is the pilot signal section PB or the data signal section DB, to update the frequency error. Furthermore, when the frequency is not synchronized (at the time of initial pull-in), the frequency error is calculated using only the signal in the pilot signal section PB, and when the frequency is synchronized (after pull-in), the frequency error is calculated using the signals in the pilot signal section PB and the data signal section DB simultaneously.

[0019] To explain this process in detail, we will explain it together with the conventional modified L&R algorithm. First, in the conventional modified L&R algorithm using only pilot signals, the frequency error estimate is expressed by the following equation: Here, N is the number of pilot signals in one block (one pilot signal section PB), M is the maximum number of delayed (differential) symbols to be used (number of symbols to be delayed), r i denotes the i-th pilot signal.

number

[0020] That is, as shown in (a) of Fig. 4, if the hatched parts are pilot signals, the original pilot signal (received signal) and the delayed pilot signal are multiplied by overlapping signals (signals marked with "#" in the figure). For example, the fourth pilot signal (#4) of the original pilot signal is multiplied by the third pilot signal (#3) delayed by one symbol, the fifth pilot signal (#5) of the original pilot signal is multiplied by the fourth pilot signal (#4) delayed by one symbol, and the fifth pilot signal (#5) of the original pilot signal is multiplied by the third pilot signal (#3) delayed by two symbols, and so on.

[0021] For this reason, as shown in FIG. 5, a multiplier 101 is provided for each delay symbol number k, and the received signal r i and the delayed signal r * i-k Next, these multiplied values ​​are integrated and accumulated by an accumulator (accumulator) 102 for each number of delayed symbols k to calculate R(k), and these R(k) are added by an adder 103 to calculate the frequency error in a frequency error conversion unit 104. This calculation is performed for each block (pilot signal section PB) to update the frequency error.

[0022] In contrast, in this embodiment, as shown in (b) of Fig. 4, the original received signal and the delayed signal are sequentially multiplied, including not only the hatched pilot signal but also the data signal. For example, the fourth signal (pilot signal) of the original signal is multiplied by the third signal (pilot signal) delayed by one symbol, and the fourth signal (pilot signal) of the original signal is multiplied by the second signal (data signal) delayed by two symbols, and so on.

[0023] Furthermore, as described above, during frequency asynchronous operation, the frequency error is calculated using only the signals where the original pilot signals and delayed pilot signals all overlap (signals marked with "#" in Fig. 4(b)). On the other hand, during frequency synchronization, the frequency error is calculated using all signals including pilot signals and data signals (all original received signals and delayed signals in Fig. 4(b)).

[0024] In this way, when the modified L&R algorithm is extended to the data signal section DB, R(k) is the average value of delayed (differential) signal results spaced k symbols apart, and does not need to be limited to the number of pilot signals in one block by N. Therefore, the frequency error estimate can be expressed by the following equation, and multiplication when calculating R(k) can be performed after the summation of signals spaced k symbols apart.

number

[0025] Therefore, as described above, all the delayed signals r * i-k After integrating, the integrated value Σ(r * i-k ) and the received signal r i and are multiplied by multiplier 5. This eliminates the need to provide multiplier 101 and accumulator 102 for each number of delayed symbols k, as in the conventional case.

[0026] On the other hand, when the frequency error is small, it is clear that the accuracy of the frequency error estimate increases as the number of delay symbols k increases. Therefore, if we extend the method to use only arbitrary symbol separations, the frequency error estimate can be expressed by the following equation: Here, g(k) is a function that is "1" for the number of delay symbols used and "0" when not used.

number

[0027] Furthermore, in this embodiment, as described above, the selectable number k of delay symbols is differentiated between asynchronous (before synchronization) and synchronized. For example, before frequency synchronization, symbols in the pilot signal section PB can be selected, and during frequency synchronization, symbols in the pilot signal section PB and data signal section DB, or symbols in the pilot signal section PB or data signal section DB can be selected. Any method may be used to determine frequency synchronization, but for example, when frame synchronization is achieved in the "frame detection" of the receiving system (when frame start timing is continuously obtained at the correct timing), it can be determined that synchronization is in progress.

[0028] The value actually calculated by the calculation is the part of the following formula, which is converted by arg conversion (argument conversion in complex numbers) using a table and multiplied by a conversion coefficient to convert it into a frequency error estimate value. For this reason, the conversion coefficient is a register setting value, and is set to a value corresponding to the number of delay symbols k used.

number

[0029] In this way, in the frequency error calculation method by the second AFC circuit 2, the received signal r i The delayed signal (r * i-k ) and integrate the integrated value Σ(r * i-k ) and the received signal r i In this case, when the frequency is asynchronous, the frequency error is calculated using only the signal in the pilot signal section PB, and when the frequency is synchronized, the frequency error is calculated using the signals in the pilot signal section PB and the data signal section DB simultaneously.

[0030] Here, in order to improve the estimation accuracy of the frequency error estimated value calculated as above, averaging processing is performed before the above arg conversion. That is, in a low CNR environment, if averaging processing is performed after arg conversion, the convergence value will shift and the accuracy will not increase, so averaging processing is performed before arg conversion.

[0031] On the other hand, as described above, the number of delayed symbols k is different before and during synchronization, so the value before arg conversion is different. Therefore, the average value R unsync The average value during synchronization is R sync In order to use it as, the conversion process is performed according to the following formula.

number

[0032] As described above, according to the wireless communication device 1 and the frequency error calculation method, since the frequency error is calculated using many signals including not only the pilot signal section PB but also the data signal section DB, it is possible to estimate the frequency error with high accuracy even when the fluctuation of the frequency error is relatively large. In other words, since the number of symbols used for frequency correction increases and frequency correction and updating is possible for each symbol, it is possible to follow the frequency fluctuation with high accuracy. In addition, since the multiplication process and accumulation process for each delayed signal as in the conventional method are not performed, the delayed signal obtained by delaying the received signal by a predetermined number of symbols is accumulated, and the frequency error is calculated based on the correlation between the accumulated value and the received signal, it is possible to simplify the second AFC circuit 2.

[0033] Furthermore, when the frequency is asynchronous, that is, when the frequency error is large, the frequency error is calculated using the pilot signal, which is a known signal, without using the signal in the data signal section DB, so that the frequency error can be estimated with high accuracy. Also, when the frequency is synchronized, that is, when the frequency error is small, the frequency error is calculated using many signals in the pilot signal section PB and the data signal section DB at the same time, so that the frequency error can be estimated with high accuracy. And, since such switching (two calculations) can be performed by the same second AFC circuit 2, the circuit configuration can be simplified.

[0034] Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there are design changes within the scope of the present invention, the present invention is included. For example, the above embodiment has been described in the case of a wireless communication device 1 used for satellite broadcasting, but the present invention is also applicable to wireless communication devices for other applications. [Explanation of symbols]

[0035] 1. Wireless communication devices 2 Second AFC circuit (AFC circuit) 3. Delay Circuit 4 Adder 5. Multiplier 6 Frequency error conversion section PB Pilot signal section DB Data signal section

Claims

1. A wireless communication device including an AFC circuit for correcting a frequency error between a transmitter and a receiver, the AFC circuit defines a signal section of a known signal in the received signal as a pilot signal section, and a signal section other than the pilot signal section as a data signal section, and accumulates a delayed signal obtained by delaying the received signal by a predetermined number of symbols using signals in the pilot signal section and the data signal section, and calculates a frequency error based on a correlation between the accumulated value and the received signal.

23. A wireless communication device comprising:

2. The AFC circuit calculates the frequency error by using a signal in the pilot signal section when the frequency is asynchronous, and calculates the frequency error by simultaneously using the signals in the pilot signal section and the data signal section when the frequency is synchronized.

2. The wireless communication device according to claim 1 .

3. A frequency error calculation method for calculating a frequency error between a transmitter and a receiver, comprising the steps of: a signal section of a known signal in the received signal is designated as a pilot signal section, and a signal section other than the pilot signal section is designated as a data signal section, and a delayed signal obtained by delaying the received signal by a predetermined number of symbols is accumulated using the signals in the pilot signal section and the data signal section, and a frequency error is calculated based on a correlation between the accumulated value and the received signal.

4. A method for calculating a frequency error comprising the steps of:

4. When the frequency is asynchronous, the signal in the pilot signal section is used to calculate the frequency error, and when the frequency is synchronized, the signal in the pilot signal section and the signal in the data signal section are used simultaneously to calculate the frequency error.

4. The frequency error calculation method according to claim 3.

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