POWER SEMICONDUCTOR DEVICE HAVING INSULATED TRENCH GATE SYSTEM AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE - Patent application
Patent Information
- Application Number
- JP2023537636
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2020-12-21
- Filing Date
- 2021-12-17
- Publication Date
- 2024-12-20
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Hot carrier injection into the gate oxide leads to trench degradation, affecting the long-term stability of insulated gate bipolar transistors (IGBTs), particularly at the trench bottom during hard turn-off switching events.
Incorporating an electrically inactive 'dummy' trench (second trench) opposite the active trench, with a charge carrier extraction contact to divert injected charge carriers and electrostatically shield the active trench, reducing avalanche occurrence and protecting the gate oxide.
Significantly enhances the long-term stability of IGBTs by minimizing trench degradation and maintaining device performance, with reduced avalanche events and electrostatic losses.
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Abstract
Description
[Technical field]
[0001] The present disclosure relates to power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), having isolated trench gate electrodes and methods of manufacturing the power semiconductor devices. [Background technology]
[0002] U.S. Pat. No. 9,825,158 and U.S. Patent Application Publication No. 2020 / 0006539 relate to insulated gate bipolar transistors having an insulated trench gate electrode.
[0003] Hot carrier injection into the gate oxide has been found to be a typical trench degradation mechanism associated with the loss of long-term stability of trench IGBTs. The injected charge carriers can be trapped at the interface between the silicon semiconductor material and the trench oxide, especially at the trench bottom. During turn-off, the current consists mostly of holes that are displaced during the expansion of the depletion layer. The holes are accelerated by the high electric field in the depletion layer towards the trench bottom, especially during the overvoltage phase of a hard turn-off switching event.
[0004] The object to be solved is to provide a power semiconductor device with improved long-term stability and to provide a method by which such a device can be reliably manufactured.
[0005] Exemplary embodiments of the present disclosure address the above mentioned drawbacks, in particular the power semiconductor device as claimed in claim 1 and the method as claimed in claim 15. Further configurations and developments are the subject of the dependent claims.
[0006] According to at least one embodiment of the power semiconductor device, the power semiconductor device comprises a semiconductor body extending vertically between an emitter side having an emitter electrode and a collector side opposite the emitter side. The power semiconductor device comprises a drift layer of a first conductivity type and a base layer of a second conductivity type different from the first conductivity type extending between the drift layer and the emitter side. The power semiconductor device further comprises a source region of the first conductivity type arranged on the base layer opposite the drift layer and at least one first trench extending from the emitter side into the drift layer, the insulated trench gate electrode extending into the first trench. The power semiconductor device further comprises at least one second trench extending from the emitter side into the drift layer, the conductive layer extending into the second trench, the conductive layer being electrically insulated from the base layer and the drift layer. The at least one second trench is arranged on the opposite side of the at least one first trench from the source region. A portion of the base layer disposed on an opposite side of the at least one second trench from the at least one first trench extends vertically from the emitter side toward the collector side to at least the same depth as the at least one second trench.
[0007] In contrast to the first trench, the second trench is electrically inactive and may be referred to as a dummy trench. For example, being electrically inactive means that in the on-state of the power semiconductor device, there is no conductive channel formed along the at least one second trench. For example, the at least one first trench is disposed between the source region and the at least one second trench such that the second trench is separated from the source region via the first trench. It has been found that the portion of the base layer extending relatively deep toward the collector side helps to significantly reduce the avalanche strength near the first trench acting as an active trench, as compared to, for example, a design in which the depth of the base layer is the same on both sides of the second trench.
[0008] If the doping concentration of the portion of the base layer does not decrease abruptly in the vertical direction, e.g., due to an implantation tail of the dopant, the vertical position can be used to determine the depth of the portion, where the doping concentration of the portion of the second conductivity type decreases to the doping concentration of the dopant of the first conductivity type in the drift layer.
[0009] The first conductivity type may be p-type and the second conductivity type may be n-type, or vice versa.
[0010] For example, the bottom of the trench is immediately adjacent to a portion of the base layer in the region. The insulated trench gate electrode is, for example, electrically isolated from at least one of the semiconductor body and the conductive layer, for example, the conductive layer is not in direct electrical contact with the at least one second trench.
[0011] During turn-off of the power semiconductor device, charge carriers, e.g., holes in the case of a p-type base layer, may be extracted through the charge carrier extraction contact, which in turn represents a plasma control feature that helps to further reduce avalanche occurrence near the first trench.
[0012] It has been found that in the presence of a charge carrier extraction contact, a significant amount of injected holes can be diverted from the first trench acting as the active trench. Furthermore, the second trench can electrostatically shield the active trench, thereby protecting the first trench with an insulating trench gate electrode. The sub-region may be electrostatically shielded by the first and second trenches, which facilitates controlled plasma extraction during turn-off switching events without unduly compromising electrostatic losses. The result is a robust power semiconductor device with less degradation without significantly affecting device performance.
[0013] Charge carrier extraction can be controlled via a voltage applied to the charge carrier extraction contact, which may correspond to or may be different from the voltage at the emitter electrode.
[0014] According to at least one embodiment of the power semiconductor device, during operation of the power semiconductor device, the charge carrier extraction contact is electrically addressable separately from the emitter electrode. The applied voltage may therefore be independent of the voltage at the emitter electrode. In other words, the charge carrier extraction contact and the emitter electrode are composed of two separate contact elements. For example, the voltage applied to the charge carrier extraction contact is positive with respect to the emitter electrode or is the same as the voltage at the emitter electrode. For example, the voltage at the charge carrier extraction contact is different for different states during operation. For example, a positive voltage during the on-state can prevent excessive charge carrier extraction. During switching to the off-state or off-state, the voltage at the charge carrier extraction contact may be negative with respect to the emitter electrode to enhance charge carrier extraction.
[0015] According to at least one embodiment of the power semiconductor device, the charge carrier extraction contact is electrically connected to the emitter electrode, so that the voltage of the charge carrier extraction contact corresponds to the voltage of the emitter electrode.
[0016] The effect of the second trench on the power semiconductor device can be further controlled via a voltage applied to the conductive layer in the second trench.
[0017] According to at least one embodiment of the power semiconductor device, the conductive layer is at the same voltage as the emitter electrode or at a positive voltage relative to the emitter electrode during operation of the power semiconductor device. For example, the conductive layer is at a voltage applied to the emitter electrode or a voltage applied to the isolated trench gate electrode. However, the applied voltage may be different from the voltages of both the isolated trench gate electrode and the emitter electrode.
[0018] According to at least one embodiment of the power semiconductor device, the charge carrier extraction contact is subdivided into a plurality of segments, for example arranged side by side in a direction extending parallel to the main extension direction of the at least one first trench, however, a single charge carrier contact without segments can also be used.
[0019] For example, the percentage of the emitter side that is covered by segments of the charge carrier extraction contact along a straight line extending parallel to the main extension direction of the at least one first trench may be at least 0.1%, or at least 10%, or at least 30% and / or at most 90% or at most 80%.
[0020] According to at least one embodiment of the power semiconductor device, the sub-region and the source region are arranged laterally alongside one another when viewed towards the emitter side, in other words, there is no source region between the first trench and the second trench.
[0021] According to at least one embodiment of the power semiconductor device, the edge-to-edge distance between the at least one first trench and the at least one second trench is 0.5 μm to 5 μm. It has been found that as the spacing between the first and second trenches increases, the proportion of avalanche events shared by the second trench decreases. Therefore, locating the second trench as close as possible to the first trench would be advantageous in terms of protection of the first trench. However, too small a spacing may result in high turn-off losses.
[0022] According to at least one embodiment of the power semiconductor device, the at least one first trench and the at least one second trench have the same depth in the vertical direction, so that the at least one first trench and the at least one second trench can be produced in a common process step.
[0023] The term "same depth" includes slight differences in depth within manufacturing tolerances, although the depths of the first and second trenches may be arbitrarily different.
[0024] In accordance with at least one embodiment of the power semiconductor device, an enhancement layer of a first conductivity type is disposed in a region between the drift layer and the base layer, the enhancement layer being more highly doped than the drift layer.
[0025] For example, the maximum doping concentration of the enhancement layer is at least 50 or 100 times greater than the maximum doping concentration of the drift layer.
[0026] The enhancement layer can act as a charge carrier barrier, thereby reducing on-state losses.
[0027] According to at least one embodiment of the power semiconductor device, the enhancement layer is arranged between at least one first trench and at least one second trench. Thus, a part of the enhancement layer may also be present in the sub-region. By the enhancement layer arranged in the sub-region between the first and second trenches, the on-state losses via the charge carrier extraction contacts can be further reduced. However, the sub-region between the first and second trenches may also not include an enhancement layer.
[0028] According to at least one embodiment of the power semiconductor device, the portion extends under the at least one second trench towards the at least one first trench. For example, the second trench completely overlaps the portion when viewed vertically. For example, the portion extends beyond the second trench when viewed towards the first trench but does not overlap the charge carrier extraction contact when viewed vertically. The portion may extend further towards the first trench. For example, the subregion completely overlaps the portion when viewed vertically. For example, the first trench completely overlaps the portion or at least in a partial area when viewed vertically.
[0029] According to at least one embodiment of the power semiconductor device, the portion of the base layer extends laterally between two partial regions of the at least one second trench in a cross-sectional view of the power semiconductor device. The two partial regions may be formed by one continuous second trench or by two separate second trenches. For example, the portions of the at least one second trench extend parallel to each other and are spaced apart from each other, for example in a direction running perpendicular to the main extension direction of the at least one first trench.
[0030] According to at least one embodiment of the power semiconductor device, the at least one second trench forms two part regions of the second trench in succession, however, the two part regions of the second trench may also be formed by two separate second trenches.
[0031] According to at least one embodiment of the power semiconductor device, the at least one second trench forms a closed loop surrounding a portion of the base layer when viewed vertically. The portion of the base layer may be spaced apart from the closed loop in a region, for example, outside the closed loop, the base layer does not extend vertically as deeply as the at least one second trench at any location.
[0032] According to at least one embodiment of the power semiconductor device, in a cross-sectional view of the power semiconductor device, the two part regions of the at least one second trench are arranged between two part regions of the at least one first trench. For example, the parts of the at least one first trench extend parallel to each other and are spaced apart from each other in a direction running perpendicular to the main extension direction of the at least one first trench. For example, the at least one first trench forms the two part regions of the first trench continuously. However, the two part regions of the second trench may also be formed by two separate first trenches. For example, the at least one first trench forms a closed loop surrounding the at least one second trench, which may be formed as a closed loop, for example.
[0033] According to at least one embodiment of the power semiconductor device, the power semiconductor device is a trench IGBT.
[0034] A trench IGBT (insulated gate bipolar transistor) comprises, on the emitter side (also called source side), a source region (also called emitter layer) of a first conductivity type and a base layer (also called well layer) of a second conductivity type different from the first conductivity type. A contact in the form of an emitter electrode (also called source electrode) contacts the source region and the base layer. An insulated trench gate electrode is arranged on the lateral emitter side of the source region and the base layer.
[0035] The concept of the present invention can be applied to different types of IGBTs, such as conventional punch-through IGBTs, non-punch-through IGBTs (NPT-IGBTs), reverse blocking IGBTs or reverse conducting IGBTs, and can also be applied to other power semiconductor devices with insulated trench gate electrodes.
[0036] The semiconductor body of a power semiconductor device may be silicon-based, however other semiconductor materials may also be used, for example wide bandgap materials such as silicon carbide (SiC) or gallium nitride (GaN).
[0037] For example, power semiconductor devices are configured to operate at high currents, eg, at least several hundred amperes, and / or at high voltages, eg, at least 500V.
[0038] Also provided is a method of manufacturing a power semiconductor device. For example, the method may be used to manufacture the power semiconductor devices described herein. Features disclosed in relation to the power semiconductor device are also disclosed in relation to the method and vice versa.
[0039] According to at least one embodiment of the method, the method comprises: a) providing a semiconductor body extending vertically between an emitter side and a collector side opposite the emitter side; b) forming at least one first trench extending into the semiconductor body from the emitter side; c) forming at least one second trench extending into the semiconductor body from the emitter side; d) forming a conductive layer extending into the second trench; Including, The power semiconductor device comprises an emitter electrode on the emitter side, a drift layer of a first conductivity type, a base layer of a second conductivity type different from the first conductivity type extending between the drift layer and the emitter side, and a source region of the first conductivity type arranged on the opposite side of the base layer from the drift layer. The power semiconductor device further comprises an insulated trench gate electrode extending into the first trench. At least one first trench extends into the drift layer from the emitter side, and at least one second trench extends into the drift layer from the emitter side, the at least one second trench being arranged on the opposite side of the at least one first trench from the source region. The conductive layer is electrically insulated from the base layer and the drift layer. The portion of the base layer arranged on the opposite side of the at least one second trench from the at least one first trench extends vertically from the emitter side towards the collector side at least as deep as the at least one second trench. A subregion of the power semiconductor device extending between the at least one first trench and the at least one second trench includes a charge carrier extraction contact electrically connected to the base layer.
[0040] For example, the steps are performed in the order shown. However, the order of the steps may also vary. For example, step c) may be performed before or together with step b) in one common step. Thus, the formation of the at least one second trench does not necessarily require a separate manufacturing step in addition to the step of forming the at least one first trench.
[0041] Further aspects of the present disclosure will become apparent from the following description of exemplary embodiments and drawings. In the exemplary embodiments and drawings, similar or similarly acting components are provided with the same reference numerals. Generally, only differences relating to individual embodiments are described. Unless otherwise specified, the description of a part or aspect in one embodiment also applies to the corresponding part or aspect in another embodiment.
[0042] In the drawings: [Brief description of the drawings]
[0043] [Figure 1A] 1 is a cross-sectional view of an exemplary embodiment of a power semiconductor device; [Figure 1B] 1 illustrates a cross-sectional view of an exemplary embodiment of a power semiconductor device with a portion of an associated schematic top view. [Figure 1C] FIG. 1 illustrates a portion of a schematic top view of an exemplary embodiment of a power semiconductor device. [Figure 1D] 1D is a cross-sectional view of an exemplary embodiment of a power semiconductor device taken along line DD' of FIG. 1C. [Figure 1E] 1D is a cross-sectional view of an exemplary embodiment of a power semiconductor device taken along line EE' of FIG. 1C. [Figure 1F] 1 shows a cross-sectional view of an exemplary embodiment of a power semiconductor device together with a further portion of an associated schematic top view. [Figure 2A] FIG. 4 shows simulation results of time-integrated avalanche occurrence A of the described power semiconductor device and of two reference designs R1 and R2 shown in FIGS. 2B and 2C, respectively. [Figure 2B] FIG. 1 is a diagram showing a reference design R1. [Figure 2C] FIG. 13 is a diagram showing reference design R2. [Figure 3A] FIG. 13 shows simulation results of time-integrated avalanche occurrence A near the first and second trenches for designs with and without charge carrier extraction contacts. [Figure 3B] FIG. 13 shows simulation results of time-integrated avalanche occurrence A for designs with and without charge carrier extraction contacts and the associated ratio between avalanche occurrence near the second trench and near the first trench as a function of edge-to-edge distance s1 between the first and second trenches. [Figure 4] FIG. 1 illustrates a further exemplary embodiment of a power semiconductor device. [Diagram 5] 1 is a schematic diagram of an exemplary embodiment of a method for manufacturing a power semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0044] The elements shown in the figures and their size relationships to each other are not necessarily drawn to scale: rather, the thickness of individual elements or layers may be represented in an exaggerated size for better representability and / or for better understanding.
[0045] A detail of the power semiconductor device 1 is shown in schematic cross-section in figure 1 A. The diagrams of figures 1B and 1F show the power semiconductor device 1 embodied as cells arranged laterally next to one another.
[0046] The power semiconductor device 1 comprises a semiconductor body 2 extending vertically between an emitter side 21 with an emitter electrode 51 and a collector side 22 opposite the emitter side 21 .
[0047] The power semiconductor device 1 comprises a drift layer 26 of a first conductivity type, and a base layer 28 of a second conductivity type different from the first conductivity type, extending between the drift layer 26 and the emitter side 21. A source region 29 of the first conductivity type is arranged on the side of the base layer 28 opposite to the drift layer 26.
[0048] In the following description of the exemplary embodiment, the first conductivity type is n-type and the second conductivity type is p-type, and thus the base layer 28 is a p-type layer, however, the layers may also be inverted with respect to their conductivity type.
[0049] The power semiconductor device 1 comprises a first trench 3 and a second trench 4. The first trench 3 and the second trench 4 extend from the emitter side 21 into the drift layer 26. An insulated trench gate electrode 30 comprises an electrically conductive gate electrode layer 31 and a gate insulating layer 32 and extends into the first trench 3. The gate electrode layer 31 is electrically isolated from the semiconductor body 2. During operation of the power semiconductor device 1, the first trench 3 represents an active trench at the potential level of the gate voltage.
[0050] The second trench 4 is disposed on the opposite side of the first trench 3 to the source region 29 and does not represent an active trench. A conductive layer 41 extends into the second trench 4. The conductive layer 41 is electrically insulated from the drift layer 26 and the base layer 28. An emitter electrode 51 is disposed on the emitter side 21. The first trench 3 and the second trench 4 can have the same depth so that they can be formed in a common process step.
[0051] In the illustrated exemplary embodiment, the second trench 4 is electrically isolated from the insulated trench gate electrode 30 and is electrically connected to the emitter electrode 51 .
[0052] However, the conductive layer 41 may be electrically isolated from the emitter electrode 51. For example, the conductive layer 41 is at the same voltage as the emitter electrode 51 or at a positive voltage with respect to the emitter electrode 51 during operation of the power semiconductor device 1. For example, the conductive layer 41 is at a voltage applied to the emitter electrode or at a voltage applied to the insulated trench gate electrode 3. However, the applied voltage may be different from the voltages of both the insulated trench gate electrode 3 and the emitter electrode. A positive voltage applied to the conductive layer 41 may provide improved electrostatic shielding of the subregion 6.
[0053] 1A, the emitter electrode 51 electrically contacts the base layer 28 next to the source region 29 in a recess in the semiconductor body 2 formed on the emitter side 21. The emitter electrode 51 directly adjoins the source region 29 and a contact portion 282 of the base layer 28 that is more highly doped than the remainder of the base layer 28. However, the emitter electrode 51 may also be provided on the emitter side 21.
[0054] On the opposite side of the second trench 4 to the first trench 3, the base layer 28 comprises a portion 281 having a depth d2 greater than or at least equal to the depth d1 of the second trench 4. For example, the portion 281 of the base layer 28 extends vertically from the emitter side 21 deeper toward the collector side 22 than the second trench 4. For example, the difference d2-d1 is 0 μm to 5 μm. The portion 281 is directly adjacent to the bottom of the second trench 4 in area.
[0055] The subregion 6 of the power semiconductor device 1 extending between the first trench 3 and the second trench 4 is provided with a charge carrier extraction contact 61, via which the base layer 28 is electrically connected.
[0056] The subregion 6 and the source region 29 are disposed on either side of the first trench 3, such that the subregion 6 does not include a source region. In the illustrated exemplary embodiment, the charge carrier extraction contact 61 is electrically connected to the emitter electrode 51. Thus, during operation of the power semiconductor device 1, the charge carrier extraction contact 61 may be at an emitter voltage Ve.
[0057] However, during operation of the power semiconductor device 1, the charge carrier extraction contact 61 may also be electrically addressable separately from the emitter electrode 51. Thus, the applied voltage may be independent of the voltage at the emitter electrode 51. For example, the voltage applied to the charge carrier extraction contact 61 may be positive with respect to the emitter electrode 51 or the same as the voltage at the emitter electrode 51. For example, the voltage at the charge carrier extraction contact 61 may be different for different states during operation.
[0058] It has been found that the second trench 4 acting as a dummy trench together with the portion 281 of the base layer 28 extending deeper towards the collector side 22 than the second trench 4 results in a significant reduction in avalanche occurrence during turn-off switching of the power semiconductor device 1. In this way, degradation of the gate insulating layer 32 due to hot carriers can be eliminated or at least reduced.
[0059] The reduction of avalanche generation near the first trench 3 has been confirmed by simulations as shown in FIG. 2A, comparing the time-integrated avalanche generation per square centimeter during turn-off switching near the first trench 3 of the power semiconductor device 1 with a first reference design R1 shown in FIG. 2B and a second reference design R2 shown in FIG. 2C. The reference design R1 includes only an active trench corresponding to the first trench 3, and does not include an inactive trench. The reference design R2 includes an additional, electrically inactive, second trench 4. However, in both reference designs, the base layer 28 has a continuous depth such that the depth of the base layer 28 is the same on both sides of the second trench 4.
[0060] FIG. 2A shows simulation results for the second reference design R2 and two options for the power semiconductor device 1, where in each case the left bar shows the time-integrated avalanche occurrence A during turn-off switching near the first trench 3 for a design without a charge carrier extraction contact, and the right bar shows the results for a design with a charge carrier extraction contact 61.
[0061] 2A shows that the time-integrated avalanche generation A can be reduced by more than one order of magnitude compared to the reference design R2 for a design without a charge carrier extraction contact, and by two orders of magnitude compared to the reference design R1. The addition of the charge carrier extraction contact 61 provides a further reduction of two orders of magnitude.
[0062] 3A shows in a bar diagram the simulation results of the power semiconductor device 1 as described in FIG. 1A, where bars 71 and 72 show the time integrated avalanche generation A near the first trench 3 (bar 71) and near the second trench 4 (bar 72) for a design without the charge carrier extraction contact 61. Bars 73 and 74 show the corresponding simulation results with the charge carrier extraction contact 61. These simulations clearly show that the charge carrier extraction contact 61 allows to control the plasma distribution such that the majority of the avalanche generation occurs near the second trench 4, thereby reducing the avalanche generation near the first trench 3.
[0063] FIG. 3B further shows the results of a simulation of the time-integrated avalanche generation A of a power semiconductor device as described in relation to FIG. 1A as a function of the edge-to-edge distance s1 between the first trench 3 and the second trench 4, where curve 75 shows a design without a charge carrier extraction contact and curve 76 shows a design with a charge carrier extraction contact 61. Curves 75 and 76 show the avalanche generation near the first trench 3. Curve 77 shows the ratio R of the avalanche generation A between the area in the vicinity of the second trench 4 and the area in the vicinity of the first trench 3. For both curves 75 and 76, the avalanche generation A decreases as the edge-to-edge distance s1 decreases. Also, the smaller the edge-to-edge distance s1, the larger the ratio R. It is therefore desirable to place the second trench 4 as close as possible to the first trench 3 from the point of view of protection of the first trench 3 acting as an active trench. However, a lower edge-to-edge distance s1 between the first trench 3 and the second trench 4 may not be preferred for minimizing turn-off losses. Thus, there is a trade-off between the protection of the first trench and the turn-off losses of the power semiconductor device cell, which needs to be designed according to the application requirements of the power semiconductor device 1.
[0064] The power semiconductor device 1 further comprises a collector layer 25. In an IGBT, the collector layer 25 is of the second conductivity type. A collector electrode 52 is arranged on the collector side 22 of the power semiconductor device 1. The collector electrode 52 is directly adjacent to the collector layer 25. In the following figures, for ease of representation, only the top part of the power semiconductor device 1 is shown in cross section.
[0065] The power semiconductor device 1 further comprises an optional enhancement layer 27 disposed between the drift layer 26 and the base layer 28 in a number of regions. The enhancement layer 27 is a layer having a maximum doping concentration at least 50 times higher than the doping concentration of the drift layer 26. The enhancement layer 27 can act as a charge carrier barrier, for example as a hole barrier for the n-type enhancement layer 27.
[0066] The enhancement layer 27 is also present in the sub-region 6 such that the enhancement layer 27 reduces charge carrier extraction at the charge carrier extraction contact 61, thereby reducing on-state losses.
[0067] The charge carrier extraction contact 61 still provides an additional escape path to the plasma during turn-off switching, but at the same time limits the on-state losses due to the electrostatic shielding of the sub-region 6 provided by the first trench 3 and the second trench 4.
[0068] For example, a typical maximum doping concentration is n - For the drift layer 26, 1*10 12 cm -3 ~1*10 14 cm -3 , 3*10 for the n-th enhancement layer 27 16 cm -3 , 1.5*10 for the p-base layer 28 17 cm -3 , 5*10 for portion 281 of base layer 28 17 cm -3 , p of the base layer 28 + For contact portion 282, 1*10 19 cm -3 It could be.
[0069] 1B , the power semiconductor device 1 includes two partial regions 39 of the first trench 3 and two partial regions 49 of the second trench 4 in a cross-sectional view perpendicular to the main extension direction L1 of the first trench 3, and the two partial regions 49 of the second trench 4 are disposed between the two partial regions 39 of the first trench 3. A portion 281 of the base layer 28 having a depth d2 deeper than the depth d1 of the second trench 4 is formed between the two partial regions 49 of the second trench 4.
[0070] 1F shows, the partial region 49 of the second trench 4 may be formed by one continuous second trench 4. Exemplarily, the second trench 4 is formed as a closed loop when viewed towards the emitter side 21. Similarly, the partial region 39 of the first trench 3 may be formed by one continuous first trench 3. Exemplarily, the second trench 4 is formed as a closed loop when viewed towards the emitter side 21.
[0071] The portion 281 of the base layer 28 lies completely within the closed loop formed by the second trench 4 when viewed vertically.
[0072] However, the partial region 39 of the first trench 3 and / or the partial region 49 of the second trench 4 may also be formed by separate trenches of other designs.
[0073] 1F further shows a gate connector 35 electrically connecting the gate electrode layer 31 in the first trench 3 of the cell to a gate potential, and a connector 45 electrically connecting the conductive layer 41 in the second trench 4 of the cell to an emitter potential Ve. However, the connector 45 may also be used to connect the conductive layer 41 to another potential.
[0074] As shown in Fig. 1C, the charge carrier extraction contact 61 can be divided into a number of segments 610. Depending on the needs of the application, the average center-to-center spacing between the segments 610 and their extension in a direction running parallel to the main extension direction L1 can vary within wide limits. For example, the extension in a direction running parallel to the main extension direction L1 is at least 0.1% or at least 10% or at least 20% and / or at most 95% or at most 80%, for example 30% to 50%.
[0075] For example, the number of segments 610 is between 20 and 200 per millimeter in a direction parallel to the main extension direction L1. However, a single segment can also be used instead.
[0076] For example, the power semiconductor device 1 has a cell design that provides a stripe trench IGBT having a length of 0.5 to 3 mm along the main extension direction L1. As shown in Fig. 1B, the cell pitch c1, which is the center-to-center distance between adjacent power semiconductor devices 1 in a direction perpendicular to the main extension direction L1, is, for example, 10 µm to 500 µm.
[0077] However, the proposed designs can also be applied to other power semiconductor devices and other design geometries.
[0078] The exemplary embodiment shown in FIG. 4 essentially corresponds to the one described in connection with FIGS. 1A-1F.
[0079] Starting there, in the power semiconductor device 1, the portion 281 extends under the second trench 4 in a direction towards the first trench 3. The second trench 4 completely overlaps the portion when viewed in the vertical direction. For example, the portion 281 extends beyond the second trench 4 when viewed towards the first trench 3, but does not overlap the charge carrier extraction contact 61 when viewed in the vertical direction. This is shown using a line 62 which indicates the edge of the charge carrier extraction contact 61 on the side facing the second trench 4.
[0080] Differing from the illustrated embodiment, the portion 281 may extend further towards the first trench 3. For example, the subregion 6 completely overlaps the portion 281 when viewed in the vertical direction. In this case, the subregion 281 may be completely of the second conductivity type. Alternatively, part of the drift layer 26 and / or part of the enhancement layer 27 may be located on the side of the portion 281 facing the emitter side 21.
[0081] Furthermore, even the first trench 3 may overlap partly or entirely with the portion 281 when viewed in the vertical direction.
[0082] 5 shows a schematic diagram of an exemplary embodiment of a method for manufacturing a power semiconductor device. The reference numerals of the individual elements formed refer to the corresponding elements of the above exemplary embodiment.
[0083] In step S11, a semiconductor body 2 is provided, extending vertically between an emitter side 21 and a collector side 22 opposite the emitter side 21.
[0084] In step S12, at least one first trench 3 is formed, which extends from the emitter side 21 into the semiconductor body 2. This can be done, for example, by etching.
[0085] In step S13, at least one second trench 4 is formed, extending from the emitter side 21 into the semiconductor body 2. Unlike in figure 5, steps S12 and S13 may be performed in a common etching process step or in the reverse order.
[0086] In step S14, a conductive layer 41 is formed extending into the at least one second trench 4. For example, the conductive layer is deposited as a metal layer, for example by chemical vapour deposition (CVD) or physical vapour deposition (PVD).
[0087] For example, the power semiconductor device 1 thus manufactured comprises an emitter electrode 51 on the emitter side 21, a drift layer 26 of a first conductivity type, a base layer 28 of a second conductivity type different from the first conductivity type extending between the drift layer 26 and the emitter side 21, a source region 29 of the first conductivity type arranged on the opposite side of the base layer (28) to the drift layer 26, and an insulated trench gate electrode 30 extending into the first trench 3. At least one first trench 3 extends from the emitter side 21 into the drift layer 26. At least one second trench 4 extends from the emitter side 21 into the drift layer 26, the at least one second trench 4 being arranged on the opposite side of the at least one first trench 3 to the source region 29. The conductive layer 41 is electrically insulated from the base layer 28 and the drift layer 26. A portion 281 of the base layer 28 arranged on a side of the at least one second trench 4 opposite the at least one first trench 3 extends vertically from the emitter side 21 towards the collector side 22 to at least the same depth as the at least one second trench 4. A subregion 6 of the power semiconductor device 1 extending between the at least one first trench 3 and the at least one second trench 4 comprises a charge carrier extraction contact 61 electrically connected to the base layer 28.
[0088] Doping of layers or parts of the semiconductor body 2 may be performed before or after steps S12 and / or S13.
[0089] This patent application claims priority to European Patent Application No. 20216115.4, the disclosure of which is incorporated herein by reference.
[0090] It should be noted that the disclosure described herein is not limited to the content described in the exemplary embodiments, but rather, the disclosure encompasses any novel feature and any combination of features, including any combination of features in the claims, even if that feature or combination itself is not explicitly set forth in the claims or exemplary embodiments.
[0091] Explanation of symbols 1. Power Semiconductor Devices 2. Semiconductor body 21 Emitter side 22 Collector side 25 Collector layer 26 Drift Layer 27 Augmentation Layer 28 Base Layer 281 Base layer part 282 Base layer contact part 29 Source Area 3. First Trench 30 Insulated trench gate electrode 31 Gate electrode layer 32 Gate insulating layer 35 Gate Connector 39 Partial region of first trench 4. Second Trench 41 Conductive layer 42 Electrical insulation layer 45 Connector 49 Partial region of second trench 51 Emitter electrode 52 Collector electrode 6 Sub-areas 61 Charge carrier extraction contact 610 Segments 71, 72, 73, 74 Bar 75,76,77 curve c1 Cell pitch d1 Depth of the second trench d2 Depth of the base layer L1 Main extension direction R1 First Reference Design R2 Second Reference Design s1 Edge distance S11, S12, S13, S14 steps Ve Emitter potential
Claims
1. A power semiconductor device (1) having a semiconductor body (2) extending vertically between an emitter side (21) having an emitter electrode (51) and a collector side (22) opposite the emitter side (21), the power semiconductor device (1) comprising: A drift layer (26) of a first conductivity type; a base layer (28) of a second conductivity type different from the first conductivity type, extending between the drift layer (26) and the emitter side (21); a source region (29) of the first conductivity type arranged on an opposite side of the base layer (28) from the drift layer (26); At least one first trench (3) extending from the emitter side (21) into the drift layer (26); an insulating trench gate electrode (30) extending into the first trench (3); at least one second trench (4) extending from the emitter side (21) into the drift layer (26), the at least one second trench (4) being arranged on an opposite side of the at least one first trench (3) to the source region (29); a conductive layer (41) extending into the second trench (4), the conductive layer (41) being electrically insulated from the base layer (28) and the drift layer (26); Equipped with a portion (281) of the base layer (28) arranged on a side of the at least one second trench (4) opposite the at least one first trench (3) extends in the vertical direction from the emitter side (21) toward the collector side (22) to at least the same depth as the at least one second trench (4); A subregion (6) of the power semiconductor device (1) extending between the at least one first trench (3) and the at least one second trench (4) comprises a charge carrier extraction contact (61) electrically connected to the base layer (28).
2. said at least one second trench (4) being electrically inactive; an enhancement layer (27) of the first conductivity type is disposed in a region between the drift layer (26) and the base layer (28), the enhancement layer (27) being doped more highly than the drift layer (26); 2. The power semiconductor device (1) according to claim 1, wherein the enhancement layer (27) is arranged between the at least one first trench (3) and the at least one second trench (4).
3. 3. The power semiconductor device (1) according to claim 1 or 2, wherein the charge carrier extraction contact (61) is configured to be electrically addressable separately from the emitter electrode (51) during operation of the power semiconductor device (1).
4. 3. The power semiconductor device (1) according to claim 1 or 2, wherein the charge carrier extraction contact (61) is electrically connected to the emitter electrode (51).
5. 10. The power semiconductor device (1) according to any of the preceding claims, wherein the conductive layer (41) is configured to be at the same voltage as the emitter electrode (51) or at a positive voltage with respect to the emitter electrode (51) during operation of the power semiconductor device (1).
6. 13. A power semiconductor device (1) as claimed in any preceding claim, wherein the charge carrier extraction contact (61) is subdivided into a plurality of segments (610), the segments (610) being arranged side by side in a direction extending parallel to a main extension direction (L) of the at least one first trench (3).
7. 10. The power semiconductor device (1) according to any of the preceding claims, wherein an edge-to-edge distance (s1) between the at least one first trench (3) and the at least one second trench (4) is ≧0.5 μm and ≦5 μm.
8. 10. The power semiconductor device (1) according to any of the preceding claims, wherein the at least one first trench (3) and the at least one second trench (4) have the same depth in the vertical direction.
9. 10. The power semiconductor device (1) according to any of the preceding claims, wherein said portion (281) extends under said at least one second trench towards said at least one first trench (3).
10. A power semiconductor device (1) according to any preceding claim, wherein the portion (281) of the base layer (2) extends laterally between two partial regions (41) of the at least one second trench (4) in a cross-sectional view of the power semiconductor device (1).
11. 11. The power semiconductor device (1) according to claim 10, wherein the at least one second trench (4) forms the two partial regions (41) of the second trench (4) in succession.
12. The power semiconductor device (1) according to claim 11, wherein the at least one second trench (4) forms a closed loop surrounding the portion (281) of the base layer (28) when viewed in the vertical direction.
13. The power semiconductor device (1) according to any one of claims 10 to 12, wherein the two partial regions (41) of the at least one second trench (4) are arranged between two partial regions (39) of the at least one first trench (3) in a cross-sectional view of the power semiconductor device (1).
14. 10. The power semiconductor device (1) according to any of the preceding claims, wherein the power semiconductor device (1) is an insulated gate bipolar transistor (IGBT).
15. a) providing a semiconductor body (2) extending vertically between an emitter side (21) and a collector side (22) opposite said emitter side (21); b) forming at least one first trench (3) extending into the semiconductor body (2) from the emitter side (21); c) forming at least one second trench (4) extending into the semiconductor body (2) from the emitter side (21); d) forming a conductive layer (41) extending into said at least one second trench (4); A method for manufacturing a power semiconductor device (1), comprising: The power semiconductor device (1) comprises: An emitter electrode (51) on the emitter side (21); A drift layer (26) of a first conductivity type; a base layer (28) of a second conductivity type different from the first conductivity type, extending between the drift layer (26) and the emitter side (21); a source region (29) of the first conductivity type arranged on an opposite side of the base layer (28) from the drift layer (26); an insulating trench gate electrode (30) extending into the first trench (3); Equipped with The at least one first trench (3) extends from the emitter side (21) into the drift layer (26); the at least one second trench (4) extends from the emitter side (21) into the drift layer (26), the at least one second trench (4) being arranged on a side opposite the source region (29) of the at least one first trench (3); the conductive layer (41) is electrically insulated from the base layer (28) and the drift layer (26); a portion (281) of the base layer (28) arranged on a side of the at least one second trench (4) opposite the at least one first trench (3) extends in the vertical direction from the emitter side (21) toward the collector side (22) to at least the same depth as the at least one second trench (4); A subregion (6) of the power semiconductor device (1) extending between the at least one first trench (3) and the at least one second trench (4) comprises a charge carrier extraction contact (61) electrically connected to the base layer (28).
16. A method according to claim 15, in which a power semiconductor device (1) according to any of claims 1 to 14 is manufactured.