Display substrate and display panel

Abstract

A display substrate and a display panel, the display substrate includes a base substrate, the base substrate includes a display area (10) and a peripheral area (20) located on at least one side of the display area (10). The display area (10) includes pixel units (11) arranged in an array, first gate scanning signal lines (E1-Em) and second gate scanning signal lines (RT1-RTm), the peripheral area (20) includes a first scanning drive circuit (21) connected to the first gate scanning signal lines (E1-Em) via a first connection wiring (30), a second scanning drive circuit (22) connected to the second gate scanning signal lines (RT1-RTm) via a second connection wiring (40), a first voltage signal line (Evgh) configured to provide a first voltage, and a second voltage signal line (GNvgh) configured to provide a second voltage, the second scanning drive circuit (22) being located on a side of the first scanning drive circuit (21) closer to the display area (10). The ratio of the second resistance value to the first resistance value is smaller than the ratio of the average line width of the second voltage signal line (GNvgh) to the average line width of the first voltage signal line (Evgh). The display substrate can reduce the difference in signal delay time caused by the difference in resistance of different connection wirings.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202111033089.8, filed on September 3, 2021, the entire contents of which are incorporated by introduction into this application.

[0002] SUMMARY OF THE DISCLOSURE The embodiments of the present disclosure relate to a display substrate and a display panel. [Background technology]

[0003] In the display technology field, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines alternately arranged with the gate lines. The driving of the gate lines can be realized by a combined integrated driving circuit. Recently, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can also be directly integrated on a thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide switching state voltage signals (scanning signals) to multiple rows of gate lines of a pixel array, thereby controlling, for example, multiple rows of gate lines to be turned on sequentially, and at the same time, data signals are provided from the data lines to pixel units of corresponding rows in the pixel array to form gray scale voltages required for each pixel unit to display each gray scale of an image, and further display one frame of an image. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display substrate, the display substrate including a base substrate including a display region and a peripheral region located on at least one side of the display region, the display region including a plurality of rows and a plurality of columns of pixel units arranged in an array, a plurality of first gate scanning signal lines respectively connected to emission control sub-circuits of the pixel units in the plurality of rows and the plurality of columns of pixel units, and a plurality of second gate scanning signal lines respectively connected to first reset sub-circuits of the pixel units in the plurality of rows, the peripheral region including a first scanning driving circuit respectively connected to the plurality of first gate scanning signal lines via a plurality of first connection wirings having a first resistance value, the first scanning driving circuit respectively providing emission control signals to the emission control sub-circuits of the pixel units in the plurality of rows, and a first reset sub-circuit of the pixel units in the plurality of rows. a second scan driving circuit located near the first gate scanning signal line and connected to the second gate scanning signal lines via a plurality of second connection wirings having a second resistance value, respectively, to provide first reset control signals to first reset sub-circuits of the plurality of rows of pixel units; a first voltage signal line configured to provide a first voltage; and a second voltage signal line configured to provide a second voltage, wherein the first scan driving circuit is connected to the first voltage signal line and outputs the first voltage as a first portion of the light emission control signal, and the second scan driving circuit is connected to the second voltage signal line and outputs the second voltage as the first portion of the first reset control signal, and a ratio of the second resistance value to the first resistance value is smaller than a ratio of an average line width of the second voltage signal line to an average line width of the first voltage signal line.

[0005] For example, in a display substrate provided in at least one embodiment of the present disclosure, the peripheral region further includes a third voltage signal line configured to provide a third voltage and a fourth voltage signal line configured to provide a fourth voltage, the first scanning drive circuit is further connected to the third voltage signal line to output the third voltage as a second part of the light emission control signal, the second scanning drive circuit is further connected to the fourth voltage signal line to output the fourth voltage as a second part of the first reset control signal, the third voltage being smaller than the first voltage and the fourth voltage being smaller than the second voltage.

[0006] For example, in a display substrate provided in at least one embodiment of the present disclosure, a ratio of the second resistance value to the first resistance value is smaller than a ratio of an average line width of the fourth voltage signal line to an average line width of the third voltage signal line.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area further includes a plurality of third gate scanning signal lines respectively connected to the threshold compensation sub-circuits of the pixel units in the plurality of rows, and the second scanning driving circuit is further connected to the plurality of third gate scanning signal lines respectively through a plurality of third connecting wires, to respectively provide threshold compensation control signals to the threshold compensation sub-circuits of the pixel units in the plurality of rows, and a resistance value of each of the third connecting wires is a third resistance value.

[0008] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area further includes a plurality of fourth gate scanning signal lines respectively connected to the data writing sub-circuits of the pixel units in the plurality of rows, the peripheral area further includes a third scan driving circuit respectively connected to the plurality of fourth gate scanning signal lines via a plurality of fourth connecting wires and providing data writing control signals to the data writing sub-circuits of the pixel units in the plurality of rows, the second scan driving circuit is located between the first scan driving circuit and the third scan driving circuit with respect to the display area, and a resistance value of each of the fourth connecting wires is a fourth resistance value, and the fourth resistance value is smaller than the third resistance value.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the average line width of the first voltage signal line and the average line width of the second voltage signal line satisfy the following relationship:

number

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the average line width of the first voltage signal line and the average line width of the second voltage signal line satisfy the following relationship:

number

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the average line width of the fourth voltage signal line and the average line width of the third voltage signal line satisfy the following relationship:

number

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the average line width of the fourth voltage signal line and the average line width of the third voltage signal line satisfy the following relationship:

number

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first resistance value, the second resistance value, and the third resistance value are:

number

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first resistance value, the second resistance value, and the third resistance value are:

number

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first resistance value and the third resistance value satisfy the following relationship:

number

[0016] For example, in a display substrate provided in at least one embodiment of the present disclosure, the second scan driving circuit includes a plurality of cascaded first shift register units, wherein the i-th first shift register unit is connected to the i-th third gate scanning signal line through the i-th third connecting wire, the i-th third gate scanning signal line is connected to a threshold compensation sub-circuit of a pixel unit in the i-th row, the i-th first shift register unit is further connected to the i+n-th second gate scanning signal line through the i+n-th second connecting wire, and the i+n-th second gate scanning signal line is connected to a first reset sub-circuit of a pixel unit in the i+n-th row, and both i and n are integers greater than 0.

[0017] For example, in a display substrate provided in at least one embodiment of the present disclosure, the second scan driving circuit further includes n additional shift register units connected in cascade to n second gate scanning signal lines corresponding to the pixel units in the previous n rows via n second connecting wirings, respectively, and providing the first reset control signals to first reset sub-circuits in the pixel units in the previous n rows, wherein the jth additional shift register unit is connected to the jth second gate scanning signal line via the jth second connecting wiring, and the jth second gate scanning signal line is connected to the pixel unit in the jth row, where j is an integer greater than or equal to 1 and less than or equal to n.

[0018] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area includes a first display sub-region and a second display sub-region, the number of pixel units in each row in the second display sub-region is equal, and the number of pixel units in any row in the first display sub-region is less than the number of pixel units in a row in the second display sub-region.

[0019] For example, in a display substrate provided in at least one embodiment of the present disclosure, the first display sub-region includes a pixel unit in a pth row, and the second display sub-region includes a pixel unit in a qth row, a difference between a resistance value of the first connection wiring connected to the pth row pixel unit and a resistance value of the first connection wiring connected to the qth row pixel unit is a fifth resistance value, a difference between a resistance value of the third connection wiring connected to the pth row pixel unit and a resistance value of the third connection wiring connected to the qth row pixel unit is a sixth resistance value, and a difference between a resistance value of the fourth connection wiring connected to the pth row pixel unit and a resistance value of the fourth connection wiring connected to the qth row pixel unit is a seventh resistance value, the fifth resistance value, the sixth resistance value, and the seventh resistance value all increase as a number of missing pixel units of the pth row pixel unit increases relative to the qth row pixel unit, and p is an integer greater than 0, and q is an integer greater than p.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the fifth resistance value, the sixth resistance value and the seventh resistance value satisfy the following relationship:

number

[0021] For example, in a display substrate provided in at least one embodiment of the present disclosure, the peripheral region includes a third scan driving circuit configured to provide a data writing control signal to a data writing sub-circuit of the pixel units of the plurality of rows, the first connection wiring includes at least two first transfer electrodes and a plurality of first connection electrodes, the at least two first transfer electrodes are located in a layer different from the plurality of first connection electrodes, the plurality of first connection electrodes are respectively connected to the at least two first transfer electrodes through vias penetrating an insulating layer to form the first connection wiring, the resistivity of each of the first transfer electrodes is smaller than the resistivity of each of the first connection electrodes, the third connection wiring includes at least one second transfer electrode and a plurality of second connection electrodes, the at least one second transfer electrode is located in a layer different from the plurality of second connection electrodes, the plurality of second connection electrodes are respectively connected to the at least one second transfer electrode through vias penetrating an insulating layer to form the third connection wiring, the resistivity of each of the second transfer electrodes is smaller than the resistivity of each of the second connection electrodes, and the number of the first transfer electrodes is greater than the number of the second transfer electrodes.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between two adjacent first transfer electrodes satisfies the following relationship:

number

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between the two connection terminals of each of the first transfer electrodes satisfies the following relationship:

number

number

[0024] For example, in a display substrate provided in at least one embodiment of the present disclosure, the second connection wiring includes at least one third transfer electrode extending along a second direction different from a first direction, and a plurality of third connection electrodes extending along the second direction, the at least one third transfer electrode is located in a layer different from the plurality of third connection electrodes, the plurality of third connection electrodes are each connected to the at least one third transfer electrode through a via penetrating an insulating layer to form the second connection wiring, the resistivity of the third transfer electrode is smaller than the resistivity of the third connection electrode, and a distance between two adjacent third transfer electrodes satisfies the following relationship:

number

[0025] For example, in a display substrate provided in at least one embodiment of the present disclosure, the first transfer electrode and the first signal line of the second scanning driving circuit at least partially overlap in a direction perpendicular to the base substrate, and / or the second transfer electrode and the second signal line of the third scanning driving circuit at least partially overlap in a direction perpendicular to the base substrate.

[0026] For example, in a display substrate provided in at least one embodiment of the present disclosure, the peripheral region further includes a first auxiliary electrode layer, a pixel unit in the display region includes a light-emitting element, the light-emitting element includes a first electrode layer, a second electrode layer located on a side of the first electrode layer away from the base substrate, and a light-emitting layer located between the first electrode layer and the second electrode layer, the first auxiliary electrode layer is disposed in the same layer as the first electrode layer of the light-emitting element included in the pixel unit in the display region, the first auxiliary electrode layer is located on a side of the first scanning driving circuit away from the base substrate, an electrode exhaust hole is provided in the first auxiliary electrode layer, at least one end of the first transfer electrode and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate, and / or at least one end of the second transfer electrode and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate.

[0027] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second voltage signal line is provided with a signal line exhaust hole, and the size of the signal line exhaust hole satisfies the following relationship:

number

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, a signal line exhaust hole is provided on the second voltage signal line, and the size of the signal line exhaust hole satisfies the following relationship:

number

[0029] For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the first shift register units includes a first switching transistor, a difference between a distance between two adjacent signal line exhaust holes and a channel size of the first switching transistor is smaller than a predetermined threshold, and a connection via between the first voltage signal line and a first pole of the second capacitance is located between two adjacent signal line exhaust holes or at least partially overlaps with the signal line exhaust hole.

[0030] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display region further includes a pixel definition layer, the pixel definition layer includes an opening, and the opening is configured to define a light-emitting region of a pixel unit in the display region; the peripheral region further includes an auxiliary insulating layer and a second auxiliary electrode layer, the auxiliary insulating layer is disposed in the same layer as the pixel definition layer located in the display region, the second auxiliary electrode layer is disposed in the same layer as the second electrode layer located in the display region, the auxiliary insulating layer is disposed on a side of the first auxiliary electrode layer away from the base substrate, and the second auxiliary electrode layer is disposed on a side of the auxiliary insulating layer away from the base substrate; the auxiliary insulating layer has at least one opening, and a size of the opening of the auxiliary insulating layer satisfies the following relationship:

number

[0031] For example, in a display substrate provided in at least one embodiment of the present disclosure, at least one of the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit and at least one opening of the auxiliary insulating layer at least partially overlap in a direction perpendicular to the base substrate.

[0032] For example, in a display substrate provided in at least one embodiment of the present disclosure, when the peripheral area on the display area side includes a plurality of scanning drive circuits, the closer the distance between the scanning drive circuits and the display area is relative to the plurality of scanning drive circuits, the fewer the number of transfer electrodes installed on the connection wiring connected to the scanning drive circuits, the plurality of scanning drive circuits include the first scanning drive circuit and the second scanning drive circuit, and the connection wiring includes the first connection wiring and the second connection wiring.

[0033] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area further includes a plurality of fifth gate scanning signal lines respectively connected to the second reset sub-circuits of the pixel units in the plurality of rows, and the peripheral area further includes a fourth scan driving circuit respectively connected to the plurality of fifth gate scanning signal lines via a plurality of fifth connecting wires, for respectively providing second reset control signals to the second reset sub-circuits of the pixel units in the plurality of rows, the fourth scan driving circuit being located on a side of the third scan driving circuit away from the display area, and a resistance value of each of the fifth connecting wires is an eighth resistance value, and the eighth resistance value is greater than the third resistance value.

[0034] For example, in the display substrate provided in at least one embodiment of the present disclosure, the fourth scan driving circuit is located between the first scan driving circuit and the third scan driving circuit, and the eighth resistance value is smaller than the first resistance value.

[0035] For example, in the display substrate provided in at least one embodiment of the present disclosure, the peripheral region further includes a fifth voltage signal line and a sixth voltage signal line, the fourth scan driving circuit is connected to the fifth voltage signal line and outputs a fifth voltage as a first portion of the second reset control signal, the fourth scan driving circuit is connected to the sixth voltage signal line and outputs a sixth voltage as a second portion of the second reset control signal, an average line width of the fifth voltage signal line is larger than an average line width of the first voltage signal line and smaller than an average line width of the third voltage signal line, and an average line width of the sixth voltage signal line is larger than an average line width of the second voltage signal line and smaller than an average line width of the fourth voltage signal line.

[0036] For example, in a display substrate provided in at least one embodiment of the present disclosure, the display area further includes a plurality of sixth gate scanning signal lines respectively connected to the emission control sub-circuits of the pixel units in the plurality of rows, and the peripheral area further includes a fifth scan driving circuit respectively connected to the plurality of sixth gate scanning signal lines via a plurality of sixth connecting wires to provide emission control signals to the emission control sub-circuits of the pixel units in the plurality of rows, the fifth scan driving circuit being located on a side of the third scan driving circuit away from the display area, and the resistance value of each of the sixth connecting wires is a ninth resistance value, and the ninth resistance value is greater than the third resistance value.

[0037] For example, in the display substrate provided in at least one embodiment of the present disclosure, the fifth scan driving circuit is located on a side of the first scan driving circuit away from the display area, and the ninth resistance value is greater than the first resistance value.

[0038] For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the pixel units in the multiple rows and multiple columns includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a driving subcircuit, the data writing subcircuit, the threshold compensation subcircuit, a reset subcircuit and a light emission control subcircuit, the driving subcircuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light-emitting element, the data writing subcircuit is connected to the first terminal of the driving subcircuit, a data line and the fourth gate scanning signal line, and is configured to write a data signal provided from the data line to the first terminal of the driving subcircuit in response to the data write control signal provided from the fourth gate scanning signal line, and the threshold compensation subcircuit is connected to the control terminal and the second terminal of the driving subcircuit, a first voltage line and the third gate scanning signal line. and configured to compensate the driving sub-circuit in response to the threshold compensation control signal provided from the third gate scanning signal line and a written data signal; the reset sub-circuit includes the first reset sub-circuit, the first reset sub-circuit is connected to the second terminal of the driving sub-circuit, an initial signal line, and the second gate scanning signal line, and is configured to apply an initial voltage provided from the initial signal line to the second terminal of the driving sub-circuit in response to the first reset control signal provided from the second gate scanning signal line; and the light emission control sub-circuit includes a first light emission control sub-circuit, the first voltage line, the first terminal of the driving sub-circuit, and the first gate scanning signal line, and is configured to apply a first voltage provided from the first voltage line to the first terminal of the driving sub-circuit in response to the light emission control signal provided from the first gate scanning signal line.

[0039] For example, in a display substrate provided in at least one embodiment of the present disclosure, the reset subcircuit further includes a second reset subcircuit, the plurality of fourth gate scanning signal lines are further connected to the second reset subcircuits of the pixel units in the plurality of rows, respectively; the third scanning driving circuit provides second reset control signals to the second reset subcircuits of the pixel units in the plurality of rows via the plurality of fourth gate scanning signal lines, respectively; the second reset subcircuit is connected to the initial signal line, the fourth gate scanning signal line, and a first terminal of the light-emitting element, and is configured to apply an initial voltage provided from the initial signal line to the first terminal of the light-emitting element in response to the second reset control signal provided from the fourth gate scanning signal line; and the light-emitting control subcircuit further includes a second light-emitting control subcircuit, the second light-emitting control subcircuit is connected to the second terminal of the driving subcircuit, the first terminal of the light-emitting element, and the first gate scanning signal line, and is configured to apply the driving current to the first terminal of the light-emitting element in response to the light-emitting control signal provided from the first gate scanning signal line.

[0040] At least one embodiment of the present disclosure further provides a display panel, which includes the display substrate according to any one of the above aspects.

[0041] In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings of the embodiments are briefly described below. Obviously, the drawings described below are only related to some embodiments of the present invention, and are not intended to limit the present invention. [Brief description of the drawings]

[0042] [Figure 1] FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram of a pixel unit according to at least one embodiment of the present disclosure. [Figure 3A] FIG. 3A is a circuit diagram of a second shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 3B]FIG. 3B is a schematic diagram of a layout of the second shift register unit shown in FIG. 3A on a display substrate. [Figure 4A] FIG. 4A is a circuit diagram of a first shift register unit according to at least one embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of partial signal lines in the layout on the display substrate of the first shift register unit shown in FIG. 4A. [Figure 5A] FIG. 5A is a circuit diagram of a third shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 5B] FIG. 5B is a schematic diagram of a partial layout of the third shift register unit shown in FIG. 5A on the display substrate. [Figure 6] FIG. 6 is a timing diagram of the emission control signal and the first reset control signal according to at least one embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic plan view of a partial region of a display substrate according to at least one embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic plan view of a partial region of a display substrate according to at least one embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic diagram of a partial layout of a peripheral area in accordance with at least one embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view of some examples of the peripheral region 20 shown in FIG. 7 along the AA' direction. [Figure 11A] FIG. 11A is a schematic plan view of another display substrate in accordance with at least one embodiment of the present disclosure. [Figure 11B] FIG. 11B is a schematic plan view of another display substrate in accordance with at least one embodiment of the present disclosure. [Figure 11C] FIG. 11C is a schematic plan view of another display substrate in accordance with at least one embodiment of the present disclosure. [Figure 11D] FIG. 11D is a schematic plan view of another display substrate in accordance with at least one embodiment of the present disclosure. [Figure 12]FIG. 12 is a schematic diagram of a display panel in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described clearly and completely below with reference to the drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without requiring creative labor all belong to the protection scope of the present invention.

[0044] Unless otherwise defined, technical or scientific terms used in this disclosure have common meanings that can be understood by those skilled in the art. The terms "first", "second" and similar terms used in this disclosure do not indicate any order, number or importance, but are merely for distinguishing different components. Similarly, similar terms such as "one", "one" or "the" do not limit the number, but mean that there is at least one. Similar terms such as "comprise" or "include" mean that the element or member described before the term includes the element or member listed after the term and their equivalents, and do not exclude other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly connected. Terms such as "upper", "lower", "left", "right" and the like are merely for indicating relative positional relationships, and when the absolute position of the described object is changed, the relative positional relationships may change accordingly.

[0045] The present disclosure will be described below by means of some specific embodiments. In order to make the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present invention is present in more than one drawing, the component is represented by the same reference symbol in each drawing.

[0046] The display substrate includes a display area and a peripheral area, the display area includes pixel units arranged in an array, and the peripheral area can be located on at least one side of the display area. The peripheral area located on the display area side can be provided with one or more (two or more) GOAs, and when multiple GOAs are provided in the peripheral area, the distances between the GOAs and the display area at different positions are different, so the lengths of the wiring from the output terminals of the GOAs at different positions to the display area are different, and therefore the resistances of the wiring from the output terminals of the GOAs at different positions to the display area are different, and the resistances of the wiring affect the delay times of the output signals of the GOAs, so the delay times of the output signals of the GOAs at different positions are different.

[0047] At least one embodiment of the present disclosure provides a display substrate, including a base substrate, the base substrate including a display region and a peripheral region located on at least one side of the display region, the display region including a plurality of rows and a plurality of columns of pixel units arranged in an array, a plurality of first gate scanning signal lines respectively connected to the emission control sub-circuits of the pixel units in the plurality of rows and the plurality of columns of pixel units, and a plurality of second gate scanning signal lines respectively connected to the first reset sub-circuits of the pixel units in the plurality of rows, the peripheral region including a first scanning driving circuit respectively connected to the plurality of first gate scanning signal lines via a plurality of first connection wirings having a first resistance value, and respectively providing emission control signals to the emission control sub-circuits of the pixel units in the plurality of rows, and a plurality of second gate scanning signal lines respectively connected to the first reset sub-circuits of the pixel units in the plurality of rows. The pixel circuit includes a second scanning driving circuit located on a side closer to the display area of ​​the driving circuit, the second scanning driving circuit being respectively connected to a plurality of second gate scanning signal lines via a plurality of second connecting wirings having a second resistance value, and providing first reset control signals to first reset sub-circuits of the pixel units in a plurality of rows, a first voltage signal line configured to provide a first voltage, and a second voltage signal line configured to provide a second voltage, wherein the first scanning driving circuit is connected to the first voltage signal line and outputs the first voltage as a first portion of the light emission control signal, and the second scanning driving circuit is connected to the second voltage signal line and outputs the second voltage as the first portion of the first reset control signal, and a ratio of the second resistance value to the first resistance value is smaller than a ratio of an average line width of the second voltage signal line to an average line width of the first voltage signal line.

[0048] The display substrate provided in the embodiment of the present disclosure adjusts the line width of the first voltage signal line connected to the first scanning driving circuit and the line width of the second voltage signal line connected to the second scanning driving circuit, thereby balancing the influence of delay time caused by the resistance of the first connecting wiring and the resistance of the second connecting wiring, and further reducing the difference in signal delay time caused by different resistances of the first connecting wiring and the second connecting wiring.

[0049] Hereinafter, embodiments of the present disclosure and some examples thereof will be described in detail with reference to the drawings.

[0050] FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. For example, as shown in FIG. 1, a display substrate 1 includes a display area (i.e., a pixel array area) 10 and a peripheral area 20 located on at least one side of the display area 10, and the display area 10 includes a plurality of rows and a plurality of columns of pixel units 11 arranged in an array, a plurality of first gate scanning signal lines (E1, ..., Ei, ..., Em (i is an integer equal to or greater than 1, and m is an integer equal to or greater than i)) respectively connected to the emission control sub-circuits of the plurality of rows of pixel units 11, a plurality of second gate scanning signal lines (RT1, ..., RTi, ..., RTm) respectively connected to the first reset sub-circuits of the plurality of rows of pixel units 11, a plurality of third gate scanning signal lines (GN1, ..., GNi, ..., GNm) respectively connected to the threshold compensation sub-circuits of the plurality of rows of pixel units 11, and a plurality of fourth gate scanning signal lines (GP1, ..., GPi, ..., GPm) respectively connected to the data writing sub-circuits of the plurality of rows of pixel units 11. For example, each pixel unit 11 may include a pixel circuit and a light emitting element having a circuit structure such as 7T1C, 7T2C, 8T2C or 4T1C in the art.

[0051] For example, the peripheral area 20 includes a first scan driving circuit 21 and a second scan driving circuit 22 .

[0052] For example, the first scanning driving circuit 21 is respectively connected to a plurality of first gate scanning signal lines E1, E2, ..., Ei, ..., Em through a plurality of first connection wirings 30 to respectively provide light emission control signals to the light emission control sub-circuits of the pixel units 11 in a plurality of rows, and the resistance value of each of the first connection wirings 30 is a first resistance value R1. Since the first scanning driving circuit 21 is used to drive the light emission control sub-circuits of the pixel units 11, the first scanning driving circuit 21 may be called an EM GOA (light emission control gate scanning driving circuit). Each of the first connection wirings 30 and the first gate scanning signal lines connected thereto may be integrally formed, and in FIG. 1, the first connection wirings and the first gate scanning signal lines are represented by lines of different widths to distinguish the first connection wirings and the first gate scanning signal lines, but in the actual application process, the widths of the first connection wirings 30 and the first gate scanning signal lines may be the same or different, and the present disclosure does not limit this.

[0053] For example, the second scan driving circuit 22 is located on the side closer to the display area 10 of the first scan driving circuit 21, and is respectively connected to a plurality of second gate scan signal lines RT1, RT2, ..., RTi, ..., RTm via a plurality of second connecting wires 40, to respectively provide first reset control signals to the first reset sub-circuits of the pixel units of a plurality of rows, and the resistance value of each second connecting wire 40 is a second resistance value R2. For example, the second scan driving circuit 22 provides a gate scan driving signal to the N-type transistor in the pixel unit 11, so the second scan driving circuit 22 may be called GATE GOA N, and is abbreviated as GN. Each second connecting wire 40 and the second gate scanning signal line connected thereto may be integrally formed. In FIG. 1, the second connecting wires and the second gate scanning signal lines are represented using lines of different widths to distinguish the second connecting wires from the second gate scanning signal lines. However, in an actual application process, the widths of the second connecting wires and the first gate scanning signal lines may be the same or different, and the present disclosure does not limit this.

[0054] For example, the second scanning driving circuit 22 is further connected to a plurality of third gate scanning signal lines GN1, ..., GNi, ..., GNm through a plurality of third connecting wires 50, respectively, to provide threshold compensation control signals to the threshold compensation sub-circuits of the pixel units of a plurality of rows, and the resistance value of each third connecting wire 50 is a third resistance value R3. Each third connecting wire 50 and the third gate scanning signal line connected thereto may be integrally formed, and in FIG. 1, the third connecting wire 50 and the third gate scanning signal line are represented by lines of different widths to distinguish the third connecting wire 50 and the third gate scanning signal line, but in the actual application process, the widths of the third connecting wire 50 and the third gate scanning signal line may be the same or different, and the present disclosure does not limit this.

[0055] For example, the peripheral area 20 further includes a third scan driving circuit 23, which is connected to a plurality of fourth gate scanning signal lines GP1, ..., GPi, ..., GPm through a plurality of fourth connecting wires 60, respectively, to provide data write control signals to the data write sub-circuits of the pixel units in a plurality of rows. The second scan driving circuit 22 is located between the first scan driving circuit 21 and the third scan driving circuit 23 with respect to the display area 10, that is, the third scan driving circuit 23 is located on the side of the second scan driving circuit 22 closer to the display area 10. The resistance value of each fourth connecting wire 60 is a fourth resistance value R4. For example, the third scan driving circuit 23 provides a gate scan driving signal to the P-type transistor in the pixel unit 11, so the third scan driving circuit 23 may be called GATE GOA P, abbreviated as GP. Each fourth connecting wire 60 and the fourth gate scanning signal line connected thereto may be integrally formed. In FIG. 1, the fourth connecting wire 60 and the fourth gate scanning signal line are represented using lines of different widths to distinguish the fourth connecting wire 60 from the fourth gate scanning signal line. However, in actual application, the widths of the fourth connecting wire 60 and the fourth gate scanning signal line may be the same or different, and the present disclosure does not limit this.

[0056] As shown in FIG. 1, data lines DL1 to DLN (N is an integer greater than 1) pass vertically through a display area 10 to provide data signals to pixel units 11 arranged in an array. For example, each pixel unit 11 may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 7T2C, 8T2C, or 4T1C in the art, and the pixel circuit 11 operates under the control of a data signal transmitted through the data line and a gate scanning driving signal and a light-emitting control signal transmitted through the gate line to drive the light-emitting element to emit light and realize operations such as display. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and the embodiments of the present disclosure are not limited thereto.

[0057] 2 is a circuit structure diagram of a pixel unit according to at least one embodiment of the present disclosure. As shown in FIG. 2, each pixel unit 11 of the pixel units of multiple rows and columns includes a light emitting element 111 and a pixel circuit 112 for driving the light emitting element 111 to emit light, and the pixel circuit 112 includes a driving sub-circuit 1123, a data writing sub-circuit 1124, a threshold compensation sub-circuit 1122, a reset sub-circuit, a light emission control sub-circuit and a storage capacitance Cst.

[0058] The first reset sub-circuit 1121 includes a first reset transistor BT1, the threshold compensation sub-circuit 1122 includes a threshold compensation transistor BT2, the driving sub-circuit 1123 includes a driving transistor BT3, the data write sub-circuit 1124 includes a data write transistor BT4, the first light-emitting control sub-circuit 1125 includes a first light-emitting control transistor BT5, the second light-emitting control sub-circuit 1126 includes a second light-emitting control transistor BT6, and the second reset sub-circuit 1127 includes a second reset transistor BT7. For example, the first reset transistor BT1 and the threshold compensation transistor BT2 are N-type transistors, and the data write transistor BT4 and the second reset transistor BT7 are P-type transistors. The connection relationship and operation principle of the pixel unit in the embodiment of the present disclosure are only examples, and the pixel unit may further use other structures as necessary, and the present disclosure is not limited thereto.

[0059] For example, the driving sub-circuit 1123 includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the light-emitting element 111. For example, the control terminal of the driving sub-circuit 1123 is connected to a first node S1, the first terminal is connected to a second node S2, and the second terminal is connected to a third node S3.

[0060] For example, as shown in Figures 1 and 2, the data write sub-circuit 1124 is connected to a first terminal of the driving sub-circuit 1123, a data line Vdata, and a fourth gate scanning signal line GPi (i is an integer greater than or equal to 1 and less than or equal to m), and is configured to write a data signal provided from the data line Vdata to the first terminal of the driving sub-circuit 1123 in response to a data write control signal provided from the fourth gate scanning signal line GPi.

[0061] For example, the threshold compensation subcircuit 1122 is connected to the control terminal and the second terminal of the driving subcircuit 1123, the first voltage line VDD and the third gate scanning signal line GNi, and is configured to compensate the driving subcircuit 1123 in response to the threshold compensation control signal provided from the third gate scanning signal line GNi and the written data signal.

[0062] For example, the reset subcircuit includes a first reset subcircuit 1121, which is connected to a control terminal of the driving subcircuit 1123, an initial signal line Vinit1 and a second gate scanning signal line RTi, and is configured to apply an initial voltage provided from the initial signal line to the second terminal of the driving subcircuit 1123 in response to a first reset control signal provided from the second gate scanning signal line RTi.

[0063] For example, the reset subcircuit further includes a second reset subcircuit 1127, a plurality of fourth gate scanning signal lines GPi are further connected to the second reset subcircuits 1127 of the pixel units of the plurality of rows, respectively, and the third scanning driving circuit 23 provides second reset control signals to the second reset subcircuits 1127 of the pixel units of the plurality of rows via the plurality of fourth gate scanning signal lines GPi, respectively. For example, the second reset subcircuit 1127 is connected to the initial signal line Vinit2, the fourth gate scanning signal line GPi, and the first terminal of the light-emitting element 111, and is configured to apply an initial voltage provided from the initial signal line Vinit2 to the first terminal of the light-emitting element 111 in response to the second reset control signal provided from the fourth gate scanning signal line GPi. The second terminal of the light-emitting element 111 is connected to the second voltage line VSS.

[0064] For example, the light-emitting control subcircuit includes a first light-emitting control subcircuit 1125, which is connected to a first voltage line VDD, a first terminal of the driving subcircuit 1123 and a first gate scanning signal line Ei, and is configured to apply a first voltage provided from the first voltage line VDD to the first terminal of the driving subcircuit 1123 in response to a light-emitting control signal provided from the first gate scanning signal line Ei.

[0065] For example, the light-emitting control subcircuit further includes a second light-emitting control subcircuit 1126, which is connected to the second terminal of the driving subcircuit 1123, the first terminal of the light-emitting element 111 and the first gate scanning signal line Ei, and is configured to apply a driving current to the first terminal of the light-emitting element 111 in response to a light-emitting control signal provided from the first gate scanning signal line Ei.

[0066] For example, as shown in Fig. 1, the first scan driving circuit 21 includes a plurality of cascaded second shift register units 211 (for example, represented by blocks 211 filled with a diamond lattice in the dashed frame 21 in Fig. 1), and each of the second shift register units 211 is used to drive one or more rows of pixel units 11. The embodiment of the present disclosure is described taking as an example that each of the second shift register units 211 is used to drive one row of pixel units 11, but the embodiment of the present disclosure is not limited thereto.

[0067] For example, the peripheral region further includes a first voltage signal line Evgh (not shown in FIG. 1) and a third voltage signal line Evgl (not shown in FIG. 1), where the first voltage signal line Evgh is configured to provide a first voltage, and the third voltage signal line Evgl is configured to provide a third voltage, where the third voltage is smaller than the first voltage. The first scan driving circuit 21 is connected to the first voltage signal line Evgh to output a first voltage as a first portion of the light emitting control signal, for example, the first voltage signal line Evgh is all connected to a plurality of second shift register units 211 in the first scan driving circuit 21. The first portion of the light emitting control signal is, for example, a high level portion of the light emitting control signal, for example, the high level portion of the light emitting control signal can turn off the first light emitting control transistor BT5 and the second light emitting control transistor BT6 in a non-light emitting stage. The first scanning driving circuit 21 is further connected to a third voltage signal line Evgl to output a third voltage as the second part of the light emitting control signal, for example, the third voltage signal line Evgl is all connected to a plurality of second shift register units 211 in the first scanning driving circuit 21. The second part of the light emitting control signal is, for example, a low level part of the light emitting control signal, for example, the low level of the light emitting control signal can turn on the first light emitting control transistor BT5 and the second light emitting control transistor BT6 in the light emitting stage.

[0068] Fig. 3A is a circuit diagram of a second shift register unit according to at least one embodiment of the present disclosure. Fig. 3B is a schematic diagram of the layout of the second shift register unit shown in Fig. 3A on a display substrate. Hereinafter, the second shift register unit will be briefly described with reference to Figs. 3A and 3B.

[0069] As shown in FIGS. 3A and 3B , the second shift register unit 211 includes 12 transistors (a first transistor ET1, a second transistor ET2, a third transistor ET3, a fourth transistor ET4, a fifth transistor ET5, a sixth transistor ET6, a seventh transistor ET7, an eighth transistor ET8, a ninth transistor ET9 (also referred to as an output transistor), a tenth transistor ET10 (also referred to as an output control transistor or an output transistor, and the embodiments of the present disclosure are not limited thereto), an eleventh transistor ET11, and a twelfth transistor ET12), and three capacitances (a first capacitance EC1, a second capacitance EC2, and a third capacitance EC3). In some embodiments, the second shift register unit 211 may be a 10T3C circuit that does not include the eleventh transistor ET11 and the twelfth transistor ET12. In other embodiments, the second shift register unit 211 may be a 13T3C circuit as shown in FIG. 4A , or a 12T3C circuit that does not include the thirteenth transistor GNT13.

[0070] For example, when a plurality of second shift register units 211 are cascaded, the second pole of the first transistor ET1 in the first-stage second shift register unit 211 is connected to the input terminal EI, and the input terminal EI is connected to the trigger signal line ESTV and configured to receive a trigger signal as an input signal, and the second pole of the first transistor ET1 in each of the other stages second shift register units 211 is electrically connected to the output terminal of the previous stage second shift register unit 211 to receive an output signal output from the output terminal EOUT (e.g., output terminals E021 and E022) of the previous stage second shift register unit 211 as an input signal, thereby realizing shift output and providing a light emission control signal shifted, for example, row by row, to the pixel units 11 arranged in an array in the display area 10 of the display panel. For example, the following description will be given taking the ninth transistor ET9 as an example of an output transistor.

[0071] 3A and 3B, the second shift register unit 211 further includes a first clock signal terminal ECK and a second clock signal terminal ECB, where ECK further represents the first clock signal line and ECB further represents the second clock signal line. For example, the first clock signal and the second clock signal can be pulse signals with a duty cycle greater than 50%, and the difference between them is, for example, half a cycle.

[0072] For example, Evgh represents the first voltage provided from the first voltage signal line and the first voltage signal line, and Evgl represents the third voltage provided from the third voltage signal line and the third voltage signal line, where the third voltage is smaller than the first voltage, for example, the first voltage is a DC high level and the third voltage is a DC low level.

[0073] 3A and 3B, the gate of the first transistor ET1 is connected to a first clock signal terminal ECK (the first clock signal terminal is connected to a first clock signal line ECK) to receive a first clock signal, the second pole of the first transistor ET1 is connected to an input terminal EI, and the first pole of the first transistor ET1 is connected to a first node ED1. For example, when the second shift register unit is the second shift register unit of the first stage, the input terminal EI is connected to a trigger signal line ESTV to receive a trigger signal, and when the second shift register unit is the second shift register unit of each stage other than the second shift register unit of the first stage, the input terminal EI is connected to the output terminal EOUT of the second shift register unit of the previous stage.

[0074] The gate of the second transistor ET2 is connected to the first node ED1, the first electrode of the second transistor ET2 is connected to the second node ED2, and the second electrode of the second transistor ET2 is connected to the first clock signal terminal ECK to receive the first clock signal.

[0075] The gate of the third transistor ET3 is connected to the first clock signal terminal ECK to receive the first clock signal, the first electrode of the third transistor ET3 is connected to the second node ED2, and the second electrode of the third transistor ET3 is connected to the third voltage signal line Evgl to receive the third voltage.

[0076] A gate of the fourth transistor ET4 is connected to a second clock signal terminal ECB (e.g., the second clock signal terminal ECB is connected to the second clock signal line ECB) to receive a second clock signal, a first electrode of the fourth transistor ET4 is connected to the first node ED1, and a second electrode of the fourth transistor ET4 is connected to a second electrode of the fifth transistor ET5.

[0077] The gate of the fifth transistor ET5 is connected to the second node ED2, and the first electrode of the fifth transistor ET5 is connected to the first voltage signal line Evgh to receive the first voltage.

[0078] The gate of the sixth transistor ET6 is connected to the second electrode of the eleventh transistor ET11, the first electrode of the sixth transistor ET6 is connected to the second clock signal terminal ECB to receive the second clock signal, and the second electrode of the sixth transistor ET6 is connected to the third node ED3.

[0079] A first electrode of the first capacitance EC1 is connected to a second electrode of the eleventh transistor ET11, and a second electrode of the first capacitance EC2 is connected to the third node ED3.

[0080] The gate of the seventh transistor ET7 is connected to the second clock signal terminal ECB to receive the second clock signal, the first electrode of the seventh transistor ET7 is connected to the third node ED3, and the second electrode of the seventh transistor ET7 is connected to the fourth node ED4.

[0081] The gate of the eighth transistor ET8 is connected to the first node ED1, the first electrode of the eighth transistor ET8 is connected to the fourth node ED4, and the second electrode of the eighth transistor ET8 is connected to the first voltage signal line Evgh to receive the first voltage.

[0082] The gate of the output transistor ET9 is connected to the fourth node ED4, the first electrode of the output transistor ET9 is connected to the first voltage signal line Evgh to receive the first voltage, and the second electrode of the output transistor ET9 is connected to the output terminal EOUT.

[0083] A first pole of the third capacitance EC3 is connected to the fourth node ED4, and a second pole of the third capacitance EC3 is connected to the first voltage signal line Evgh to receive the third voltage.

[0084] The gate of the tenth transistor ET10 is connected to the second electrode of the twelfth transistor ET12, the first electrode of the tenth transistor ET10 is connected to the third voltage signal line Evgl to receive the third voltage, and the second electrode of the tenth transistor ET10 is connected to the output terminal EOUT.

[0085] A first electrode of the second capacitance EC2 is connected to a second electrode of the twelfth transistor ET12, and a second electrode of the second capacitance EC2 is connected to a second clock signal terminal ECB to receive the second clock signal.

[0086] The gate of the eleventh transistor ET11 is connected to the third voltage signal line Evgl to receive the third voltage, and the first electrode of the eleventh transistor ET11 is connected to the second node ED2.

[0087] The gate of the twelfth transistor ET12 is connected to the third voltage signal line Evgl to receive the third voltage, and the first electrode of the twelfth transistor ET12 is connected to the first node ED1.

[0088] The operation principle of the second shift register unit can be referred to in the art, and detailed description is omitted here.

[0089] As shown in FIG. 3B, the signal lines ECB, ECK, Evgl, and Evgh can be arranged along a first direction (eg, the X-axis direction) and can all extend along a second direction (eg, the Y-axis direction).

[0090] 3A, the transistors in the second shift register unit 211 are all P-type transistors, that is, each transistor is turned on when its gate is connected to a low level (on level), and turned off when its gate is connected to a high level (off level). At this time, the first pole of the transistor may be the source, and the second pole of the transistor may be the drain.

[0091] The second shift register unit includes, but is not limited to, the layout manner of Figure 3A, for example, the second shift register unit 105 may not include ET11 and ET12, and a transistor having the same function as ET11 or ET12 may be installed at the position of the ED3 or ED4 node, and each transistor may use an N-type transistor, or may use a mixture of P-type and N-type transistors, and the port polarity of the selected type of transistor may be connected simultaneously according to the port polarity of the corresponding transistor in the embodiment of the present disclosure. The layout shown in Figure 3B is only an example, and the layout of the second shift register unit on the display substrate can be determined according to actual needs, and the embodiment of the present disclosure is not limited thereto.

[0092] For example, as shown in FIG. 1, the second scan driving circuit 22 includes m cascaded first shift register units 221 (for example, represented by the block 221 filled by the lower diagonal of the dashed frame 22 in FIG. 1) and n cascaded additional shift register units 222 (for example, represented by the block 222 filled by the horizontal line of the dashed frame 22 in FIG. 1), for example, m is an integer greater than 1, n is an integer greater than 0, m is greater than n, and n is an integer greater than 1 and less than 10. Each first shift register unit 221 is used to drive one or more rows of pixel units 11, and each additional shift register unit 222 is used to drive one or more rows of pixel units 11. The embodiment of the present disclosure is described as an example in which each first shift register unit 221 is used to drive one row of pixel units 11, and each additional shift register unit 222 drives one row of pixel units 11, but the embodiment of the present disclosure is not limited thereto. The n additional shift register units 222 are cascaded to the m first shift register units 221 .

[0093] For example, the n additional shift register units 222 are respectively connected to the n second gate scanning signal lines RT1 to RTn corresponding to the pixel units in the previous n rows via the n second connection wirings 40, and provide the first reset control signals to the first reset sub-circuits in the pixel units in the previous n rows. The j-th additional shift register unit 222 is connected to the j-th second gate scanning signal line RTj via the j-th second connection wiring 40, and the j-th second gate scanning signal line RTj is connected to the pixel unit in the j-th row. j is an integer between 1 and n.

[0094] For example, in some examples, the second scan driving circuit 22 may include four additional shift register units 222, which are respectively connected to the second gate scanning signal lines RT1 to RT4 of the pixel units in the previous four rows via four second connection wirings 40, and further connected to the first reset sub-circuits (or first reset transistors BT1) of the pixel units in the previous four rows. That is, the first additional shift register unit 222 is connected to the second gate scanning signal line RT1 of the pixel units in the first row via one second connection wiring 40, and further connected to the first reset sub-circuit of the pixel units in the first row to provide a first reset control signal to the first reset sub-circuit. The second additional shift register unit 222 and the third additional shift register unit 222, etc. are similar.

[0095] It should be noted that the embodiment of the present disclosure relates to the cascade connection relationship of the first shift register unit, and is not limited to four additional shift register units, which can be determined according to specific circumstances, and the embodiment of the present disclosure does not limit the same.

[0096] For example, a plurality (mn) of first shift register units 221 located behind the n additional shift register units 222 are respectively connected to the (n+1)th second gate scanning signal line to the mth second gate scanning signal line (RTn+1 to RTm) via a plurality (mn) of second connection wirings 40, and the m first shift register units 221 are respectively connected to the 1st third gate scanning signal line to the mth third gate scanning signal line (GN1 to GNm) via m third connection wirings 50.

[0097] For example, the i-th first shift register unit 221 is connected to the i-th third gate scanning signal line GNi via the i-th third connection wiring 50, and the i-th third gate scanning signal line GNi is connected to the threshold compensation sub-circuit of the pixel unit in the i-th row. The i-th first shift register unit is further connected to the i+n-th second gate scanning signal line RTi+n via the i+n-th second connection wiring 40, and the i+n-th second gate scanning signal line RTi+n is connected to the first reset sub-circuit of the pixel unit in the i+n-th row, where both i and n are integers greater than 0.

[0098] For example, when the second scan driving circuit 22 may include four additional shift register units 222 (i.e., n is equal to 4), the first first shift register unit 221 may be connected to the first third gate scanning signal line GN1 through one third connection wiring 50, and further connected to the threshold compensation sub-circuit of the pixel unit in the first row. And the first first shift register unit 221 may be connected to the fifth second gate scanning signal line RT5 through one second connection wiring 40, and further connected to the first reset sub-circuit of the pixel unit in the fifth row. Both the second connection wiring 40 and the third connection wiring 50 are connected to the output terminal of the first shift register unit 221. The remaining first shift register units 221 are similar. In this way, the output signal of each first shift register unit 221 can drive the pixel units in one or more lower rows to reset, and drive the pixel units in the same row to perform threshold compensation.

[0099] For example, the peripheral region further includes a second voltage signal line GNvgh (not shown in FIG. 1) and a fourth voltage signal line GNvgl (not shown in FIG. 1), where the second voltage signal line GNvgh is configured to provide a second voltage, and the fourth voltage signal line GNvgl is configured to provide a fourth voltage, where the fourth voltage is smaller than the second voltage. The second scan driving circuit 22 is connected to the second voltage signal line GNvgh to output a second voltage as a first portion of a first reset control signal, for example, the second voltage signal line GNvgh is connected to a plurality of first shift register units 221 in the second scan driving circuit 22. The first portion of the first reset control signal is, for example, a high level portion of the first reset control signal, for example, the high level portion of the first reset control signal can turn on the first reset transistor BT1 in the reset stage. The second scan driving circuit 22 is further connected to a fourth voltage signal line GNvgl to output a fourth voltage as the second part of the first reset control signal, for example, the fourth voltage signal line GNvgl is all connected to a plurality of first shift register units 221 in the second scan driving circuit 22. The second part of the first reset control signal is, for example, a low level part of the first reset control signal, for example, the low level part of the first reset control signal can turn off the first reset transistor BT1 in the non-reset stage.

[0100] Fig. 4A is a circuit diagram of a first shift register unit according to at least one embodiment of the present disclosure. Fig. 4B is a schematic diagram of a partial signal line in the layout on the display substrate of the first shift register unit shown in Fig. 4A. Hereinafter, the first shift register unit will be briefly described with reference to Fig. 4A and Fig. 4B.

[0101] As shown in FIG. 4A and FIG. 4B, the first shift register unit 221 includes thirteen transistors (a first transistor GNT1, a second transistor GNT2, a third transistor GNT3, a fourth transistor GNT4, a fifth transistor GNT5, a sixth transistor GNT6, a seventh transistor GNT7, an eighth transistor GNT8, a ninth transistor GNT9 (also called an output transistor), a tenth transistor GNT10 (also called an output transistor), an eleventh transistor GNT11, a twelfth transistor GNT12, and a thirteenth transistor GNT13) and three capacitances (a first capacitance GNC1, a second capacitance GNC2, and a third capacitance GNC3). For example, when a plurality of first shift register units 221 are cascaded, the second pole of the first transistor GNT1 in the first-stage first shift register unit 221 is connected to the input terminal GNI, and the input terminal GNI is connected to a trigger signal line STV to receive a trigger signal as an input signal, and the trigger signal line STV is a signal line GSTVN. The second pole of the first transistor GNT1 in the first shift register unit 221 of each of the other stages is electrically connected to the output terminal of the first shift register unit 221 of the previous stage, and receives the output signal output from the output terminal EOUT of the first shift register unit 221 of the previous stage as an input signal, thereby realizing shift output, and providing a light emission control signal shifted, for example, by row, to the pixel units 11 arranged in an array in the display area 10 of the display panel.

[0102] In some embodiments, the first shift register unit 221 may include 12 transistors excluding the thirteenth transistor GNT13. In other embodiments, the first shift register unit 221 may be a 12T3C / 10T3C circuit as shown in FIG. 3A.

[0103] In addition, as shown in Figures 4A and 4B, the first shift register unit 221 further includes a first clock signal terminal GNCK and a second clock signal terminal GNCB, where GNCK further represents a first clock signal line, and GNCB further represents a second clock signal line.

[0104] For example, GNvgh represents the second voltage provided from the second voltage signal line and the second voltage signal line, and GNvgl represents the fourth voltage provided from the fourth voltage signal line and the fourth voltage signal line, where the fourth voltage is smaller than the second voltage, for example, the second voltage is a DC high level and the fourth voltage is a DC low level.

[0105] 4A and 4B, the gate of the first transistor GNT1 is connected to a first clock signal terminal GNCK (the first clock signal terminal is connected to a first clock signal line GNCK) to receive a first clock signal, the second pole of the first transistor GNT1 is connected to an input terminal GNI, and the first pole of the first transistor GNT1 is connected to a fifth node GND5. For example, when the first shift register unit is the first shift register unit of the first stage, the input terminal GNI is connected to a trigger signal line GSTVN to receive a trigger signal, and when the first shift register unit is the first shift register unit of each stage other than the first shift register unit of the first stage, the input terminal GNI is connected to an output terminal GNOUT of the first shift register unit of the previous stage.

[0106] The gate of the second transistor GNT2 is connected to the fifth node GND5, the first electrode of the second transistor GNT2 is connected to the second node GND2, and the second electrode of the second transistor GNT2 is connected to the first clock signal terminal GNCK to receive the first clock signal.

[0107] The gate of the third transistor GNT3 is connected to the first clock signal terminal GNCK to receive the first clock signal, the first electrode of the third transistor GNT3 is connected to the second node GND2, and the second electrode of the third transistor GNT3 is connected to the fourth voltage signal line GNvgl to receive the fourth voltage.

[0108] The gate of the fourth transistor GNT4 is connected to the first node GND1, the first electrode of the fourth transistor GNT4 is connected to the second clock signal terminal GNCB (e.g., the second clock signal terminal GNCB is connected to the second clock signal line GNCB) to receive the second clock signal, the second electrode of the fourth transistor GNT4 is connected to the seventh node GND7, and the second electrode of the fourth transistor GNT4 is connected to the second electrode of the fifth transistor GNT5.

[0109] The gate of the fifth transistor GNT5 is connected to the second node GND2, and the first electrode of the fifth transistor GNT5 is connected to the second voltage signal line GNvgh to receive the second voltage.

[0110] The gate of the sixth transistor GNT6 is connected to the sixth node GND6, the first electrode of the sixth transistor GNT6 is connected to the third node GND3, the second electrode of the sixth transistor GNT6 is connected to the second clock signal terminal GNCB to receive the second clock signal, and the first electrode of the sixth transistor GNT6 is connected to the first electrode of the seventh transistor GNT7.

[0111] The gate of the seventh transistor GNT7 is connected to the second clock signal terminal GNCB to receive the second clock signal, the first electrode of the seventh transistor GNT7 is connected to the third node GND3, and the second electrode of the seventh transistor GNT7 is connected to the fourth node GND4.

[0112] The gate of the eighth transistor GNT8 is connected to the first node GND1, the first electrode of the eighth transistor GNT8 is connected to the fourth node GND4, and the second electrode of the eighth transistor GNT8 is connected to the second voltage signal line GNvgh to receive the second voltage.

[0113] The gate of the ninth transistor GNT9 is connected to the fourth node GND4, the first electrode of the ninth transistor GNT9 is connected to the second voltage signal line GNvgh to receive the second voltage, and the second electrode of the ninth transistor GNT9 is connected to the output terminal GNOUT.

[0114] The gate of the tenth transistor GNT10 is connected to the first node GND1, the first electrode of the tenth transistor GNT10 is connected to the fourth voltage signal line GNvgl to receive the fourth voltage, and the second electrode of the tenth transistor GNT10 is connected to the output terminal GNOUT.

[0115] The gate of the 11th transistor GNT11 is connected to the fourth voltage signal line GNvgl to receive the fourth voltage, the first electrode of the 11th transistor GNT11 is connected to the second node GND2, and the second electrode of the 11th transistor GNT11 is connected to the sixth node GND6.

[0116] The gate of the twelfth transistor GNT12 is connected to the fourth voltage signal line GNvgl to receive the fourth voltage, the first electrode of the twelfth transistor GNT12 is connected to the fifth node GND5, and the second electrode of the twelfth transistor GNT12 is connected to the first node GND1.

[0117] The gate of the thirteenth transistor GNT13 is connected to the signal line NCX, the first electrode of the thirteenth transistor GNT13 is connected to the second voltage signal line GNvgh to receive the second voltage, and the second electrode of the thirteenth transistor GNT13 is connected to the first node GND1.

[0118] A first electrode of the first capacitance GNC1 is connected to the sixth node GND6, and a second electrode of the first capacitance GNC2 is connected to the third node GND3.

[0119] A first electrode of the second capacitance GNC2 is connected to the fourth node GND4, and a second electrode of the second capacitance GNC2 is connected to the second voltage signal line GNvgh to receive the fourth voltage.

[0120] A first pole of the third capacitance GNC3 is connected to the first node GND1, and a second pole of the third capacitance GNC3 is connected to the first node GND1.

[0121] The operation principle of the first shift register unit can be referred to in the art, and a detailed description thereof will be omitted here.

[0122] 4B, the signal lines GNCB, GNCK, GNvgl, GSTVN, and GNvgh may all extend along the second direction (Y-axis direction) and be arranged along the first direction (X-axis direction). Each transistor (GNT1 to GNT13) and each capacitor (GNC1 to GNC3) may be formed in an area 401, and the specific layout manner of each transistor and capacitor on the display substrate may be determined as necessary, and an existing layout in the present field may be used, and the embodiment of the present disclosure does not limit this.

[0123] The first shift register unit includes, but is not limited to, the layout scheme of FIG. 4A, and each transistor (GNT1 to GNT13) may be a P-type transistor, an N-type transistor, or a mixture of P-type and N-type transistors, and the port polarities of the selected types of transistors may be connected simultaneously according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0124] 1, the third scan driving circuit 23 includes a plurality of cascaded third shift register units 231 (e.g., represented by blocks 231 filled with small black dots in the dashed frame 23 in FIG. 1), and each of the third shift register units 231 is used to drive one or more rows of pixel units 11. The embodiment of the present disclosure is described taking as an example that each of the third shift register units 231 drives one row of pixel units 11, but the embodiment of the present disclosure is not limited thereto.

[0125] For example, the peripheral area further includes a fifth voltage signal line GPvgh and a sixth voltage signal line GPvgl (not shown in FIG. 1) connected to the third scanning driving circuit 23, where the fifth voltage signal line GPvgh is configured to provide a high-level voltage and the sixth voltage signal line GPvgl is configured to provide a low-level voltage.

[0126] FIG. 5A is a circuit diagram of a third shift register unit according to at least one embodiment of the present disclosure. FIG. 5B is a schematic diagram of a partial layout of the third shift register unit shown in FIG. 5A on a display substrate. As shown in FIG. 5A and FIG. 5B, the third shift register unit 231 includes eight transistors (first transistor GPT1, second transistor GPT2, third transistor GPT3, fourth transistor GPT4, fifth transistor GPT5, sixth transistor GPT6, seventh transistor GPT7 and eighth transistor GPT8), two capacitors (first capacitor GPC1 and second capacitor GPC2), and a number of nodes (GPD1 to GPD3).

[0127] For example, when a plurality of third shift register units 231 are cascaded, the second pole of the first transistor GPT1 in the first-stage third shift register unit 231 is connected to the input terminal GPI, and the input terminal GPI is connected to the trigger signal line GSTVP to receive a trigger signal as an input signal. The second pole of the first transistor GPT1 in each of the other stages of the third shift register units 231 is electrically connected to the output terminal of the third shift register unit 231 of the previous stage to realize a shift output by receiving an output signal output from the output terminal GPOUT of the third shift register unit 231 of the previous stage as an input signal.

[0128] For example, in some embodiments, a trigger signal line GSTVN electrically connected to the first shift register unit of the first stage, a trigger signal line ESTV electrically connected to the second shift register unit of the first stage, and a trigger signal line GSTVP electrically connected to the third shift register unit of the first stage may all be located above the second scan drive circuit, or all may be located above the first scan drive circuit, or all may be located above the third scan drive circuit, or all may be located between the first scan drive circuit and the second scan drive circuit, or all may be located between the second scan drive circuit and the third scan drive circuit, or both of the two trigger signal lines are located between the first scan drive circuit and the second scan drive circuit, or both of the two trigger signal lines are located between the second scan drive circuit and the third scan drive circuit.

[0129] In addition, as shown in Figures 5A and 5B, the third shift register unit 231 further includes a first clock signal terminal GPCK and a second clock signal terminal GPCB, where GPCK further represents the first clock signal line, and GPCB further represents the second clock signal line.

[0130] For example, GPvgh represents a fifth voltage provided from the fifth voltage signal line and the fifth voltage signal line, GPvgl represents a sixth voltage provided from the sixth voltage signal line and the sixth voltage signal line, the sixth voltage being smaller than the fifth voltage, for example, the fifth voltage is a DC high level and the sixth voltage is a DC low level.

[0131] The operation principle of the first shift register unit can be referred to in the art, and a detailed description thereof will be omitted here.

[0132] 5B, the signal lines GPCB, GPCK, GPvgl, and GPvgh can all extend along the second direction (Y-axis direction) and be arranged along the first direction (X-axis direction). Each transistor (GPT1 to GPT8) and each capacitor (GPC1 to GPC2) can be formed in an area 501, and the specific layout manner of each transistor on the display substrate can be determined as needed, and an existing layout in the present field can be used, and the embodiment of the present disclosure does not limit this.

[0133] The third shift register unit includes, but is not limited to, the layout scheme of FIG. 5A, and each transistor (GPT1 to GPT8) may be a P-type transistor, an N-type transistor, or a mixture of P-type and N-type transistors, and the port polarities of the selected types of transistors may be connected simultaneously according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0134] The transistors used in the first shift register unit, the second shift register unit, and the third shift register unit may be thin film transistors, or field effect transistors, or other switching devices having the same characteristics. Here, thin film transistors are used as an example. For example, the active layer (channel region) of the transistor may be made of a semiconductor material such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, or indium gallium tin oxide (IGZO), and the gate, source, drain, etc. may be made of a metal material such as metal aluminum or an aluminum alloy. The source and drain of the transistor used here may be structurally symmetrical, so that the source and drain may not be structurally distinct. In the embodiment of the present disclosure, in order to distinguish between the two poles excluding the gate of the transistor, it is directly described that one of the poles is a first pole and the other pole is a second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitance may be made of a metal electrode, or one of the electrodes may be made of a semiconductor material (e.g., doped polycrystalline silicon).

[0135] Fig. 6 is a timing diagram of the light emission control signal and the first reset control signal according to at least one embodiment of the present disclosure. EM in Fig. 6 represents the light emission control signal, and as shown in Fig. 6, due to factors such as the resistance of the first connection wiring, the signal of the first voltage signal line Evgh and the signal of the third voltage signal line Evgl are delayed in the process of transmitting to the first gate scanning line, that is, the light emission control signal is delayed, and for example, when the output signal of the first scanning driving circuit transitions between a high level and a low level, there are a rising edge 701 and a falling edge 702 in the light emission control signal. The duration t1 of the rising edge 701 represents the delay time for transmitting the signal of the first voltage signal line Evgh to the first gate scanning line when the first scanning drive circuit transitions from outputting the voltage of the third voltage signal line Evgl to outputting the voltage of the first voltage signal line Evgh (i.e., when transitioning from the third voltage (low level) to the first voltage (high level)), and the duration t2 of the falling edge 702 represents the delay time for transmitting the signal of the third voltage signal line Evgl to the first gate scanning line when the first scanning drive circuit transitions from outputting the voltage of the first voltage signal line Evgh to outputting the voltage of the third voltage signal line Evgl (i.e., when transitioning from high level to low level).

[0136] For example, Re in Figure 6 represents the first reset signal, and as shown in Figure 6, due to factors such as the resistance of the second connecting wiring, the signal is delayed in the process of transmitting the signals of the second voltage signal line GNvgh and the fourth voltage signal line GNvgl to the second gate scanning line, i.e., the first reset control signal is delayed, and for example, when the output signal of the second scanning driving circuit transitions between a high level and a low level, the first reset control signal has a rising edge 703 and a falling edge 704. The duration t3 of the rising edge 703 represents the delay time for transmitting the signal of the second voltage signal line GNvgh to the second gate scanning line when the second scanning drive circuit transitions from outputting the voltage of the fourth voltage signal line GNvgl to outputting the voltage of the second voltage signal line GNvgh (i.e., when transitioning from the fourth voltage (low level) to the second voltage (high level)), and the duration t4 of the falling edge 704 represents the delay time for transmitting the signal of the fourth voltage signal line GNvgl to the second gate scanning line when the second scanning drive circuit transitions from outputting the voltage of the second voltage signal line GNvgh to outputting the voltage of the fourth voltage signal line GNvgl (i.e., when transitioning from high level to low level).

[0137] For example, factors that affect the delay time of a voltage signal line include not only the resistance of the connection wiring but also the line width of the voltage signal line itself (the line width described in the embodiments of the present disclosure can be understood as the average line width). For example, when the line width of the voltage signal line itself is increased, the resistance of the voltage signal line itself is reduced, the voltage transmission of the voltage signal line becomes smoother, and the delay time is shortened.

[0138] For example, factors affecting the delay time of the first voltage signal line Evgh include not only the resistance of the first connection wiring but also the line width of the first voltage signal line Evgh itself. The delay time of the first voltage signal line Evgh becomes longer as the resistance of the first connection wiring increases, and becomes shorter as the line width of the first voltage signal line Evgh increases. That is, the greater the resistance of the first connection wiring, the longer the delay time of the first voltage, and the greater the line width of the first voltage signal line Evgh, the shorter the delay time of the first voltage. The same is true for the third voltage signal line Evgl, and the greater the resistance of the first connection wiring, the longer the delay time of the third voltage, and the greater the line width of the third voltage signal line Evgl, the shorter the delay time of the third voltage.

[0139] For example, factors affecting the delay time of the second voltage signal line GNvgh include not only the resistance of the second connection wiring but also the line width of the second voltage signal line GNvgh itself. The delay time of the second voltage signal line GNvgh becomes longer as the resistance of the second connection wiring increases, and becomes shorter as the line width of the second voltage signal line GNvgh increases. That is, the greater the resistance of the second connection wiring, the longer the delay time of the second voltage, and the greater the line width of the second voltage signal line GNvgh, the shorter the delay time of the second voltage. The same is true for the fourth voltage signal line GNvgl, where the greater the resistance of the second connection wiring, the longer the delay time of the fourth voltage, and the greater the line width of the fourth voltage signal line GNvgl, the shorter the delay time of the fourth voltage.

[0140] For example, by adjusting the line width of the voltage signal line (e.g., the first voltage signal line) connected to the first scanning drive circuit and the line width of the voltage signal line (e.g., the second voltage signal line) connected to the second scanning drive circuit, it is possible to balance the effects of delay time due to the resistance of the first connecting wiring and the resistance of the second voltage signal line, and further reduce the difference in signal delay time due to the difference in resistance of the first connecting wiring and the second connecting wiring.

[0141] In addition, when there are multiple first voltage signal lines, second voltage signal lines, third voltage signal lines, and fourth voltage signal lines, the average line width of the first voltage signal lines may refer to the average line width of the first voltage signal lines electrically connected to the output transistors of the second shift register unit included in the first scan drive circuit, the average line width of the third voltage signal lines may refer to the average line width of the third voltage signal lines electrically connected to the output transistors of the second shift register unit included in the first scan drive circuit, the average line width of the second voltage signal lines may refer to the average line width of the second voltage signal lines electrically connected to the output transistors of the first shift register unit included in the second scan drive circuit, and the average line width of the fourth voltage signal lines may refer to the average line width of the fourth voltage signal lines electrically connected to the output transistors of the first shift register unit included in the second scan drive circuit.

[0142] For example, the ratio of the second resistance value R2 to the first resistance value R1 is GNvgh and the average line width W of the first voltage signal line Evgh Evgh is smaller than the ratio of

number

[0143] In this way, the difference between the duration of the rising edge of the light emission control signal and the duration of the rising edge of the first reset control signal can be at least reduced, so that the duration of the rising edge of the light emission control signal and the duration of the rising edge of the first reset control signal tend to match (i.e. the difference between the durations of the two rising edges is less than a certain threshold value).

[0144] For example, the ratio of the second resistance value R2 to the first resistance value R1 is GNvgland the average line width W of the third voltage signal line Evgl Evgl is smaller than the ratio of

number

[0145] In this way, the difference between the duration of the falling edge of the light emission control signal and the duration of the falling edge of the first reset control signal can be at least reduced, so that the duration of the falling edge of the light emission control signal and the duration of the falling edge of the first reset control signal tend to match (i.e. the difference between the durations of the two falling edges is less than a certain threshold value).

[0146] For example, the first resistance value R1 of the first connection wiring 30 is smaller than the second resistance value R2 of the second connection wiring 40, and the first resistance value R1 of the first connection wiring 30 is larger than the third resistance value R3 of the third connection wiring 50. Since the third scanning drive circuit is closest to the pixel region, the fourth resistance value R4 of the fourth connection wiring 60 is small, and the fourth resistance value R4 is smaller than the third resistance value R3.

[0147] For example, in some examples, the first resistance value R1, the second resistance value R2, and the third resistance value R3 may satisfy the relationships shown in the following equations (3) and (4).

number

[0148] For example, in some other examples, the first resistance value R1, the second resistance value R2, and the third resistance value R3 can further satisfy the relationships shown in the following equations (5) and (6).

number

[0149] For example, the first resistance value R1 and the third resistance value R3 can further satisfy the following relationship:

number

[0150] For example, the line width ranges of the first voltage signal line Evgh and the third voltage signal line Evgl of the first scanning driving circuit EMGOA, the line width ranges of the second voltage signal line GNvgh and the fourth voltage signal line GNvgl of the second scanning driving circuit Gate GOA N, and the line width ranges of the fifth voltage signal line GPvgh and the sixth voltage signal line GPvgl of the third scanning driving circuit Gate GOA P can be shown in Table 1 below.

[0151] [Table 1]

[0152] For example, from Table 1, 3≦W GNvgh / W Evgh ≦9.4, and combine this with the above formula (3) or (5) to obtain R2 / R1≦W GNvgh / W Evgh Based on the range of values ​​in Table 1, the delay times of the rising edge of the light emission control signal and the rising edge of the first reset control signal can be substantially matched.

[0153] For example, the average line width of the first voltage signal line and the average line width of the second voltage signal line satisfy the following relationship:

number

[0154] Based on the above formula (8), by further limiting the numerical relationship between the resistance of the first connecting wiring, the resistance of the second connecting wiring, and the resistance of the third connecting wiring and the line width of the first voltage signal line and the line width of the second voltage signal line, the line width of the first voltage signal line and the line width of the second voltage signal line can be accurately controlled, so that the line width of the first voltage signal line and the line width of the second voltage signal line can more accurately balance the difference in the resistance of each connecting wiring, and further reduce the difference in the duration of the signal rising edge.

[0155] For example, in some examples, the value range of the constant a in equation (8) may be further limited to 0.6≦a≦3. By narrowing the value range of the constant a, the line width of the first voltage signal line and the line width of the second voltage signal line can be more precisely controlled.

[0156] For example, the average line width of the fourth voltage signal line and the average line width of the third voltage signal line can satisfy the following relationship:

number

[0157] Based on the above formula (9), by further limiting the numerical relationship between the resistance of the first connecting wiring, the resistance of the second connecting wiring, and the resistance of the third connecting wiring and the line width of the third voltage signal line and the line width of the fourth voltage signal line, the line width of the third voltage signal line and the line width of the fourth voltage signal line can be accurately controlled, so that the line width of the third voltage signal line and the line width of the fourth voltage signal line can more accurately balance the difference in the resistance of each connecting wiring, and further reduce the difference in the duration of the signal falling edges.

[0158] For example, in some examples, the value range of the constant b in formula (9) may be further limited to 1.5≦b≦3.5. By narrowing the value range of the constant b, the line width of the third voltage signal line and the line width of the fourth voltage signal line can be more precisely controlled.

[0159] 7 is a schematic plan view of a partial region of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG 7, for example, the display region includes a first display sub-region 101 and a second display sub-region 102, the number of pixel units 11 in each row in the second display sub-region 102 is equal, and the number of pixel units 11 in any row in the first display sub-region 101 is smaller than the number of pixel units in one row in the second display sub-region 102.

[0160] For example, the first display sub-region 101 is a corner display region, corresponding to a corner of the display substrate, and the number of pixel units in each row in the first display sub-region 101 can be increased row by row. The first display sub-region 101 is a normal display region, and the number of pixel units in each row in the second display sub-region 102 is equal. The number of pixel units in each row in the first display sub-region 101 is smaller than the number of pixel units in one row in the second display sub-region 102. The peripheral region is provided with a first scan driving circuit including a second shift register unit 211, a second scan driving circuit including a first shift register unit 221, and a third scan driving circuit including a third shift register unit 231, and the peripheral region corresponds to the first display sub-region 101 and the second display sub-region 102, and the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit can drive the pixel units in the first display sub-region 101 and the second display sub-region 102.

[0161] For example, the above formulas (1) to (9) can be applied to the second display region 102 instead of the first display region 101. Alternatively, the above formulas (1) to (9) can be applied to the second display region 102 and the first display region 101.

[0162] For example, the first display sub-region 101 includes pixel units in the pth row, and the second display sub-region 102 includes pixel units in the qth row. A difference between the resistance value of the first connection wiring 30 connected to the pixel units in the pth row and the resistance value of the first connection wiring 30 connected to the pixel units in the qth row is a fifth resistance value R5. A difference between the resistance value of the third connection wiring 50 connected to the pixel units in the pth row and the resistance value of the third connection wiring 50 connected to the pixel units in the qth row is a sixth resistance value R6. A difference between the resistance value of the fourth connection wiring 60 connected to the pixel units in the pth row and the resistance value of the fourth connection wiring 60 connected to the pixel units in the qth row is a seventh resistance value R7. The fifth resistance value, the sixth resistance value, and the seventh resistance value all increase as the number of missing pixel units in the pth row increases relative to the pixel units in the qth row, where p is an integer greater than 0 and q is an integer greater than p.

[0163] For example, taking p=1 and q=10 as an example, the pixel units in the first row are located in the first display sub-region 101, and the pixel units in the tenth row are located in the second display sub-region 102. The distance between the pixel unit in the first row that is closest to the peripheral region and each scan driving circuit is greater than the distance between the pixel unit in the tenth row that is closest to the peripheral region and each scan driving circuit, and therefore the length of each connection wire connected to the pixel unit in the first row is also greater than the length of each connection wire connected to the pixel unit in the tenth row. For example, the resistance of the first connection wire 30 connected to the pixel unit in the tenth row is a first resistance value R1, and the resistance of the first connection wire 30 connected to the pixel unit in the first row is greater than the first resistance value R1 by a fifth resistance value R5, and the greater the number of missing pixel units in the first row compared to the pixel unit in the tenth row, the greater the fifth resistance value R5. For example, the resistance of the third connection wiring 50 connected to the pixel unit in the tenth row is the third resistance value R3, the resistance of the third connection wiring 50 connected to the pixel unit in the first row is greater than the third resistance value R3 by a sixth resistance value R6, and the sixth resistance value R6 increases as the number of pixel units missing from the pixel unit in the first row increases relative to the pixel unit in the tenth row. For example, the resistance of the fourth connection wiring 60 connected to the pixel unit in the tenth row is the fourth resistance value R4, the resistance of the fourth connection wiring 60 connected to the pixel unit in the first row is greater than the fourth resistance value R4 by a seventh resistance value R7, and the seventh resistance value R7 increases as the number of pixel units missing from the pixel unit in the first row increases relative to the pixel unit in the tenth row.

[0164] For example, the fifth resistance value, the sixth resistance value, and the seventh resistance value satisfy the following relationship:

number

[0165] For example, according to the above formulas (10), (11) and (12), a theoretical resistance difference between each connecting wire in the corner region and the corresponding connecting wire in the normal display region is determined according to parameters such as the missing subpixels in each row of the corner region, the size of the subpixels, and the resistivity of the connecting wire. When the connecting wires in the corner region and the normal display region satisfy the theoretical resistance difference, the pixel units in the corner region can have the same delay time as the pixel units in the relative positions (e.g., located in the same column) of each row in the normal display region when receiving a signal. For example, the first pixel unit in the third row in the corner region is located in the same column as the fifth pixel unit in each row in the normal display region, and according to the above formulas (10), (11) and (12), the first pixel unit in the third row has the same delay time as the fifth pixel unit in each row in the normal display region when receiving a signal, and the difference in signal delay time caused by the corner can be reduced.

[0166] 8 is a schematic plan view of a partial region of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1 and FIG. 8, the first connection wiring 30 includes at least two first transfer electrodes 31 and a plurality of first connection electrodes 32, the at least two first transfer electrodes 31 are located in a layer different from the plurality of first connection electrodes 32, the plurality of first connection electrodes 32 are connected to the at least two first transfer electrodes 31 through vias penetrating an insulating layer, respectively, to form the first connection wiring 30, and the resistivity of each first transfer electrode 31 is smaller than the resistivity of each first connection electrode 32. The third connection wiring 50 includes at least one second transfer electrode 51 and a plurality of second connection electrodes 52, the at least one second transfer electrode 51 is located in a layer different from the plurality of second connection electrodes 52, the plurality of second connection electrodes 52 are connected to the at least one second transfer electrode 51 through vias penetrating an insulating layer, respectively, to form the third connection wiring 50, and the resistivity of each second transfer electrode 51 is smaller than the resistivity of each second connection electrode 52. The number of first transfer electrodes 31 is greater than the number of second transfer electrodes 51. Because the transfer electrodes are located on a different layer than the connection electrodes, the transfer electrodes may be referred to as an interlayer structure.

[0167] For example, both the first scan driving circuit and the second scan driving circuit include layer structures such as a semiconductor layer (Poly layer), a first insulating layer, a first conductive layer (Gate1 layer), a second insulating layer, a second conductive layer (Gate2 layer), a third insulating layer, and a third conductive layer (SD1 layer) that are sequentially formed in a direction perpendicular to the base substrate. The first connection electrode 32 may be located in the first conductive layer (or the second conductive layer), and the first transfer electrode 31 may be located in the third conductive layer, and the first connection electrode 32 and the first transfer electrode 31 may be connected through a via that penetrates the third insulating layer (or penetrates the third insulating layer and the second insulating layer). The multiple first connection electrodes 32 and the at least two first transfer electrodes 31 all extend along a first direction (X-axis direction) and can be sequentially arranged along the first direction, with each first transfer electrode 31 being inserted between two first connection electrodes 32, and adjacent first connection electrodes 32 and first transfer electrodes 31 being jumper-connected end-to-end in sequence to form the first connection wiring 30. The second connection electrode 52 can be located on the first conductive layer (or the second conductive layer), and the second transfer electrode 51 can be located on the third conductive layer, and the second connection electrode 52 and the second transfer electrode 51 can be connected through a via penetrating the third insulating layer (or penetrating the third insulating layer and the second insulating layer). The multiple second connection electrodes 52 and the at least one second transfer electrode 51 all extend along a first direction (X-axis direction) and can be arranged sequentially along the first direction, with each second transfer electrode 51 being inserted between two second connection electrodes 52, and adjacent second connection electrodes 52 and second transfer electrodes 51 being jumper-connected sequentially from end to end to form a third connection wiring 50.

[0168] For example, since the resistivity of the material of the first transfer electrode 31 is smaller than that of the material of the first connection electrode 32, the resistance of the first connection wiring 30 can be reduced by providing at least two first transfer electrodes 31 on the first connection wiring 30, and the resistance of the first connection wiring 30 can be adjusted by designing the number, size, etc. of the first transfer electrodes 31. Since the resistivity of the material of the second transfer electrode 51 is smaller than that of the material of the second connection electrode 52, the resistance of the third connection wiring 50 can be reduced by providing at least one second transfer electrode 51 on the third connection wiring 50, and the resistance of the third connection wiring 50 can be adjusted by designing the number, size, etc. of the second transfer electrodes 51. The number of the first transfer electrodes 31 is larger than the number of the second transfer electrodes 51, and thereby the resistance difference between the first connection wiring 30 and the third connection wiring 50 can be reduced.

[0169] For example, the distance between two adjacent first transfer electrodes 31 satisfies the following relationship:

number

[0170] In this manner, the distance between two adjacent first transfer electrodes 31 can be accurately set using equation (13), and the static electricity and resistance generated by the long first connection wiring can be balanced.

[0171] For example, the distance between the two connection terminals of each of the first transfer electrodes 31 satisfies the following relationship:

number

[0172] For example, the distance between the two connection terminals of each second transfer electrode 51 satisfies the following relationship:

number

[0173] For example, based on equations (14) and (15), by adjusting the size of the inter-layer structure based on the size of the scan drive circuit, the difference in delay due to different scan drive circuit sizes can be reduced or eliminated.

[0174] 1 and 8, for example, the second connection wiring 40 includes at least one third transfer electrode 41 extending along a second direction (Y-axis direction) different from the first direction, and a plurality of third connection electrodes 42 extending along the second direction, where the at least one third transfer electrode 41 is located in a layer different from the plurality of third connection electrodes 42, and the plurality of third connection electrodes 42 are each connected to the at least one third transfer electrode 41 through a via that penetrates an insulating layer to form the second connection wiring 40. The resistivity of the third transfer electrode 41 is smaller than the resistivity of the third connection electrode 42.

[0175] For example, the third connection electrode 42 may be located on the first conductive layer (or the second conductive layer), the third transfer electrode 41 may be located on the third conductive layer, and the third connection electrode 42 and the third transfer electrode 41 may be connected through a via penetrating the third insulating layer (or penetrating the third insulating layer and the second insulating layer). The multiple third connection electrodes 42 and at least one third transfer electrode 41 may all extend along the second direction and be sequentially arranged along the second direction, with each third transfer electrode 41 being inserted between two third connection electrodes 42, and adjacent third connection electrodes 42 and third transfer electrodes 41 being jumper-connected in sequence from end to end to form the second connection wiring 40.

[0176] For example, since the resistivity of the material of the third transfer electrode 41 is smaller than the resistivity of the material of the third connection electrode 42, the resistance of the second connection wiring 40 can be reduced by placing at least one third transfer electrode 41 on the second connection wiring 40, and the resistance of the second connection wiring 40 can be adjusted by designing the number and size of the third transfer electrodes 41, etc.

[0177] For example, the distance between two adjacent third transfer electrodes 41 satisfies the following relationship:

number

[0178] According to formula (16), the distance between two adjacent third transfer electrodes 41 can be accurately set to reduce the resistance and the crosstalk with other signal lines introduced into the display area.

[0179] 9 is a schematic diagram of a partial layout of the peripheral region according to at least one embodiment of the present disclosure. As shown in FIG. 9, for example, the first transfer electrodes 31 and the first signal lines of the second scan driving circuit 22 at least partially overlap in a direction perpendicular to the base substrate.

[0180] For example, the first signal line may be a clock signal line (GNCB or GNCK) or a trigger signal line (STV signal line such as ESTV, GSTVN or GSTVP) connected to the second scan driving circuit 22. By at least partially overlapping the orthogonal projection on the base substrate of the first transfer electrode 31 of the first connection wiring and the orthogonal projection on the base substrate of the first signal line of the second scan driving circuit 22, crosstalk between the signal lines can be reduced.

[0181] For example, the second transfer electrodes 51 and the second signal lines of the third scan driving circuit 23 at least partially overlap in a direction perpendicular to the base substrate.

[0182] For example, the second signal line may be a clock signal line (GPCB or GPCK) or a trigger signal line (GSTVP) connected to the third scanning drive circuit 23. By at least partially overlapping the orthogonal projection on the base substrate of the second transfer electrode 51 of the third connection wiring and the orthogonal projection on the base substrate of the second signal line of the third scanning drive circuit 23, crosstalk between the signal lines can be reduced.

[0183] For example, the pixel unit of the display area includes a light-emitting element, the light-emitting element including a first electrode layer, a second electrode layer located on a side of the first electrode layer away from the base substrate, and a light-emitting layer located between the first electrode layer and the second electrode layer. The display area further includes a pixel definition layer, the pixel definition layer including an opening, the opening of the pixel definition layer configured to define a light-emitting area of ​​the pixel unit of the display area. For example, the first electrode layer is an anode layer, the second electrode layer is a cathode layer, and the light-emitting layer is located in the opening of the pixel definition layer.

[0184] Fig. 10 is a cross-sectional view of some examples along the A-A' direction of the peripheral region 20 shown in Fig. 7. As shown in Fig. 10, for example, the peripheral region 20 includes a base substrate 801, and a first scan drive circuit 21, a second scan drive circuit 22, and a third scan drive circuit 23 formed on the base substrate, and the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 may include a plurality of layer structures, for example, layer structures such as a semiconductor layer (Poly layer), a first insulating layer, a first conductive layer (Gate1 layer), a second insulating layer, a second conductive layer (Gate2 layer), a third insulating layer, and a third conductive layer (SD1 layer) formed in sequence in a direction perpendicular to the base substrate. For example, the multiple layer structures included in the first scan drive circuit 21, the second scan drive circuit 22 and the third scan drive circuit 23 may further include a fourth conductive layer (Gate3 layer) located between the second conductive layer (Gate2 layer) and the third conductive layer (SD1 layer), and may further include a fifth conductive layer (SD2 layer) located on the side of the third conductive layer (SD1 layer) away from the base substrate.

[0185] For example, each signal line in the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 may be formed on the first conductive layer to the fifth conductive layer, the source and drain of each transistor in the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 may be formed on the third conductive layer, the scan signal lines and connection lines in the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 may be formed on the first conductive layer, the second conductive layer, or the fourth conductive layer, and each clock signal line in the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 may be formed on the third conductive layer or the fifth conductive layer. The first portion 802 of the second voltage line VSS connected to the second terminal of the light-emitting element may be formed on the third conductive layer. The peripheral region 20 further includes a fourth insulating layer 803 formed on the side of the scan driving circuits (first scan driving circuit 21, second scan driving circuit 22, and third scan driving circuit 23) facing away from the base substrate 801, a second portion 804 of the second voltage line VSS formed on the side of the fourth insulating layer 803 facing away from the base substrate 801, a fifth insulating layer 805 formed on the side of the second portion 804 of the second voltage line VSS facing away from the base substrate 801, a first auxiliary electrode layer 806 formed on the side of the fifth insulating layer 805 facing away from the base substrate 801, an auxiliary insulating layer 807 formed on the side of the first auxiliary electrode layer 806 facing away from the base substrate 801, and a second auxiliary electrode layer 808 formed on the side of the auxiliary insulating layer 807 facing away from the base substrate 801.

[0186] For example, the first auxiliary electrode layer 806 is disposed in the same layer as the first electrode layer (i.e., anode layer) of the light-emitting element included in the pixel unit in the display area, and for example, the material of the first auxiliary electrode layer 806 may be the same as the material of the first electrode layer. The auxiliary insulating layer 807 is disposed in the same layer as the pixel definition layer located in the display area, and for example, the material of the auxiliary insulating layer 807 may be the same as the material of the pixel definition layer, and the auxiliary insulating layer 807 and the pixel definition layer may be integrally formed. The second auxiliary electrode layer 808 is disposed in the same layer as the second electrode layer (i.e., cathode layer) located in the display area, and for example, the material of the second auxiliary electrode layer 808 may be the same as the material of the second electrode layer, and the second auxiliary electrode layer 808 and the second electrode layer may be integrally formed.

[0187] For example, the base substrate 10 can be made of, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure are not limited thereto.

[0188] For example, the material of the semiconductor layer may include an oxide semiconductor, an organic semiconductor, or amorphous silicon, polycrystalline silicon, etc., and for example, the oxide semiconductor may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon may include low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited thereto. The source and drain may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited thereto.

[0189] For example, the material of the third conductive layer may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, and the embodiments of the present disclosure are not limited thereto. For example, the material of the first conductive layer and the second conductive layer may be the same as the material of the third conductive layer, and detailed description is omitted here.

[0190] For example, the materials of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the auxiliary insulating layer may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or other suitable materials, and the embodiments of the present disclosure are not limited thereto.

[0191] For example, the first electrode layer (anode layer) and the second electrode layer (cathode layer) of the light-emitting element may be made of a material including a transparent metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and have high light transmittance. The material of the anode layer and the cathode layer of the light-emitting element is a metal, for example, the metal may be a material such as magnesium, magnesium alloy, aluminum or aluminum alloy. The material of the first auxiliary electrode layer is the same as the material of the first electrode layer, and the material of the second auxiliary electrode layer is the same as the material of the second electrode layer.

[0192] For example, the first auxiliary electrode layer 806 is located on the side of the first scan driving circuit 21 away from the base substrate, and an electrode exhaust hole is provided in the first auxiliary electrode layer 806. At least one end of the first transfer electrode 31 and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate, and / or at least one end of the second transfer electrode 51 and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate.

[0193] For example, the auxiliary insulating layer has at least one opening, and the opening size B of the auxiliary insulating layer satisfies the following relationship:

number

[0194] According to Equation (17), the peripheral area can be utilized rationally to realize effective contact between the cathode layer and the second voltage line VSS.

[0195] For example, at least one of the first scan drive circuit 21, the second scan drive circuit 22, and the third scan drive circuit 23 and at least one opening of the auxiliary insulating layer 807 at least partially overlap in a direction perpendicular to the base substrate.

[0196] For example, the second voltage signal line GNvgh is provided with a plurality of signal line exhaust holes. In one example, the size of each signal line exhaust hole satisfies the following relationship:

number

[0197] For example, in another example, the size of the signal line exhaust hole satisfies the following relationship:

number

[0198] For example, each first shift register unit 221 includes a first switching transistor, the difference between the distance between two adjacent signal line exhaust holes and the channel size of the first switching transistor is smaller than a predetermined threshold, and the connection via between the first voltage signal line and the first pole of the second capacitance is located between the two adjacent signal line exhaust holes or at least partially overlaps with the signal line exhaust hole.

[0199] For example, the first switching transistor may be any one of the transistors GNT1 to GNT13 in the first shift register unit 221. The channel aspect ratios of the transistors GNT2 to GNT13 in the first shift register unit 221 are shown in, for example, Table 2 below, and the units of width and length are, for example, μm (microns).

[0200] [Table 2]

[0201] For example, the first switching transistor may be one of the transistors GNT2 to GNT13 having a width of approximately 3.5 μm, and the first switching transistor is, for example, one of the transistors GNT2, GNT3, GNT4, GNT6, GNT7, GNT8, and GNT13.

[0202] 11A is a schematic plan view of another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 11A, in addition to the first scan driving circuit (EMGOA) 21, the second scan driving circuit (GN) 22, and the third scan driving circuit (GP) 23, the peripheral area may further include a fourth scan driving circuit (GN2) 24, and the fourth scan driving circuit 24 can be used to drive, for example, an N-type transistor.

[0203] For example, the display area further includes a plurality of fifth gate scanning signal lines respectively connected to the second reset sub-circuits (BT7 shown in FIG. 2) of the pixel units of the plurality of rows. The fourth scanning driving circuit is respectively connected to the plurality of fifth gate scanning signal lines via a plurality of fifth connecting wires 91 to respectively provide second reset control signals to the second reset sub-circuits of the pixel units of the plurality of rows.

[0204] For example, as shown in FIG. 11A, the first scanning drive circuit 21 is connected to the first emission control transistor BT5 and the second emission control transistor BT6 of each pixel unit via a plurality of first connection wirings 30 (only one is shown in the figure) and a plurality of first gate scanning signal lines Ei. The second scanning drive circuit 22 is connected to the first reset transistor BT1 of each pixel unit via a plurality of second connection wirings 40 and a plurality of second gate scanning signal lines RTi, and the second scanning drive circuit 22 is further connected to the threshold compensation transistor BT2 of each pixel unit via a plurality of third connection wirings 50 and a plurality of third gate scanning signal lines GNi. The third scanning drive circuit 23 is connected to the data write transistor BT4 of each pixel unit via a plurality of fourth connection wirings 60 and a plurality of fourth gate scanning signal lines GPi, and the fourth scanning drive circuit 24 is connected to the second reset transistor BT7 of each pixel unit via a plurality of fifth connection wirings 91 and a plurality of fifth gate scanning signal lines GNi', and in this example, the second reset transistor BT7 may be an N-type transistor. Fig. 11A shows only one of the first connection wirings 30, one of the first gate scanning signal lines Ei, one of the second connection wirings 40, etc. Fig. 11A is merely for clarifying the connection relationship and facilitating the explanation, and is not intended to limit the number of lines such as the first connection wirings and the first gate scanning signal lines, nor is it intended to limit the specific connection method of each line and transistor. The following Figs. 11B, 11C, and 11D are similar.

[0205] For example, the fourth scan drive circuit 24 is located on the side of the third scan drive circuit 23 that is farther from the display area 10, and the resistance value of each of the fifth connection wirings 91 is an eighth resistance value, which is greater than the third resistance value. The fourth scan drive circuit 24 may be located between the first scan drive circuit 21 and the third scan drive circuit 23, and the eighth resistance value is smaller than the first resistance value. The fourth scan drive circuit 24 may be located on the side of the second scan drive circuit 22 that is closer to the display area 10, or on the side of the second scan drive circuit 22 that is farther from the display area 10, and the present disclosure does not limit this.

[0206] For example, the peripheral area further includes a fifth voltage signal line and a sixth voltage signal line, the fourth scan driving circuit is connected to the fifth voltage signal line to output a fifth voltage as a first portion (e.g., a high-level portion) of the second reset control signal, and the fourth scan driving circuit is connected to the sixth voltage signal line to output a sixth voltage as a second portion (e.g., a low-level portion) of the second reset control signal. The average line width of the fifth voltage signal line is larger than the average line width of the first voltage signal line and smaller than the average line width of the third voltage signal line, and the average line width of the sixth voltage signal line is larger than the average line width of the second voltage signal line and smaller than the average line width of the fourth voltage signal line.

[0207] 11B is a schematic plan view of another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 11B, the peripheral area may further include a fifth scan driving circuit (EMGOA2) 25 in addition to the first scan driving circuit (EMGOA) 21, the second scan driving circuit (GN) 22, and the third scan driving circuit (GP) 23.

[0208] For example, the display area further includes a plurality of sixth gate scanning signal lines respectively connected to the emission control sub-circuits of the pixel units in the plurality of rows. The fifth scanning driving circuit 25 is respectively connected to the plurality of sixth gate scanning signal lines via a plurality of sixth connecting wires 92 to respectively provide emission control signals to the emission control sub-circuits of the pixel units in the plurality of rows.

[0209] For example, in some examples, the first scanning drive circuit 21 is connected to the first emission control transistor BT5 of the pixel unit via a plurality of first connection wirings 30 and a plurality of first gate scanning signal lines Ei, and the fifth scanning drive circuit 25 is connected to the second emission control transistor BT6 of the pixel unit via a plurality of sixth connection wirings 92 and a plurality of sixth gate scanning signal lines Ei'. The second scanning drive circuit 22 is connected to the first reset transistor BT1 of each pixel unit via a plurality of second connection wirings 40 and a plurality of second gate scanning signal lines RTi, and the second scanning drive circuit 22 is further connected to the threshold compensation transistor BT2 of each pixel unit via a plurality of third connection wirings 50 and a plurality of third gate scanning signal lines GNi. The third scanning drive circuit 23 is connected to the data write transistor BT4 and the second reset transistor BT7 of each pixel unit via a plurality of fourth connection wirings 60 and a plurality of fourth gate scanning signal lines GPi. In this example, the second reset transistor BT7 may be a P-type transistor.

[0210] 11C is a schematic plan view of another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 11C, the peripheral area may include a first scan driving circuit (EMGOA) 21, a second scan driving circuit (GN) 22, a third scan driving circuit (GP) 23, a fourth scan driving circuit (EMGOA) 24, and a fifth scan driving circuit (EMGOA2) 25.

[0211] For example, the first scanning drive circuit 21 is connected to the first emission control transistor BT5 of the pixel unit via a plurality of first connection wirings 30 and a plurality of first gate scanning signal lines Ei, and the fifth scanning drive circuit 25 is connected to the second emission control transistor BT6 of the pixel unit via a plurality of sixth connection wirings 92 and a plurality of sixth gate scanning signal lines Ei'. The second scanning drive circuit 22 is connected to the first reset transistor BT1 of each pixel unit via a plurality of second connection wirings 40 and a plurality of second gate scanning signal lines RTi, and the second scanning drive circuit 22 is further connected to the threshold compensation transistor BT2 of each pixel unit via a plurality of third connection wirings 50 and a plurality of third gate scanning signal lines GNi. The third scanning drive circuit 23 is connected to the data write transistor BT4 of each pixel unit via a plurality of fourth connection wirings 60 and a plurality of fourth gate scanning signal lines GPi. The fourth scanning drive circuit 24 is connected to the second reset transistor BT7 of each pixel unit via a plurality of fifth connection wirings 91 and a plurality of fifth gate scanning signal lines GNi′, and in this example, the second reset transistor BT7 may be an N-type transistor.

[0212] 11D is a schematic plan view of another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 11D, the peripheral area may include a first scan driving circuit (EMGOA) 21, a second scan driving circuit (GN) 22, a third scan driving circuit (GP) 23, a fourth scan driving circuit (EMGOA) 24, and a fifth scan driving circuit (EMGOA2) 25.

[0213] For example, in some examples, each pixel unit may further include a third emission control transistor BT8 in addition to the first emission control transistor BT5 and the second emission control transistor BT6. The first scanning drive circuit 21 is connected to the first emission control transistor BT5 and the second emission control transistor BT6 of the pixel unit via a plurality of first connection wirings 30 and a plurality of first gate scanning signal lines Ei, and the fifth scanning drive circuit 25 is connected to the third emission control transistor BT8 of the pixel unit via a plurality of sixth connection wirings 92 and a plurality of sixth gate scanning signal lines Ei'. For example, the second scanning drive circuit 22 is connected to the first reset transistor BT1 of each pixel unit via a plurality of second connection wirings 40 and a plurality of second gate scanning signal lines RTi, and the second scanning drive circuit 22 is further connected to the threshold compensation transistor BT2 of each pixel unit via a plurality of third connection wirings 50 and a plurality of third gate scanning signal lines GNi. The third scanning drive circuit 23 is connected to the data write transistor BT4 of each pixel unit via a plurality of fourth connection wirings 60 and a plurality of fourth gate scanning signal lines GPi. The fourth scanning drive circuit 24 is connected to the second reset transistor BT7 of each pixel unit via a plurality of fifth connection wirings 91 and a plurality of fifth gate scanning signal lines GNi′.

[0214] For example, the fifth scan driving circuit 25 may be located on the side away from the display area of ​​the third scan driving circuit 23, and the resistance value of each sixth connection wire is a ninth resistance value, which is greater than the third resistance value. The fifth scan driving circuit 25 may be located on the side away from the display area of ​​the first scan driving circuit 21, and the ninth resistance value is greater than the first resistance value.

[0215] For example, in some examples, the peripheral area may further include a sixth scan driving circuit, and the sixth scan driving circuit may be configured to drive a P-type transistor. The display area may further include a plurality of seventh gate scanning signal lines respectively connected to the emission control sub-circuits of the pixel units of the plurality of rows. The sixth scan driving circuit is respectively connected to the plurality of seventh gate scanning signal lines via a plurality of seventh connecting wires to respectively provide reset control signals to the second reset sub-circuits of the pixel units of the plurality of rows. In this example, the third scan driving circuit 23 is connected to the data write transistor BT4 of the pixel unit via the fourth connecting wire 60 and the fourth gate scanning signal line, and the sixth scan driving circuit is connected to the second reset transistor BT7 of the pixel unit via the seventh connecting wire and the seventh gate scanning signal line, and in this example, the second reset transistor BT7 may be a P-type transistor.

[0216] For example, when the peripheral area on the display area side includes a plurality of scanning drive circuits, the closer the distance between the scanning drive circuits and the display area is to the plurality of scanning drive circuits, the fewer the number of transfer electrodes provided on the connection wiring connected to the scanning drive circuits. The plurality of scanning drive circuits include a first scanning drive circuit and a second scanning drive circuit, and the connection wiring includes a first connection wiring and a second connection wiring.

[0217] For example, in the case where the peripheral region includes the first scan drive circuit 21, the second scan drive circuit 22, the third scan drive circuit 23, the fourth scan drive circuit 24, and the fifth scan drive circuit 25, as the third scan drive circuit 23, the second scan drive circuit 22, the fourth scan drive circuit 24, the first scan drive circuit 21, and the fifth scan drive circuit 25 are successively farther from the display region 10, the fourth connection wiring 60, the third connection wiring 50, the fifth connection wiring 91, the first connection wiring 30, and the sixth connection wiring 92 become successively longer, and the number of transfer electrodes installed on the fourth connection wiring 60, the number of transfer electrodes installed on the third connection wiring 50, the number of transfer electrodes installed on the fifth connection wiring 91, the number of transfer electrodes installed on the first connection wiring 30, and the number of transfer electrodes installed on the sixth connection wiring 92 increase successively, thereby making it possible to reduce the resistance difference between each connection wiring.

[0218] At least one embodiment of the present disclosure further provides a display panel. Fig. 12 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. As shown in Fig. 12, the display panel 1200 includes a display substrate 1 provided in any embodiment of the present disclosure, for example, the display substrate 1 shown in Fig. 1.

[0219] For example, the display panel 1200 may be a liquid crystal display panel or an organic light emitting diode (OLED) display panel, etc. For example, if the display panel 1200 is a liquid crystal display panel, the display substrate 1200 may be an array substrate or a color filter substrate. If the display panel 1200 is an organic light emitting diode display panel, the display substrate 1200 may be an array substrate.

[0220] For example, the display panel 1200 may be a rectangular panel, a circular panel, an elliptical panel, a polygonal panel, etc. Furthermore, the display panel 1200 may not only be a flat panel, but also a curved panel or even a spherical panel.

[0221] For example, the display panel 1200 may further include a touch function, that is, the display panel 1200 may be a touch display panel.

[0222] For example, the display panel 1200 can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

[0223] For example, the display panel 1200 may be a flexible display panel, so as to meet various practical application needs, for example, the display panel 1200 may be applied to a curved screen, etc.

[0224] In addition, the display panel 1200 may further include other components, such as a data driving circuit, a timing controller, etc., and the embodiments of the present disclosure are not limited thereto. For clarity and conciseness, the embodiments of the present disclosure do not show all the components of the display panel 1200. In order to achieve the basic functions of the display panel 1200, those skilled in the art can provide and install other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited thereto.

[0225] Regarding the technical effects of the display panel 1200 provided in the above embodiment, reference may be made to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, and detailed descriptions thereof will be omitted here.

[0226] Several points need to be explained:

[0227] (1) The drawings of the embodiments of the present disclosure only relate to the structures of the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0228] (2) Where no contradiction exists, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0229] The above are merely exemplary embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure, which is determined by the appended claims. [Explanation of symbols]

[0230] 1 Display board 10 Display area 11 Pixel Unit 20 Surrounding Areas 21 First scan drive circuit 22 Second scan drive circuit 23 Third scan drive circuit 24 4th scan drive circuit 25 5th scan drive circuit 30 First connecting wire 40 Second connection wire 50 Third connection wire 60 4th connecting wire 101 First display sub-area 102 Second display sub-area 211 Second shift register unit 221 1st shift register unit 222 1st, 2nd, 3rd additional shift register units 231 3rd shift register unit 801 Base Board 802 Part 1 803 4th insulating layer 804 Part 2 805 5th insulating layer 806 1st auxiliary electrode layer 807 Auxiliary Insulation Layer 808 2nd auxiliary electrode layer

Claims

1. A display substrate, a base substrate including a display area and a peripheral area located on at least one side of the display area; the display area includes pixel units arranged in an array of a plurality of rows and a plurality of columns, a plurality of first gate scanning signal lines respectively connected to light emission control sub-circuits of pixel units in a plurality of rows in the pixel units of the plurality of rows and a plurality of columns, and a plurality of second gate scanning signal lines respectively connected to first reset sub-circuits of pixel units in the plurality of rows; The peripheral region is a first scanning driving circuit connected to the plurality of first gate scanning signal lines via a plurality of first connecting wires, each having a first resistance value, and providing a light emission control signal to the light emission control sub-circuits of the plurality of rows of pixel units; a second scan driving circuit located on a side of the first scan driving circuit close to the display area, connected to the second gate scanning signal lines via second connection wirings having a second resistance value, respectively, to provide first reset control signals to the first reset sub-circuits of the pixel units of the rows; a first voltage signal line configured to provide a first voltage; a second voltage signal line configured to provide a second voltage; the first scan driving circuit is connected to the first voltage signal line and outputs the first voltage as a first portion of the light emission control signal; the second scan driving circuit is connected to the second voltage signal line and outputs the second voltage as a first portion of the first reset control signal; a ratio of the second resistance value to the first resistance value is smaller than a ratio of an average line width of the second voltage signal line to an average line width of the first voltage signal line.

2. The peripheral region is a third voltage signal line configured to provide a third voltage; a fourth voltage signal line configured to provide a fourth voltage; the first scan driving circuit is further connected to the third voltage signal line to output the third voltage as a second part of the light emission control signal; the second scan drive circuit is further connected to the fourth voltage signal line to output the fourth voltage as a second portion of the first reset control signal; The display substrate of claim 1 , wherein the third voltage is lower than the first voltage and the fourth voltage is lower than the second voltage.

3. The display substrate of claim 2 , wherein a ratio of the second resistance value to the first resistance value is smaller than a ratio of an average line width of the fourth voltage signal line to an average line width of the third voltage signal line.

4. the display area further includes a plurality of third gate scanning signal lines respectively connected to the threshold compensation sub-circuits of the pixel units of the plurality of rows; 3. The display substrate of claim 2, wherein the second scanning driving circuit is further connected to the third gate scanning signal lines through third connecting wires, respectively, to provide threshold compensation control signals to the threshold compensation sub-circuits of the pixel units in the rows, and each of the third connecting wires has a third resistance value.

5. the display area further includes a plurality of fourth gate scanning signal lines respectively connected to the data writing sub-circuits of the pixel units of the plurality of rows; the peripheral region further includes a third scan driving circuit connected to the fourth gate scanning signal lines via fourth connecting wires, respectively, to provide data writing control signals to the data writing sub-circuits of the pixel units of the rows, respectively; the second scan drive circuit is located between the first scan drive circuit and the third scan drive circuit with respect to the display area; 5. The display substrate according to claim 4, wherein each of the fourth connection wires has a fourth resistance value, and the fourth resistance value is smaller than the third resistance value.

6. the average line width of the first voltage signal line and the average line width of the second voltage signal line satisfy the following relationship: [Equation 1] R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, and W ＧＮｖｇｈ is the average line width of the second voltage signal line, and W Ｅｖｇｈ 5. The display substrate of claim 4, wherein a is an average line width of the first voltage signal line, a is a constant, and 0.5≦a≦7.

5.

7. the average line width of the first voltage signal line and the average line width of the second voltage signal line satisfy the following relationship: [Equation 2] R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, and W ＧＮｖｇｈ is the average line width of the second voltage signal line, and W Ｅｖｇｈ 5. The display substrate of claim 4, wherein a is an average line width of the first voltage signal line, a is a constant, and 0.6≦a≦3.

8. the average line width of the fourth voltage signal line and the average line width of the third voltage signal line satisfy the following relationship: [Equation 3] R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, and W ＧＮｖｇｌ is the average line width of the third voltage signal line, and W Ｅｖｇｌ 8. The display substrate of claim 4, wherein is an average line width of the fourth voltage signal line, and b is a constant, and 0.3≦b≦4.

5.

9. the average line width of the fourth voltage signal line and the average line width of the third voltage signal line satisfy the following relationship: [Equation 4] R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, and W ＧＮｖｇｌ is the average line width of the third voltage signal line, and W Ｅｖｇｈ 8. The display substrate of claim 4, wherein is an average line width of the fourth voltage signal line, and b is a constant, and 1.5≦b≦3.

5.

10. The first resistance value, the second resistance value, and the third resistance value are [Equation 5] 8. The display substrate according to claim 4, wherein the following relationship is satisfied:

11. The first resistance value, the second resistance value, and the third resistance value are [Equation 6] 8. The display substrate according to claim 4, wherein the following relationship is satisfied:

12. the first resistance value and the third resistance value satisfy the following relationship: [Equation 7] 8. The display substrate of claim 4, wherein GN(T(out)W / L) represents the aspect ratio of the output transistor included in the second scan driving circuit, d represents the number of rows of pixels driven by one first shift register unit included in the second scan driving circuit, EM(T(out)W / L) represents the aspect ratio of the output transistor included in the first scan driving circuit, and c is a constant, 0.5≦c≦1.

5.

13. the second scan driving circuit includes a plurality of cascaded first shift register units; the i-th first shift register unit is connected to the i-th third gate scanning signal line through the i-th third connection wiring, and the i-th third gate scanning signal line is connected to the threshold compensation sub-circuit of the i-th row pixel unit; the i-th first shift register unit is further connected to an i+n-th second gate scanning signal line via an i+n-th second connection wiring, and the i+n-th second gate scanning signal line is connected to a first reset sub-circuit of a pixel unit in an i+n-th row; 8. The display substrate according to claim 4, wherein both i and n are integers greater than 0.

14. the second scan driving circuit further includes n additional cascaded shift register units respectively connected to n second gate scan signal lines corresponding to the pixel units of the previous n rows via n second connecting wires, and respectively providing the first reset control signals to the first reset sub-circuits in the pixel units of the previous n rows; the j-th additional shift register unit is connected to the j-th second gate scanning signal line via the j-th second connection wiring, and the j-th second gate scanning signal line is connected to the j-th pixel unit; 14. The display substrate according to claim 13, wherein j is an integer of 1 or more and n or less.

15. the display area includes a first display sub-area and a second display sub-area; the number of pixel units in each row in the second display sub-region is equal; The display substrate of claim 4 , wherein the number of pixel units in any row in the first display sub-region is smaller than the number of pixel units in a row in the second display sub-region.

16. the first display sub-region includes pixel units in a p-th row, and the second display sub-region includes pixel units in a q-th row; a difference between a resistance value of the first connection wiring connected to the pixel unit in the p-th row and a resistance value of the first connection wiring connected to the pixel unit in the q-th row is a fifth resistance value; a difference between a resistance value of the third connection wiring connected to the pixel unit in the p-th row and a resistance value of the third connection wiring connected to the pixel unit in the q-th row is a sixth resistance value; a difference between a resistance value of the fourth connection wiring connected to the pixel unit in the p-th row and a resistance value of the fourth connection wiring connected to the pixel unit in the q-th row is a seventh resistance value; the fifth resistance value, the sixth resistance value, and the seventh resistance value all increase as the number of missing pixel units in the p-th row increases relative to the number of pixel units in the q-th row, 16. The display substrate of claim 15, wherein p is an integer greater than 0 and q is an integer greater than p.

17. the fifth resistance value, the sixth resistance value, and the seventh resistance value satisfy the following relationship: [Equation 8] Rf is the resistance when the number of missing pixel units in the pth row relative to the qth row pixel unit is 1, and f ｐ is the number of pixel units missing from the pixel units in the p-th row relative to the pixel units in the q-th row, e5, e6, and e7 are constants, k1, k2, and k4 are the resistivities of the first connection wiring, the third connection wiring, and the fourth connection wiring connected to the pixel units in the p-th row, respectively, w1, w2, and w4 are the average line widths of the first connection wiring, the third connection wiring, and the fourth connection wiring connected to the pixel units in the p-th row, respectively, u1, u2, and u4 are the average thicknesses of the first connection wiring, the third connection wiring, and the fourth connection wiring connected to the pixel units in the p-th row, respectively, g5, g6, and g7 are constants, and W ｐｉｔｃｈ The display substrate according to claim 16 , wherein is the size of one pixel unit in the first direction.

18. the peripheral region includes a third scan drive circuit configured to provide data write control signals to data write sub-circuits of the plurality of rows of pixel units; the first connection wiring includes at least two first transfer electrodes and a plurality of first connection electrodes, the at least two first transfer electrodes are located in a layer different from the plurality of first connection electrodes, the plurality of first connection electrodes are connected to the at least two first transfer electrodes via vias penetrating an insulating layer, respectively, to form the first connection wiring, and the resistivity of each of the first transfer electrodes is smaller than the resistivity of each of the first connection electrodes; the third connection wiring includes at least one second transfer electrode and a plurality of second connection electrodes, the at least one second transfer electrode is located in a layer different from the plurality of second connection electrodes, the plurality of second connection electrodes are connected to the at least one second transfer electrode through vias penetrating an insulating layer, respectively, to form the third connection wiring, and the resistivity of each of the second transfer electrodes is smaller than the resistivity of each of the second connection electrodes; 8. The display substrate according to claim 4, wherein the number of said first transfer electrodes is greater than the number of said second transfer electrodes.

19. The distance between two adjacent first transfer electrodes satisfies the following relationship: [Equation 9] D ｔ１ is the distance between two adjacent first transfer electrodes, and W ｐｉｔｃｈ is the size of one pixel unit in the first direction, and W Ｇｎ is the size of the second scan driving circuit in the first direction, and W Ｇｐ 19. The display substrate of claim 18, wherein: is the size of the third scan driving circuit in the first direction.

20. The distance between the two connection terminals of each of the first transfer electrodes satisfies the following relationship: [Equation 10] L ｔ１ is the distance between the two connection terminals of each of the first transfer electrodes, and W ＥＭ is the size of the first scan driving circuit in the first direction, and s １ is a constant, and 1 / 9≦s １ ≦1 / 5, The distance between the two connection terminals of each of the second transfer electrodes satisfies the following relationship: [0011] L ｔ１ is the distance between the two connection terminals of each of the second transfer electrodes, and W ＧＮ is the size of the second scan driving circuit in the first direction, and s ２ is a constant, and 1 / 11≦s ２ 19. The display substrate of claim 18, wherein ≦1 / 9.

21. the second connection wiring includes at least one third transfer electrode extending along a second direction different from the first direction, and a plurality of third connection electrodes extending along the second direction, the at least one third transfer electrode being located in a layer different from the plurality of third connection electrodes, the plurality of third connection electrodes being connected to the at least one third transfer electrode via a via that penetrates an insulating layer, respectively, to form the second connection wiring, and the resistivity of the third transfer electrode is smaller than the resistivity of the third connection electrode; The distance between two adjacent third transfer electrodes satisfies the following relationship: [0012] D ｔ３ is the distance between two adjacent third transfer electrodes, and W ｐｉｔｃｈ１ The display substrate of claim 18 , wherein x is the size of one pixel unit in the second direction.

22. the first transfer electrodes and the first signal lines of the second scanning driving circuit at least partially overlap each other in a direction perpendicular to the base substrate, and / or The display substrate of claim 18 , wherein the second transfer electrodes and the second signal lines of the third scan driving circuit at least partially overlap each other in a direction perpendicular to the base substrate.

23. the peripheral region further includes a first auxiliary electrode layer, and the pixel units in the display region include light-emitting elements, the light-emitting elements including a first electrode layer, a second electrode layer located on a side of the first electrode layer away from the base substrate, and a light-emitting layer located between the first electrode layer and the second electrode layer; the first auxiliary electrode layer is disposed in the same layer as the first electrode layer of the light-emitting element included in the pixel unit of the display area; the first auxiliary electrode layer is located on a side of the first scan driving circuit that is farther from the base substrate, and an electrode exhaust hole is formed in the first auxiliary electrode layer; At least one end of the first transfer electrode and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate, and / or The display substrate of claim 18 , wherein at least one end of the second transfer electrode and the electrode exhaust hole at least partially overlap in a direction perpendicular to the base substrate.

24. The second voltage signal line is provided with a signal line exhaust hole, and the size of the signal line exhaust hole satisfies the following relationship: [0013] H1 is the size of the signal line exhaust hole, and W ｐｉｔｃｈ 8. The display substrate of claim 1, wherein z is a constant, and 1 / 7≦z≦1 / 3.

25. The second voltage signal line is provided with a signal line exhaust hole, and the size of the signal line exhaust hole satisfies the following relationship: [0014] H1 is the size of the signal line exhaust hole, and W ＧＮｖｇｈ 8. The display substrate according to claim 1, wherein is an average line width of the second voltage signal lines.

26. Each of the first shift register units includes a first switching transistor; 25. The display substrate of claim 24, wherein a difference between a distance between two adjacent signal line exhaust holes and a channel size of the first switching transistor is smaller than a predetermined threshold, and a connection via between the first voltage signal line and the first electrode of the second capacitor is located between two adjacent signal line exhaust holes or at least partially overlaps with the signal line exhaust hole.

27. the display area further includes a pixel definition layer, the pixel definition layer including openings, the openings configured to define light-emitting areas of pixel units in the display area; the peripheral region further includes an auxiliary insulating layer and a second auxiliary electrode layer, the auxiliary insulating layer being disposed in the same layer as a pixel definition layer located in the display region, the second auxiliary electrode layer being disposed in the same layer as the second electrode layer located in the display region, the auxiliary insulating layer being disposed on a side of the first auxiliary electrode layer that is farther from the base substrate, and the second auxiliary electrode layer being disposed on a side of the auxiliary insulating layer that is farther from the base substrate; the auxiliary insulating layer has at least one opening; The opening size of the auxiliary insulating layer satisfies the following relationship: [Equation 15] B is the size of the opening in the auxiliary insulating layer, and W ＥＭ is the size of the first scan driving circuit in the first direction, and W ＧＮ is the size of the second scan driving circuit in the first direction, and W ＧＰ 24. The display substrate of claim 23, wherein: is the size of the third scan driving circuit in the first direction.

28. 28. The display substrate of claim 27, wherein at least one of the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit and at least one opening of the auxiliary insulating layer at least partially overlap in a direction perpendicular to the base substrate.

29. When the peripheral area on the display area side includes a plurality of scanning drive circuits, the closer the distance between the scanning drive circuits and the display area is to the plurality of scanning drive circuits, the fewer the number of transfer electrodes installed on the connection wiring connected to the scanning drive circuits becomes; 19. The display substrate of claim 18, wherein the plurality of scan driving circuits include the first scan driving circuit and the second scan driving circuit, and the connection wiring includes the first connection wiring and the second connection wiring.

30. the display area further includes a plurality of fifth gate scanning signal lines respectively connected to the second reset sub-circuits of the pixel units of the plurality of rows; the peripheral region further includes a fourth scan driving circuit connected to the fifth gate scanning signal lines via fifth connecting lines, respectively, to provide second reset control signals to the second reset sub-circuits of the pixel units in the rows, respectively; the fourth scanning drive circuit is located on a side of the third scanning drive circuit that is farther from the display area, The display substrate according to claim 5 , wherein the resistance value of each of the fifth connection wirings is an eighth resistance value, and the eighth resistance value is greater than the third resistance value.

31. the fourth scan driving circuit is located between the first scan driving circuit and the third scan driving circuit; The display substrate of claim 30 , wherein the eighth resistance value is less than the first resistance value.

32. the peripheral region further includes a fifth voltage signal line and a sixth voltage signal line; the fourth scan driving circuit is connected to the fifth voltage signal line and outputs a fifth voltage as a first portion of the second reset control signal, and the fourth scan driving circuit is connected to the sixth voltage signal line and outputs a sixth voltage as a second portion of the second reset control signal; an average line width of the fifth voltage signal line is larger than an average line width of the first voltage signal line and smaller than an average line width of the third voltage signal line; 32. The display substrate of claim 30, wherein an average line width of the sixth voltage signal lines is greater than an average line width of the second voltage signal lines and is smaller than an average line width of the fourth voltage signal lines.

33. the display area further includes a plurality of sixth gate scanning signal lines respectively connected to the light-emitting control sub-circuits of the pixel units of the plurality of rows; the peripheral region further includes a fifth scanning driving circuit connected to the sixth gate scanning signal lines via sixth connecting wires, respectively, to provide light-emitting control signals to the light-emitting control sub-circuits of the pixel units in the rows, respectively; the fifth scanning drive circuit is located on a side of the third scanning drive circuit that is farther from the display area, The display substrate according to claim 5 , wherein the resistance value of each of the sixth connection wires is a ninth resistance value, and the ninth resistance value is greater than the third resistance value.

34. the fifth scanning drive circuit is located on a side of the first scanning drive circuit that is farther from the display area, The display substrate of claim 33 , wherein the ninth resistance value is greater than the first resistance value.

35. Each of the pixel units in the plurality of rows and the plurality of columns includes a light emitting element and a pixel circuit that drives the light emitting element to emit light, the pixel circuit including a driving sub-circuit, the data writing sub-circuit, the threshold compensation sub-circuit, a reset sub-circuit and a light emission control sub-circuit; the drive subcircuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a drive current flowing through the light-emitting element; the data write sub-circuit is connected to the first terminal of the driving sub-circuit, a data line, and the fourth gate scanning signal line, and is configured to write a data signal provided from the data line to the first terminal of the driving sub-circuit in response to the data write control signal provided from the fourth gate scanning signal line; the threshold compensation sub-circuit is connected to the control terminal and the second terminal of the driving sub-circuit, the first voltage line, and the third gate scanning signal line, and is configured to compensate the driving sub-circuit in response to the threshold compensation control signal and a written data signal provided from the third gate scanning signal line; the reset subcircuit includes the first reset subcircuit, the first reset subcircuit is connected to the second terminal of the driving subcircuit, an initial signal line, and the second gate scanning signal line, and is configured to apply an initial voltage provided from the initial signal line to the second terminal of the driving subcircuit in response to the first reset control signal provided from the second gate scanning signal line; 6. The display substrate of claim 5, wherein the light-emitting control subcircuit includes a first light-emitting control subcircuit connected to the first voltage line, the first terminal of the driving subcircuit, and the first gate scanning signal line, and configured to apply a first voltage provided from the first voltage line to the first terminal of the driving subcircuit in response to the light-emitting control signal provided from the first gate scanning signal line.

36. the reset sub-circuit further includes a second reset sub-circuit, the plurality of fourth gate scanning signal lines are further connected to the second reset sub-circuits of the pixel units of the plurality of rows respectively, and the third scanning driving circuit provides second reset control signals to the second reset sub-circuits of the pixel units of the plurality of rows respectively via the plurality of fourth gate scanning signal lines; 36. The display substrate of claim 35, wherein the second reset sub-circuit is connected to the initial signal line, the fourth gate scanning signal line, and the first terminal of the light-emitting element, and is configured to apply an initial voltage provided from the initial signal line to the first terminal of the light-emitting element in response to the second reset control signal provided from the fourth gate scanning signal line; and the light-emitting control sub-circuit further includes a second light-emitting control sub-circuit, which is connected to the second terminal of the driving sub-circuit, the first terminal of the light-emitting element, and the first gate scanning signal line, and is configured to apply the driving current to the first terminal of the light-emitting element in response to the light-emitting control signal provided from the first gate scanning signal line.

37. A display panel comprising the display substrate according to claim 1 .

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