Indication device

Abstract

To provide a display device that improves light transmittance, and to provide a display device manufacturing method.SOLUTION: A display device according to an embodiment comprises: a base material; a lower electrode that is arranged on the base material; a rib that has an opening overlapping with the lower electrode; a diaphragm that is arranged on the rib; an organic layer that contacts with the lower electrode through the opening; and an upper electrode that is arranged on the organic layer. The lower electrode includes a plurality of first lower electrodes that is arranged in a first area, and a plurality of second lower electrodes that is arranged in a second area. The opening includes a plurality of first openings that overlaps with the plurality of first lower electrodes, and a plurality of second openings that overlaps with the plurality of second lower electrodes. The diaphragm includes a first diaphragm that partitions the plurality of first openings, and a plurality of second diaphragms that partitions each of the plurality of second openings. The second opening is smaller than the first opening. Each of the second diaphragms is connected by a transparent conductive layer arranged on the rib.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a display device and a method for manufacturing a display device. [Background technology]

[0002] 2. Description of the Related Art In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use, and it is known that electronic devices such as smartphones are equipped with such display devices.

[0003] In such electronic devices, by adopting a configuration in which a camera is disposed on the back surface of the display device (display area), it is possible to expand the display area to an area overlapping with the camera.

[0004] However, in such a configuration, light must enter the camera (its imaging element) through the display device, so it is necessary to ensure sufficient light transmittance in the display device (the area of ​​the display area that overlaps with the camera). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of improving light transmittance and a method for manufacturing the display device. [Means for solving the problem]

[0007] The display device according to the embodiment includes a substrate, a lower electrode disposed on the substrate, a rib having an opening overlapping the lower electrode, a partition having a lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion, an organic layer contacting the lower electrode through the opening, and an upper electrode disposed on the organic layer. The lower electrode includes a plurality of first lower electrodes disposed in a first region on the substrate, and a plurality of second lower electrodes disposed in a second region different from the first region. The opening includes a plurality of first openings overlapping the plurality of first lower electrodes, and a plurality of second openings overlapping the plurality of second lower electrodes. The partition includes a first partition that partitions the plurality of first openings, and a plurality of second partitions that partition each of the plurality of second openings. The area of ​​each of the plurality of second openings is smaller than the area of ​​each of the plurality of first openings. Each of the plurality of second partitions is disposed to have a gap between itself and the other second partitions, and is connected to the other second partitions by a transparent conductive layer disposed on the rib. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along the line AA in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of a partition wall. [Diagram 5] FIG. 5 is a schematic cross-sectional view for explaining a display element formed by utilizing partition walls. [Figure 6]FIG. 6 is a schematic cross-sectional view for explaining a display element formed by utilizing partition walls. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining a display element formed by utilizing partition walls. [Figure 8] FIG. 8 is a plan view showing a part of an electronic device in which a display device is incorporated. [Figure 9] FIG. 9 is a diagram illustrating an example of an arrangement of openings in a rib formed in the first display region. [Figure 10] FIG. 10 is a diagram illustrating an example of an opening in a rib formed in the second display region. [Figure 11] FIG. 11 is a schematic cross-sectional view of the display device taken along the line BB in FIG. [Figure 12] FIG. 12 is a diagram for explaining an example of a process for forming a rib, a partition wall, and a transparent conductive layer in the second display region. [Figure 13] FIG. 13 is a diagram for explaining an example of a process for forming a rib, a partition wall, and a transparent conductive layer in the second display region. [Figure 14] FIG. 14 is a diagram for explaining an example of a process for forming a rib, a partition wall, and a transparent conductive layer in the second display region. [Figure 15] FIG. 15 is a diagram showing another example of an opening in a rib formed in the second display region. [Figure 16] FIG. 16 is a diagram showing a schematic view of still another example of an opening provided in a rib formed in the second display region. [Figure 17] FIG. 17 is a diagram showing a schematic view of still another example of an opening provided in a rib formed in the second display region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0010] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0011] The display device according to the present embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on an electronic device such as a smartphone. Note that the electronic device on which the display device according to the present embodiment is mounted may be an electronic device other than a smartphone (for example, a tablet terminal, etc.).

[0012] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating base material 10. The base material 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged (disposed) in a matrix in the first direction X and the second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3. The pixel PX may also include subpixels SP of other colors instead of any of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element 20.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in Fig. 1. The pixel circuit 1 may include, for example, more thin film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, the subpixel SP1 includes a display element 20 that emits light in a red wavelength region, the subpixel SP2 includes a display element 20 that emits light in a green wavelength region, and the subpixel SP3 includes a display element 20 that emits light in a blue wavelength region.

[0019] Fig. 2 shows an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, subpixels SP1 and SP2 are aligned in the first direction X with subpixel SP3.

[0020] 2, the display area DA is formed with a column in which the subpixels SP1 and SP2 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example shown in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be aligned in order in the first direction X.

[0022] In the display region DA, a rib 5 and a partition wall 6 are arranged. The rib 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example shown in Fig. 2, the area of ​​the opening AP2 is larger than the area of ​​the opening AP1, and the area of ​​the opening AP3 is larger than the area of ​​the opening AP2. The partition wall 6 is arranged at the boundary between adjacent subpixels SP, and overlaps with the rib 5 in a plan view.

[0023] The partition 6 has a partition 6x extending in the first direction X and a partition 6y extending in the second direction Y. The partition 6x is disposed between the openings AP1 and AP2 adjacent to each other in the second direction Y and between the two openings AP3 adjacent to each other in the second direction Y. The partition 6y is disposed between the openings AP1 and AP3 adjacent to each other in the first direction X and between the openings AP2 and AP3 adjacent to each other in the first direction X.

[0024] 2, the partition walls 6x and 6y are connected to each other. As a result, the partition walls 6 as a whole have a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition walls 6 have openings in the subpixels SP1, SP2, and SP3, similar to the ribs 5.

[0025] That is, in this embodiment, the ribs 5 and the partition walls 6 are arranged so as to partition the sub-pixels SP1, SP2, and SP3 (apertures AP1, AP2, and AP3).

[0026] The subpixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The subpixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the aperture AP2. The subpixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. In the example shown in Fig. 2, the outer shapes of the upper electrode UE1 and the organic layer OR1 are the same, the outer shapes of the upper electrode UE2 and the organic layer OR2 are the same, and the outer shapes of the upper electrode UE3 and the organic layer OR3 are the same.

[0027] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 20 of the subpixel SP3.

[0028] The lower electrode LE1 is connected to a pixel circuit 1 that drives (the display element 20 of) the subpixel SP1 through a contact hole CH1. The lower electrode LE2 is connected to a pixel circuit 1 that drives (the display element 20 of) the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to a pixel circuit 1 that drives (the display element 20 of) the subpixel SP3 through a contact hole CH3.

[0029] 2, the contact holes CH1 and CH2 entirely overlap with the partition wall 6x between the openings AP1 and AP2 adjacent to each other in the second direction Y. The contact hole CH3 entirely overlaps with the partition wall 6x between the two openings AP3 adjacent to each other in the second direction Y. As another example, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the partition wall 6x.

[0030] 2, the lower electrodes LE1 and LE2 have protrusions PR1 and PR2, respectively. The protrusion PR1 protrudes from the main body of the lower electrode LE1 (portion overlapping with the opening AP1) toward the contact hole CH1. The protrusion PR2 protrudes from the main body of the lower electrode LE2 (portion overlapping with the opening AP2) toward the contact hole CH2. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0031] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along the line AA in Fig. 2. In the display device DSP, an insulating layer 11 called an undercoat layer is disposed on a light-transmitting substrate 10 such as the above-mentioned glass (on the surface on which the display element 20 and the like are disposed).

[0032] The insulating layer 11 has a three-layered structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). Note that the insulating layer 11 is not limited to a three-layered structure. The insulating layer 11 may have a layered structure of more than three layers, or may have a single-layered structure or a two-layered structure.

[0033] A circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has various circuits and wirings for driving the sub-pixels SP (SP1, SP2, and SP3) such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 12 is covered with an insulating layer 13.

[0034] The insulating layer 13 functions as a planarizing film that flattens unevenness caused by the circuit layer 12. Although not shown in FIG.

[0035] The lower electrodes LE (LE1, LE2, and LE3) are disposed on the insulating layer 13. The rib 5 is disposed on the insulating layer 13 and the lower electrodes LE. An end (part) of the lower electrode LE is covered by the rib 5.

[0036] The partition wall 6 has a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61 in the first direction X and the second direction Y. As a result, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 can be said to be an overhanging shape.

[0037] The organic layers OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3) together with the lower electrodes LE (LE1, LE2, and LE3) constitute the display element 20. As shown in FIG. 3, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a part of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts a side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0038] As shown in FIG. 3, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a part of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts a side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0039] As shown in FIG. 3, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a part of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts a side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the third organic layer OR3b.

[0040] In the example shown in FIG. 3, the subpixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical properties of the light emitted from the light emitting layers of the organic layers OR1, OR2, and OR3.

[0041] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0042] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0043] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0044] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers each component of the subpixel SP1, including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer SE2 continuously covers each component of the subpixel SP2, including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer SE3 continuously covers each component of the subpixel SP3, including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0045] 3, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition 6.

[0046] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15. The sealing layer 15 is further covered with a resin layer 16.

[0047] The insulating layer 13 and the resin layers 14 and 16 are made of an organic material. The rib 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of an inorganic material such as silicon nitride (SiNx).

[0048] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may be made of a conductive oxide such as ITO.

[0049] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE corresponds to an anode and the upper electrode UE corresponds to a cathode. When the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE corresponds to an anode and the lower electrode LE corresponds to a cathode.

[0050] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order.

[0051] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multiple thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. Furthermore, these multiple thin films have different refractive indices. The material of the thin films constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. The cap layer CP may be omitted.

[0052] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 included in each of the subpixels SP (SP1, SP2, and SP3).

[0053] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength region. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength region. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength region.

[0054] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of colors corresponding to the subpixels SP1, SP2, and SP3.

[0055] Fig. 4 is a schematic enlarged cross-sectional view of the partition wall 6. Elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted in Fig. 4. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1, LE2, and LE3 described above. The partition walls 6x and 6y have the same structure as the partition wall 6 shown in Fig. 4.

[0056] In the example shown in FIG. 4, the lower portion 61 of the partition wall 6 includes a barrier layer (bottom portion) 611 disposed on the rib 5, and a metal layer (shaft portion) 612 disposed on the barrier layer 611. The barrier layer 611 is formed of a material different from that of the metal layer 612, and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed to be thicker than the barrier layer 611. The metal layer 612 may have a single-layer structure or a laminated structure of different metal materials. As an example, the metal layer 612 is formed of aluminum (Al), for example.

[0057] The upper portion (top portion) 62 is thinner than the lower portion 61. In the example shown in Fig. 4, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is made of, for example, titanium (Ti), and the second layer 622 is made of, for example, ITO.

[0058] 4, the width of the lower portion 61 decreases toward the upper portion 62. That is, side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0059] The protrusion amount D of the ends 62a and 62b from the side surfaces 61a and 61b (hereinafter referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in this embodiment corresponds to the distance in the width direction (first direction X or second direction Y) perpendicular to the third direction Z of the partition wall 6 between the lower ends (barrier layers 611) of the side surfaces 61a and 61b and the ends 62a and 62b.

[0060] 4, the side surface of the barrier layer 611 and the side surface of the metal layer 612 are aligned to form a flat surface without any steps, but for example, the side surface of the barrier layer 611 may be slightly recessed from the side surface of the metal layer 612 or may protrude from the side surface of the metal layer 612. Also, in FIG. 4, the side surfaces of the barrier layer 611 and the metal layer 612 (i.e., the side surfaces 61a and 61b of the lower portion 61) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0061] The structure of the partition walls 6 and the material of each portion of the partition walls 6 can be appropriately selected in consideration of, for example, the method of forming the partition walls 6, etc.

[0062] Here, in this embodiment, the partitions 6 are formed so as to partition the sub-pixels SP in a plan view. The above-mentioned organic layer OR is formed, for example, by an anisotropic or directional vacuum deposition method. When an organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partitions 6 arranged, the partitions 6 have a shape as shown in Figures 3 and 4, so that the organic layer OR is hardly formed on the side surfaces of the partitions 6. This makes it possible to form an organic layer OR (display element 20) that is divided into sub-pixels SP by the partitions 6.

[0063] 5 to 7 are schematic cross-sectional views for explaining a display element 20 formed by using the partition walls 6. Note that the base material 10, the insulating layer 11, and the circuit layer 12 are omitted in Figs. 5 to 7. Also, the subpixels SPα, SPβ, and SPγ shown in Figs. 5 to 7 correspond to any one of the subpixels SP1, SP2, and SP3.

[0064] First, in a state where the partition 6 is disposed as described above, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are sequentially formed by deposition on the entire substrate 10 as shown in FIG. 5. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the subpixel SPα. The overhanging partition 6 divides the organic layer OR into a first organic layer ORa that contacts the lower electrode LE through the opening AP and a second organic layer ORb on the partition 6, the upper electrode UE is divided into a first upper electrode UEa that covers the first organic layer ORa and a second upper electrode UEb that covers the second organic layer ORb, and the cap layer CP is divided into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition 6.

[0065] Next, as shown in Fig. 6, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is disposed directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the subpixel SPα. The resist R is also located directly above the portions of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that are closer to the subpixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0066] Furthermore, by etching using the resist R as a mask, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are removed in portions exposed from the resist R, as shown in Fig. 7. As a result, a display element 20 including a lower electrode LE, a first organic layer ORa, a first upper electrode UEa, and a first cap layer CPa is formed in the subpixel SPα. Meanwhile, the lower electrode LE is exposed in the subpixels SPβ and SPγ. The above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0067] After the display element 20 of the subpixel SPα is formed as described above, the resist R is removed, and the display elements 20 of the subpixels SPβ and SPγ are formed in sequence, similar to the subpixel SPα.

[0068] As illustrated above for the sub-pixels SPα, SPβ and SPγ, display elements 20 for sub-pixels SP1, SP2 and SP3 are formed, and then a resin layer 14, a sealing layer 15 and a resin layer 16 are formed, thereby realizing the structure of the display device DSP shown in Figure 3.

[0069] Here, it is assumed that the display device DSP according to this embodiment is incorporated into an electronic device such as a smartphone together with a camera for use.

[0070] 8 is a plan view showing a part of an electronic device incorporating a display device DSP (display panel) according to this embodiment. As described above, in the display device DSP, the display area DA includes a plurality of pixels PX (sub-pixels SP1, SP2, and SP3) arranged in a matrix in the first direction X and the second direction Y, and the display device DSP has a display surface having the display area DA and a rear surface (hereinafter referred to as the rear surface of the display device DSP) facing the display surface. In an electronic device incorporating the display device DSP according to this embodiment, for example, a camera 100 for capturing an image is disposed on the rear side of the display device DSP.

[0071] In this case, as shown in FIG. 8, in order to enlarge the display area DA in the electronic device (display device DSP) (to widen the range of the display area DA), it is possible to place the camera 100 in a position that overlaps with the display area DA (i.e., multiple pixels PX).

[0072] However, when the camera 100 is positioned at a position overlapping with the display area DA in a planar view, the light transmittance of the area overlapping with the camera 100 (i.e., the area including the pixel PX) may decrease due to the influence of the pixel circuit 1 and lower electrode LE of each of the pixels PX overlapping with the camera 100, and there is a possibility that sufficient light may not enter the camera 100 (its imaging element) via the display device DSP.

[0073] In this case, for example, a configuration may be considered in which pixels PX are thinned out in the area overlapping with the camera 100. However, simply thinning out the pixels PX would reduce the resolution of the area overlapping with the camera 100 and would make the camera 100 more easily visible from that area, which may result in a decrease in the display quality of the display device DSP.

[0074] Therefore, in this embodiment, a configuration is adopted in which the area (size) of the opening in the rib 5 in a region of the display area DA that does not overlap with the camera 100 (hereinafter referred to as the first display area DA1) is smaller than the area (size) of the opening in the display area DA that overlaps with the camera 100 (hereinafter referred to as the second display area DA2).

[0075] Fig. 9 shows an example of the arrangement of the openings AP1, AP2, and AP3 of the rib 5 formed in the first display area DA1, while Fig. 10 shows an example of the arrangement of the openings AP1, AP2, and AP3 of the rib 5 formed in the second display area DA2.

[0076] 9 and 10 show a plurality of openings AP1, AP2, and AP3 that the rib 5 has in four pixels PX (sub-pixels SP1, SP2, and SP3). That is, in this embodiment, the number of openings AP1, AP2, and AP3 per unit area in the first display area DA1 is the same as the number of openings AP1, AP2, and AP3 per unit area in the second display area DA2.

[0077] 9 and 10, the area of ​​the opening AP1 in the second display region DA2 is smaller than the area of ​​the opening AP1 in the first display region DA1. Similarly, the area of ​​the opening AP2 in the second display region DA2 is smaller than the area of ​​the opening AP2 in the first display region DA1, and the area of ​​the opening AP3 in the second display region DA2 is smaller than the area of ​​the opening AP3 in the first display region DA1.

[0078] In the example shown in FIGS. 9 and 10, the area ratio of the openings AP1, AP2, and AP3 in the first display area DA1 is approximately the same as the area ratio of the openings AP1, AP2, and AP3 in the second display area DA2.

[0079] In the example shown in FIGS. 9 and 10, the openings AP1, AP2, and AP3 in the first display area DA1 have a rectangular shape, whereas the openings AP1, AP2, and AP3 in the second display area DA2 have a circular shape.

[0080] Furthermore, in the first display area DA1 as shown in FIG. 9, the multiple openings AP1, AP2, and AP3 are defined by partition walls 6 which are integrally formed, whereas in the second display area DA2 as shown in FIG. 10, each of the multiple openings AP1, AP2, and AP3 is formed as an independent island pattern (i.e., island-like) and is defined by multiple partition walls 6 which independently surround each of the openings AP1, AP2, and AP3.

[0081] Incidentally, the above-mentioned Figure 3 is a schematic cross-sectional view of the display device DSP in the first display area DA1, and as explained in Figure 3, by supplying a common voltage to the partition 6 formed in the first display area DA1, the common voltage can be supplied to the upper electrode UE (upper electrodes UE1, UE2 and UE3 overlapping with the openings AP1, AP2 and AP3) in contact with the side of the partition 6 (lower part 61) via the partition 6.

[0082] On the other hand, since each of the multiple partitions 6 formed in the second display area DA2 is formed as an independent island pattern as described above (i.e., arranged so as to have gaps between them), a mechanism is required to supply the above-mentioned common voltage to the multiple partitions 6.

[0083] In this case, in this embodiment, a transparent conductive layer 7 is disposed to electrically connect each of the plurality of partition walls 6 formed in the second display area DA2. The transparent conductive layer 7 is formed of a transparent conductive oxide such as ITO or IZO. With this configuration, a common voltage can be supplied to the plurality of partition walls 6 formed in the second display area DA2, and high transmittance can be achieved in the area where the transparent conductive layer 7 is disposed.

[0084] Fig. 11 is a schematic cross-sectional view of the display device DSP taken along the line BB in Fig. 10. Here, the same parts as those in Fig. 3 are given the same reference numerals and detailed description thereof will be omitted.

[0085] As shown in FIG. 11, in the second display area DA2, a partition 6 is arranged to define an opening AP1, and a display element 20 (lower electrode LE1, first organic layer OR1a, first upper electrode UE1a, and first cap layer CP1a) is formed at a position overlapping with the opening AP1.

[0086] Since the display element 20 is formed as described with reference to FIGS. 5 to 7, the second organic layer OR1b, the second upper electrode UE1b, and the second cap layer CP1b are disposed on the partition wall 6 on the opening AP1 side.

[0087] On the other hand, in the second display area DA2 (i.e., the area between the partition wall 6 defining the opening AP1 shown in FIG. 11 and the partition wall 6 defining other openings) that does not overlap with the opening AP1 (i.e., the lower electrode LE1), a transparent conductive layer 7 (e.g., an ITO layer) is arranged on the rib 5.

[0088] In this case, since a part of the transparent conductive layer 7 is covered with the partition wall 6 (lower part 61), the partition wall 6 (partition wall 6 defining the opening AP1) is electrically connected to the partition walls 6 defining other openings. In other words, a common voltage is supplied to each of the multiple partition walls 6 formed in the second display area DA2 via the transparent conductive layer 7.

[0089] Here, an example of a process for forming the ribs 5, the partition walls 6, and the transparent conductive layer 7 in the second display area DA2 will be described with reference to Figures 12 to 14. Note that the base material 10, the insulating layer 11, and the circuit layer 12 are omitted in Figures 12 to 14. Also, the subpixel SPα shown in Figures 12 to 14 corresponds to any one of the subpixels SP1, SP2, and SP3.

[0090] First, as shown in Figure 12, assuming that a lower electrode LE is formed on an insulating layer 13, an insulating layer 5a made of an inorganic material to be processed into a rib 5 is formed so as to cover the insulating layer 13 and the lower electrode LE, and a transparent conductive layer 7 is formed on the insulating layer 5a.

[0091] The insulating layer 5a is formed by, for example, chemical vapor deposition. The transparent conductive layer 7 is formed by forming a transparent conductive layer (conductive oxide layer) at least in the entire second display area DA2 by, for example, sputtering, and then removing the portion of the transparent conductive layer exposed from a resist (not shown) arranged on the transparent conductive layer by wet etching.

[0092] 13, the partition wall 6 is formed so that a part of the transparent conductive layer 7 is covered by the lower portion 61. The partition wall 6 is formed by forming a first layer to be processed into the lower portion 61 and a second layer to be processed into the upper portion 62 by a sputtering method, and then removing the portions exposed from a resist (not shown) arranged on the second layer and the first layer by wet etching, dry etching, or the like.

[0093] Furthermore, a resist patterned in the planar shape of the rib 5 is disposed, and the portion of the insulating layer 5a exposed from the resist is removed by dry etching, thereby forming the rib 5 having the openings AP (AP1, AP2, and AP3) as shown in FIG.

[0094] Here, it has been described that the ribs 5, the partitions 6 and the transparent conductive layer 7 are formed in the second display area DA2, but the ribs 5 and the partitions 6 are also formed in the first display area DA1 in the same process as the ribs 5 and the partitions 6 in the second display area DA2.

[0095] When the ribs 5 and the partition walls 6 are formed in the first display region DA1 and the ribs 5, the partition walls 6 and the transparent conductive layer 7 are formed in the second display region DA2 in this manner, the display elements 20 are formed in the openings AP1, AP2 and AP3 as described with reference to Figures 5 to 7, and further the resin layer 14, the sealing layer 15 and the resin layer 16 are formed. This realizes the structure of the display device DSP according to this embodiment.

[0096] 12 to 14, the ribs 5, the partition walls 6, and the transparent conductive layer 7 may be formed in a different order as long as the structure shown in Fig. 14 is realized. Specifically, for example, the insulating layer 5a formed so as to cover the insulating layer 13 and the lower electrode LE may be processed into the rib 5, and then the transparent conductive layer 7 and the partition walls 6 may be formed. In other words, the openings AP1, AP2, and AP3 may be formed before the transparent conductive layer 7 and the partition walls 6 are formed.

[0097] As described above, the display device DSP according to this embodiment includes a substrate 10, a lower electrode LE arranged on the substrate 10, a rib 5 having an opening AP overlapping the lower electrode, a partition wall 6 having a lower portion 61 arranged on the rib 5 and an upper portion 62 protruding from a side surface of the lower portion 61, an organic layer OR in contact with the lower electrode LE through the opening AP, an upper electrode UE arranged on the organic layer OR, and a sealing layer SE covering the upper electrode UE and the partition wall 6. In this embodiment, the lower electrode LE includes a plurality of lower electrodes LE (first lower electrodes) arranged in a first display region DA (first region) on the substrate 10 and a plurality of lower electrodes LE (second lower electrodes) arranged in a second display region DA2 different from the first display region DA1, and the opening AP includes a plurality of openings AP (first openings) overlapping with a plurality of lower electrodes LE arranged in the first display region DA1 and a plurality of openings AP (second openings) overlapping with a plurality of lower electrodes LE arranged in the second display region DA2.

[0098] In this case, in this embodiment, the partition 6 includes a partition 6 (first partition) that defines the plurality of openings AP in the first display region DA1 and a plurality of partitions 6 that define each of the plurality of openings AP in the second display region DA2, and the area of ​​each of the plurality of openings AP in the second display region DA2 is smaller than the area of ​​each of the plurality of openings AP in the first display region DA1. Furthermore, each of the plurality of partitions 6 in the second display region DA2 is disposed to have a gap with the other partitions 6, and is electrically connected to the other partitions 6 by a transparent conductive layer 7 disposed on the rib portion 5. In this way, as in the first display region DA1, in the second display region DA2, the organic layer OR is sealed by the lower electrode LE, the rib portion 5, the partition 6, and the sealing layer SE, and each pixel is formed independently. Therefore, even if one pixel becomes a dark spot due to moisture intrusion, moisture does not spread to other pixels, and the spread of the dark spot in the pixel can be suppressed. In this embodiment, the second display area DA2 is disposed at a position overlapping with the camera 100 (image pickup element) into which light is incident via the display device DSP, for example.

[0099] In this embodiment, the above-mentioned configuration allows light to be incident on the camera 100 to be transmitted through the transparent conductive layer 7 formed in the second display area DA2, thereby improving the light transmittance in the second display area DA2. Also, in this embodiment, as shown in Fig. 11 above, there is no need to place the upper electrode UE or the sealing layer SE at a position overlapping with the transparent conductive layer 7, so that high light transmittance can be achieved in the area where the transparent conductive layer 7 is placed.

[0100] Furthermore, in this embodiment, each of the multiple partition walls 6 in the second display area DA2 is arranged so as to cover a part of the transparent conductive layer 7, and the multiple partition walls 6 are electrically connected to each other via the transparent conductive layer 7. Therefore, in the second display area DA2, as in the first display area DA1, a common voltage can be appropriately supplied to the upper electrode UE via each of the multiple partition walls 6.

[0101] Furthermore, in this embodiment, since it is possible to make the number of apertures AP per unit area in the second display area DA2 the same as the number of apertures AP per unit area in the first display area DA1 (that is, to make the resolution the same in the first display area DA1 and the second display area DA2), it is possible to reduce the difference in display quality between the first display area DA1 and the second display area DA2. Also, it is considered that by reducing the difference in display quality between the first display area DA1 and the second display area DA2, it is possible to suppress the boundary between the first display area DA1 and the second display area DA2 from being visually recognized, or to make it difficult to visually recognize the camera 100 located on the back of the display device DSP.

[0102] However, since the area of ​​the openings AP1, AP2, and AP3 in the second display area DA2 is smaller than the area of ​​the openings AP1, AP2, and AP3 in the first display area DA1, the luminance of the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the second display area DA2 is lower than that of the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the first display area DA1. Therefore, in this embodiment, it is preferable to reduce the difference in luminance between the pixels PX arranged in the first display area DA1 and the second display area DA2 by adjusting the voltage supplied to the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the second display area DA1.

[0103] In the present embodiment, for example, the ratio of the areas of the openings AP1, AP2, and AP3 in the first display area DA1 and the ratio of the areas of the openings AP1, AP2, and AP3 in the second display area DA2 have been described as being substantially the same, but the ratios may be different. Specifically, for example, in the first display area DA1, the area of ​​the opening AP2 is larger than the area of ​​the opening AP1, and the area of ​​the opening AP3 is larger than the area of ​​the opening AP2, but the areas of the openings AP1, AP2, and AP3 in the second display area DA2 may be the same.

[0104] In addition, the area (aperture ratio) of the openings AP1, AP2 and AP3 in the above-mentioned second display area DA2 may be designed based on the performance (such as the amount of light required by the camera 100) of the camera 100 arranged on the back of the display device DSP.

[0105] Furthermore, if a higher transmittance is required depending on the performance of the camera 100 described above, a configuration may be adopted in which the pixels PX arranged in the second display area DA2 are thinned out (i.e., the number of openings AP per unit area in the second display area DA2 is made less than the number of openings AP per unit area in the first display area DA1, thereby increasing the area occupied by the transparent conductive layer 7 in the second display area DA2), as shown in FIG. 15.

[0106] In addition, in the example shown in FIG. 10, the openings AP1, AP2, and AP3 in the second display area DA2 are described as having a circular shape, but the openings AP1, AP2, and AP3 in the second display area DA2 may have other shapes as long as they have areas smaller than the openings AP1, AP2, and AP3 in the first display area DA1. Specifically, the openings AP1, AP2, and AP3 in the second display area DA2 may have rectangular shapes as shown in FIG. 16 and FIG. 17. Furthermore, the openings AP1, AP2, and AP3 in the second display area DA2 may have different shapes. Note that even in the case of the openings AP1, AP2, and AP3 having the rectangular shapes shown in FIG. 16 and FIG. 17 or other shapes, the configuration of thinning out the pixels PX described in FIG. 15 above may be applied.

[0107] In this embodiment, light passes through the transparent conductive layer 7 arranged between the partitions 6 and enters the camera 100. If the partitions 6 form slits, the light passing through (transmitting) the slits may diffract, and interference fringes may be formed on the camera 100 (imaging surface of the image sensor) located below the slits. In this case, compared to when the partitions 6 are formed linearly, when the partitions 6 are formed to have a curved shape, the direction (angle) of diffraction of the light passing through the slits formed by the partitions 6 can be dispersed, so that interference fringes that affect the image captured by the camera 100 are not formed on the imaging surface. That is, it is preferable that the shapes of the openings AP1, AP2, and AP3 and the partitions 6 in the second display area DA2 are designed from the viewpoint of not affecting the image captured by the camera 100.

[0108] In addition, in this embodiment, it is assumed that the camera 100 (the imaging element of the camera 100) is disposed on the back of the display device DSP, but this embodiment is applicable to a case where a sensor including a light receiving element that converts incident light into an electrical signal or a device including the sensor is disposed on the back of the display device DSP. In other words, the DSP according to this embodiment only needs to be configured to improve the light transmittance in a predetermined area of ​​the display area DA, and is not limited to being disposed on the back of the display device DSP.

[0109] In this embodiment, the area of ​​each of the multiple openings AP in the second display area DA2 has been described as being smaller than the area of ​​each of the multiple openings AP in the first display area DA1. However, this embodiment can also be described as being configured such that, for example, the area of ​​each of the sub-pixels SP1, SP2 and SP3 arranged in the second display area DA is smaller than the area of ​​each of the sub-pixels SP1, SP2 and SP3 arranged in the first display area DA1.

[0110] All display devices and display device manufacturing methods that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and display device manufacturing method described above as embodiments of the present invention fall within the scope of the present invention as long as they include the gist of the present invention.

[0111] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0112] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0113] DSP...display device, DA...display area, DA1...first display area, DA2...second display area, NDA...non-display area, PX...pixel, SP, SP1, SP2, SP3...sub-pixel, AP, AP1, AP2, AP3...opening, LE, LE1, LE2, LE3...lower electrode, UE, UE1, UE2, UE3...upper electrode, OR, OR1, OR2, OR3...organic layer, SE, SE1, SE2, SE3...sealing layer, 1...pixel circuit, 2...pixel switch, 3...driving transistor, 4...capacitor, 5...rib, 6...partition wall, 7...transparent conductive layer, 10...substrate, 11...insulating layer, 12...circuit layer, 13...insulating layer, 14...resin layer, 15...sealing layer, 16...resin layer, 20...display element, 61...lower part, 62...upper part.

Claims

1. Substrate and A lower electrode placed on the substrate, A rib having an opening that overlaps with the lower electrode, A partition wall having a lower part positioned on the rib and an upper part protruding from the side surface of the lower part, An organic layer in contact with the lower electrode through the opening, An upper electrode placed on the aforementioned organic layer and It is equipped with, The lower electrode includes a plurality of first lower electrodes arranged in a first region on the substrate and a plurality of second lower electrodes arranged in a second region different from the first region. The opening includes a plurality of first openings superimposed on the plurality of first lower electrodes and a plurality of second openings superimposed on the plurality of second lower electrodes. The partition wall includes a first partition wall that demarcates the plurality of first openings and a plurality of second partition walls that demarcate each of the plurality of second openings. The area of ​​each of the plurality of second openings is smaller than the area of ​​each of the plurality of first openings. Each of the plurality of second partitions is arranged to have a gap between it and the other second partitions, and is connected to the other second partitions by a transparent conductive layer placed on the rib. Display device.

2. The display device according to claim 1, wherein the second region is positioned to overlap with a light-receiving element that receives light via the display device.

3. The display device according to claim 1, wherein the number of second apertures per unit area in the second region is the same as the number of first apertures per unit area in the first region.

4. The display device according to claim 1, wherein the number of second apertures per unit area in the second region is less than the number of first apertures per unit area in the first region.

5. The display device according to claim 1, wherein the shape of the second opening is different from the shape of the first opening.

6. The shape of the first opening is rectangular, The shape of the second opening is circular. The display device according to claim 5.

7. The display device according to claim 1, wherein each of the plurality of second partitions is arranged to cover a portion of the transparent conductive layer.

8. A cap layer placed on the upper electrode, A sealing layer disposed on the cap layer and It is equipped with, The cap layer and the sealing layer are not placed on the transparent conductive layer. The display device according to claim 1.

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