Pixel and display device including the same

Abstract

To provide a pixel which can be applied to a high-resolution panel, and a display device including the pixel.SOLUTION: A pixel includes: a first transistor in which a first electrode is connected to a first node, a second electrode is connected to a second node, and a gate electrode is connected to a third node; a second transistor which is connected between a data line and the third node and in which the gate electrode is electrically connected to a first scan line; a third transistor which is connected between a first power line to which a voltage of a first driving power source is supplied and the first node and in which the gate electrode is electrically connected to an emission control line; a first capacitor which is connected between the first node and the third node; a second capacitor which is connected between the second node and the third node; a third capacitor which is connected between the third node and a second power line to which a voltage of a second driving power source is supplied; and a light-emitting element which is connected between the second node and the second power line.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a pixel and a display device including the pixel. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is increasing. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Publication No. 9,626,904 [Patent Document 2] US Patent Publication No. 2022-0366849 [Patent Document 3] US Patent No. 11430390 [Patent Document 4] US Patent No. 11387304

[0004] Recently, a head mounted display device (HMD) has been developed. A head mounted display device is a display device that a user wears in the form of glasses or a helmet to realize Virtual Reality (VR) or Augmented Reality (AR) in which a focus is formed at a close distance in front of the user's eyes. A high-resolution panel is applied to the head mounted display device, and therefore pixels applicable to the high-resolution panel are required.

[0005] The above content is merely intended to aid in understanding the background art related to the technical concept of the present invention, and should not be construed as content that corresponds to prior art known to those skilled in the art of the present invention. Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a pixel applicable to a high-resolution panel and a display device including the same. [Means for solving the problem]

[0007] A display device according to an embodiment of the present disclosure includes a first sub-pixel including a first pixel circuit, a second sub-pixel including a second pixel circuit and arranged in a first direction from the first sub-pixel, a 1_2 power line overlapping the first pixel circuit and extending in a second direction intersecting the first direction, a 2_2 power line overlapping the second pixel circuit and extending in the second direction, a 1_1 power line connecting the 1_2 power line and the second sub-pixel and extending in the first direction, and a 2_1 power line connecting the 2_2 power line and the first sub-pixel and extending in the first direction.

[0008] The pixel circuit may further include a first data line overlapping the first pixel circuit and extending in the second direction, and a second data line overlapping the second pixel circuit and extending in the second direction, and the first_2 power supply line may be disposed between the first data line and the second data line.

[0009] The second data line may be disposed between the 1_2 power supply line and the 2_2 power supply line.

[0010] The resistance of the 1_2 power supply line and the resistance of the 2_2 power supply line may be the same.

[0011] The display device may further include a base layer, a semiconductor layer disposed on the base layer, an interlayer insulating layer disposed on the semiconductor layer and including a first via hole exposing at least a portion of the semiconductor layer overlapping with the first pixel circuit, a first conductive layer disposed on the interlayer insulating layer, a via layer disposed on the first conductive layer and including a second via hole exposing at least a portion of the first conductive layer overlapping with the first pixel circuit, and a second conductive layer disposed on the via layer.

[0012] The via layer may not expose the first conductive layer that overlaps the second pixel circuit.

[0013] The 1_2 power line formed of the second conductive layer extends in the second direction from a region overlapping with the first pixel circuit, and the 1_2 power line contacts a connecting electrode formed of the first conductive layer through the second via hole, and the connecting electrode contacts a first pixel circuit including the semiconductor layer through the first via hole.

[0014] The interlayer insulating layer further includes a third via hole exposing at least a portion of the semiconductor layer overlapping the second pixel circuit, the connecting electrode extends in the first direction from the first pixel circuit to a region overlapping with the second pixel circuit, and the connecting electrode can contact the second pixel circuit including the active layer through the third via hole on the second pixel circuit.

[0015] The pixel may further include a gate layer disposed between the semiconductor layer and the interlayer insulating layer, the interlayer insulating layer including a fourth via hole exposing at least a portion of the gate layer overlapping the second pixel circuit.

[0016] The via layer may include a fifth via hole exposing at least a portion of the first conductive layer overlapping the first pixel circuit.

[0017] In the display device, each of the first sub-pixel and the second sub-pixel may include a light-emitting element, a driving transistor connected between the 1_1 power line and a second node and configured to control a driving current supplied to the light-emitting element in response to a voltage of the first node connected to a first gate electrode, a first capacitor having one electrode connected to the first node and another electrode connected to a third node, a second transistor connected between the third node and one of the first data line or the second data line and turned on by a first scan signal, a third transistor connected between the first node and the second node and turned on by a second scan signal, a fourth transistor connected between the first node and an initialization power supply and turned on by a third scan signal, and a fifth transistor connected between the 2_1 power line and the third node and turned on by the second scan signal.

[0018] The display device may further include a sixth transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and turned on by a first light emission control signal, a seventh transistor connected between the fourth node and an anode initialization power line and turned on by a fourth scan signal, and a second capacitor having one electrode connected to the 1_1 power line and another electrode connected to the third node.

[0019] The display device may further include a sixth transistor connected between the 1_1 power line and a fifth node connected to one electrode of the driving transistor and turned on by a first light emission control signal, a seventh transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and turned on by a second light emission control signal, an eighth transistor connected between the fourth node and an anode initialization power supply and turned on by a fourth scan signal, and a ninth transistor connected between the fifth node and a bias power supply and turned on by the fourth scan signal.

[0020] The display device can be characterized in that the drive transistor and the second to ninth transistors are P-type transistors.

[0021] The display device may be characterized in that the second transistor, the third transistor, the fourth transistor, and the fifth transistor are N-type transistors, and the drive transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors.

[0022] The display device may further include a tenth transistor connected between the 1_1 power line and the fifth node and turned on by the second scan signal.

[0023] In the display device, each of the first sub-pixel and the second sub-pixel may include a light-emitting element, a driving transistor connected between a second node and a fifth node and configured to control a driving current supplied to the light-emitting element in response to a voltage of the first node connected to a first gate electrode, a second transistor connected between one of the first data line or the second data line and a third node and turned on by a first scan signal, a first capacitor having one electrode connected to the third node and another electrode connected to the first node, a third transistor connected between the first node and a second node connected to one electrode of the driving transistor and turned on by a second scan signal, a fourth transistor connected between the third node and the 2_1 power line and turned on by the second scan signal, and a fifth transistor connected between the 1_1 power line and the fifth node and turned on by a first emission control signal.

[0024] The display device may further include a second capacitor having one electrode connected to the 1_1 power line and another electrode connected to the third node, a sixth transistor connected between the second node and a fourth node connected to one electrode of the light emitting element and turned on by a second light emission control signal, a seventh transistor connected between the fourth node and an anode initialization power line and turned on by the first light emission control signal, and an eighth transistor connected between the fifth node and a bias power supply and turned on by the first scan signal.

[0025] Another aspect of the present disclosure may be embodied by an electronic device. The electronic device according to an embodiment of the present disclosure includes a processor providing input image data to a display device, and the display device displaying an image based on the input image data. The display device includes a first sub-pixel including a first pixel circuit, a second sub-pixel including a second pixel circuit and spaced apart from the first sub-pixel in a first direction, a 1_2 power line overlapping the first pixel circuit and extending in a second direction intersecting the first direction, a 2_2 power line overlapping the second pixel circuit and extending in the second direction, a 1_1 power line connecting the 1_2 power line and the second sub-pixel and extending in the first direction, and a 2_1 power line connecting the 2_2 power line and the first sub-pixel and extending in the first direction.

[0026] The electronic device may further include a first data line overlapping the first pixel circuit and extending in the second direction, and a second data line overlapping the second pixel circuit and extending in the second direction, and the first_2 power supply line may be disposed between the first data line and the second data line. Effect of the Invention

[0027] A display device according to an embodiment of the present disclosure and an electronic device including the same may be driven with relatively low power consumption.

[0028] The effects of the embodiments are not limited to those exemplified above, and various other effects are included in the present specification. [Brief description of the drawings]

[0029] [Figure 1] FIG. 2 illustrates a transistor according to one embodiment of the present invention. [Diagram 2] 1 is a diagram showing a display device according to an embodiment of the present invention; [Diagram 3] 3 is a diagram illustrating an embodiment of a scan driver, a data driver, and a power supply unit illustrated in FIG. 2. [Figure 4] FIG. 3 illustrates an embodiment of the pixel shown in FIG. 2. [Diagram 5] 5 is a waveform diagram showing an embodiment of a method for driving the pixel shown in FIG. 4. [Figure 6] 6 is a diagram illustrating an embodiment of an operation process of a pixel corresponding to the driving waveforms of FIG. 5. [Figure 7] 6 is a diagram illustrating an embodiment of an operation process of a pixel corresponding to the driving waveforms of FIG. 5. [Figure 8] 6 is a diagram illustrating an embodiment of an operation process of a pixel corresponding to the driving waveforms of FIG. 5. [Figure 9] 6 is a diagram illustrating an embodiment of an operation process of a pixel corresponding to the driving waveforms of FIG. 5. [Figure 10] FIG. 3 shows another embodiment of the pixel shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation of the present invention will be described, and it should be noted that the description of other parts will be omitted so as not to obscure the gist of the present invention. In addition, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. The embodiments described herein are merely provided to provide a detailed description to the extent that a person having ordinary skill in the art to which the present invention pertains can easily implement the technical idea of ​​the present invention.

[0031] Throughout the specification, when a part is described as being "connected" to another part, this includes not only the case where the part is "directly connected" to the other part, but also the case where the part is "indirectly connected" to the other part through another element therebetween. The terms used herein are for the purpose of describing a particular embodiment, and are not intended to limit the present invention. Throughout the specification, when a part is described as "comprising" a certain component, this means that the part can further include other components, not excluding other components, unless otherwise specified to the contrary. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the applicable components.

[0032] Here, terms such as first, second, etc. may be used to describe various components, but such components are not limited to such terms. Such terms are used to distinguish one component from another component. Thus, a first component can refer to a second component within a scope that does not deviate from what is disclosed herein.

[0033] Various embodiments are described with reference to drawings that illustrate idealized embodiments. It is to be understood that variations in shape may occur as a result of, for example, tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as limited to the particular shapes shown, but should be construed to include, for example, variations in shapes that result from manufacturing. As such, the shapes shown in the drawings may not represent the actual shape of a region of a device, and the embodiments are not limited thereto.

[0034] FIG. 1 is a diagram showing a transistor according to an embodiment of the present invention.

[0035] 1, a transistor 10 according to an embodiment of the present invention may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. For example, the transistor 10 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor 10 (MOSFET, for example) including the body electrode 18 has a small mounting area and is suitable for implementing a high-resolution pixel.

[0036] The transistor 10 may be formed on a silicon wafer. As an example, a panel may be realized by stacking a transistor layer, a light-emitting layer, a cover layer, and the like on a silicon wafer. However, this is merely an example, and the transistor 10 may be formed on various currently known substrates (for example, a glass substrate).

[0037] The first electrode 12 of the transistor 10 may be set as a source electrode (or drain electrode), and the second electrode 14 may be set as a drain electrode (or source electrode). If the transistor 10 includes a body electrode 18, the threshold voltage of the transistor 10 may be changed by a body effect. The body effect means that the threshold voltage of the transistor 10 is changed by a voltage difference between the body electrode 18 and the first electrode 12 of the transistor.

[0038] According to an embodiment of the present invention, threshold voltage compensation may be possible while still using transistor 10, including body electrode 18, as a drive transistor.

[0039] 2 is a diagram illustrating a display device according to an embodiment of the present invention, and FIG 3 is a diagram illustrating an embodiment of a scan driver, a data driver, and a power supply unit shown in FIG 2.

[0040] 2, a display device 100 according to an embodiment of the present invention may include a pixel unit 110 (or a panel), a timing control unit 120, a scan driver 130, a data driver 140, a power supply unit 150, and an emission driver 160. The above-mentioned components may be implemented as separate integrated circuits, or two or more of the above-mentioned components may be integrated into one integrated circuit. Also, the scan driver 130 and / or the emission driver 160 may be formed in the pixel unit 110.

[0041] The pixel section 110 can include pixels PX (where n, m, and o are integers equal to or greater than 0) connected to write scan lines SL11 to SL1n, initialization scan lines SL21 to SL2n, data lines DL1 to DLm, light emission control lines EL1 to ELo, and power supply lines PL1, PL2, and PL3.

[0042] For example, a pixel PXij (see FIG. 4) located on the ith horizontal line (or pixel row) and the jth vertical line (or pixel column) may be connected to the ith write scan line SL1i, the ith initialization scan line SL2i, the kth light emission control line ELk, and the jth data line DLj (where i is an integer equal to or less than n, j is an integer equal to or less than m, and k is an integer equal to or less than o). Here, k may be the same as i or a smaller number than i. As an example, when each of the light emission control lines EL1-ELo is connected to a pixel PX located on one horizontal line, k may be the same number as i. As an example, when each of the light emission control lines EL1-ELo is connected to a pixel PX located on two or more horizontal lines, k may be a smaller number than i.

[0043] When a first scan signal is supplied to each of the write scan lines SL11 to SL1n, the pixels PX are selected in units of horizontal lines (for example, pixels PX connected to the same scan line may be classified as one horizontal line (or pixel row)), and the pixel PX selected by the first scan signal can receive a data signal from the data line (any one of DL1 to DLm) connected to it. The pixel PX that receives the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0044] The timing control unit 120 can receive input data Din and a control signal CS from a host system via an interface. As an example, the timing control unit 120 can receive the input data Din and a control signal CS from at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and an AP (Application Processor) included in the host system. The control signal CS may include various signals including a clock signal.

[0045] The timing control unit 120 can generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be provided to the scan driving unit 130, the data driving unit 140, and the emission driving unit 160, respectively.

[0046] The timing controller 120 may realign the input data Din according to the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate output data Dout and provide the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result measured during a process.

[0047] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required for driving the scan driver 130. The scan driver 130 may generate a first scan signal and a second scan signal by shifting the scan start signal in response to the clock signal.

[0048] For this reason, the scan driver 130 may include a first scan driver 132 and a second scan driver 134, as shown in FIG.

[0049] The first scan driver 132 may receive the first scan start signal FLM1 and generate the first scan signal by shifting the first scan start signal FLM1 according to a clock signal. The first scan driver 132 may sequentially supply the first scan signal to the write scan lines SL11 to SL1n.

[0050] The second scan driver 134 may receive the second scan start signal FLM2 and generate the second scan signal while shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 134 may sequentially supply the second scan signal to the initialization scan lines SL21 to SL2n. The first scan signal and the second scan signal may be set to a gate-on voltage so that the transistor included in the pixel PX can be turned on.

[0051] For example, the first and second scan signals may be supplied at a low level to the P-type transistor, and the first and second scan signals may be supplied at a high level to the N-type transistor. The transistor that receives the first or second scan signal may be turned on in response to the first or second scan signal. Hereinafter, the supply of the first and second scan signals may mean that a gate-on voltage is supplied to the write scan line SL1 and the initialization scan line SL2. And, the absence of the first and second scan signals may mean that a gate-off voltage is supplied to the write scan line SL1 and the initialization scan line SL2.

[0052] 3, the first scan driver 132 and the second scan driver 134 are shown connected to the write scan line SL1 and the initialization scan line SL2, respectively, but the embodiment of the present invention is not limited thereto. As an example, the write scan line SL1 and the initialization scan line SL2 may be driven by one scan driver.

[0053] The data driver 140 may receive the output data Dout and a data driving signal DCS from the timing control unit 120. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driver 140.

[0054] The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the gray scale of the output data Dout.

[0055] The data driver 140 may apply a constant voltage to the data lines DL1 to DLm based on the generated analog data signal. For example, referring to FIG 5, the data driver 140 may supply a data signal voltage Vdata (see FIG 5) to the data lines DL1 to DLm for one horizontal period (1H) (see FIG 5).

[0056] The power supply unit 150 may generate various power supplies necessary for driving the display device 100. For example, the power supply unit 150 may generate a first driving power supply VDD, a second driving power supply VSS, and an initialization power supply Vint.

[0057] The first driving power supply VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power supply VSS may be a power supply that receives a driving current from the pixel PX. During a period in which the pixel PX is set to a light-emitting state, the first driving power supply VDD may be set to a voltage higher than the second driving power supply VSS.

[0058] The initialization power supply Vint may be a voltage for initializing a first electrode (or an anode electrode) of the light emitting element LD (see FIG. 4) included in each of the pixels PX. When the initialization power supply Vint is supplied to the first electrode of the light emitting element LD, the initialization power supply Vint may have a voltage value that turns off the light emitting element LD.

[0059] The first driving power supply VDD generated by the power supply unit 150 may be supplied to the first power line PL1, the second driving power supply VSS to the second power line PL2, and the initialization power supply Vint to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixels PX, but the embodiment of the present invention is not limited thereto.

[0060] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX from each other. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX from each other. In an embodiment of the present invention, the pixel PX may be connected to any one of the first power lines PL1, any one of the second power lines PL2, and any one of the third power lines PL3.

[0061] The light emission driving unit 160 may receive a light emission driving signal ECS from the timing control unit 120. The light emission driving signal ECS may include a light emission start signal and a clock signal required for driving the light emission driving unit 160. The light emission driving unit 160 may generate a light emission control signal while shifting the light emission start signal EFLM in response to the clock signal. The light emission driving unit 160 may sequentially supply the light emission control signal to the light emission control lines EL1 to ELo. The light emission control signal may be set to a gate-off voltage so that a transistor included in the pixel PX can be turned off.

[0062] For example, a high level light emission control signal may be supplied to a P-type transistor, and a low level light emission control signal may be supplied to an N-type transistor. A transistor receiving a light emission control signal may be turned off in response to the light emission control signal. Hereinafter, the supply of a light emission control signal may mean that a gate-off voltage is supplied to the light emission control line EL. And, the absence of a light emission control signal may mean that a gate-on voltage is supplied to the light emission control line EL.

[0063] Fig. 4 is a diagram showing an embodiment of the pixel shown in Fig. 2. Fig. 4 shows a pixel located on the ith horizontal line and the jth vertical line.

[0064] 4, the pixel PXij according to the embodiment of the present invention may be connected to the corresponding signal lines (SL1i, SL2i, ELk, DLj). For example, the pixel PXij may be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk, and the j-th data line DLj. In the embodiment, the pixel PXij may further be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0065] A pixel PXij according to an embodiment of the present invention may include a light emitting element LD, and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0066] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. As an example, a first electrode (or an anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the second node N2, the first transistor M1, the first node N1, and the third transistor M3, and a second electrode (or a cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0067] The light emitting element LD may be selected as an organic light emitting diode. The light emitting element LD may also be selected as an inorganic light emitting diode such as a micro LED (light emitting diode) or a quantum dot light emitting diode. Furthermore, the light emitting element LD may be an element having a composite structure of organic and inorganic materials. In FIG. 4, the pixel PXij is illustrated as including a single light emitting element LD, but in other embodiments, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected in series, in parallel, or in series-parallel.

[0068] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0069] The first to fourth transistors M1 to M4 may be transistors including a body electrode. For example, each of the first to fourth transistors M1 to M4 may be a metal oxide semiconductor field effect transistor (MOSFET). In this case, the first to fourth transistors M1 to M4 may be mounted in a small area, and thus the pixel PXij may be applied to a high-resolution panel. The body electrodes of the first to fourth transistors M1 to M4 may be supplied with a first driving power supply VDD. As an example, the body electrodes of the first to fourth transistors M1 to M4 may be electrically connected to a first power supply line PL1.

[0070] In an embodiment, the first transistor M1 to the fourth transistor M4 may be formed of P-type transistors, but this is merely an example, and at least one of the first transistor M1 to the fourth transistor M4 may be replaced with an N-type transistor.

[0071] A first electrode of the first transistor M1 may be connected to a first node N1, and a second electrode of the first transistor M1 may be connected to a second node N2. Here, being connected includes the meaning of being electrically connected. A gate electrode of the first transistor M1 may be connected to a third node N3. The first node N1 may refer to a node to which a second electrode of the third transistor M3 is connected, and the second node N2 may refer to a node to which a first electrode of the light emitting element LD is connected. The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in response to the voltage of the third node N3.

[0072] The second transistor M2 may be connected between the data line DLj and a third node N3. A gate electrode of the second transistor M2 may be electrically connected to the i-th write scan line SL1i. The second transistor M2 may be turned on when a first scan signal GW is supplied to the i-th write scan line SL1i, thereby electrically connecting the data line DLj and the third node N3.

[0073] A first electrode of the third transistor M3 may be electrically connected to the first power line PL1, and a second electrode of the third transistor M3 may be connected to the first node N1. A gate electrode of the third transistor M3 may be electrically connected to the light emitting control line ELk. The third transistor M3 may be turned off when a light emitting control signal is supplied to the light emitting control line ELk, and may be turned on when the light emitting control signal is not supplied. When the third transistor M3 is turned off, the first power line PL1 and the first node N1 may be electrically disconnected.

[0074] A first electrode of the fourth transistor M4 is connected to the second node N2, and a second electrode of the fourth transistor M4 is electrically connected to the third power line PL3. A gate electrode of the fourth transistor M4 is electrically connected to the i-th initialization scan line SL2i. The fourth transistor M4 is turned on when a second scan signal GB is supplied to the i-th initialization scan line SL2i, thereby electrically connecting the second node N2 and the third power line PL3.

[0075] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may operate as a coupling capacitor and transfer a voltage change amount of the first node N1 to the third node N3. The first capacitor C1 may also store the voltage of the third node N3.

[0076] The second capacitor C2 may be connected between the second node N2 and the third node N3, and may transmit a voltage change amount of the second node N2 to the third node N3 while operating as a coupling capacitor.

[0077] The third capacitor C3 may be connected between the third node N3 and the second power line PL2 to which the second driving power VSS is supplied. When the pixel PXji is driven, the voltage or the voltage change amount of the third node N3 may vary depending on the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3. Details will be described later with reference to FIGS. 6 to 9.

[0078] FIG. 5 is a timing chart (waveform diagram) showing one embodiment of a method for driving the pixel shown in FIG.

[0079] Referring to Figures 2, 4, and 5, a horizontal period (1H) (or a specific horizontal period) in which a data signal is supplied to a pixel PXij located on the i-th horizontal line and the j-th vertical line may be divided into a first period T1, a second period T2, and a third period T3.

[0080] The data driver 140 may supply a voltage Vdata of a data signal to the data line DLj during a first period T1, a second period T2, and a third period T3.

[0081] The scan driver 130 (or the first scan driver 132) may supply a first scan signal GW to the i-th write scan line SL1i during the first period T1 and the second period T2.

[0082] The scan driver 130 (or the second scan driver 134) may supply the second scan signal GB to the i-th initialization scan line SL2i during the first period T1 to the third period T3.

[0083] The light emitting driver 160 may supply the light emitting control signal EM to the light emitting control line ELk during the second period T2.

[0084] The first period T1 is a period during which the voltage of the first driving power supply VDD is supplied to the first node N1, the voltage of the initialization power supply Vint is supplied to the second node N2, and the voltage Vdata of the data signal is supplied to the third node N3. During the first period T1, the light emitting element LD may be initialized. During the first period T1, the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be initialized and may simultaneously store the voltage Vdata of the data signal supplied to the third node N3. Such a first period T1 may be called an initialization period and a data signal writing period.

[0085] The second period T2 is a period during which the voltage of the initialization power supply Vint is supplied to the second node N2 and the voltage of the data signal Vdata is supplied to the third node N3. During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1. Such a second period T2 may be referred to as a first threshold voltage compensation period.

[0086] During the third period T3, the first transistor M1 controls the amount of current supplied from the first driving power supply VDD to the initialization power supply Vint in response to the voltage of the third node N3. In this case, it is possible to prevent unnecessary current from being supplied to the light emitting element LD after the second period T2. Such a third period T3 can be called a brightness control period.

[0087] During the fourth period T4, the first transistor M1 controls the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light emitting element LD in response to the voltage of the third node N3. In this case, during the fourth period T4, the light emitting element LD can emit light with a luminance corresponding to the amount of current supplied from the first transistor M1. Such a fourth period T4 can be named a light emitting period and a second threshold voltage compensation period.

[0088] 6 to 9 are diagrams showing an embodiment of the operation process of a pixel corresponding to the driving waveform of FIG.

[0089] 6, during a first period T1, a first scan signal GW is supplied to the i-th write scan line SL1i, and a second scan signal GB is supplied to the i-th initialization scan line SL2i. During the first period T1, no light emitting control signal EM is supplied to the light emitting control line ELk, so that the third transistor M3 is set to a turn-on state. When the third transistor M3 is turned on, the voltage of the first driving power supply VDD is supplied to the first node N1.

[0090] When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the voltage Vdata of the data signal is supplied to the third node N3 from the data line DLj. At this time, the first capacitor C1 may be initialized by the voltage Vdata of the data signal and the voltage of the first driving power supply VDD. As an example, the first capacitor C1 may be charged with a voltage corresponding to the voltage Vdata of the data signal and the first driving power supply VDD during the first period T1, regardless of the voltage charged in the previous period (or the previous frame period).

[0091] When the second scan signal GB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the initialization power supply Vint is supplied to the second node N2. When the voltage of the initialization power supply Vint is supplied to the second node N2, the light emitting element LD may be initialized. As an example, when the voltage of the initialization power supply Vint is supplied, a parasitic capacitor (not shown) of the light emitting element LD may be discharged. Here, the voltage of the initialization power supply Vint may be set to a voltage at which the light emitting element LD is turned off (or does not emit light), and thus the light emitting element LD may be set to a non-emitting state.

[0092] The second capacitor C2 may be initialized by the voltage Vdata of the data signal supplied to the third node N3 and the voltage of the initialization power supply Vint supplied to the second node N2. As an example, the second capacitor C2 may be charged with a voltage corresponding to the voltage Vdata of the data signal and the initialization power supply Vint during the first period T1, regardless of the voltage charged in the previous period (or the previous frame period).

[0093] The third capacitor C3 may be initialized by the voltage Vdata of the data signal supplied via the data line DLj. For example, the third capacitor C3 may be charged with a voltage corresponding to the voltage Vdata of the data signal during the first period T1, regardless of the voltage charged in the previous period (or the previous frame period).

[0094] During the first period T1, the current supplied from the first transistor M1 corresponding to the voltage of the third node N3 may be supplied to the initialization power source Vint via the fourth transistor M4, so that the light emitting element LD can maintain a non-emitting state during the first period T1.

[0095] Referring to FIG. 7, during the second period T2, the second transistor M2 can be maintained in a turned-on state by the first scan signal GW supplied to the i-th write scan line SL1i, and the fourth transistor M4 can be maintained in a turned-on state by the second scan signal GB supplied to the i-th initialization scan line SL2i.

[0096] During the second period T2, the third transistor M3 may be turned off by the light emission control signal EM supplied to the light emission control line ELk. When the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 is cut off.

[0097] During the second period T2, the second transistor M2 is set to a turn-on state, and therefore the voltage Vdata of the data signal is supplied to the third node N3 from the data line DLj. In this case, the voltage of the first node N1 can drop from the voltage of the first driving power supply VDD to a voltage (Vdata + |Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal.

[0098] That is, during the second period T2, the third node N3 may be set to the voltage Vdata of the data signal, and the first node N1 may be set to a voltage (Vdata + |Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal. Therefore, during the second period T2, the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0099] Since the fourth transistor M4 is set to a turn-on state during the second period T2, the current supplied from the first node N1 to the second node N2 via the first transistor M1 may be supplied to the initialization power source Vint via the fourth transistor M4, so that the light emitting element LD can maintain a non-emitting state during the second period T2.

[0100] 8, during the third period T3, the supply of the light emitting control signal EM to the light emitting control line ELk may be stopped, thereby setting the third transistor M3 to a turn-on state. During the third period T3, the supply of the first scan signal GW to the i-th write scan line SL1i may be stopped, thereby setting the second transistor M2 to a turn-off state. During the third period T3, the supply of the second scan signal GB to the i-th initialization scan line SL2i is maintained, thereby setting the fourth transistor M4 to a turn-on state.

[0101] During the third period T3, the third transistor M3 is set to a turn-on state, and therefore the first transistor M1 controls the amount of current supplied from the first driving power supply VDD to the second node N2 in response to the voltage applied to the third node N3. At this time, the fourth transistor M4 is set to a turn-on state, and therefore the current supplied to the second node N2 may be supplied to the initialization power supply Vint. As a result, during the third period T3, the light emitting element LD is set to a non-emitting state, and accurate gray scale expression of the display device 100 may be possible. For example, the voltage of the second node N2 may rise to a voltage higher than a desired voltage during the second period T2. As a result, an unintended current may be supplied to the light emitting element LD. For example, even when implementing a black gray scale in the pixel PXij, the light emitting element LD may temporarily emit light. According to the embodiment of the present invention, the current supplied from the first transistor M1 is supplied to the initialization power supply Vint during the third period T3, and therefore unintended emission of the light emitting element LD may be prevented. However, if the display device 100 can stably implement gray scales, the third period T3 may be omitted.

[0102] 9, during a fourth period T4, the supply of the second scan signal GB to the i-th initialization scan line SL2i may be stopped, thereby turning off the fourth transistor M4. During the fourth period T4, the first scan signal GW is not supplied to the i-th write scan line SL1i, thereby causing the second transistor M2 to maintain a turned-off state. During the fourth period T4, the light emitting control signal EM is not supplied to the light emitting control line ELk, thereby causing the third transistor M3 to maintain a turned-on state.

[0103] At this time, the first transistor M1 can control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light emitting element LD in response to the voltage of the third node N3. During the fourth period T4, the light emitting element LD can generate light with a brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0104] A threshold voltage compensation process according to an embodiment of the present invention will now be described in detail with reference to FIGS.

[0105] First, referring to FIG. 7, the threshold voltage of the first transistor M1 may be determined by a voltage difference between the body electrode and the source electrode (e.g., the first node N1). For example, assuming that the voltage of the driving power supply VDD is set to 8V, the body electrode of the first transistor M1 may be set to 8V and the source electrode may be set to a voltage lower than the body electrode during the second period T2. As an example, assuming that the first node N1 is set to 4V, the voltage difference between the body electrode and the source electrode of the first transistor M1 may be set to 4V (e.g., VBS=4V). In this case, the first transistor M1 may have a first threshold voltage corresponding to 4V, which is the voltage difference between the body electrode and the source electrode.

[0106] During the second period T2, the first threshold voltage may be compensated. For example, during the second period T2, the third node N3 is set to the voltage Vdata of the data signal, and the first node N1 is set to a voltage (Vdata + |Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal. The threshold voltage of the first transistor M1 may be stored in the first capacitor C1. Thus, according to an embodiment of the present invention, the threshold voltage of the first transistor M1 may be primarily compensated during the second period T2. For example, after the second period T2, the third transistor M3 is turned on, and the threshold voltage reflected in the first node N1 may be reflected in the voltage of the third node N3, and the turn-on and / or turn-off of the first transistor M1 may be controlled according to the voltage of the third node N3. Thus, the first threshold voltage of the first transistor M1 may be compensated.

[0107] Meanwhile, referring to FIG. 9, the threshold voltage of the first transistor M1 may be changed during a fourth period T4. For example, during the fourth period T4, the first node N1 may be set to the voltage of the first driving power supply VDD. Thus, the source electrode of the first transistor M1 may have the same voltage as the body electrode. For example, the voltage difference between the source electrode and the body electrode of the first transistor M1 may be about 0V. In response to the changed voltage difference between the body electrode and the source electrode of the first transistor M1, the first transistor M1 may have a second threshold voltage different from the first threshold voltage.

[0108] During the fourth period T4, when the voltage of the first driving power supply VDD is supplied to the first node N1, the voltage of the third node N3 may change according to the change in the voltage of the first node N1. As described above, the third period T3 may be provided, and the emission control signal EM may be enabled to a low level in the third period T3 prior to the fourth period T4. In this case, the voltage of the third node N3 during the third period T3 may change according to the change in the voltage of the first node N1. In the embodiment, the voltage of the third node N3 may be set as shown in Equation 1.

[0109] VN3a ∝ Vdata + (VDD - (Vdata + |Vth(M1)|)) Х C1 / (C1+C2+C3) (Formula 1)

[0110] Referring to Equation 1, VN3a may represent the voltage of the third node N3. During the fourth period T4, the voltage of the first node N1 may be changed from a voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal to the voltage of the first driving power supply VDD. Therefore, VDD-(Vdata+|Vth(M1)|) may represent the amount of change in the voltage of the first node N1.

[0111] In response to the voltage change of the first node N1, the voltage of the third node N3 may also be changed by the coupling of the first capacitor C1. The changed voltage of the third node N3 may be defined as the sum of the voltage Vdata of the data signal and the voltage change amount of the third node N3.

[0112] The voltage change amount of the third node N3 may be determined by the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3. For example, as in Equation 1, the voltage change amount of the third node N3 caused by the voltage change amount of the first node N1 may be a value obtained by multiplying the voltage change amount of the first node N1 by C1 / (C1+C2+C3). In this way, when the voltage change amount of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the voltage range of the data signal can be sufficiently wide. For example, the voltage range of the data signal may be determined by the components included in the pixel PXij. In an embodiment of the present invention, the voltage of the third node N3 may be changed according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, and the voltage Vdata range of the data signal may be set wide. For example, the voltage change amount of the third node N3 may be relatively low depending on the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, and therefore the voltage of the third node N3 may also be relatively low. As a result, even if the voltage range of the data signal is designed to be relatively wide, the voltage applied to the third node N3 may be within a required voltage range. For example, the data driver 140 may implement 255 gray levels by using a relatively wide voltage range of about 3.29V. As a result, the pixel PXij according to the embodiment of the present invention may be able to express fine gray levels.

[0113] The third capacitor C3 adjusts the ratio of the voltage change amount of the first node N1 to the voltage change amount of the third node N3. For example, as the third capacitor C3 increases, the voltage change amount of the third node N3 may decrease with respect to the voltage change amount of the first node N1. In this case, the voltage range of the data signal may be selected to be more suitable for the display device 100.

[0114] Meanwhile, after the voltage of the third node N3 is set as in Equation 1, the amount of current supplied to the second node N2 through the first transistor M1 may change in response to the voltage of the third node N3, thereby changing the voltage of the anode electrode (e.g., the second node N2) of the first transistor M1.

[0115] The second node N2 and the third node N3 are coupled via a second capacitor C2. The voltage of the third node N3 may be further changed according to the voltage change amount of the second node N2. For example, the voltage of the third node N3 may be changed by the coupling of the second capacitor C2.

[0116] VN3b ∝ VN3a + ΔVN2 Х C2 / (C1+C2+C3) (Formula 2)

[0117] Referring to Equation 2, ΔVN2 may represent the voltage change amount of the second node N2, and VN3b may represent the voltage of the third node N3 corresponding to the voltage change amount (ΔVN2) of the second node N2. As shown in Equation 2, the voltage of the third node N3 may be determined by the voltage change amount (ΔVN2) of the second node N2 multiplied by C2 / (C1+C2+C3) and VN3a in Equation 1.

[0118] According to an embodiment of the present invention, the voltage change amount (ΔN2) of the second node N2 is reflected in the voltage of the third node N3 via the second capacitor C2, thereby making it possible to supplementarily compensate the threshold voltage of the first transistor M1.

[0119] The voltage change amount (ΔVN2) of the second node N2 may be set in response to a change in the threshold voltage of the first transistor M1. For example, the voltage change amount (ΔVN2) of the second node N2 may be determined to be different in response to a change from the first threshold voltage to the second threshold voltage of the first transistor M1. For example, the voltage change amount (ΔVN2) of the second node N2 may reflect the second threshold voltage of the first transistor M1. The voltage of the third node N3 may be further changed in response to the voltage change amount (ΔVN2) of the second node N2, and the first transistor M1 may be turned on and / or off, thereby compensating for the second threshold voltage of the first transistor M1.

[0120] If the threshold voltage of the first transistor is not compensated for, the current deviation (Current Error Rate (%)) may be large. Here, the current deviation may be a percentage [%] of the change in the driving current corresponding to the change in the threshold voltage of the first transistor. According to an embodiment of the present invention, when the threshold voltage of the first transistor M1 included in the pixel PXij is changed by 20 mV, the current deviation may be set to about 3.4% or less, and when the threshold voltage is changed by -20 mV, the current deviation may be set to about -3.5% or less. For example, in the case of an embodiment of the present invention, the current deviation may be set between about 3.4% and -3.5% corresponding to the change in the threshold voltage, thereby confirming that the threshold voltage of the first transistor M1 is stably compensated.

[0121] According to the embodiment of the present invention, threshold voltage compensation is performed independently for each of the first transistors M1 included in the pixel PX of FIG. 2. For example, each of the pixels PX included in the pixel unit 110 of FIG. 2 may include a first transistor. In this case, in a driving process of the display device 100, the first transistors of each of the pixels PX may have different threshold voltages. In this case, the voltage change amounts of the first and second nodes N1 and N2 of the pixel PX may also be set to be different corresponding to the threshold voltages of each of the first transistors. The threshold voltages of the first transistors included in each of the pixels PX may be compensated by reflecting the voltage change amounts of the first and second nodes N1 and N2 to the third node N3. According to the embodiment of the present invention, the display device 100 may have improved gray scale expression.

[0122] FIG. 10 is a diagram showing another embodiment of the pixel shown in FIG.

[0123] 10, the pixel PXija according to the embodiment of the present invention may be connected to the corresponding signal lines (SL1i, SL2i, ELk, DLj). For example, the pixel PXija may be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk, and the j-th data line DLj. In the embodiment, the pixel PXija may further be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0124] The pixel PXija according to the embodiment of the present invention can include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0125] Moreover, a pixel circuit according to an embodiment of the present invention may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3a.

[0126] Hereinafter, the pixel PXija in FIG. 10 can be described similarly to the pixel PXij in FIG. 4, except for the third capacitor C3a, and duplicated descriptions will be simplified or omitted.

[0127] 10 can be driven in the same manner as the operation process of pixel PXij in FIGS. 6 to 9 in response to the driving waveform of pixel PXij in FIG. 5, and duplicated explanations will be simplified or omitted.

[0128] The third capacitor C3a may be connected between the third node N3 and the first power line PL1 to which the first driving power VDD is supplied. When the pixel PXija is driven, the voltage change amount of the third node N3 may reflect the first threshold voltage and the second threshold voltage of the first transistor M1, as described with reference to FIG. 4. At this time, the voltage change amount of the third node N3 may vary depending on the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a.

[0129] 5, during the first period T1, the first node N1 of the pixel PXija may be supplied with the voltage of the first driving power supply VDD, the second node N2 may be supplied with the voltage of the initialization power supply Vint, and the third node N3 may be supplied with the voltage Vdata of the data signal. During the first period T1, the first capacitor C1, the second capacitor C2, and the third capacitor C3a may be initialized and simultaneously store the voltage Vdata of the data signal supplied to the third node N3. For example, the third capacitor C3a may be initialized by the voltage Vdata of the data signal supplied via the data line DLj. Thus, during the first period T1, the third capacitor C3a may be charged with a voltage corresponding to the voltage Vdata of the data signal, regardless of the voltage charged in the previous period (or the previous frame period).

[0130] 6, the first threshold voltage of the first transistor M1 of the pixel PXija may be compensated during the second period T2. For example, during the second period T2, the third node N3 is set to the voltage Vdata of the data signal, and the first node N1 is set to a voltage (Vdata + |Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal. The threshold voltage of the first transistor M1 may be stored in the first capacitor C1. As a result, the voltage between the gate electrode and the source electrode of the first transistor M1 may be maintained the same. Thus, according to an embodiment of the present invention, the threshold voltage of the first transistor M1 may be primarily compensated during the second period T2.

[0131] 9, during the fourth period T4, the voltage of the first node N1 of the pixel PXija may be changed from a voltage (Vdata + |Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage of the first driving power supply VDD. As a result, the voltage of the third node N3 may also be changed due to the coupling of the first capacitor C1.

[0132] The voltage change amount of the third node N3 of the pixel PXija may be determined according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a. For example, the voltage of the third node N3 may be changed from the voltage Vdata of the data signal by a value obtained by multiplying the voltage change amount of the first node N1 by C1 / (C1+C2+C3a).

[0133] In this way, when the voltage change amount of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a, the voltage range of the data signal can be sufficiently wide. For example, the voltage range of the data signal may be determined according to the layout of the pixel PXija. In the embodiment of the present invention, the voltage of the third node N3 may be changed according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a, so that the voltage Vdata range of the data signal may be set wide. In addition, according to the embodiment of the present invention, the data driver 140 of FIG. 2 may implement 32 to 255 gray levels by using a voltage range of about 3.5V. This allows the pixel PXija of the embodiment of the present invention to express fine gray levels.

[0134] Thereafter, the voltage of the third node N3 may be changed according to the change in the voltage of the second node N2. For example, the voltage of the third node N3 may be changed by the coupling of the second capacitor C2. During the fourth period T4, the voltage of the third node N3 may be changed by a value obtained by multiplying the voltage change amount (ΔVN2) of the second node N2 by C2 / (C1+C2+C3a).

[0135] According to an embodiment of the present invention, the threshold voltage of the first transistor M1 included in the pixel PXija circuit can be compensated by reflecting the voltage change amount (ΔN2) of the second node N2 in the voltage of the third node N3. For example, in the fourth period T4, the voltage change amount (ΔVN2) of the second node N2 may be determined such that the voltage change amount (ΔN2) of the second node N2 is different in response to the change from the first threshold voltage to the second threshold voltage of the first transistor M1. This allows the threshold voltage of the first transistor M1 included in the pixel PXija circuit to be stably compensated.

[0136] Although specific embodiments and applications are described herein, other embodiments and variations may be derived from the above description, and the spirit of the present invention is not limited to these embodiments, but extends to the following claims, various obvious modifications, and equivalents. [Explanation of symbols]

[0137] 10. Transistor 12 1st electrode 14 2nd electrode 16 Gate electrode 18 Body Electrodes 100 display device 110 Pixel section PXij, Pxija pixel 120 Timing control section 130, 132, 134 Scanning drive unit 140 Data Drive Unit 150 Power supply section 160 Light emitting driver

Claims

1. a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, the second transistor having a gate electrode electrically connected to the first scan line; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor having a gate electrode electrically connected to the light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and a second power line to which a second driving power source is supplied; a light-emitting element connected between the second node and the second power line.

2. 2. The pixel of claim 1, further comprising a fourth transistor having a first electrode connected to the second node, a second electrode electrically connected to a third power line through which an initialization power source is supplied, and a gate electrode electrically connected to the second scan line.

3. The pixel of claim 2 , wherein the light emitting element is turned off when the voltage of the initialization power supply is provided to the second node.

4. The pixel of claim 2 , wherein each of the first to fourth transistors is a MOSFET including a body electrode.

5. The pixel according to claim 4 , wherein a voltage of the first driving power supply is supplied to a body electrode of each of the first transistor to the fourth transistor.

6. one horizontal period includes a first period, a second period, and a third period, During the first period, the second transistor, the third transistor, and the fourth transistor are set to a turned-on state; During the second period, the second transistor and the fourth transistor are set to a turn-on state, and the third transistor is set to a turn-off state; The pixel of claim 2 , wherein during the third period, the third transistor and the fourth transistor are set to a turned-on state, and the second transistor is set to a turned-off state.

7. The pixel according to claim 6 , wherein a voltage of a data signal is supplied to the data line during the first period to the third period.

8. a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, the second transistor having a gate electrode electrically connected to the first scan line; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor having a gate electrode electrically connected to the light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and the first power supply line; a light emitting element connected between the second node and a second power line.

9. The pixel according to claim 8 , wherein the third capacitor is supplied with the first driving power source through the first power source line.

10. 9. The pixel of claim 8, further comprising a fourth transistor having a first electrode connected to the second node, a second electrode electrically connected to a third power line through which an initialization power source is supplied, and a gate electrode electrically connected to the second scan line.

11. The pixel of claim 10 , wherein the light emitting element is turned off when the voltage of the initialization power supply is provided to the second node.

12. The pixel according to claim 10 , wherein each of the first to fourth transistors is a MOSFET including a body electrode, and a voltage of the first driving power supply is supplied to the body electrode of each of the first to fourth transistors.

13. one horizontal period includes a first period, a second period, and a third period, During the first period, the second transistor, the third transistor, and the fourth transistor are set to a turned-on state; During the second period, the second transistor and the fourth transistor are set to a turn-on state, and the third transistor is set to a turn-off state; During the third period, the third transistor and the fourth transistor are set to a turn-on state, and the second transistor is set to a turn-off state; The pixel according to claim 10 , wherein a voltage of a data signal is supplied to the data line during the first period to the third period.

14. The pixel includes a pixel connected to a write scan line, an initialization scan line, a data line, and a light emission control line; The pixel located in the i-th (i is an integer equal to or greater than 0) pixel row and the j-th (j is an integer equal to or greater than 0) pixel column is a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line of the data lines and the third node, and turned on when a first scan signal is supplied to a first scan line of the write scan lines; a third transistor connected between a first power supply line to which a voltage of a first driving power supply is supplied and the first node, and turned off when a light emission control signal is supplied to a kth (k is an integer equal to or greater than 0) light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected to the third node; a light emitting element connected between the second node and a second power line to which a second driving power source is supplied.

15. The display device according to claim 14 , wherein the third capacitor is connected between the third node and the second power supply line to which the second driving power supply is supplied.

16. The display device of claim 14 , wherein the third capacitor is connected between the third node and the first power supply line to which a first driving power is supplied.

17. The pixel located in the i pixel row and the j pixel column is 15. The display device of claim 14, further comprising a fourth transistor having a first electrode connected to the second node and a second electrode electrically connected to a third power line through which an initialization power source is supplied, the fourth transistor being turned on when a second scan signal is supplied to the second scan line.

18. The display device according to claim 17 , wherein each of the first to fourth transistors is a MOSFET including a body electrode, and the body electrode is supplied with a voltage of the first driving power supply.

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