Aggregation device, memory performance switching method, and buffer control device

Abstract

To switch the type of memory performance of a buffer while preventing frame loss.SOLUTION: A device according to an embodiment of the present disclosure is an aggregation device that aggregates communications from a plurality of terminal devices, and includes a buffer including a plurality of buffer memories, a frame processing unit that determines whether communication frames originating or destined for the plurality of terminal devices are to be transmitted externally or buffered to avoid congestion, and a memory control unit that switches the type of memory performance of the buffer while maintaining operation of some of the plurality of buffer memories.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to an aggregation device, a memory performance switching method, and a buffer control device. [Background technology]

[0002] Patent Document 1 describes a network relay device that includes a relay processing unit and an interface unit, each of which can switch its operating clock individually. In the network relay device of Patent Document 1, in order to reduce power consumption while maintaining necessary performance such as switching capacity, the operating clock of the relay processing unit and the operating clock of the interface unit are changed individually depending on the operational status of the device, etc. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-228491 A Summary of the Invention [Problem to be solved by the invention]

[0004] In an aggregation device that aggregates communications from a plurality of terminal devices (ONUs), such as an OLT for 10G-EPON, a buffer made of, for example, a DDR memory may be provided to avoid frame loss during congestion. In such an aggregate device, if you try to switch the operating clock of the DDR memory to save power, for example, you will not be able to read or write data during calibration, which will result in communication frames not being saved and frame losses.

[0005] In view of the above-mentioned problems in the related art, the present disclosure has an object to make it possible to switch the type of memory performance of a buffer while preventing frame losses. [Means for solving the problem]

[0006] An apparatus according to one aspect of the present disclosure is an aggregation apparatus that aggregates communications from a plurality of terminal devices, and includes a buffer including a plurality of buffer memories, a frame processing unit that determines whether communication frames originating or destined for the plurality of terminal devices should be transmitted externally or buffered to avoid congestion, and a memory control unit that switches the type of memory performance of the buffer while maintaining operation of some of the plurality of buffer memories.

[0007] The present disclosure can be realized not only as a system and device having the above-mentioned characteristic configuration, but also as a program for causing a computer to execute such characteristic configuration. Furthermore, the present disclosure can be realized as a semiconductor integrated circuit that realizes part or all of the system and device. Effect of the Invention

[0008] According to the present disclosure, it is possible to switch the type of memory performance of a buffer while preventing frame loss. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a network configuration diagram showing an example of the configuration of a communication system. [Diagram 2] FIG. 2 is a block diagram showing an example of the internal configuration of the OLT. [Diagram 3] FIG. 3 is a block diagram illustrating an example of the internal configuration of the memory control unit. [Figure 4] FIG. 4 is a table showing the variations in buffer performance types and switching types. [Diagram 5] FIG. 5 is an explanatory diagram showing the data flow of user frames in a low bandwidth setting. [Figure 6] FIG. 6 is an explanatory diagram showing the data flow of user frames in the medium bandwidth setting. [Figure 7] FIG. 7 is an explanatory diagram showing the data flow of user frames in a wide bandwidth setting. [Figure 8] FIG. 8 is an explanatory diagram showing the data flow of user frames in the intermediate state of the switching control 1. In FIG. [Figure 9] FIG. 9 is an explanatory diagram showing the data flow of user frames in the intermediate state of the switching control 2. In FIG. [Figure 10] FIG. 10 is a block diagram showing another example of the internal configuration of the OLT. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Overview of the embodiment of the present disclosure> Below, an overview of the embodiments of the present disclosure will be listed and described. (1) An apparatus according to one aspect of this embodiment is an aggregation apparatus that aggregates communications from a plurality of terminal devices, and includes a buffer including a plurality of buffer memories, a frame processing unit that determines whether communication frames originating from or destined for the plurality of terminal devices should be transmitted to the outside or buffered to avoid congestion, and a memory control unit that switches the type of memory performance of the buffer while maintaining operation of some of the plurality of buffer memories.

[0011] According to the aggregation device of this embodiment, the memory control unit switches the type of buffer memory performance while maintaining the operation of some of the multiple buffer memories, thereby making it possible to switch the type of buffer memory performance while preventing frame loss.

[0012] (2) In the aggregation device of (1) described above, when the multiple buffer memories include a first memory and a second memory described below, the type of memory performance may include a low bandwidth setting that operates the first memory at a low data transfer rate and pauses the second memory. First memory: A part of a plurality of buffer memories Second memory: A buffer memory other than the first memory among a plurality of buffer memories In this case, the second memory is put to a halt, thereby realizing power saving in the aggregation device.

[0013] (3) In the aggregation device of (2) above, the type of memory performance may include a medium bandwidth setting that pauses the first memory and operates the second memory at a high data transfer rate. In this case, the first memory is put to sleep, thereby realizing power saving in the aggregation device.

[0014] (4) In the aggregation device of (2) or (3) above, the type of memory performance may include a high bandwidth setting that operates both the first memory and the second memory at a high data transfer speed. In this case, the first and second controllers are operated at a high data transfer rate, so that frame loss can be dealt with appropriately even if the number of terminal devices accommodated in the line network increases.

[0015] (5) In the aggregation device of (3) or (4) described above, the memory control unit may switch from the low bandwidth setting to an intermediate state in which the second memory writes and the first memory reads, and may switch from the intermediate state to the medium bandwidth setting on condition that there is no data in the first memory. In this way, the low bandwidth setting can be switched to the medium bandwidth setting without changing the order of communication frames, so that the type of memory performance can be changed while continuing communication services.

[0016] (6) In the aggregation device of (4) or (5) above, the memory control unit may switch from the medium bandwidth setting to an intermediate state in which the first memory writes data for its own use and the second memory reads and writes data for its own use, and may switch from the intermediate state to the high bandwidth setting on condition that there is no data for the first memory in the second memory. In this way, the medium bandwidth setting can be switched to the high bandwidth setting without changing the order of communication frames, so that the type of memory performance can be changed while continuing communication services.

[0017] (7) The aggregation device of (1) to (7) above may further include a plurality of receiving ports sharing the buffer, and a front-end buffer corresponding to each of the plurality of receiving ports, and the front-end buffer may be interposed between the buffer and the receiving port. By adopting the above-mentioned front-end buffer, even if communication frames are received simultaneously, the output of the communication frames to the frame processing unit can be shifted in time, so that the communication frames once stored in the front-end buffer can be appropriately stored in the shared buffer.

[0018] (8) The method according to the present embodiment is a memory performance switching method executed by the aggregation device described above in (1) to (7). Therefore, the switching method according to the present embodiment has the same effects as those of the aggregation device described above in (1) to (7).

[0019] (9) An apparatus according to another aspect of the present embodiment is a buffer control device including a plurality of buffer memories, the buffer including the first memory and the second memory described above, and the control device includes a first PHY that performs data write operations and read operations on the first memory, a first controller that adjusts operating parameters of the first PHY, a second PHY that performs data write operations and read operations on the second memory, a second controller that adjusts operating parameters of the second PHY, and a switch that can switch the flow of data of a communication frame to be buffered to a path that passes through either the first controller or the second controller.

[0020] As described above, the control device of this embodiment includes a switch capable of switching the data flow of communication frames to be buffered to a path passing through either the first controller or the second controller. Therefore, for example, by putting the controller that does not receive communication frame data into a sleep state, it is possible to reduce power consumption of the aggregation device.

[0021] <Details of the embodiment of the present disclosure> Hereinafter, the details of the embodiments of the present disclosure will be described with reference to the drawings. Note that at least some of the embodiments described below may be combined in any combination.

[0022] [Overall configuration of communication system] FIG. 1 is a network configuration diagram showing an example of the configuration of a communication system 100. As shown in FIG. As shown in FIG. 1, a communication system 100 of this embodiment is a P2MP (Point to Multi Point) network in which an aggregation device 1 and a plurality of terminal devices 2 are connected by a line network 3 having a tree structure.

[0023] Hereinafter, the direction from aggregation device 1 to terminal device 2 will be referred to as the “downstream direction,” and the opposite direction will be referred to as the “upstream direction.” Additionally, a communication frame transmitted in the downstream direction will be referred to as a “downstream frame,” and a communication frame transmitted in the upstream direction will be referred to as an “upstream frame.” In this embodiment, a PON (Passive Optical Network) is assumed as an example of the P2MP communication system 100. When the communication system 100 is a PON, the "aggregation device", the "terminal device", and the "line network" can be expressed as follows.

[0024] Aggregation device → "OLT" (Optical Line Terminal) Terminal device → “ONU” (Optical Network Unit) Line network → "PON line"

[0025] The PON line 3 includes a single-core bidirectional transmission optical fiber 4 (trunk) having one end connected to the OLT 1, an optical coupler 5 which is a passive optical branching node connected to the other end of the optical fiber 4, and a single-core bidirectional transmission optical fiber (branch) 6 which branches out into multiple branches from the optical coupler 5. An ONU 2 is connected to each of the downstream ends of the plurality of optical fibers 6. The OLT 1 ​​is connected to a higher-level network 7 such as a core network, and each of the ONUs 2 is connected to a user network 8.

[0026] The OLT 1 ​​is installed in, for example, a telephone exchange or other central office. The ONUs 2 are installed in, for example, the homes of PON subscribers who use the communication services. In this way, the OLT 1 ​​is a relay node between the upper network 7 and the PON, and functions as a device that aggregates communications between a plurality of ONUs 2 and the upper network 7.

[0027] The OLT 1 ​​is an OLT that can be connected to a plurality of PON lines 3A and 3B. Specifically, the OLT 1 ​​communicates with at least one ONU 2 accommodated in at least one line or all lines of the plurality of PON lines 3A and 3B using a PON protocol. 1, the PON line 3A accommodates three ONUs 2, and the PON line 3B accommodates two ONUs 2. By branching, for example, 32 optical fibers 6 from the optical coupler 5, each of the PON lines 3A and 3B can accommodate a maximum of 32 ONUs 2.

[0028] In the configuration example of FIG. 1, each of the PON lines 3A and 3B includes only one optical coupler 5, but the PON lines 3A and 3B may be configured in a multi-stage configuration by providing multiple stages of optical couplers 5 in a vertical row. An upstream optical signal with a wavelength of λ1 is transmitted from the ONU 2 to the OLT 1. A downstream optical signal with a wavelength of λ2 is transmitted from the OLT 1 ​​to the ONU 2. In this embodiment, a PON conforming to the 10G-EPON standard (IEEE 802.3av), for example, is assumed.

[0029] In this case, the wavelength λ1 of the upstream optical signal and the wavelength λ2 of the downstream optical signal are set to values ​​within the following numerical ranges, for example. 1260nm≦λ1≦1280nm 1575nm≦λ2≦1580nm

[0030] The OLT 1 ​​includes a plurality of optical transceivers 12. Optical fibers 4 of the PON lines 3A and 3B are connected to each optical transceiver 12. The optical transceivers 12 transmit time-division multiplexed downstream optical signals UO to the optical fibers 4 of the PON lines 3A and 3B. The downstream optical signal DO is split by the optical coupler 5 and transmitted to each optical fiber 6, and reaches an optical transceiver (not shown) of each ONU 2. The ONU 2 performs reception processing of downstream frames addressed to itself contained in the downstream optical signal DO, and discards downstream frames not addressed to itself.

[0031] The optical transceiver of each ONU 2 transmits an upstream optical signal UO to the optical fiber 6 of each PON line 3A, 3B. The transmitted upstream optical signal UO is multiplexed by an optical coupler 5 and transmitted to an optical fiber 4, and reaches optical transceivers 12, 12 of the OLT 1. The OLT 1 ​​multiplexes and controls the transmission timing of each ONU 2 in a time-division manner so that the upstream optical signals UO do not collide on a single optical fiber 4. For this reason, the upstream optical signals UO sent from each ONU 2 are aligned on the time axis with guard times therebetween.

[0032] A management terminal 9 is connected to the OLT 1. A LAN (Local Area Network) may be interposed between the OLT 1 ​​and the management terminal 9. The management terminal 9 is, for example, a management computer operated by a communications manager, and is capable of communicating with the management control unit 11 of the OLT 1. The management terminal 9 generates setting information related to communications of the OLT 1 ​​in response to operational input by the communications manager using a command line or the like, and transmits the generated setting information to the management control unit 11.

[0033] Therefore, the management control unit 11 receives its own setting information from the management terminal 9. The management control unit 11 performs various setting processes related to communication of the OLT 1 ​​based on the received setting information. Specifically, the management control unit 11 can perform settings such as setting the maximum upstream and downstream bandwidths of the OLT 1, setting the wavelength of the optical transceiver 12, setting a Quality of Service (QoS) policy for each Logical Link ID (LLID), setting a Virtual LAN (VLAN), and setting the memory performance of the buffer 20 (see Figure 2), which will be described later.

[0034] [OLT configuration example] FIG. 2 is a block diagram showing an example of the internal configuration of the OLT 1. As shown in FIG. As shown in Figure 2, OLT 1 ​​includes a management control unit 11, a lower side transceiver 12, a lower side receiving processing unit 13, a lower side transmitting processing unit 14, an upstream frame processing unit 15, a downstream frame processing unit 16, an upper side receiving processing unit 17, an upper side transmitting processing unit 18, an upper side transceiver 19, a buffer 20, and a memory control unit 21.

[0035] Since the aggregation device 1 in FIG. 2 is the OLT 1, the downstream transceiver 12 is the optical transceiver 12 described above. 2, the OLT 1 ​​is equipped with a plurality of (two in the example) optical transceivers 12, 12 corresponding to the PON lines 3A, 3B. In the following, the reference symbols for the optical transceiver 12, the lower-side reception processing unit 13, and the lower-side transmission processing unit 14 are defined as follows:

[0036] Optical transceiver 12A: Optical transceiver 12 to which the PON line 3A is connected Optical transceiver 12B: Optical transceiver 12 to which PON line 3B is connected Lower-side reception processing unit 13A: A reception processing unit 13 electrically connected to the optical transceiver 12A. Lower side reception processing unit 13B: A reception processing unit 13 electrically connected to the optical transceiver 12B Lower-side transmission processing unit 14A: A transmission processing unit 14 electrically connected to the optical transceiver 12A. Lower-side transmission processing unit 14B: A transmission processing unit 14 electrically connected to the optical transceiver 12B. The PON line 3A may be abbreviated as "PON1," and the PON line 3B may be abbreviated as "PON2."

[0037] The management control unit 11 is, for example, an arithmetic processing device including a CPU (Central Processing Unit) and a volatile memory. The management control unit 11 may include a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), or an application specific standard product (ASSP). The management control unit 11 may be configured with at least one of an FPGA, an ASIC, and an ASSP.

[0038] The management control unit 11 is on the master side of serial communication such as I2C (Inter-Integrated Circuit) and communicates with other electronic devices mounted on the OLT 1 ​​on the slave side. 2, the functional units listed below may be configured by electronic devices including one or more FPGAs. The electronic devices may include at least one of an ASIC and an ASSP.

[0039] Functional unit 1: Lower-level receiving processing unit 13 Functional unit 2: Lower transmission processing unit 14 Functional section 3: Upstream frame processing section 15 Functional unit 4: downstream frame processing unit 16 Functional section 5: Upper side receiving processing section 17 Functional unit 6: Upper transmission processing unit 18 Functional unit 7: memory control unit 21 However, the memory control unit 21 (functional unit 7) may be configured by an FPGA separate from the other functional units 1-6.

[0040] The buffer 20 includes a plurality of sets (two sets in the illustrated example) of buffer memories 20A, 20B. The number of buffer memories 20A, 20B in each set may be one or more. The buffer memories 20A and 20B are volatile memories that operate at a predetermined data transfer speed. As the volatile memory, SDR (Single Data Rate) memory or DDR (Double Data Rate) memory may be adopted, but in this embodiment, DDR memory is assumed. The generation of the DDR memory does not matter, but DDR3 or higher is preferable.

[0041] The optical transceivers 12A and 12B convert upstream optical signals input from the PON lines 3A and 3B into electrical signals, and output the converted electrical signals to the downstream reception processors 13A and 13B. The optical transceivers 12A and 12B convert the electrical signals input from the downstream transmission processors 14A and 14B into downstream optical signals, and transmit the converted downstream optical signals to the PON lines 3A and 3B. The lower-side reception processing units 13A and 13B reconstruct an upstream frame from the input electrical signal, and output the reconstructed upstream frame to the upstream frame processing unit 15.

[0042] If the upstream frame is a report frame based on the MPCP (Multi-Point Control Protocol), the upstream frame processing unit 15 generates a gate frame including the upstream transmission timing of the ONU 2 and outputs the gate frame to the downstream frame processing unit 16 . If the upstream frame is a user frame, the upstream frame processing unit 15 performs statistical multiplexing on the user frame (upstream). In addition, the upstream frame processing unit 15 performs upstream bandwidth control based on the QoS policy specified by the management and control unit 11.

[0043] The upstream frame processing unit 15 determines whether a user frame originating from a plurality of ONUs 2 is to be transmitted to an upper network 7 outside the OLT 1, or whether it is to be buffered to avoid congestion. That is, the upstream frame processing unit 15 determines whether to output a user frame to the upper transmission processing unit 18 or to the memory control unit 21, for example, based on the upstream bandwidth usage rate Bu. The upstream bandwidth usage rate BU is calculated, for example, by the following formula (1).

[0044] BU=DT / Bmax ……(1) however, BU: Bandwidth usage rate (%), DT: Frame transfer speed (bps) being output by the upstream frame processing unit 15 Bmax: Maximum bandwidth (bps) of the upper - side transmission processing unit 18

[0045] More specifically, the upstream frame processing unit 15 executes one of the following processes according to the amount of the upstream bandwidth utilization rate BU. Process 1: When BU ≥ THb, output the user frame to the memory control unit 21. Process 2: When BU < THb, output the user frame to the upper - side transmission processing unit 18.

[0046] Here, "Thb" is a threshold value for congestion avoidance specified by the management control unit 11. The frame transfer speed DT is a measured value monitored by the upstream frame processing unit 15. The maximum bandwidth Bmax is a set value specified by the management control unit 11. Since both PON1 and PON2 are 10G - EPON optical lines, the maximum bandwidth Bmax of the upper - side transmission processing unit 18 can be set to, for example, 20G (bps).

[0047] However, when only one of PON1 or PON2 is operated, the maximum bandwidth Bmax may be set to 10G (bps). The upstream frame processing unit 15 distributes and outputs to any one of a plurality of input ports P1, P2 provided in the memory control unit 21. The distribution of the upstream frame can be executed based on the transmission source address of the ONU2, the LLID, or the communication service type, etc.

[0048] The upper - side transmission processing unit 18 shapes the input user frame into a modifiable electrical signal and outputs it to the upper - side transceiver 19. The upper - side transceiver 19 modulates the input electrical signal into a carrier signal of a predetermined frequency according to the upper - side communication standard, and sends the modulated carrier signal to the upper - side network 7.

[0049] The upper - side transceiver 19 demodulates the carrier signal input from the upper - side network 7 into an electrical signal of a predetermined frequency, and outputs the demodulated electrical signal to the upper - side reception processing unit 17. The upper side reception processing unit 17 reconstructs a downstream frame from the electrical signal input from the upper side transceiver 19 , and outputs the reconstructed downstream frame to the downstream frame processing unit 16 .

[0050] The downstream frame processing unit 16 distributes downstream frames to either the lower-side transmission processing units 13A or 13B and outputs the frames. The distribution of downstream frames can be performed based on the destination address or LLID of the ONU 2, or the like. The downstream frame processing unit 16 performs statistical multiplexing on user frames (downstream). The downstream frame processing unit 16 also performs downstream bandwidth control based on the QoS policy specified by the management and control unit 11.

[0051] In the configuration example of FIG. 2, a memory control unit 21 and a buffer 20 for saving downstream frames may be connected to the downstream frame processing unit 16 in order to avoid congestion in the downstream direction.

[0052] [Example of memory control unit configuration] FIG. 3 is a block diagram showing an example of the internal configuration of the memory control unit 21. As shown in FIG. Hereinafter, one of the buffer memories 20A constituting the buffer 20 will be referred to as the "first memory 20A," and the remaining buffer memory 20B will be referred to as the "first memory 20B." The first and second memories 20A and 20B may be one or more. In addition to the first memory 20B and the second memory 20B, another buffer memory may be included.

[0053] As shown in FIG. 3, the memory control unit 21 includes a first switch 31, a second switch 32, a first controller 33A, a second controller 33B, a first PHY 34A, and a second PHY 34B. The memory control unit 21 may be configured as an integrated circuit including, for example, an FPGA, which is circuit-set as a control device for the buffer 20. The memory control unit 21 may also include other integrated circuits such as an ASIC, an ASSP, or a System on a Chip (SoC).

[0054] The first switch 31 is, for example, a two-input, two-output logic circuit capable of switching the output to either one or both. The two input ports of the first switch 31 correspond to the input ports P1 and P2 of the memory control unit 21 that are connected to the upstream frame processing unit 15. One output port of the first switch 31 is connected to the first controller 33A. The other output port of the first switch 31 is connected to the second controller 33B.

[0055] Of the upstream frames sorted by the upstream frame processing unit 15, upstream frames of a predetermined type enter the input port P1, and upstream frames of other predetermined types enter the input port P2. In this embodiment, as an example, the predetermined type is an upstream frame originating from PON1, the source of which is ONU2 belonging to PON1, and the other predetermined type is an upstream frame originating from PON2, the source of which is ONU2 belonging to PON2.

[0056] When the first switch 31 operates with two inputs and one output, it outputs both upstream frames originating from PON1 and upstream frames originating from PON2 from one output port. When the first switch 31 operates with two inputs and two outputs, it outputs upstream frames originating from PON1 to the first controller 33A and outputs upstream frames originating from PON2 to the second controller 33B.

[0057] The second switch 32 is, for example, a two-input, one-output logic circuit capable of switching one or both inputs. One input port of the second switch 32 is connected to the first controller 33 A. The other input port of the second switch 32 is connected to the second controller 33 B. One output port of the second switch 32 is connected to the upper transmission processing unit 18.

[0058] The first memory 20A is connected to the first PHY 34A. The first PHY 34A is connected to the first controller 33A. The first PHY 34A is a physical layer circuit that complies with the SDRAM (Synchronous Dynamic Random Access Memory) standard. The first controller 33A can switch the data transfer speed for the first memory 20A by adjusting the operation parameters (operation clock, bus width, etc.) of the first PHY 34A.

[0059] The first controller 33A converts the upstream frame input from the first switch 31 into parallel digital data, and outputs the converted data to the first PHY 34A. The first controller 33A reconstructs an upstream frame from the digital data input from the first PHY 34A, and outputs the reconstructed upstream frame to the second switch 32.

[0060] The first PHY 34A converts the digital data from the first controller 33A into a predetermined electrical signal, and transmits the converted electrical signal to the SDRAM of the first memory 20A via the I / O (data write operation). The first PHY 34A converts the electrical signal received from the SDRAM of the first memory 20A via the I / O into parallel digital data, and transmits the converted digital data to the first controller 33A (data read operation).

[0061] The second memory 20B is connected to the second PHY 34B. The second PHY 34B is connected to the second controller 33B. The second PHY 34B is a physical layer circuit that complies with the SDRAM standard. The second controller 33B can switch the data transfer speed for the second memory 20B by adjusting the operation parameters (operation clock, bus width, etc.) of the second PHY 34B.

[0062] The second controller 33B converts the upstream frame input from the first switch 31 into parallel digital data, and outputs the converted data to the second PHY 34B. The second controller 33B reconstructs an upstream frame from the digital data input from the second PHY 34B, and outputs the reconstructed upstream frame to the second switch 32.

[0063] The second PHY 34B converts the digital data from the second controller 33B into a predetermined electric signal, and transmits the converted electric signal to the SDRAM of the second memory 20B via the I / O (data write operation). The second PHY 34B converts the electrical signal received from the SDRAM of the second memory 20B via the I / O into parallel digital data, and transmits the converted digital data to the second controller 33B (data read operation).

[0064] When the first controller 33A and the second controller 33B are both in an operating state (Act1, Act2) and outputting an upstream frame to the second switch 32 (Figure 7), they perform arbitration control to adjust the output timing so that data output to the second switch 32 is alternated for each upstream frame.

[0065] The memory control unit (control device) 21 of this embodiment is provided with switches 31, 32 that can switch the flow of data of user frames to be buffered to either a path that passes only through the first controller 33A (Figure 5) or a path that passes only through the second controller 33B (Figure 6). Therefore, for example, by putting the controllers 33A, 33B to which no data is input into a sleep state (Stby1, Stby2), it is possible to conserve power in the OLT 1.

[0066] [Control signals for memory control unit] 3, the memory control unit 21 functions as a slave side communication node of serial communication such as I2C, and can receive a variety of control signals S1, S2, S3, and S4 from the management control unit 11. The following describes the definitions and contents of parameters applied to the control signals S1, S2, S3, and S4. In the following, "ES1" means the execution speed of data transfer of the first memory 20A, and "ES2" means the execution speed of data transfer of the second memory 20B.

[0067] Control signal S1: This is a control signal that indicates the type of operation state (OS1) to be executed by the first controller 33A. The types of operation state (OS1) include, for example, an active state (Act1), a dormant state (Stby1), a type (Lo1, Hi1) of the execution speed (ES1) of data transfer, write only (WO1), and read only (RO1).

[0068] The operating state (Act1) is a state in which control of both data writing and reading is executed for the first PHY 34A. The sleep state (Stby1) is a state in which the first controller 33A does not allow the first PHY 34A to execute either read or write, and reduces its own power consumption to an extent that the control signal S1 can be received.

[0069] When the first controller 33A itself goes into a sleep state (Stby1), it also instructs the first PHY 34A to sleep. In this case, the first PHY 34A drops the operating clock to perform a power saving operation and stops reading and writing from and to the first memory 20A. The types of the execution speed (ES1) instructed to the first controller 33A include, for example, low speed (Lo1) and high speed (Hi1). Note that the execution speed of the data transfer when the first PHY 34A is in the sleep state is described as "ES1=0".

[0070] The write only state (WO1) is a state in which only the control of writing data is executed. When the first controller 33A receives the control signal S1 including WO1, the first controller 33A causes the first PHY 34A to execute the writing of data. The read only state (RO1) is a state in which only control of reading data is executed. When the first controller 33A receives the control signal S1 including RO1, the first controller 33A causes the first PHY 34A to execute only reading data.

[0071] The first controller 33A determines the data transfer rate to be instructed to the first PHY 34A based on the type (Lo1, Hi1) of the execution rate (ES1) included in the control signal S1. The low speed (Lo1) is, for example, 1 / 2 the maximum transfer speed (Gbps) of the first memory 20A. When the first controller 33A receives the control signal S1 including Lo1, it adjusts the operation parameters (operation clock, bus width, etc.) of the first PHY 34A so that the execution speed (ES1) of the first memory 20A becomes 1 / 2 the maximum transfer speed.

[0072] The high speed (Hi1) is, for example, the maximum transfer speed (Gbps) of the first memory 20A. When the first controller 33A receives the control signal S1 including Hi1, the first controller 33A adjusts the operating parameters of the first PHY 34A so that the execution speed (ES1) of the first memory 20A becomes the maximum transfer speed.

[0073] Control signal S2: This is a control signal for instructing the type of operation state (OS2) to be executed by the second controller 33B. The types of operation state (OS2) include, for example, an active state (Act2), a dormant state (Stby2), a type (Lo2, Hi2) of the execution speed (ES2) of data transfer, write only (WO2), and read only (RO2).

[0074] The operating state (Act2) is a state in which control is exercised over both data writing and reading for the second PHY 34B. The sleep state (Stby2) is a state in which the second controller 33B does not allow the second PHY 34B to execute either read or write, and reduces its own power consumption to an extent that the control signal S2 can be received.

[0075] When the second controller 33B itself goes into a sleep state (Stby2), it instructs the second PHY 34B to also sleep. In this case, the second PHY 34B drops the operating clock to perform a power saving operation and stops reading and writing from and to the second memory 20B. The type of the execution speed (ES2) instructed to the second controller 33B includes, for example, a low speed (ES2) and a high speed (Hi2). Note that the execution speed of the data transfer when the second PHY 34B is in a quiescent state is described as "ES2=0".

[0076] Write only (WO2) is a state in which only control of writing data is executed. Upon receiving the control signal S2 including WO2, the second controller 33B causes the second PHY 34B to execute only writing data. The read only state (RO2) is a state in which only control of reading data is executed. Upon receiving the control signal S2 including RO2, the second controller 33B causes the second PHY 34B to execute only data reading.

[0077] The second controller 33B determines the data transfer rate to be instructed to the second PHY 34B based on the type (Lo2, Hi2) of the execution rate (ES2) included in the control signal S2. The low speed (Lo2) is, for example, 1 / 2 the maximum transfer speed (Gbps) of the second memory 20B. When the second controller 33B receives the control signal S2 including Lo2, it adjusts the operating parameters (operating clock, bus width, etc.) of the second PHY 34B so that the execution speed (ES2) of the second memory 20B becomes 1 / 2 the maximum transfer speed.

[0078] The high speed (Hi2) is, for example, the maximum transfer speed (Gbps) of the second memory 20B. When the second controller 33B receives the control signal S2 including Hi2, the second controller 33B adjusts the operating parameters of the second PHY 34B so that the execution speed (ES2) of the second memory 20B becomes the maximum transfer speed.

[0079] Control signal S3: This is a control signal that instructs the first switch 31 on the type of data output destination OD. The types of output destinations (OD) include, for example, the first controller 34A (CTL_A), the second controller 34B (CTL_B), and both the first controller 34A and the second controller 34B (CTL_AB).

[0080] When the first switch 31 receives the control signal S3 with the OD type CTL_A, it sets the output destination of the upstream frame to only the first controller 33A. When the first switch 31 receives the control signal S3 with the OD type CTL_B, it sets the output destination of the upstream frame to only the second controller 33B. When the first switch 31 receives the control signal S3 whose OD type is CTL_AB, it sets the output destination of the upstream frame to both the first controller 33A and the second controller 33B.

[0081] Control signal S4: This is a control signal that instructs the second switch 32 on the type of data input source IS. The types of the input source (IS) include, for example, the first controller 34A (CTL_A), the second controller 34B (CTL_B), and both the first controller 34A and the second controller 34B (CTL_AB).

[0082] When the second switch 32 receives the control signal S4 in which the IS type is CTL_A, the second switch 32 sets the input source of the upstream frame to only the first controller 33A. When the second switch 32 receives the control signal S4 with the IS type CTL_B, it sets the input source of the upstream frame to only the second controller 33B. When the second switch 32 receives the control signal S4 in which the IS type is CTL_AB, it sets the input sources of the upstream frames to both the first controller 33A and the second controller 33B.

[0083] [Buffer memory performance scalability] FIG. 4 is a table showing variations in performance types and switching types of the buffer 20, which are realized by the memory control unit 21 illustrated in FIG. 4, "performance type" refers to the type of memory performance set in the buffer 20. The performance types include, for example, "low bandwidth setting", "medium bandwidth setting", and "high bandwidth setting". The contents of these performance types will be described below.

[0084] (Low bandwidth setting) As shown in FIG. 4, in the "low band setting", the parameters of the control signals S1, S2, S3, and S4 are set as follows. Control signal S1: OS1=Act, Lo1 Control signal S2: OS2=Stby2 (ES2=0) Control signal S3: OD=CTL_A Control signal S4: IS=CTL_A

[0085] 5 is an explanatory diagram showing the data flow of user frames in a low bandwidth setting. The data flow is indicated by solid arrows. 5, in the low bandwidth setting, an upstream frame input to the first switch 31 is not output to the inactive second controller 33B, but is output only to the active first controller 34A. The active first controller 34A controls the first PHY 34A so that the execution speed ES1 of the data transfer of the first memory 20A becomes the low speed Lo1.

[0086] In this manner, in the low bandwidth setting, the data transfer rate of the first memory 20A out of the first and second memories 20A, 20B is set to the low rate Lo1. Therefore, the low bandwidth setting is suitable for cases where there is a considerable margin of upstream bandwidth usage, such as when only ONU2, whose maximum upstream communication speed is 1G, is connected to PON1 or PON2. In this case, power saving of OLT1 is realized by putting the second controller 33B, which operates the second memory 20B, into a sleep state (Stby2).

[0087] (Medium Bandwidth Settings) As shown in FIG. 4, in the "medium band setting", the parameters of the control signals S1, S2, S3, and S4 are set as follows. Control signal S1: OS1=Stby1 (ES1=0) Control signal S2: OS2=Act2, Hi2 Control signal S3: OD=CTL_B Control signal S4: IS=CTL_B

[0088] 6 is an explanatory diagram showing the data flow of user frames in the medium bandwidth setting. The data flow is indicated by solid arrows. 6, in the medium bandwidth setting, an upstream frame input to the first switch 31 is not output to the inactive first controller 33A, but is output only to the active second controller 34B. The active second controller 34B controls the second PHY 34B so that the execution speed ES2 of the data transfer of the second memory 20B becomes the high speed Hi2.

[0089] In this way, in the medium bandwidth setting, of the first and second memories 20A and 20B, the data transfer rate of the second memory 20B is set to the high speed Hi2. Therefore, the medium bandwidth setting is suitable for cases where there is still room for upstream bandwidth usage, such as when an ONU2 with a maximum upstream communication speed of 10G starts to be connected to PON1 or PON2. In this case, power saving of the OLT1 is realized by putting the first controller 33A that operates the first memory 20A into a sleep state (Stby1).

[0090] (High bandwidth setting) As shown in FIG. 4, in the "wide band setting", the parameters of the control signals S1, S2, S3, and S4 are set as follows. Control signal S1: OS1=Act1, Hi1 Control signal S3: OS2=Act2, Hi2 Control signal S5: OD=CTL_AB Control signal S6:IS=CTL_AB

[0091] 7 is an explanatory diagram showing the data flow of user frames in the high bandwidth setting. The data flow is indicated by solid arrows. As shown in FIG. 7, in the high bandwidth setting, an upstream frame input to the first switch 31 is output to both the first controller 34A and the second controller 34B, both of which are in the operating state (Act1, Act2).

[0092] The first controller 34A controls the first PHY 34A so that the execution speed ES1 of the data transfer of the first memory 20A becomes the high speed Hi1. The second controller 34B controls the second PHY 34B so that the execution speed ES2 of the data transfer of the second memory 20B becomes the high speed Hi2.

[0093] In this way, in the high bandwidth setting, the execution speed of the first memory 20A is set to the high speed Hi1, and the execution speed of the second memory 20B is also set to the high speed Hi2. Therefore, the high bandwidth setting is suitable when the upstream bandwidth usage becomes relatively large, for example, when a plurality of ONUs 2 with a maximum upstream communication speed of 10 G are connected to PON1 or PON2.

[0094] In this case, the first and second controllers 33A, 33B operate to maximize the execution speeds ES1, ES2 of the first and second memories 20A, 20B, so that frame loss during congestion can be appropriately prevented even if the number of 10G-compatible ONU2 connected to at least one of PON1 and PON2 increases.

[0095] (Effect of changing memory performance type) As described above, according to the OLT 1 ​​of this embodiment, a memory control unit 21 is adopted that can switch the type of memory performance of the buffer 20 including two sets of buffer memories 20A, 20B to any one of "low bandwidth setting," "medium bandwidth setting," and "high bandwidth setting," so that the memory performance of the buffer 20 to prevent frame loss can be switched in a scalable manner.

[0096] [Memory performance switching control] In FIG. 4, “switching type” refers to the type of switching control for switching the type of memory performance of the buffer 20. The switching types include "switching control 1" for switching the memory performance type from a low bandwidth setting to a medium bandwidth setting, and "switching control 2" for switching the memory performance type from a medium bandwidth setting to a high bandwidth setting. The details of these switching controls will be described below.

[0097] (Switching control 1) As shown in FIG. 4, “switching control 2” is a control for switching the parameters of the above-mentioned control signals S1, S2, S3, and S4 from the contents of the initial state (low bandwidth setting) to the contents of the intermediate state ST11, and then switching them to the contents of the final state ST12 (medium bandwidth setting) if a predetermined condition is met.

[0098] 1) Intermediate state ST11 In the intermediate state ST11 of the switching control 1, the parameters of the control signals S1, S2, S3, and S4 are set as follows. Control signal S1: OS1=RO1, Lo1 Control signal S2: OS2=WO2, Hi2 Control signal S3: OD=CTL_B Control signal S4:IS=CTL_A(Inherit)

[0099] 8 is an explanatory diagram showing the data flow of user frames in intermediate state ST11 of switching control 1. The data flow is indicated by solid arrows. As shown in FIG. 8, in an intermediate state ST11 of switching control 1, an upstream frame input to the first switch 31 is output only to the second controller 33B, and the second controller 33B instructs the second PHY 34B to write only at high speed Hi2.

[0100] Moreover, the second switch 32 continues to be connected only to the first controller 33A, and the first controller 33A instructs the first PHY 34A to perform only reading at the low speed Lo1. Therefore, when the low bandwidth setting is switched to the intermediate state ST11, the write destination of the upstream frames is changed to the second memory 20B, and only reading of the upstream frames is executed from the first memory 20A.

[0101] 2) Final state ST12 4, the parameters of the control signals S1, S2, S3, and S4 in the final state ST12 of the switching control 1 are the same as those in the medium bandwidth setting. However, the switching from the intermediate state ST11 to the final state ST12 is performed under the condition that the buffer amount (DT_A) of the first memory 20A is zero.

[0102] In this way, in switching control 1, the low bandwidth setting is the initial state, and then it is switched to an intermediate state ST11 in which the second memory 20B writes and the first memory 20A reads, and then it is switched to a medium bandwidth setting (final state ST12) on the condition that there is no data in the first memory 20A. Therefore, it is possible to switch from a low bandwidth setting to a medium bandwidth setting without changing the order of upstream frames, and it is possible to change the type of memory performance while continuing communication services.

[0103] 3) How to execute Switch Control 1 The switching control 1 may be executed by the management control unit 11, triggered by an execution command manually inputted from the management terminal 9. In this case, the management control unit 11 switches the control signals S1, S2, S3, and S4 in the order from the intermediate state ST11 to the final state ST12. A program for issuing a command to execute switching control 1 may be incorporated into the management control unit 11 depending on the number of 10G-compatible ONUs 2 installed that belong to PON1 and PON2. In this way, the OLT 1 ​​can be made to automatically execute switching control 1.

[0104] (Switching control 2) As shown in FIG. 4, “switching control 2” is a control for switching the parameters of the above-mentioned control signals S1, S2, S3, and S4 from the contents of the initial state (medium band setting) to the contents of an intermediate state ST21, and then switching them to the contents of a final state ST12 (high band setting) if a predetermined condition is met.

[0105] 1) Intermediate state ST21 In the intermediate state ST21 of the switching control 2, the parameters of the control signals S1, S2, S3, and S4 are set as follows. Control signal S1: OS1=WO1, Hi1 Control signal S2:OS2=Act2,Hi2(Inherit) Control signal S3: OD=CTL_AB Control signal S4:IS=CTL_B(Inherit)

[0106] 9 is an explanatory diagram showing the data flow of user frames in intermediate state ST21 of switching control 2. The data flow is indicated by solid arrows. As shown in FIG. 9, in the intermediate state ST21 of switching control 2, the first switch 31 is connected to the first and second controllers 33A, 33B, but the second controller 33B continues to operate (Act2) at high speed (Hi2), and the second switch 32 continues to be connected only to the second controller 33B.

[0107] In this case, the second controller 33B instructs the second PHY 34B to write and read the upstream frames originating from PON2 and input to the first switch 31 at high speed Hi2. Furthermore, the first controller 33A instructs the second PHY 34A to write upstream frames originating from PON1 and input to the first switch 31 only at high speed Hi1.

[0108] Therefore, when the medium bandwidth setting is switched to the intermediate state ST21, the first memory 20A starts writing data for itself (upstream frames originating from PON1). Moreover, the second memory 20B stops reading and writing data for the first memory 20A (upstream frames originating from PON1) and continues reading and writing only data for itself (upstream frames originating from PON2).

[0109] 2) Final state ST22 4, the parameters of the control signals S1, S2, S3, and S4 in the final state ST22 of the switching control 2 are the same as those in the high bandwidth setting. However, the switching from the intermediate state ST21 to the final state ST22 is performed on the condition that the buffer amount (DT1_B) of data for the first memory 20A in the second memory 20B is zero. In this embodiment, the data for the first memory 20A is data of an upstream frame originating from PON1, and the second controller 33B has a function of determining whether the upstream frame originates from PON1 or PON2 based on header information or the like.

[0110] In this way, in switching control 2, the medium bandwidth setting is used as the initial state, and the first memory 20A writes its own data (upstream frames originating from PON1) and the second memory 20B is switched to an intermediate state ST21 in which it continues to read and write its own data (upstream frames originating from PON2), and when the second memory 20B does not have data for the first memory 20A (upstream frames originating from PON1), it is switched to a high bandwidth setting (final state ST22). Therefore, it is possible to switch from the medium bandwidth setting to the high bandwidth setting without changing the order of the upstream frames, and it is possible to change the type of memory performance while continuing the communication service.

[0111] 3) How to execute switch control 2 The switching control 2 may be executed by the management control unit 11, triggered by an execution command manually input from the management terminal 9. In this case, the management control unit 11 switches the control signals S1, S2, S3, and S4 in the order from the intermediate state ST21 to the final state ST22. A program for issuing an execution command for switching control 2 may be incorporated into the management control unit 11 depending on the number of 10G-compatible ONUs 2 installed that belong to PON1 and PON2. In this way, the OLT 1 ​​can be made to automatically execute switching control 2.

[0112] [First Modification] FIG. 10 is a block diagram showing another example of the internal configuration of the OLT 1. In FIG. The OLT 1 ​​in FIG. 10 includes a front-end buffer 22A arranged between the upstream frame processing unit 15 and the lower-level receiving processing unit 13A, and a front-end buffer 22B arranged between the upstream frame processing unit 15 and the lower-level receiving processing unit 13B.

[0113] The front-end buffer 22A is a receive buffer corresponding to the receive port of the lower transceiver 12A, and the front-end buffer 22B is a receive buffer corresponding to the receive port of the lower transceiver 12B. The front-end buffers 22A and 22B are buffers for taking into account various circumstances of the receiving ports (receiving timing, communication speed, etc.), and can be set to a smaller capacity than the buffer 20 shared by each receiving port in order to avoid congestion.

[0114] By providing such front-end buffers 22A, 22B, even if upstream frames are received simultaneously from PON1 and PON2, the output of the upstream frames to the upstream frame processing unit 15 can be shifted in time. Therefore, the received data once stored in the small-capacity front-end buffers 22A, 22B is appropriately stored in the buffer 20 even if congestion occurs.

[0115] Furthermore, the pre-buffers 22A and 22B may be set to a data capacity that guarantees the upstream frame processor 15 a processing time for determining whether an upstream frame is abnormal, such as determining whether an abnormality is based on the CRC header and the CRC calculation value of the upstream frame. In other words, when viewed from each receiving port (PON1 and PON2), a large-capacity buffer 20 that operates in accordance with the circumstances of its own line is provided.

[0116] The performance (data transfer rate, etc.) required for the buffer 20 shared by multiple receiving ports should be determined according to the total degree of service provided by the multiple receiving ports, and therefore there is a large range of variation from the minimum performance to the maximum performance. In this regard, according to the OLT 1 ​​of this embodiment, since it has scalability that allows the performance of the shared buffer 20 to be changed even during operation, appropriate power saving can be achieved according to the operating status of the OLT 1.

[0117] [Other Modifications] The embodiments disclosed herein are illustrative and not restrictive in all respects. The scope of the present invention is not limited to the above-described embodiments, but includes all modifications within the scope of the equivalents of the configurations described in the claims.

[0118] In the above embodiment, the memory control unit 21 and the buffer 20 may be connected to the downstream frame processing unit 16, and downstream frames addressed to the ONU 2 may be buffered to avoid congestion in the same manner as the upstream frames. In the above-described embodiment, the aggregation device 1 may be a relay device that aggregates communications of a plurality of terminal devices 2. Therefore, the communication system 100 is not limited to a PON, and may be a system that employs a transmission path other than an optical line. [Explanation of symbols]

[0119] 1. Aggregation device (OLT) 2 Terminal equipment (ONU) 3 Line network (PON line) 3A,3B line network (PON line) 4 Optical fiber (trunk line) 5 Optical Coupler 6 Optical fiber (branch) 7 Upper network 8 User Network 9. Management Terminal 11 Management and Control Unit 12 Lower-level transceiver (optical transceiver) 12A, 12B Lower transceiver (optical transceiver) 13 Lower side receiving processing unit 13A, 13B Lower side receiving processing unit 14 Lower transmission processing unit 14A, 14B Lower transmission processing unit 15 Upstream frame processing section 16 Downstream frame processing section 17 Upper side receiving processing unit 18. Transmission processing unit on the above side 19 Upper Transceiver 20 Buffers 20A Buffer Memory (1st Memory) 20B Buffer memory (second memory) 21 Memory control unit (buffer control device) 22A Pre-buffer 22B prepending buffer 31 First Switch 32 Second Switch 33A First Controller 33B Second Controller 34A 1st PHY 34B 2nd PHY 100 Communication Systems

Claims

1. An aggregation device that aggregates communications of a plurality of terminal devices, A buffer including a plurality of buffer memories; a frame processing unit that determines whether a communication frame having the plurality of terminal devices as a source or destination is to be transmitted to an outside source or buffered to avoid congestion; a memory control unit that switches a type of memory performance of the buffer while maintaining operation of some of the plurality of buffer memories.

2. The plurality of buffer memories include The present invention includes a first memory and a second memory as described below, The memory performance type is: The aggregation device of claim 1 , further comprising a low bandwidth setting that operates the first memory at a slow data transfer rate and idles the second memory. First memory: a buffer memory among a plurality of buffer memories Second memory: A buffer memory other than the first memory among a plurality of buffer memories

3. The memory performance type is: The aggregation device of claim 2 , further comprising a medium bandwidth setting that causes the first memory to pause and the second memory to operate at a high data transfer rate.

4. The memory performance type is: The aggregation device of claim 3 , further comprising a high bandwidth setting that operates both the first memory and the second memory at a high data transfer rate.

5. The memory control unit 4. The aggregation device of claim 3, further comprising: a first memory configured to read from said first memory and to write to said second memory; a second memory configured to read from said first memory; and a second memory configured to read from said first memory;

6. The memory control unit 5. The aggregation device of claim 4, further comprising: a first memory configured to write data for itself and a second memory configured to read and write data for itself; and a second memory configured to read and write data for itself and to switch from the first memory to the high bandwidth setting on the condition that there is no data for the first memory in the second memory.

7. a plurality of receiving ports sharing the buffer; a front-end buffer corresponding to each of the plurality of receiving ports; The aggregation device according to claim 1 , wherein the front-end buffer is interposed between the buffer and the receiving port.

8. A method for switching memory performance of a buffer for avoiding congestion mounted in an aggregation device that aggregates communications of a plurality of terminal devices, comprising: The buffer comprises: A plurality of buffer memories are included, The method comprises: activating a portion of the plurality of buffer memories; and operating the inactive buffer memory while maintaining the operation of the portion of the memory, thereby switching the memory performance.

9. A control device for a buffer including a plurality of buffer memories, The buffer comprises: The present invention includes a first memory and a second memory as described below, The control device includes: a first PHY for performing data write and read operations on the first memory; a first controller for adjusting operating parameters of the first PHY; a second PHY configured to write and read data to and from the second memory; a second controller for adjusting operating parameters of the second PHY; a switch capable of switching a data flow of a communication frame to be buffered to a path passing through either the first controller or the second controller. First memory: a buffer memory among a plurality of buffer memories Second memory: A buffer memory other than the first memory among a plurality of buffer memories

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